// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
// Date        : Mon Jul 31 18:37:35 2023
// Host        : DESKTOP-PDKL47M running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_sim_netlist.v
// Design      : u_ila_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7z035ffg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "u_ila_0,ila,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "ila,Vivado 2018.3" *) 
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
   (clk,
    probe0,
    probe1,
    probe2);
  input clk;
  input [20:0]probe0;
  input [21:0]probe1;
  input [21:0]probe2;

  wire clk;
  wire [20:0]probe0;
  wire [21:0]probe1;
  wire [21:0]probe2;
  wire NLW_inst_clkdiv_out_UNCONNECTED;
  wire NLW_inst_trig_in_ack_UNCONNECTED;
  wire NLW_inst_trig_out_UNCONNECTED;
  wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;

  (* C_ADV_TRIGGER = "1" *) 
  (* C_BUILD_REVISION = "0" *) 
  (* C_CAPTURE_TYPE = "0" *) 
  (* C_CLKFBOUT_MULT_F = "10" *) 
  (* C_CLKOUT0_DIVIDE_F = "10" *) 
  (* C_CLK_FREQ = "200" *) 
  (* C_CLK_PERIOD = "5.000000" *) 
  (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_CORE_MAJOR_VER = "6" *) 
  (* C_CORE_MINOR_VER = "2" *) 
  (* C_CORE_TYPE = "1" *) 
  (* C_CSE_DRV_VER = "2" *) 
  (* C_DATA_DEPTH = "1024" *) 
  (* C_DDR_CLK_GEN = "0" *) 
  (* C_DIVCLK_DIVIDE = "3" *) 
  (* C_ENABLE_ILA_AXI_MON = "0" *) 
  (* C_EN_DDR_ILA = "0" *) 
  (* C_EN_STRG_QUAL = "1" *) 
  (* C_EN_TIME_TAG = "0" *) 
  (* C_ILA_CLK_FREQ = "2000000" *) 
  (* C_INPUT_PIPE_STAGES = "0" *) 
  (* C_MAJOR_VERSION = "2018" *) 
  (* C_MINOR_VERSION = "3" *) 
  (* C_MU_TYPE = "0" *) 
  (* C_NEXT_SLAVE = "0" *) 
  (* C_NUM_MONITOR_SLOTS = "1" *) 
  (* C_NUM_OF_PROBES = "3" *) 
  (* C_PIPE_IFACE = "1" *) 
  (* C_PROBE0_MU_CNT = "4" *) 
  (* C_PROBE0_TYPE = "0" *) 
  (* C_PROBE0_WIDTH = "21" *) 
  (* C_PROBE1000_MU_CNT = "1" *) 
  (* C_PROBE1000_TYPE = "1" *) 
  (* C_PROBE1000_WIDTH = "1" *) 
  (* C_PROBE1001_MU_CNT = "1" *) 
  (* C_PROBE1001_TYPE = "1" *) 
  (* C_PROBE1001_WIDTH = "1" *) 
  (* C_PROBE1002_MU_CNT = "1" *) 
  (* C_PROBE1002_TYPE = "1" *) 
  (* C_PROBE1002_WIDTH = "1" *) 
  (* C_PROBE1003_MU_CNT = "1" *) 
  (* C_PROBE1003_TYPE = "1" *) 
  (* C_PROBE1003_WIDTH = "1" *) 
  (* C_PROBE1004_MU_CNT = "1" *) 
  (* C_PROBE1004_TYPE = "1" *) 
  (* C_PROBE1004_WIDTH = "1" *) 
  (* C_PROBE1005_MU_CNT = "1" *) 
  (* C_PROBE1005_TYPE = "1" *) 
  (* C_PROBE1005_WIDTH = "1" *) 
  (* C_PROBE1006_MU_CNT = "1" *) 
  (* C_PROBE1006_TYPE = "1" *) 
  (* C_PROBE1006_WIDTH = "1" *) 
  (* C_PROBE1007_MU_CNT = "1" *) 
  (* C_PROBE1007_TYPE = "1" *) 
  (* C_PROBE1007_WIDTH = "1" *) 
  (* C_PROBE1008_MU_CNT = "1" *) 
  (* C_PROBE1008_TYPE = "1" *) 
  (* C_PROBE1008_WIDTH = "1" *) 
  (* C_PROBE1009_MU_CNT = "1" *) 
  (* C_PROBE1009_TYPE = "1" *) 
  (* C_PROBE1009_WIDTH = "1" *) 
  (* C_PROBE100_MU_CNT = "1" *) 
  (* C_PROBE100_TYPE = "1" *) 
  (* C_PROBE100_WIDTH = "1" *) 
  (* C_PROBE1010_MU_CNT = "1" *) 
  (* C_PROBE1010_TYPE = "1" *) 
  (* C_PROBE1010_WIDTH = "1" *) 
  (* C_PROBE1011_MU_CNT = "1" *) 
  (* C_PROBE1011_TYPE = "1" *) 
  (* C_PROBE1011_WIDTH = "1" *) 
  (* C_PROBE1012_MU_CNT = "1" *) 
  (* C_PROBE1012_TYPE = "1" *) 
  (* C_PROBE1012_WIDTH = "1" *) 
  (* C_PROBE1013_MU_CNT = "1" *) 
  (* C_PROBE1013_TYPE = "1" *) 
  (* C_PROBE1013_WIDTH = "1" *) 
  (* C_PROBE1014_MU_CNT = "1" *) 
  (* C_PROBE1014_TYPE = "1" *) 
  (* C_PROBE1014_WIDTH = "1" *) 
  (* C_PROBE1015_MU_CNT = "1" *) 
  (* C_PROBE1015_TYPE = "1" *) 
  (* C_PROBE1015_WIDTH = "1" *) 
  (* C_PROBE1016_MU_CNT = "1" *) 
  (* C_PROBE1016_TYPE = "1" *) 
  (* C_PROBE1016_WIDTH = "1" *) 
  (* C_PROBE1017_MU_CNT = "1" *) 
  (* C_PROBE1017_TYPE = "1" *) 
  (* C_PROBE1017_WIDTH = "1" *) 
  (* C_PROBE1018_MU_CNT = "1" *) 
  (* C_PROBE1018_TYPE = "1" *) 
  (* C_PROBE1018_WIDTH = "1" *) 
  (* C_PROBE1019_MU_CNT = "1" *) 
  (* C_PROBE1019_TYPE = "1" *) 
  (* C_PROBE1019_WIDTH = "1" *) 
  (* C_PROBE101_MU_CNT = "1" *) 
  (* C_PROBE101_TYPE = "1" *) 
  (* C_PROBE101_WIDTH = "1" *) 
  (* C_PROBE1020_MU_CNT = "1" *) 
  (* C_PROBE1020_TYPE = "1" *) 
  (* C_PROBE1020_WIDTH = "1" *) 
  (* C_PROBE1021_MU_CNT = "1" *) 
  (* C_PROBE1021_TYPE = "1" *) 
  (* C_PROBE1021_WIDTH = "1" *) 
  (* C_PROBE1022_MU_CNT = "1" *) 
  (* C_PROBE1022_TYPE = "1" *) 
  (* C_PROBE1022_WIDTH = "1" *) 
  (* C_PROBE1023_MU_CNT = "1" *) 
  (* C_PROBE1023_TYPE = "1" *) 
  (* C_PROBE1023_WIDTH = "1" *) 
  (* C_PROBE102_MU_CNT = "1" *) 
  (* C_PROBE102_TYPE = "1" *) 
  (* C_PROBE102_WIDTH = "1" *) 
  (* C_PROBE103_MU_CNT = "1" *) 
  (* C_PROBE103_TYPE = "1" *) 
  (* C_PROBE103_WIDTH = "1" *) 
  (* C_PROBE104_MU_CNT = "1" *) 
  (* C_PROBE104_TYPE = "1" *) 
  (* C_PROBE104_WIDTH = "1" *) 
  (* C_PROBE105_MU_CNT = "1" *) 
  (* C_PROBE105_TYPE = "1" *) 
  (* C_PROBE105_WIDTH = "1" *) 
  (* C_PROBE106_MU_CNT = "1" *) 
  (* C_PROBE106_TYPE = "1" *) 
  (* C_PROBE106_WIDTH = "1" *) 
  (* C_PROBE107_MU_CNT = "1" *) 
  (* C_PROBE107_TYPE = "1" *) 
  (* C_PROBE107_WIDTH = "1" *) 
  (* C_PROBE108_MU_CNT = "1" *) 
  (* C_PROBE108_TYPE = "1" *) 
  (* C_PROBE108_WIDTH = "1" *) 
  (* C_PROBE109_MU_CNT = "1" *) 
  (* C_PROBE109_TYPE = "1" *) 
  (* C_PROBE109_WIDTH = "1" *) 
  (* C_PROBE10_MU_CNT = "1" *) 
  (* C_PROBE10_TYPE = "1" *) 
  (* C_PROBE10_WIDTH = "1" *) 
  (* C_PROBE110_MU_CNT = "1" *) 
  (* C_PROBE110_TYPE = "1" *) 
  (* C_PROBE110_WIDTH = "1" *) 
  (* C_PROBE111_MU_CNT = "1" *) 
  (* C_PROBE111_TYPE = "1" *) 
  (* C_PROBE111_WIDTH = "1" *) 
  (* C_PROBE112_MU_CNT = "1" *) 
  (* C_PROBE112_TYPE = "1" *) 
  (* C_PROBE112_WIDTH = "1" *) 
  (* C_PROBE113_MU_CNT = "1" *) 
  (* C_PROBE113_TYPE = "1" *) 
  (* C_PROBE113_WIDTH = "1" *) 
  (* C_PROBE114_MU_CNT = "1" *) 
  (* C_PROBE114_TYPE = "1" *) 
  (* C_PROBE114_WIDTH = "1" *) 
  (* C_PROBE115_MU_CNT = "1" *) 
  (* C_PROBE115_TYPE = "1" *) 
  (* C_PROBE115_WIDTH = "1" *) 
  (* C_PROBE116_MU_CNT = "1" *) 
  (* C_PROBE116_TYPE = "1" *) 
  (* C_PROBE116_WIDTH = "1" *) 
  (* C_PROBE117_MU_CNT = "1" *) 
  (* C_PROBE117_TYPE = "1" *) 
  (* C_PROBE117_WIDTH = "1" *) 
  (* C_PROBE118_MU_CNT = "1" *) 
  (* C_PROBE118_TYPE = "1" *) 
  (* C_PROBE118_WIDTH = "1" *) 
  (* C_PROBE119_MU_CNT = "1" *) 
  (* C_PROBE119_TYPE = "1" *) 
  (* C_PROBE119_WIDTH = "1" *) 
  (* C_PROBE11_MU_CNT = "1" *) 
  (* C_PROBE11_TYPE = "1" *) 
  (* C_PROBE11_WIDTH = "1" *) 
  (* C_PROBE120_MU_CNT = "1" *) 
  (* C_PROBE120_TYPE = "1" *) 
  (* C_PROBE120_WIDTH = "1" *) 
  (* C_PROBE121_MU_CNT = "1" *) 
  (* C_PROBE121_TYPE = "1" *) 
  (* C_PROBE121_WIDTH = "1" *) 
  (* C_PROBE122_MU_CNT = "1" *) 
  (* C_PROBE122_TYPE = "1" *) 
  (* C_PROBE122_WIDTH = "1" *) 
  (* C_PROBE123_MU_CNT = "1" *) 
  (* C_PROBE123_TYPE = "1" *) 
  (* C_PROBE123_WIDTH = "1" *) 
  (* C_PROBE124_MU_CNT = "1" *) 
  (* C_PROBE124_TYPE = "1" *) 
  (* C_PROBE124_WIDTH = "1" *) 
  (* C_PROBE125_MU_CNT = "1" *) 
  (* C_PROBE125_TYPE = "1" *) 
  (* C_PROBE125_WIDTH = "1" *) 
  (* C_PROBE126_MU_CNT = "1" *) 
  (* C_PROBE126_TYPE = "1" *) 
  (* C_PROBE126_WIDTH = "1" *) 
  (* C_PROBE127_MU_CNT = "1" *) 
  (* C_PROBE127_TYPE = "1" *) 
  (* C_PROBE127_WIDTH = "1" *) 
  (* C_PROBE128_MU_CNT = "1" *) 
  (* C_PROBE128_TYPE = "1" *) 
  (* C_PROBE128_WIDTH = "1" *) 
  (* C_PROBE129_MU_CNT = "1" *) 
  (* C_PROBE129_TYPE = "1" *) 
  (* C_PROBE129_WIDTH = "1" *) 
  (* C_PROBE12_MU_CNT = "1" *) 
  (* C_PROBE12_TYPE = "1" *) 
  (* C_PROBE12_WIDTH = "1" *) 
  (* C_PROBE130_MU_CNT = "1" *) 
  (* C_PROBE130_TYPE = "1" *) 
  (* C_PROBE130_WIDTH = "1" *) 
  (* C_PROBE131_MU_CNT = "1" *) 
  (* C_PROBE131_TYPE = "1" *) 
  (* C_PROBE131_WIDTH = "1" *) 
  (* C_PROBE132_MU_CNT = "1" *) 
  (* C_PROBE132_TYPE = "1" *) 
  (* C_PROBE132_WIDTH = "1" *) 
  (* C_PROBE133_MU_CNT = "1" *) 
  (* C_PROBE133_TYPE = "1" *) 
  (* C_PROBE133_WIDTH = "1" *) 
  (* C_PROBE134_MU_CNT = "1" *) 
  (* C_PROBE134_TYPE = "1" *) 
  (* C_PROBE134_WIDTH = "1" *) 
  (* C_PROBE135_MU_CNT = "1" *) 
  (* C_PROBE135_TYPE = "1" *) 
  (* C_PROBE135_WIDTH = "1" *) 
  (* C_PROBE136_MU_CNT = "1" *) 
  (* C_PROBE136_TYPE = "1" *) 
  (* C_PROBE136_WIDTH = "1" *) 
  (* C_PROBE137_MU_CNT = "1" *) 
  (* C_PROBE137_TYPE = "1" *) 
  (* C_PROBE137_WIDTH = "1" *) 
  (* C_PROBE138_MU_CNT = "1" *) 
  (* C_PROBE138_TYPE = "1" *) 
  (* C_PROBE138_WIDTH = "1" *) 
  (* C_PROBE139_MU_CNT = "1" *) 
  (* C_PROBE139_TYPE = "1" *) 
  (* C_PROBE139_WIDTH = "1" *) 
  (* C_PROBE13_MU_CNT = "1" *) 
  (* C_PROBE13_TYPE = "1" *) 
  (* C_PROBE13_WIDTH = "1" *) 
  (* C_PROBE140_MU_CNT = "1" *) 
  (* C_PROBE140_TYPE = "1" *) 
  (* C_PROBE140_WIDTH = "1" *) 
  (* C_PROBE141_MU_CNT = "1" *) 
  (* C_PROBE141_TYPE = "1" *) 
  (* C_PROBE141_WIDTH = "1" *) 
  (* C_PROBE142_MU_CNT = "1" *) 
  (* C_PROBE142_TYPE = "1" *) 
  (* C_PROBE142_WIDTH = "1" *) 
  (* C_PROBE143_MU_CNT = "1" *) 
  (* C_PROBE143_TYPE = "1" *) 
  (* C_PROBE143_WIDTH = "1" *) 
  (* C_PROBE144_MU_CNT = "1" *) 
  (* C_PROBE144_TYPE = "1" *) 
  (* C_PROBE144_WIDTH = "1" *) 
  (* C_PROBE145_MU_CNT = "1" *) 
  (* C_PROBE145_TYPE = "1" *) 
  (* C_PROBE145_WIDTH = "1" *) 
  (* C_PROBE146_MU_CNT = "1" *) 
  (* C_PROBE146_TYPE = "1" *) 
  (* C_PROBE146_WIDTH = "1" *) 
  (* C_PROBE147_MU_CNT = "1" *) 
  (* C_PROBE147_TYPE = "1" *) 
  (* C_PROBE147_WIDTH = "1" *) 
  (* C_PROBE148_MU_CNT = "1" *) 
  (* C_PROBE148_TYPE = "1" *) 
  (* C_PROBE148_WIDTH = "1" *) 
  (* C_PROBE149_MU_CNT = "1" *) 
  (* C_PROBE149_TYPE = "1" *) 
  (* C_PROBE149_WIDTH = "1" *) 
  (* C_PROBE14_MU_CNT = "1" *) 
  (* C_PROBE14_TYPE = "1" *) 
  (* C_PROBE14_WIDTH = "1" *) 
  (* C_PROBE150_MU_CNT = "1" *) 
  (* C_PROBE150_TYPE = "1" *) 
  (* C_PROBE150_WIDTH = "1" *) 
  (* C_PROBE151_MU_CNT = "1" *) 
  (* C_PROBE151_TYPE = "1" *) 
  (* C_PROBE151_WIDTH = "1" *) 
  (* C_PROBE152_MU_CNT = "1" *) 
  (* C_PROBE152_TYPE = "1" *) 
  (* C_PROBE152_WIDTH = "1" *) 
  (* C_PROBE153_MU_CNT = "1" *) 
  (* C_PROBE153_TYPE = "1" *) 
  (* C_PROBE153_WIDTH = "1" *) 
  (* C_PROBE154_MU_CNT = "1" *) 
  (* C_PROBE154_TYPE = "1" *) 
  (* C_PROBE154_WIDTH = "1" *) 
  (* C_PROBE155_MU_CNT = "1" *) 
  (* C_PROBE155_TYPE = "1" *) 
  (* C_PROBE155_WIDTH = "1" *) 
  (* C_PROBE156_MU_CNT = "1" *) 
  (* C_PROBE156_TYPE = "1" *) 
  (* C_PROBE156_WIDTH = "1" *) 
  (* C_PROBE157_MU_CNT = "1" *) 
  (* C_PROBE157_TYPE = "1" *) 
  (* C_PROBE157_WIDTH = "1" *) 
  (* C_PROBE158_MU_CNT = "1" *) 
  (* C_PROBE158_TYPE = "1" *) 
  (* C_PROBE158_WIDTH = "1" *) 
  (* C_PROBE159_MU_CNT = "1" *) 
  (* C_PROBE159_TYPE = "1" *) 
  (* C_PROBE159_WIDTH = "1" *) 
  (* C_PROBE15_MU_CNT = "1" *) 
  (* C_PROBE15_TYPE = "1" *) 
  (* C_PROBE15_WIDTH = "1" *) 
  (* C_PROBE160_MU_CNT = "1" *) 
  (* C_PROBE160_TYPE = "1" *) 
  (* C_PROBE160_WIDTH = "1" *) 
  (* C_PROBE161_MU_CNT = "1" *) 
  (* C_PROBE161_TYPE = "1" *) 
  (* C_PROBE161_WIDTH = "1" *) 
  (* C_PROBE162_MU_CNT = "1" *) 
  (* C_PROBE162_TYPE = "1" *) 
  (* C_PROBE162_WIDTH = "1" *) 
  (* C_PROBE163_MU_CNT = "1" *) 
  (* C_PROBE163_TYPE = "1" *) 
  (* C_PROBE163_WIDTH = "1" *) 
  (* C_PROBE164_MU_CNT = "1" *) 
  (* C_PROBE164_TYPE = "1" *) 
  (* C_PROBE164_WIDTH = "1" *) 
  (* C_PROBE165_MU_CNT = "1" *) 
  (* C_PROBE165_TYPE = "1" *) 
  (* C_PROBE165_WIDTH = "1" *) 
  (* C_PROBE166_MU_CNT = "1" *) 
  (* C_PROBE166_TYPE = "1" *) 
  (* C_PROBE166_WIDTH = "1" *) 
  (* C_PROBE167_MU_CNT = "1" *) 
  (* C_PROBE167_TYPE = "1" *) 
  (* C_PROBE167_WIDTH = "1" *) 
  (* C_PROBE168_MU_CNT = "1" *) 
  (* C_PROBE168_TYPE = "1" *) 
  (* C_PROBE168_WIDTH = "1" *) 
  (* C_PROBE169_MU_CNT = "1" *) 
  (* C_PROBE169_TYPE = "1" *) 
  (* C_PROBE169_WIDTH = "1" *) 
  (* C_PROBE16_MU_CNT = "1" *) 
  (* C_PROBE16_TYPE = "1" *) 
  (* C_PROBE16_WIDTH = "1" *) 
  (* C_PROBE170_MU_CNT = "1" *) 
  (* C_PROBE170_TYPE = "1" *) 
  (* C_PROBE170_WIDTH = "1" *) 
  (* C_PROBE171_MU_CNT = "1" *) 
  (* C_PROBE171_TYPE = "1" *) 
  (* C_PROBE171_WIDTH = "1" *) 
  (* C_PROBE172_MU_CNT = "1" *) 
  (* C_PROBE172_TYPE = "1" *) 
  (* C_PROBE172_WIDTH = "1" *) 
  (* C_PROBE173_MU_CNT = "1" *) 
  (* C_PROBE173_TYPE = "1" *) 
  (* C_PROBE173_WIDTH = "1" *) 
  (* C_PROBE174_MU_CNT = "1" *) 
  (* C_PROBE174_TYPE = "1" *) 
  (* C_PROBE174_WIDTH = "1" *) 
  (* C_PROBE175_MU_CNT = "1" *) 
  (* C_PROBE175_TYPE = "1" *) 
  (* C_PROBE175_WIDTH = "1" *) 
  (* C_PROBE176_MU_CNT = "1" *) 
  (* C_PROBE176_TYPE = "1" *) 
  (* C_PROBE176_WIDTH = "1" *) 
  (* C_PROBE177_MU_CNT = "1" *) 
  (* C_PROBE177_TYPE = "1" *) 
  (* C_PROBE177_WIDTH = "1" *) 
  (* C_PROBE178_MU_CNT = "1" *) 
  (* C_PROBE178_TYPE = "1" *) 
  (* C_PROBE178_WIDTH = "1" *) 
  (* C_PROBE179_MU_CNT = "1" *) 
  (* C_PROBE179_TYPE = "1" *) 
  (* C_PROBE179_WIDTH = "1" *) 
  (* C_PROBE17_MU_CNT = "1" *) 
  (* C_PROBE17_TYPE = "1" *) 
  (* C_PROBE17_WIDTH = "1" *) 
  (* C_PROBE180_MU_CNT = "1" *) 
  (* C_PROBE180_TYPE = "1" *) 
  (* C_PROBE180_WIDTH = "1" *) 
  (* C_PROBE181_MU_CNT = "1" *) 
  (* C_PROBE181_TYPE = "1" *) 
  (* C_PROBE181_WIDTH = "1" *) 
  (* C_PROBE182_MU_CNT = "1" *) 
  (* C_PROBE182_TYPE = "1" *) 
  (* C_PROBE182_WIDTH = "1" *) 
  (* C_PROBE183_MU_CNT = "1" *) 
  (* C_PROBE183_TYPE = "1" *) 
  (* C_PROBE183_WIDTH = "1" *) 
  (* C_PROBE184_MU_CNT = "1" *) 
  (* C_PROBE184_TYPE = "1" *) 
  (* C_PROBE184_WIDTH = "1" *) 
  (* C_PROBE185_MU_CNT = "1" *) 
  (* C_PROBE185_TYPE = "1" *) 
  (* C_PROBE185_WIDTH = "1" *) 
  (* C_PROBE186_MU_CNT = "1" *) 
  (* C_PROBE186_TYPE = "1" *) 
  (* C_PROBE186_WIDTH = "1" *) 
  (* C_PROBE187_MU_CNT = "1" *) 
  (* C_PROBE187_TYPE = "1" *) 
  (* C_PROBE187_WIDTH = "1" *) 
  (* C_PROBE188_MU_CNT = "1" *) 
  (* C_PROBE188_TYPE = "1" *) 
  (* C_PROBE188_WIDTH = "1" *) 
  (* C_PROBE189_MU_CNT = "1" *) 
  (* C_PROBE189_TYPE = "1" *) 
  (* C_PROBE189_WIDTH = "1" *) 
  (* C_PROBE18_MU_CNT = "1" *) 
  (* C_PROBE18_TYPE = "1" *) 
  (* C_PROBE18_WIDTH = "1" *) 
  (* C_PROBE190_MU_CNT = "1" *) 
  (* C_PROBE190_TYPE = "1" *) 
  (* C_PROBE190_WIDTH = "1" *) 
  (* C_PROBE191_MU_CNT = "1" *) 
  (* C_PROBE191_TYPE = "1" *) 
  (* C_PROBE191_WIDTH = "1" *) 
  (* C_PROBE192_MU_CNT = "1" *) 
  (* C_PROBE192_TYPE = "1" *) 
  (* C_PROBE192_WIDTH = "1" *) 
  (* C_PROBE193_MU_CNT = "1" *) 
  (* C_PROBE193_TYPE = "1" *) 
  (* C_PROBE193_WIDTH = "1" *) 
  (* C_PROBE194_MU_CNT = "1" *) 
  (* C_PROBE194_TYPE = "1" *) 
  (* C_PROBE194_WIDTH = "1" *) 
  (* C_PROBE195_MU_CNT = "1" *) 
  (* C_PROBE195_TYPE = "1" *) 
  (* C_PROBE195_WIDTH = "1" *) 
  (* C_PROBE196_MU_CNT = "1" *) 
  (* C_PROBE196_TYPE = "1" *) 
  (* C_PROBE196_WIDTH = "1" *) 
  (* C_PROBE197_MU_CNT = "1" *) 
  (* C_PROBE197_TYPE = "1" *) 
  (* C_PROBE197_WIDTH = "1" *) 
  (* C_PROBE198_MU_CNT = "1" *) 
  (* C_PROBE198_TYPE = "1" *) 
  (* C_PROBE198_WIDTH = "1" *) 
  (* C_PROBE199_MU_CNT = "1" *) 
  (* C_PROBE199_TYPE = "1" *) 
  (* C_PROBE199_WIDTH = "1" *) 
  (* C_PROBE19_MU_CNT = "1" *) 
  (* C_PROBE19_TYPE = "1" *) 
  (* C_PROBE19_WIDTH = "1" *) 
  (* C_PROBE1_MU_CNT = "4" *) 
  (* C_PROBE1_TYPE = "0" *) 
  (* C_PROBE1_WIDTH = "22" *) 
  (* C_PROBE200_MU_CNT = "1" *) 
  (* C_PROBE200_TYPE = "1" *) 
  (* C_PROBE200_WIDTH = "1" *) 
  (* C_PROBE201_MU_CNT = "1" *) 
  (* C_PROBE201_TYPE = "1" *) 
  (* C_PROBE201_WIDTH = "1" *) 
  (* C_PROBE202_MU_CNT = "1" *) 
  (* C_PROBE202_TYPE = "1" *) 
  (* C_PROBE202_WIDTH = "1" *) 
  (* C_PROBE203_MU_CNT = "1" *) 
  (* C_PROBE203_TYPE = "1" *) 
  (* C_PROBE203_WIDTH = "1" *) 
  (* C_PROBE204_MU_CNT = "1" *) 
  (* C_PROBE204_TYPE = "1" *) 
  (* C_PROBE204_WIDTH = "1" *) 
  (* C_PROBE205_MU_CNT = "1" *) 
  (* C_PROBE205_TYPE = "1" *) 
  (* C_PROBE205_WIDTH = "1" *) 
  (* C_PROBE206_MU_CNT = "1" *) 
  (* C_PROBE206_TYPE = "1" *) 
  (* C_PROBE206_WIDTH = "1" *) 
  (* C_PROBE207_MU_CNT = "1" *) 
  (* C_PROBE207_TYPE = "1" *) 
  (* C_PROBE207_WIDTH = "1" *) 
  (* C_PROBE208_MU_CNT = "1" *) 
  (* C_PROBE208_TYPE = "1" *) 
  (* C_PROBE208_WIDTH = "1" *) 
  (* C_PROBE209_MU_CNT = "1" *) 
  (* C_PROBE209_TYPE = "1" *) 
  (* C_PROBE209_WIDTH = "1" *) 
  (* C_PROBE20_MU_CNT = "1" *) 
  (* C_PROBE20_TYPE = "1" *) 
  (* C_PROBE20_WIDTH = "1" *) 
  (* C_PROBE210_MU_CNT = "1" *) 
  (* C_PROBE210_TYPE = "1" *) 
  (* C_PROBE210_WIDTH = "1" *) 
  (* C_PROBE211_MU_CNT = "1" *) 
  (* C_PROBE211_TYPE = "1" *) 
  (* C_PROBE211_WIDTH = "1" *) 
  (* C_PROBE212_MU_CNT = "1" *) 
  (* C_PROBE212_TYPE = "1" *) 
  (* C_PROBE212_WIDTH = "1" *) 
  (* C_PROBE213_MU_CNT = "1" *) 
  (* C_PROBE213_TYPE = "1" *) 
  (* C_PROBE213_WIDTH = "1" *) 
  (* C_PROBE214_MU_CNT = "1" *) 
  (* C_PROBE214_TYPE = "1" *) 
  (* C_PROBE214_WIDTH = "1" *) 
  (* C_PROBE215_MU_CNT = "1" *) 
  (* C_PROBE215_TYPE = "1" *) 
  (* C_PROBE215_WIDTH = "1" *) 
  (* C_PROBE216_MU_CNT = "1" *) 
  (* C_PROBE216_TYPE = "1" *) 
  (* C_PROBE216_WIDTH = "1" *) 
  (* C_PROBE217_MU_CNT = "1" *) 
  (* C_PROBE217_TYPE = "1" *) 
  (* C_PROBE217_WIDTH = "1" *) 
  (* C_PROBE218_MU_CNT = "1" *) 
  (* C_PROBE218_TYPE = "1" *) 
  (* C_PROBE218_WIDTH = "1" *) 
  (* C_PROBE219_MU_CNT = "1" *) 
  (* C_PROBE219_TYPE = "1" *) 
  (* C_PROBE219_WIDTH = "1" *) 
  (* C_PROBE21_MU_CNT = "1" *) 
  (* C_PROBE21_TYPE = "1" *) 
  (* C_PROBE21_WIDTH = "1" *) 
  (* C_PROBE220_MU_CNT = "1" *) 
  (* C_PROBE220_TYPE = "1" *) 
  (* C_PROBE220_WIDTH = "1" *) 
  (* C_PROBE221_MU_CNT = "1" *) 
  (* C_PROBE221_TYPE = "1" *) 
  (* C_PROBE221_WIDTH = "1" *) 
  (* C_PROBE222_MU_CNT = "1" *) 
  (* C_PROBE222_TYPE = "1" *) 
  (* C_PROBE222_WIDTH = "1" *) 
  (* C_PROBE223_MU_CNT = "1" *) 
  (* C_PROBE223_TYPE = "1" *) 
  (* C_PROBE223_WIDTH = "1" *) 
  (* C_PROBE224_MU_CNT = "1" *) 
  (* C_PROBE224_TYPE = "1" *) 
  (* C_PROBE224_WIDTH = "1" *) 
  (* C_PROBE225_MU_CNT = "1" *) 
  (* C_PROBE225_TYPE = "1" *) 
  (* C_PROBE225_WIDTH = "1" *) 
  (* C_PROBE226_MU_CNT = "1" *) 
  (* C_PROBE226_TYPE = "1" *) 
  (* C_PROBE226_WIDTH = "1" *) 
  (* C_PROBE227_MU_CNT = "1" *) 
  (* C_PROBE227_TYPE = "1" *) 
  (* C_PROBE227_WIDTH = "1" *) 
  (* C_PROBE228_MU_CNT = "1" *) 
  (* C_PROBE228_TYPE = "1" *) 
  (* C_PROBE228_WIDTH = "1" *) 
  (* C_PROBE229_MU_CNT = "1" *) 
  (* C_PROBE229_TYPE = "1" *) 
  (* C_PROBE229_WIDTH = "1" *) 
  (* C_PROBE22_MU_CNT = "1" *) 
  (* C_PROBE22_TYPE = "1" *) 
  (* C_PROBE22_WIDTH = "1" *) 
  (* C_PROBE230_MU_CNT = "1" *) 
  (* C_PROBE230_TYPE = "1" *) 
  (* C_PROBE230_WIDTH = "1" *) 
  (* C_PROBE231_MU_CNT = "1" *) 
  (* C_PROBE231_TYPE = "1" *) 
  (* C_PROBE231_WIDTH = "1" *) 
  (* C_PROBE232_MU_CNT = "1" *) 
  (* C_PROBE232_TYPE = "1" *) 
  (* C_PROBE232_WIDTH = "1" *) 
  (* C_PROBE233_MU_CNT = "1" *) 
  (* C_PROBE233_TYPE = "1" *) 
  (* C_PROBE233_WIDTH = "1" *) 
  (* C_PROBE234_MU_CNT = "1" *) 
  (* C_PROBE234_TYPE = "1" *) 
  (* C_PROBE234_WIDTH = "1" *) 
  (* C_PROBE235_MU_CNT = "1" *) 
  (* C_PROBE235_TYPE = "1" *) 
  (* C_PROBE235_WIDTH = "1" *) 
  (* C_PROBE236_MU_CNT = "1" *) 
  (* C_PROBE236_TYPE = "1" *) 
  (* C_PROBE236_WIDTH = "1" *) 
  (* C_PROBE237_MU_CNT = "1" *) 
  (* C_PROBE237_TYPE = "1" *) 
  (* C_PROBE237_WIDTH = "1" *) 
  (* C_PROBE238_MU_CNT = "1" *) 
  (* C_PROBE238_TYPE = "1" *) 
  (* C_PROBE238_WIDTH = "1" *) 
  (* C_PROBE239_MU_CNT = "1" *) 
  (* C_PROBE239_TYPE = "1" *) 
  (* C_PROBE239_WIDTH = "1" *) 
  (* C_PROBE23_MU_CNT = "1" *) 
  (* C_PROBE23_TYPE = "1" *) 
  (* C_PROBE23_WIDTH = "1" *) 
  (* C_PROBE240_MU_CNT = "1" *) 
  (* C_PROBE240_TYPE = "1" *) 
  (* C_PROBE240_WIDTH = "1" *) 
  (* C_PROBE241_MU_CNT = "1" *) 
  (* C_PROBE241_TYPE = "1" *) 
  (* C_PROBE241_WIDTH = "1" *) 
  (* C_PROBE242_MU_CNT = "1" *) 
  (* C_PROBE242_TYPE = "1" *) 
  (* C_PROBE242_WIDTH = "1" *) 
  (* C_PROBE243_MU_CNT = "1" *) 
  (* C_PROBE243_TYPE = "1" *) 
  (* C_PROBE243_WIDTH = "1" *) 
  (* C_PROBE244_MU_CNT = "1" *) 
  (* C_PROBE244_TYPE = "1" *) 
  (* C_PROBE244_WIDTH = "1" *) 
  (* C_PROBE245_MU_CNT = "1" *) 
  (* C_PROBE245_TYPE = "1" *) 
  (* C_PROBE245_WIDTH = "1" *) 
  (* C_PROBE246_MU_CNT = "1" *) 
  (* C_PROBE246_TYPE = "1" *) 
  (* C_PROBE246_WIDTH = "1" *) 
  (* C_PROBE247_MU_CNT = "1" *) 
  (* C_PROBE247_TYPE = "1" *) 
  (* C_PROBE247_WIDTH = "1" *) 
  (* C_PROBE248_MU_CNT = "1" *) 
  (* C_PROBE248_TYPE = "1" *) 
  (* C_PROBE248_WIDTH = "1" *) 
  (* C_PROBE249_MU_CNT = "1" *) 
  (* C_PROBE249_TYPE = "1" *) 
  (* C_PROBE249_WIDTH = "1" *) 
  (* C_PROBE24_MU_CNT = "1" *) 
  (* C_PROBE24_TYPE = "1" *) 
  (* C_PROBE24_WIDTH = "1" *) 
  (* C_PROBE250_MU_CNT = "1" *) 
  (* C_PROBE250_TYPE = "1" *) 
  (* C_PROBE250_WIDTH = "1" *) 
  (* C_PROBE251_MU_CNT = "1" *) 
  (* C_PROBE251_TYPE = "1" *) 
  (* C_PROBE251_WIDTH = "1" *) 
  (* C_PROBE252_MU_CNT = "1" *) 
  (* C_PROBE252_TYPE = "1" *) 
  (* C_PROBE252_WIDTH = "1" *) 
  (* C_PROBE253_MU_CNT = "1" *) 
  (* C_PROBE253_TYPE = "1" *) 
  (* C_PROBE253_WIDTH = "1" *) 
  (* C_PROBE254_MU_CNT = "1" *) 
  (* C_PROBE254_TYPE = "1" *) 
  (* C_PROBE254_WIDTH = "1" *) 
  (* C_PROBE255_MU_CNT = "1" *) 
  (* C_PROBE255_TYPE = "1" *) 
  (* C_PROBE255_WIDTH = "1" *) 
  (* C_PROBE256_MU_CNT = "1" *) 
  (* C_PROBE256_TYPE = "1" *) 
  (* C_PROBE256_WIDTH = "1" *) 
  (* C_PROBE257_MU_CNT = "1" *) 
  (* C_PROBE257_TYPE = "1" *) 
  (* C_PROBE257_WIDTH = "1" *) 
  (* C_PROBE258_MU_CNT = "1" *) 
  (* C_PROBE258_TYPE = "1" *) 
  (* C_PROBE258_WIDTH = "1" *) 
  (* C_PROBE259_MU_CNT = "1" *) 
  (* C_PROBE259_TYPE = "1" *) 
  (* C_PROBE259_WIDTH = "1" *) 
  (* C_PROBE25_MU_CNT = "1" *) 
  (* C_PROBE25_TYPE = "1" *) 
  (* C_PROBE25_WIDTH = "1" *) 
  (* C_PROBE260_MU_CNT = "1" *) 
  (* C_PROBE260_TYPE = "1" *) 
  (* C_PROBE260_WIDTH = "1" *) 
  (* C_PROBE261_MU_CNT = "1" *) 
  (* C_PROBE261_TYPE = "1" *) 
  (* C_PROBE261_WIDTH = "1" *) 
  (* C_PROBE262_MU_CNT = "1" *) 
  (* C_PROBE262_TYPE = "1" *) 
  (* C_PROBE262_WIDTH = "1" *) 
  (* C_PROBE263_MU_CNT = "1" *) 
  (* C_PROBE263_TYPE = "1" *) 
  (* C_PROBE263_WIDTH = "1" *) 
  (* C_PROBE264_MU_CNT = "1" *) 
  (* C_PROBE264_TYPE = "1" *) 
  (* C_PROBE264_WIDTH = "1" *) 
  (* C_PROBE265_MU_CNT = "1" *) 
  (* C_PROBE265_TYPE = "1" *) 
  (* C_PROBE265_WIDTH = "1" *) 
  (* C_PROBE266_MU_CNT = "1" *) 
  (* C_PROBE266_TYPE = "1" *) 
  (* C_PROBE266_WIDTH = "1" *) 
  (* C_PROBE267_MU_CNT = "1" *) 
  (* C_PROBE267_TYPE = "1" *) 
  (* C_PROBE267_WIDTH = "1" *) 
  (* C_PROBE268_MU_CNT = "1" *) 
  (* C_PROBE268_TYPE = "1" *) 
  (* C_PROBE268_WIDTH = "1" *) 
  (* C_PROBE269_MU_CNT = "1" *) 
  (* C_PROBE269_TYPE = "1" *) 
  (* C_PROBE269_WIDTH = "1" *) 
  (* C_PROBE26_MU_CNT = "1" *) 
  (* C_PROBE26_TYPE = "1" *) 
  (* C_PROBE26_WIDTH = "1" *) 
  (* C_PROBE270_MU_CNT = "1" *) 
  (* C_PROBE270_TYPE = "1" *) 
  (* C_PROBE270_WIDTH = "1" *) 
  (* C_PROBE271_MU_CNT = "1" *) 
  (* C_PROBE271_TYPE = "1" *) 
  (* C_PROBE271_WIDTH = "1" *) 
  (* C_PROBE272_MU_CNT = "1" *) 
  (* C_PROBE272_TYPE = "1" *) 
  (* C_PROBE272_WIDTH = "1" *) 
  (* C_PROBE273_MU_CNT = "1" *) 
  (* C_PROBE273_TYPE = "1" *) 
  (* C_PROBE273_WIDTH = "1" *) 
  (* C_PROBE274_MU_CNT = "1" *) 
  (* C_PROBE274_TYPE = "1" *) 
  (* C_PROBE274_WIDTH = "1" *) 
  (* C_PROBE275_MU_CNT = "1" *) 
  (* C_PROBE275_TYPE = "1" *) 
  (* C_PROBE275_WIDTH = "1" *) 
  (* C_PROBE276_MU_CNT = "1" *) 
  (* C_PROBE276_TYPE = "1" *) 
  (* C_PROBE276_WIDTH = "1" *) 
  (* C_PROBE277_MU_CNT = "1" *) 
  (* C_PROBE277_TYPE = "1" *) 
  (* C_PROBE277_WIDTH = "1" *) 
  (* C_PROBE278_MU_CNT = "1" *) 
  (* C_PROBE278_TYPE = "1" *) 
  (* C_PROBE278_WIDTH = "1" *) 
  (* C_PROBE279_MU_CNT = "1" *) 
  (* C_PROBE279_TYPE = "1" *) 
  (* C_PROBE279_WIDTH = "1" *) 
  (* C_PROBE27_MU_CNT = "1" *) 
  (* C_PROBE27_TYPE = "1" *) 
  (* C_PROBE27_WIDTH = "1" *) 
  (* C_PROBE280_MU_CNT = "1" *) 
  (* C_PROBE280_TYPE = "1" *) 
  (* C_PROBE280_WIDTH = "1" *) 
  (* C_PROBE281_MU_CNT = "1" *) 
  (* C_PROBE281_TYPE = "1" *) 
  (* C_PROBE281_WIDTH = "1" *) 
  (* C_PROBE282_MU_CNT = "1" *) 
  (* C_PROBE282_TYPE = "1" *) 
  (* C_PROBE282_WIDTH = "1" *) 
  (* C_PROBE283_MU_CNT = "1" *) 
  (* C_PROBE283_TYPE = "1" *) 
  (* C_PROBE283_WIDTH = "1" *) 
  (* C_PROBE284_MU_CNT = "1" *) 
  (* C_PROBE284_TYPE = "1" *) 
  (* C_PROBE284_WIDTH = "1" *) 
  (* C_PROBE285_MU_CNT = "1" *) 
  (* C_PROBE285_TYPE = "1" *) 
  (* C_PROBE285_WIDTH = "1" *) 
  (* C_PROBE286_MU_CNT = "1" *) 
  (* C_PROBE286_TYPE = "1" *) 
  (* C_PROBE286_WIDTH = "1" *) 
  (* C_PROBE287_MU_CNT = "1" *) 
  (* C_PROBE287_TYPE = "1" *) 
  (* C_PROBE287_WIDTH = "1" *) 
  (* C_PROBE288_MU_CNT = "1" *) 
  (* C_PROBE288_TYPE = "1" *) 
  (* C_PROBE288_WIDTH = "1" *) 
  (* C_PROBE289_MU_CNT = "1" *) 
  (* C_PROBE289_TYPE = "1" *) 
  (* C_PROBE289_WIDTH = "1" *) 
  (* C_PROBE28_MU_CNT = "1" *) 
  (* C_PROBE28_TYPE = "1" *) 
  (* C_PROBE28_WIDTH = "1" *) 
  (* C_PROBE290_MU_CNT = "1" *) 
  (* C_PROBE290_TYPE = "1" *) 
  (* C_PROBE290_WIDTH = "1" *) 
  (* C_PROBE291_MU_CNT = "1" *) 
  (* C_PROBE291_TYPE = "1" *) 
  (* C_PROBE291_WIDTH = "1" *) 
  (* C_PROBE292_MU_CNT = "1" *) 
  (* C_PROBE292_TYPE = "1" *) 
  (* C_PROBE292_WIDTH = "1" *) 
  (* C_PROBE293_MU_CNT = "1" *) 
  (* C_PROBE293_TYPE = "1" *) 
  (* C_PROBE293_WIDTH = "1" *) 
  (* C_PROBE294_MU_CNT = "1" *) 
  (* C_PROBE294_TYPE = "1" *) 
  (* C_PROBE294_WIDTH = "1" *) 
  (* C_PROBE295_MU_CNT = "1" *) 
  (* C_PROBE295_TYPE = "1" *) 
  (* C_PROBE295_WIDTH = "1" *) 
  (* C_PROBE296_MU_CNT = "1" *) 
  (* C_PROBE296_TYPE = "1" *) 
  (* C_PROBE296_WIDTH = "1" *) 
  (* C_PROBE297_MU_CNT = "1" *) 
  (* C_PROBE297_TYPE = "1" *) 
  (* C_PROBE297_WIDTH = "1" *) 
  (* C_PROBE298_MU_CNT = "1" *) 
  (* C_PROBE298_TYPE = "1" *) 
  (* C_PROBE298_WIDTH = "1" *) 
  (* C_PROBE299_MU_CNT = "1" *) 
  (* C_PROBE299_TYPE = "1" *) 
  (* C_PROBE299_WIDTH = "1" *) 
  (* C_PROBE29_MU_CNT = "1" *) 
  (* C_PROBE29_TYPE = "1" *) 
  (* C_PROBE29_WIDTH = "1" *) 
  (* C_PROBE2_MU_CNT = "4" *) 
  (* C_PROBE2_TYPE = "0" *) 
  (* C_PROBE2_WIDTH = "22" *) 
  (* C_PROBE300_MU_CNT = "1" *) 
  (* C_PROBE300_TYPE = "1" *) 
  (* C_PROBE300_WIDTH = "1" *) 
  (* C_PROBE301_MU_CNT = "1" *) 
  (* C_PROBE301_TYPE = "1" *) 
  (* C_PROBE301_WIDTH = "1" *) 
  (* C_PROBE302_MU_CNT = "1" *) 
  (* C_PROBE302_TYPE = "1" *) 
  (* C_PROBE302_WIDTH = "1" *) 
  (* C_PROBE303_MU_CNT = "1" *) 
  (* C_PROBE303_TYPE = "1" *) 
  (* C_PROBE303_WIDTH = "1" *) 
  (* C_PROBE304_MU_CNT = "1" *) 
  (* C_PROBE304_TYPE = "1" *) 
  (* C_PROBE304_WIDTH = "1" *) 
  (* C_PROBE305_MU_CNT = "1" *) 
  (* C_PROBE305_TYPE = "1" *) 
  (* C_PROBE305_WIDTH = "1" *) 
  (* C_PROBE306_MU_CNT = "1" *) 
  (* C_PROBE306_TYPE = "1" *) 
  (* C_PROBE306_WIDTH = "1" *) 
  (* C_PROBE307_MU_CNT = "1" *) 
  (* C_PROBE307_TYPE = "1" *) 
  (* C_PROBE307_WIDTH = "1" *) 
  (* C_PROBE308_MU_CNT = "1" *) 
  (* C_PROBE308_TYPE = "1" *) 
  (* C_PROBE308_WIDTH = "1" *) 
  (* C_PROBE309_MU_CNT = "1" *) 
  (* C_PROBE309_TYPE = "1" *) 
  (* C_PROBE309_WIDTH = "1" *) 
  (* C_PROBE30_MU_CNT = "1" *) 
  (* C_PROBE30_TYPE = "1" *) 
  (* C_PROBE30_WIDTH = "1" *) 
  (* C_PROBE310_MU_CNT = "1" *) 
  (* C_PROBE310_TYPE = "1" *) 
  (* C_PROBE310_WIDTH = "1" *) 
  (* C_PROBE311_MU_CNT = "1" *) 
  (* C_PROBE311_TYPE = "1" *) 
  (* C_PROBE311_WIDTH = "1" *) 
  (* C_PROBE312_MU_CNT = "1" *) 
  (* C_PROBE312_TYPE = "1" *) 
  (* C_PROBE312_WIDTH = "1" *) 
  (* C_PROBE313_MU_CNT = "1" *) 
  (* C_PROBE313_TYPE = "1" *) 
  (* C_PROBE313_WIDTH = "1" *) 
  (* C_PROBE314_MU_CNT = "1" *) 
  (* C_PROBE314_TYPE = "1" *) 
  (* C_PROBE314_WIDTH = "1" *) 
  (* C_PROBE315_MU_CNT = "1" *) 
  (* C_PROBE315_TYPE = "1" *) 
  (* C_PROBE315_WIDTH = "1" *) 
  (* C_PROBE316_MU_CNT = "1" *) 
  (* C_PROBE316_TYPE = "1" *) 
  (* C_PROBE316_WIDTH = "1" *) 
  (* C_PROBE317_MU_CNT = "1" *) 
  (* C_PROBE317_TYPE = "1" *) 
  (* C_PROBE317_WIDTH = "1" *) 
  (* C_PROBE318_MU_CNT = "1" *) 
  (* C_PROBE318_TYPE = "1" *) 
  (* C_PROBE318_WIDTH = "1" *) 
  (* C_PROBE319_MU_CNT = "1" *) 
  (* C_PROBE319_TYPE = "1" *) 
  (* C_PROBE319_WIDTH = "1" *) 
  (* C_PROBE31_MU_CNT = "1" *) 
  (* C_PROBE31_TYPE = "1" *) 
  (* C_PROBE31_WIDTH = "1" *) 
  (* C_PROBE320_MU_CNT = "1" *) 
  (* C_PROBE320_TYPE = "1" *) 
  (* C_PROBE320_WIDTH = "1" *) 
  (* C_PROBE321_MU_CNT = "1" *) 
  (* C_PROBE321_TYPE = "1" *) 
  (* C_PROBE321_WIDTH = "1" *) 
  (* C_PROBE322_MU_CNT = "1" *) 
  (* C_PROBE322_TYPE = "1" *) 
  (* C_PROBE322_WIDTH = "1" *) 
  (* C_PROBE323_MU_CNT = "1" *) 
  (* C_PROBE323_TYPE = "1" *) 
  (* C_PROBE323_WIDTH = "1" *) 
  (* C_PROBE324_MU_CNT = "1" *) 
  (* C_PROBE324_TYPE = "1" *) 
  (* C_PROBE324_WIDTH = "1" *) 
  (* C_PROBE325_MU_CNT = "1" *) 
  (* C_PROBE325_TYPE = "1" *) 
  (* C_PROBE325_WIDTH = "1" *) 
  (* C_PROBE326_MU_CNT = "1" *) 
  (* C_PROBE326_TYPE = "1" *) 
  (* C_PROBE326_WIDTH = "1" *) 
  (* C_PROBE327_MU_CNT = "1" *) 
  (* C_PROBE327_TYPE = "1" *) 
  (* C_PROBE327_WIDTH = "1" *) 
  (* C_PROBE328_MU_CNT = "1" *) 
  (* C_PROBE328_TYPE = "1" *) 
  (* C_PROBE328_WIDTH = "1" *) 
  (* C_PROBE329_MU_CNT = "1" *) 
  (* C_PROBE329_TYPE = "1" *) 
  (* C_PROBE329_WIDTH = "1" *) 
  (* C_PROBE32_MU_CNT = "1" *) 
  (* C_PROBE32_TYPE = "1" *) 
  (* C_PROBE32_WIDTH = "1" *) 
  (* C_PROBE330_MU_CNT = "1" *) 
  (* C_PROBE330_TYPE = "1" *) 
  (* C_PROBE330_WIDTH = "1" *) 
  (* C_PROBE331_MU_CNT = "1" *) 
  (* C_PROBE331_TYPE = "1" *) 
  (* C_PROBE331_WIDTH = "1" *) 
  (* C_PROBE332_MU_CNT = "1" *) 
  (* C_PROBE332_TYPE = "1" *) 
  (* C_PROBE332_WIDTH = "1" *) 
  (* C_PROBE333_MU_CNT = "1" *) 
  (* C_PROBE333_TYPE = "1" *) 
  (* C_PROBE333_WIDTH = "1" *) 
  (* C_PROBE334_MU_CNT = "1" *) 
  (* C_PROBE334_TYPE = "1" *) 
  (* C_PROBE334_WIDTH = "1" *) 
  (* C_PROBE335_MU_CNT = "1" *) 
  (* C_PROBE335_TYPE = "1" *) 
  (* C_PROBE335_WIDTH = "1" *) 
  (* C_PROBE336_MU_CNT = "1" *) 
  (* C_PROBE336_TYPE = "1" *) 
  (* C_PROBE336_WIDTH = "1" *) 
  (* C_PROBE337_MU_CNT = "1" *) 
  (* C_PROBE337_TYPE = "1" *) 
  (* C_PROBE337_WIDTH = "1" *) 
  (* C_PROBE338_MU_CNT = "1" *) 
  (* C_PROBE338_TYPE = "1" *) 
  (* C_PROBE338_WIDTH = "1" *) 
  (* C_PROBE339_MU_CNT = "1" *) 
  (* C_PROBE339_TYPE = "1" *) 
  (* C_PROBE339_WIDTH = "1" *) 
  (* C_PROBE33_MU_CNT = "1" *) 
  (* C_PROBE33_TYPE = "1" *) 
  (* C_PROBE33_WIDTH = "1" *) 
  (* C_PROBE340_MU_CNT = "1" *) 
  (* C_PROBE340_TYPE = "1" *) 
  (* C_PROBE340_WIDTH = "1" *) 
  (* C_PROBE341_MU_CNT = "1" *) 
  (* C_PROBE341_TYPE = "1" *) 
  (* C_PROBE341_WIDTH = "1" *) 
  (* C_PROBE342_MU_CNT = "1" *) 
  (* C_PROBE342_TYPE = "1" *) 
  (* C_PROBE342_WIDTH = "1" *) 
  (* C_PROBE343_MU_CNT = "1" *) 
  (* C_PROBE343_TYPE = "1" *) 
  (* C_PROBE343_WIDTH = "1" *) 
  (* C_PROBE344_MU_CNT = "1" *) 
  (* C_PROBE344_TYPE = "1" *) 
  (* C_PROBE344_WIDTH = "1" *) 
  (* C_PROBE345_MU_CNT = "1" *) 
  (* C_PROBE345_TYPE = "1" *) 
  (* C_PROBE345_WIDTH = "1" *) 
  (* C_PROBE346_MU_CNT = "1" *) 
  (* C_PROBE346_TYPE = "1" *) 
  (* C_PROBE346_WIDTH = "1" *) 
  (* C_PROBE347_MU_CNT = "1" *) 
  (* C_PROBE347_TYPE = "1" *) 
  (* C_PROBE347_WIDTH = "1" *) 
  (* C_PROBE348_MU_CNT = "1" *) 
  (* C_PROBE348_TYPE = "1" *) 
  (* C_PROBE348_WIDTH = "1" *) 
  (* C_PROBE349_MU_CNT = "1" *) 
  (* C_PROBE349_TYPE = "1" *) 
  (* C_PROBE349_WIDTH = "1" *) 
  (* C_PROBE34_MU_CNT = "1" *) 
  (* C_PROBE34_TYPE = "1" *) 
  (* C_PROBE34_WIDTH = "1" *) 
  (* C_PROBE350_MU_CNT = "1" *) 
  (* C_PROBE350_TYPE = "1" *) 
  (* C_PROBE350_WIDTH = "1" *) 
  (* C_PROBE351_MU_CNT = "1" *) 
  (* C_PROBE351_TYPE = "1" *) 
  (* C_PROBE351_WIDTH = "1" *) 
  (* C_PROBE352_MU_CNT = "1" *) 
  (* C_PROBE352_TYPE = "1" *) 
  (* C_PROBE352_WIDTH = "1" *) 
  (* C_PROBE353_MU_CNT = "1" *) 
  (* C_PROBE353_TYPE = "1" *) 
  (* C_PROBE353_WIDTH = "1" *) 
  (* C_PROBE354_MU_CNT = "1" *) 
  (* C_PROBE354_TYPE = "1" *) 
  (* C_PROBE354_WIDTH = "1" *) 
  (* C_PROBE355_MU_CNT = "1" *) 
  (* C_PROBE355_TYPE = "1" *) 
  (* C_PROBE355_WIDTH = "1" *) 
  (* C_PROBE356_MU_CNT = "1" *) 
  (* C_PROBE356_TYPE = "1" *) 
  (* C_PROBE356_WIDTH = "1" *) 
  (* C_PROBE357_MU_CNT = "1" *) 
  (* C_PROBE357_TYPE = "1" *) 
  (* C_PROBE357_WIDTH = "1" *) 
  (* C_PROBE358_MU_CNT = "1" *) 
  (* C_PROBE358_TYPE = "1" *) 
  (* C_PROBE358_WIDTH = "1" *) 
  (* C_PROBE359_MU_CNT = "1" *) 
  (* C_PROBE359_TYPE = "1" *) 
  (* C_PROBE359_WIDTH = "1" *) 
  (* C_PROBE35_MU_CNT = "1" *) 
  (* C_PROBE35_TYPE = "1" *) 
  (* C_PROBE35_WIDTH = "1" *) 
  (* C_PROBE360_MU_CNT = "1" *) 
  (* C_PROBE360_TYPE = "1" *) 
  (* C_PROBE360_WIDTH = "1" *) 
  (* C_PROBE361_MU_CNT = "1" *) 
  (* C_PROBE361_TYPE = "1" *) 
  (* C_PROBE361_WIDTH = "1" *) 
  (* C_PROBE362_MU_CNT = "1" *) 
  (* C_PROBE362_TYPE = "1" *) 
  (* C_PROBE362_WIDTH = "1" *) 
  (* C_PROBE363_MU_CNT = "1" *) 
  (* C_PROBE363_TYPE = "1" *) 
  (* C_PROBE363_WIDTH = "1" *) 
  (* C_PROBE364_MU_CNT = "1" *) 
  (* C_PROBE364_TYPE = "1" *) 
  (* C_PROBE364_WIDTH = "1" *) 
  (* C_PROBE365_MU_CNT = "1" *) 
  (* C_PROBE365_TYPE = "1" *) 
  (* C_PROBE365_WIDTH = "1" *) 
  (* C_PROBE366_MU_CNT = "1" *) 
  (* C_PROBE366_TYPE = "1" *) 
  (* C_PROBE366_WIDTH = "1" *) 
  (* C_PROBE367_MU_CNT = "1" *) 
  (* C_PROBE367_TYPE = "1" *) 
  (* C_PROBE367_WIDTH = "1" *) 
  (* C_PROBE368_MU_CNT = "1" *) 
  (* C_PROBE368_TYPE = "1" *) 
  (* C_PROBE368_WIDTH = "1" *) 
  (* C_PROBE369_MU_CNT = "1" *) 
  (* C_PROBE369_TYPE = "1" *) 
  (* C_PROBE369_WIDTH = "1" *) 
  (* C_PROBE36_MU_CNT = "1" *) 
  (* C_PROBE36_TYPE = "1" *) 
  (* C_PROBE36_WIDTH = "1" *) 
  (* C_PROBE370_MU_CNT = "1" *) 
  (* C_PROBE370_TYPE = "1" *) 
  (* C_PROBE370_WIDTH = "1" *) 
  (* C_PROBE371_MU_CNT = "1" *) 
  (* C_PROBE371_TYPE = "1" *) 
  (* C_PROBE371_WIDTH = "1" *) 
  (* C_PROBE372_MU_CNT = "1" *) 
  (* C_PROBE372_TYPE = "1" *) 
  (* C_PROBE372_WIDTH = "1" *) 
  (* C_PROBE373_MU_CNT = "1" *) 
  (* C_PROBE373_TYPE = "1" *) 
  (* C_PROBE373_WIDTH = "1" *) 
  (* C_PROBE374_MU_CNT = "1" *) 
  (* C_PROBE374_TYPE = "1" *) 
  (* C_PROBE374_WIDTH = "1" *) 
  (* C_PROBE375_MU_CNT = "1" *) 
  (* C_PROBE375_TYPE = "1" *) 
  (* C_PROBE375_WIDTH = "1" *) 
  (* C_PROBE376_MU_CNT = "1" *) 
  (* C_PROBE376_TYPE = "1" *) 
  (* C_PROBE376_WIDTH = "1" *) 
  (* C_PROBE377_MU_CNT = "1" *) 
  (* C_PROBE377_TYPE = "1" *) 
  (* C_PROBE377_WIDTH = "1" *) 
  (* C_PROBE378_MU_CNT = "1" *) 
  (* C_PROBE378_TYPE = "1" *) 
  (* C_PROBE378_WIDTH = "1" *) 
  (* C_PROBE379_MU_CNT = "1" *) 
  (* C_PROBE379_TYPE = "1" *) 
  (* C_PROBE379_WIDTH = "1" *) 
  (* C_PROBE37_MU_CNT = "1" *) 
  (* C_PROBE37_TYPE = "1" *) 
  (* C_PROBE37_WIDTH = "1" *) 
  (* C_PROBE380_MU_CNT = "1" *) 
  (* C_PROBE380_TYPE = "1" *) 
  (* C_PROBE380_WIDTH = "1" *) 
  (* C_PROBE381_MU_CNT = "1" *) 
  (* C_PROBE381_TYPE = "1" *) 
  (* C_PROBE381_WIDTH = "1" *) 
  (* C_PROBE382_MU_CNT = "1" *) 
  (* C_PROBE382_TYPE = "1" *) 
  (* C_PROBE382_WIDTH = "1" *) 
  (* C_PROBE383_MU_CNT = "1" *) 
  (* C_PROBE383_TYPE = "1" *) 
  (* C_PROBE383_WIDTH = "1" *) 
  (* C_PROBE384_MU_CNT = "1" *) 
  (* C_PROBE384_TYPE = "1" *) 
  (* C_PROBE384_WIDTH = "1" *) 
  (* C_PROBE385_MU_CNT = "1" *) 
  (* C_PROBE385_TYPE = "1" *) 
  (* C_PROBE385_WIDTH = "1" *) 
  (* C_PROBE386_MU_CNT = "1" *) 
  (* C_PROBE386_TYPE = "1" *) 
  (* C_PROBE386_WIDTH = "1" *) 
  (* C_PROBE387_MU_CNT = "1" *) 
  (* C_PROBE387_TYPE = "1" *) 
  (* C_PROBE387_WIDTH = "1" *) 
  (* C_PROBE388_MU_CNT = "1" *) 
  (* C_PROBE388_TYPE = "1" *) 
  (* C_PROBE388_WIDTH = "1" *) 
  (* C_PROBE389_MU_CNT = "1" *) 
  (* C_PROBE389_TYPE = "1" *) 
  (* C_PROBE389_WIDTH = "1" *) 
  (* C_PROBE38_MU_CNT = "1" *) 
  (* C_PROBE38_TYPE = "1" *) 
  (* C_PROBE38_WIDTH = "1" *) 
  (* C_PROBE390_MU_CNT = "1" *) 
  (* C_PROBE390_TYPE = "1" *) 
  (* C_PROBE390_WIDTH = "1" *) 
  (* C_PROBE391_MU_CNT = "1" *) 
  (* C_PROBE391_TYPE = "1" *) 
  (* C_PROBE391_WIDTH = "1" *) 
  (* C_PROBE392_MU_CNT = "1" *) 
  (* C_PROBE392_TYPE = "1" *) 
  (* C_PROBE392_WIDTH = "1" *) 
  (* C_PROBE393_MU_CNT = "1" *) 
  (* C_PROBE393_TYPE = "1" *) 
  (* C_PROBE393_WIDTH = "1" *) 
  (* C_PROBE394_MU_CNT = "1" *) 
  (* C_PROBE394_TYPE = "1" *) 
  (* C_PROBE394_WIDTH = "1" *) 
  (* C_PROBE395_MU_CNT = "1" *) 
  (* C_PROBE395_TYPE = "1" *) 
  (* C_PROBE395_WIDTH = "1" *) 
  (* C_PROBE396_MU_CNT = "1" *) 
  (* C_PROBE396_TYPE = "1" *) 
  (* C_PROBE396_WIDTH = "1" *) 
  (* C_PROBE397_MU_CNT = "1" *) 
  (* C_PROBE397_TYPE = "1" *) 
  (* C_PROBE397_WIDTH = "1" *) 
  (* C_PROBE398_MU_CNT = "1" *) 
  (* C_PROBE398_TYPE = "1" *) 
  (* C_PROBE398_WIDTH = "1" *) 
  (* C_PROBE399_MU_CNT = "1" *) 
  (* C_PROBE399_TYPE = "1" *) 
  (* C_PROBE399_WIDTH = "1" *) 
  (* C_PROBE39_MU_CNT = "1" *) 
  (* C_PROBE39_TYPE = "1" *) 
  (* C_PROBE39_WIDTH = "1" *) 
  (* C_PROBE3_MU_CNT = "1" *) 
  (* C_PROBE3_TYPE = "1" *) 
  (* C_PROBE3_WIDTH = "1" *) 
  (* C_PROBE400_MU_CNT = "1" *) 
  (* C_PROBE400_TYPE = "1" *) 
  (* C_PROBE400_WIDTH = "1" *) 
  (* C_PROBE401_MU_CNT = "1" *) 
  (* C_PROBE401_TYPE = "1" *) 
  (* C_PROBE401_WIDTH = "1" *) 
  (* C_PROBE402_MU_CNT = "1" *) 
  (* C_PROBE402_TYPE = "1" *) 
  (* C_PROBE402_WIDTH = "1" *) 
  (* C_PROBE403_MU_CNT = "1" *) 
  (* C_PROBE403_TYPE = "1" *) 
  (* C_PROBE403_WIDTH = "1" *) 
  (* C_PROBE404_MU_CNT = "1" *) 
  (* C_PROBE404_TYPE = "1" *) 
  (* C_PROBE404_WIDTH = "1" *) 
  (* C_PROBE405_MU_CNT = "1" *) 
  (* C_PROBE405_TYPE = "1" *) 
  (* C_PROBE405_WIDTH = "1" *) 
  (* C_PROBE406_MU_CNT = "1" *) 
  (* C_PROBE406_TYPE = "1" *) 
  (* C_PROBE406_WIDTH = "1" *) 
  (* C_PROBE407_MU_CNT = "1" *) 
  (* C_PROBE407_TYPE = "1" *) 
  (* C_PROBE407_WIDTH = "1" *) 
  (* C_PROBE408_MU_CNT = "1" *) 
  (* C_PROBE408_TYPE = "1" *) 
  (* C_PROBE408_WIDTH = "1" *) 
  (* C_PROBE409_MU_CNT = "1" *) 
  (* C_PROBE409_TYPE = "1" *) 
  (* C_PROBE409_WIDTH = "1" *) 
  (* C_PROBE40_MU_CNT = "1" *) 
  (* C_PROBE40_TYPE = "1" *) 
  (* C_PROBE40_WIDTH = "1" *) 
  (* C_PROBE410_MU_CNT = "1" *) 
  (* C_PROBE410_TYPE = "1" *) 
  (* C_PROBE410_WIDTH = "1" *) 
  (* C_PROBE411_MU_CNT = "1" *) 
  (* C_PROBE411_TYPE = "1" *) 
  (* C_PROBE411_WIDTH = "1" *) 
  (* C_PROBE412_MU_CNT = "1" *) 
  (* C_PROBE412_TYPE = "1" *) 
  (* C_PROBE412_WIDTH = "1" *) 
  (* C_PROBE413_MU_CNT = "1" *) 
  (* C_PROBE413_TYPE = "1" *) 
  (* C_PROBE413_WIDTH = "1" *) 
  (* C_PROBE414_MU_CNT = "1" *) 
  (* C_PROBE414_TYPE = "1" *) 
  (* C_PROBE414_WIDTH = "1" *) 
  (* C_PROBE415_MU_CNT = "1" *) 
  (* C_PROBE415_TYPE = "1" *) 
  (* C_PROBE415_WIDTH = "1" *) 
  (* C_PROBE416_MU_CNT = "1" *) 
  (* C_PROBE416_TYPE = "1" *) 
  (* C_PROBE416_WIDTH = "1" *) 
  (* C_PROBE417_MU_CNT = "1" *) 
  (* C_PROBE417_TYPE = "1" *) 
  (* C_PROBE417_WIDTH = "1" *) 
  (* C_PROBE418_MU_CNT = "1" *) 
  (* C_PROBE418_TYPE = "1" *) 
  (* C_PROBE418_WIDTH = "1" *) 
  (* C_PROBE419_MU_CNT = "1" *) 
  (* C_PROBE419_TYPE = "1" *) 
  (* C_PROBE419_WIDTH = "1" *) 
  (* C_PROBE41_MU_CNT = "1" *) 
  (* C_PROBE41_TYPE = "1" *) 
  (* C_PROBE41_WIDTH = "1" *) 
  (* C_PROBE420_MU_CNT = "1" *) 
  (* C_PROBE420_TYPE = "1" *) 
  (* C_PROBE420_WIDTH = "1" *) 
  (* C_PROBE421_MU_CNT = "1" *) 
  (* C_PROBE421_TYPE = "1" *) 
  (* C_PROBE421_WIDTH = "1" *) 
  (* C_PROBE422_MU_CNT = "1" *) 
  (* C_PROBE422_TYPE = "1" *) 
  (* C_PROBE422_WIDTH = "1" *) 
  (* C_PROBE423_MU_CNT = "1" *) 
  (* C_PROBE423_TYPE = "1" *) 
  (* C_PROBE423_WIDTH = "1" *) 
  (* C_PROBE424_MU_CNT = "1" *) 
  (* C_PROBE424_TYPE = "1" *) 
  (* C_PROBE424_WIDTH = "1" *) 
  (* C_PROBE425_MU_CNT = "1" *) 
  (* C_PROBE425_TYPE = "1" *) 
  (* C_PROBE425_WIDTH = "1" *) 
  (* C_PROBE426_MU_CNT = "1" *) 
  (* C_PROBE426_TYPE = "1" *) 
  (* C_PROBE426_WIDTH = "1" *) 
  (* C_PROBE427_MU_CNT = "1" *) 
  (* C_PROBE427_TYPE = "1" *) 
  (* C_PROBE427_WIDTH = "1" *) 
  (* C_PROBE428_MU_CNT = "1" *) 
  (* C_PROBE428_TYPE = "1" *) 
  (* C_PROBE428_WIDTH = "1" *) 
  (* C_PROBE429_MU_CNT = "1" *) 
  (* C_PROBE429_TYPE = "1" *) 
  (* C_PROBE429_WIDTH = "1" *) 
  (* C_PROBE42_MU_CNT = "1" *) 
  (* C_PROBE42_TYPE = "1" *) 
  (* C_PROBE42_WIDTH = "1" *) 
  (* C_PROBE430_MU_CNT = "1" *) 
  (* C_PROBE430_TYPE = "1" *) 
  (* C_PROBE430_WIDTH = "1" *) 
  (* C_PROBE431_MU_CNT = "1" *) 
  (* C_PROBE431_TYPE = "1" *) 
  (* C_PROBE431_WIDTH = "1" *) 
  (* C_PROBE432_MU_CNT = "1" *) 
  (* C_PROBE432_TYPE = "1" *) 
  (* C_PROBE432_WIDTH = "1" *) 
  (* C_PROBE433_MU_CNT = "1" *) 
  (* C_PROBE433_TYPE = "1" *) 
  (* C_PROBE433_WIDTH = "1" *) 
  (* C_PROBE434_MU_CNT = "1" *) 
  (* C_PROBE434_TYPE = "1" *) 
  (* C_PROBE434_WIDTH = "1" *) 
  (* C_PROBE435_MU_CNT = "1" *) 
  (* C_PROBE435_TYPE = "1" *) 
  (* C_PROBE435_WIDTH = "1" *) 
  (* C_PROBE436_MU_CNT = "1" *) 
  (* C_PROBE436_TYPE = "1" *) 
  (* C_PROBE436_WIDTH = "1" *) 
  (* C_PROBE437_MU_CNT = "1" *) 
  (* C_PROBE437_TYPE = "1" *) 
  (* C_PROBE437_WIDTH = "1" *) 
  (* C_PROBE438_MU_CNT = "1" *) 
  (* C_PROBE438_TYPE = "1" *) 
  (* C_PROBE438_WIDTH = "1" *) 
  (* C_PROBE439_MU_CNT = "1" *) 
  (* C_PROBE439_TYPE = "1" *) 
  (* C_PROBE439_WIDTH = "1" *) 
  (* C_PROBE43_MU_CNT = "1" *) 
  (* C_PROBE43_TYPE = "1" *) 
  (* C_PROBE43_WIDTH = "1" *) 
  (* C_PROBE440_MU_CNT = "1" *) 
  (* C_PROBE440_TYPE = "1" *) 
  (* C_PROBE440_WIDTH = "1" *) 
  (* C_PROBE441_MU_CNT = "1" *) 
  (* C_PROBE441_TYPE = "1" *) 
  (* C_PROBE441_WIDTH = "1" *) 
  (* C_PROBE442_MU_CNT = "1" *) 
  (* C_PROBE442_TYPE = "1" *) 
  (* C_PROBE442_WIDTH = "1" *) 
  (* C_PROBE443_MU_CNT = "1" *) 
  (* C_PROBE443_TYPE = "1" *) 
  (* C_PROBE443_WIDTH = "1" *) 
  (* C_PROBE444_MU_CNT = "1" *) 
  (* C_PROBE444_TYPE = "1" *) 
  (* C_PROBE444_WIDTH = "1" *) 
  (* C_PROBE445_MU_CNT = "1" *) 
  (* C_PROBE445_TYPE = "1" *) 
  (* C_PROBE445_WIDTH = "1" *) 
  (* C_PROBE446_MU_CNT = "1" *) 
  (* C_PROBE446_TYPE = "1" *) 
  (* C_PROBE446_WIDTH = "1" *) 
  (* C_PROBE447_MU_CNT = "1" *) 
  (* C_PROBE447_TYPE = "1" *) 
  (* C_PROBE447_WIDTH = "1" *) 
  (* C_PROBE448_MU_CNT = "1" *) 
  (* C_PROBE448_TYPE = "1" *) 
  (* C_PROBE448_WIDTH = "1" *) 
  (* C_PROBE449_MU_CNT = "1" *) 
  (* C_PROBE449_TYPE = "1" *) 
  (* C_PROBE449_WIDTH = "1" *) 
  (* C_PROBE44_MU_CNT = "1" *) 
  (* C_PROBE44_TYPE = "1" *) 
  (* C_PROBE44_WIDTH = "1" *) 
  (* C_PROBE450_MU_CNT = "1" *) 
  (* C_PROBE450_TYPE = "1" *) 
  (* C_PROBE450_WIDTH = "1" *) 
  (* C_PROBE451_MU_CNT = "1" *) 
  (* C_PROBE451_TYPE = "1" *) 
  (* C_PROBE451_WIDTH = "1" *) 
  (* C_PROBE452_MU_CNT = "1" *) 
  (* C_PROBE452_TYPE = "1" *) 
  (* C_PROBE452_WIDTH = "1" *) 
  (* C_PROBE453_MU_CNT = "1" *) 
  (* C_PROBE453_TYPE = "1" *) 
  (* C_PROBE453_WIDTH = "1" *) 
  (* C_PROBE454_MU_CNT = "1" *) 
  (* C_PROBE454_TYPE = "1" *) 
  (* C_PROBE454_WIDTH = "1" *) 
  (* C_PROBE455_MU_CNT = "1" *) 
  (* C_PROBE455_TYPE = "1" *) 
  (* C_PROBE455_WIDTH = "1" *) 
  (* C_PROBE456_MU_CNT = "1" *) 
  (* C_PROBE456_TYPE = "1" *) 
  (* C_PROBE456_WIDTH = "1" *) 
  (* C_PROBE457_MU_CNT = "1" *) 
  (* C_PROBE457_TYPE = "1" *) 
  (* C_PROBE457_WIDTH = "1" *) 
  (* C_PROBE458_MU_CNT = "1" *) 
  (* C_PROBE458_TYPE = "1" *) 
  (* C_PROBE458_WIDTH = "1" *) 
  (* C_PROBE459_MU_CNT = "1" *) 
  (* C_PROBE459_TYPE = "1" *) 
  (* C_PROBE459_WIDTH = "1" *) 
  (* C_PROBE45_MU_CNT = "1" *) 
  (* C_PROBE45_TYPE = "1" *) 
  (* C_PROBE45_WIDTH = "1" *) 
  (* C_PROBE460_MU_CNT = "1" *) 
  (* C_PROBE460_TYPE = "1" *) 
  (* C_PROBE460_WIDTH = "1" *) 
  (* C_PROBE461_MU_CNT = "1" *) 
  (* C_PROBE461_TYPE = "1" *) 
  (* C_PROBE461_WIDTH = "1" *) 
  (* C_PROBE462_MU_CNT = "1" *) 
  (* C_PROBE462_TYPE = "1" *) 
  (* C_PROBE462_WIDTH = "1" *) 
  (* C_PROBE463_MU_CNT = "1" *) 
  (* C_PROBE463_TYPE = "1" *) 
  (* C_PROBE463_WIDTH = "1" *) 
  (* C_PROBE464_MU_CNT = "1" *) 
  (* C_PROBE464_TYPE = "1" *) 
  (* C_PROBE464_WIDTH = "1" *) 
  (* C_PROBE465_MU_CNT = "1" *) 
  (* C_PROBE465_TYPE = "1" *) 
  (* C_PROBE465_WIDTH = "1" *) 
  (* C_PROBE466_MU_CNT = "1" *) 
  (* C_PROBE466_TYPE = "1" *) 
  (* C_PROBE466_WIDTH = "1" *) 
  (* C_PROBE467_MU_CNT = "1" *) 
  (* C_PROBE467_TYPE = "1" *) 
  (* C_PROBE467_WIDTH = "1" *) 
  (* C_PROBE468_MU_CNT = "1" *) 
  (* C_PROBE468_TYPE = "1" *) 
  (* C_PROBE468_WIDTH = "1" *) 
  (* C_PROBE469_MU_CNT = "1" *) 
  (* C_PROBE469_TYPE = "1" *) 
  (* C_PROBE469_WIDTH = "1" *) 
  (* C_PROBE46_MU_CNT = "1" *) 
  (* C_PROBE46_TYPE = "1" *) 
  (* C_PROBE46_WIDTH = "1" *) 
  (* C_PROBE470_MU_CNT = "1" *) 
  (* C_PROBE470_TYPE = "1" *) 
  (* C_PROBE470_WIDTH = "1" *) 
  (* C_PROBE471_MU_CNT = "1" *) 
  (* C_PROBE471_TYPE = "1" *) 
  (* C_PROBE471_WIDTH = "1" *) 
  (* C_PROBE472_MU_CNT = "1" *) 
  (* C_PROBE472_TYPE = "1" *) 
  (* C_PROBE472_WIDTH = "1" *) 
  (* C_PROBE473_MU_CNT = "1" *) 
  (* C_PROBE473_TYPE = "1" *) 
  (* C_PROBE473_WIDTH = "1" *) 
  (* C_PROBE474_MU_CNT = "1" *) 
  (* C_PROBE474_TYPE = "1" *) 
  (* C_PROBE474_WIDTH = "1" *) 
  (* C_PROBE475_MU_CNT = "1" *) 
  (* C_PROBE475_TYPE = "1" *) 
  (* C_PROBE475_WIDTH = "1" *) 
  (* C_PROBE476_MU_CNT = "1" *) 
  (* C_PROBE476_TYPE = "1" *) 
  (* C_PROBE476_WIDTH = "1" *) 
  (* C_PROBE477_MU_CNT = "1" *) 
  (* C_PROBE477_TYPE = "1" *) 
  (* C_PROBE477_WIDTH = "1" *) 
  (* C_PROBE478_MU_CNT = "1" *) 
  (* C_PROBE478_TYPE = "1" *) 
  (* C_PROBE478_WIDTH = "1" *) 
  (* C_PROBE479_MU_CNT = "1" *) 
  (* C_PROBE479_TYPE = "1" *) 
  (* C_PROBE479_WIDTH = "1" *) 
  (* C_PROBE47_MU_CNT = "1" *) 
  (* C_PROBE47_TYPE = "1" *) 
  (* C_PROBE47_WIDTH = "1" *) 
  (* C_PROBE480_MU_CNT = "1" *) 
  (* C_PROBE480_TYPE = "1" *) 
  (* C_PROBE480_WIDTH = "1" *) 
  (* C_PROBE481_MU_CNT = "1" *) 
  (* C_PROBE481_TYPE = "1" *) 
  (* C_PROBE481_WIDTH = "1" *) 
  (* C_PROBE482_MU_CNT = "1" *) 
  (* C_PROBE482_TYPE = "1" *) 
  (* C_PROBE482_WIDTH = "1" *) 
  (* C_PROBE483_MU_CNT = "1" *) 
  (* C_PROBE483_TYPE = "1" *) 
  (* C_PROBE483_WIDTH = "1" *) 
  (* C_PROBE484_MU_CNT = "1" *) 
  (* C_PROBE484_TYPE = "1" *) 
  (* C_PROBE484_WIDTH = "1" *) 
  (* C_PROBE485_MU_CNT = "1" *) 
  (* C_PROBE485_TYPE = "1" *) 
  (* C_PROBE485_WIDTH = "1" *) 
  (* C_PROBE486_MU_CNT = "1" *) 
  (* C_PROBE486_TYPE = "1" *) 
  (* C_PROBE486_WIDTH = "1" *) 
  (* C_PROBE487_MU_CNT = "1" *) 
  (* C_PROBE487_TYPE = "1" *) 
  (* C_PROBE487_WIDTH = "1" *) 
  (* C_PROBE488_MU_CNT = "1" *) 
  (* C_PROBE488_TYPE = "1" *) 
  (* C_PROBE488_WIDTH = "1" *) 
  (* C_PROBE489_MU_CNT = "1" *) 
  (* C_PROBE489_TYPE = "1" *) 
  (* C_PROBE489_WIDTH = "1" *) 
  (* C_PROBE48_MU_CNT = "1" *) 
  (* C_PROBE48_TYPE = "1" *) 
  (* C_PROBE48_WIDTH = "1" *) 
  (* C_PROBE490_MU_CNT = "1" *) 
  (* C_PROBE490_TYPE = "1" *) 
  (* C_PROBE490_WIDTH = "1" *) 
  (* C_PROBE491_MU_CNT = "1" *) 
  (* C_PROBE491_TYPE = "1" *) 
  (* C_PROBE491_WIDTH = "1" *) 
  (* C_PROBE492_MU_CNT = "1" *) 
  (* C_PROBE492_TYPE = "1" *) 
  (* C_PROBE492_WIDTH = "1" *) 
  (* C_PROBE493_MU_CNT = "1" *) 
  (* C_PROBE493_TYPE = "1" *) 
  (* C_PROBE493_WIDTH = "1" *) 
  (* C_PROBE494_MU_CNT = "1" *) 
  (* C_PROBE494_TYPE = "1" *) 
  (* C_PROBE494_WIDTH = "1" *) 
  (* C_PROBE495_MU_CNT = "1" *) 
  (* C_PROBE495_TYPE = "1" *) 
  (* C_PROBE495_WIDTH = "1" *) 
  (* C_PROBE496_MU_CNT = "1" *) 
  (* C_PROBE496_TYPE = "1" *) 
  (* C_PROBE496_WIDTH = "1" *) 
  (* C_PROBE497_MU_CNT = "1" *) 
  (* C_PROBE497_TYPE = "1" *) 
  (* C_PROBE497_WIDTH = "1" *) 
  (* C_PROBE498_MU_CNT = "1" *) 
  (* C_PROBE498_TYPE = "1" *) 
  (* C_PROBE498_WIDTH = "1" *) 
  (* C_PROBE499_MU_CNT = "1" *) 
  (* C_PROBE499_TYPE = "1" *) 
  (* C_PROBE499_WIDTH = "1" *) 
  (* C_PROBE49_MU_CNT = "1" *) 
  (* C_PROBE49_TYPE = "1" *) 
  (* C_PROBE49_WIDTH = "1" *) 
  (* C_PROBE4_MU_CNT = "1" *) 
  (* C_PROBE4_TYPE = "1" *) 
  (* C_PROBE4_WIDTH = "1" *) 
  (* C_PROBE500_MU_CNT = "1" *) 
  (* C_PROBE500_TYPE = "1" *) 
  (* C_PROBE500_WIDTH = "1" *) 
  (* C_PROBE501_MU_CNT = "1" *) 
  (* C_PROBE501_TYPE = "1" *) 
  (* C_PROBE501_WIDTH = "1" *) 
  (* C_PROBE502_MU_CNT = "1" *) 
  (* C_PROBE502_TYPE = "1" *) 
  (* C_PROBE502_WIDTH = "1" *) 
  (* C_PROBE503_MU_CNT = "1" *) 
  (* C_PROBE503_TYPE = "1" *) 
  (* C_PROBE503_WIDTH = "1" *) 
  (* C_PROBE504_MU_CNT = "1" *) 
  (* C_PROBE504_TYPE = "1" *) 
  (* C_PROBE504_WIDTH = "1" *) 
  (* C_PROBE505_MU_CNT = "1" *) 
  (* C_PROBE505_TYPE = "1" *) 
  (* C_PROBE505_WIDTH = "1" *) 
  (* C_PROBE506_MU_CNT = "1" *) 
  (* C_PROBE506_TYPE = "1" *) 
  (* C_PROBE506_WIDTH = "1" *) 
  (* C_PROBE507_MU_CNT = "1" *) 
  (* C_PROBE507_TYPE = "1" *) 
  (* C_PROBE507_WIDTH = "1" *) 
  (* C_PROBE508_MU_CNT = "1" *) 
  (* C_PROBE508_TYPE = "1" *) 
  (* C_PROBE508_WIDTH = "1" *) 
  (* C_PROBE509_MU_CNT = "1" *) 
  (* C_PROBE509_TYPE = "1" *) 
  (* C_PROBE509_WIDTH = "1" *) 
  (* C_PROBE50_MU_CNT = "1" *) 
  (* C_PROBE50_TYPE = "1" *) 
  (* C_PROBE50_WIDTH = "1" *) 
  (* C_PROBE510_MU_CNT = "1" *) 
  (* C_PROBE510_TYPE = "1" *) 
  (* C_PROBE510_WIDTH = "1" *) 
  (* C_PROBE511_MU_CNT = "1" *) 
  (* C_PROBE511_TYPE = "1" *) 
  (* C_PROBE511_WIDTH = "1" *) 
  (* C_PROBE512_MU_CNT = "1" *) 
  (* C_PROBE512_TYPE = "1" *) 
  (* C_PROBE512_WIDTH = "1" *) 
  (* C_PROBE513_MU_CNT = "1" *) 
  (* C_PROBE513_TYPE = "1" *) 
  (* C_PROBE513_WIDTH = "1" *) 
  (* C_PROBE514_MU_CNT = "1" *) 
  (* C_PROBE514_TYPE = "1" *) 
  (* C_PROBE514_WIDTH = "1" *) 
  (* C_PROBE515_MU_CNT = "1" *) 
  (* C_PROBE515_TYPE = "1" *) 
  (* C_PROBE515_WIDTH = "1" *) 
  (* C_PROBE516_MU_CNT = "1" *) 
  (* C_PROBE516_TYPE = "1" *) 
  (* C_PROBE516_WIDTH = "1" *) 
  (* C_PROBE517_MU_CNT = "1" *) 
  (* C_PROBE517_TYPE = "1" *) 
  (* C_PROBE517_WIDTH = "1" *) 
  (* C_PROBE518_MU_CNT = "1" *) 
  (* C_PROBE518_TYPE = "1" *) 
  (* C_PROBE518_WIDTH = "1" *) 
  (* C_PROBE519_MU_CNT = "1" *) 
  (* C_PROBE519_TYPE = "1" *) 
  (* C_PROBE519_WIDTH = "1" *) 
  (* C_PROBE51_MU_CNT = "1" *) 
  (* C_PROBE51_TYPE = "1" *) 
  (* C_PROBE51_WIDTH = "1" *) 
  (* C_PROBE520_MU_CNT = "1" *) 
  (* C_PROBE520_TYPE = "1" *) 
  (* C_PROBE520_WIDTH = "1" *) 
  (* C_PROBE521_MU_CNT = "1" *) 
  (* C_PROBE521_TYPE = "1" *) 
  (* C_PROBE521_WIDTH = "1" *) 
  (* C_PROBE522_MU_CNT = "1" *) 
  (* C_PROBE522_TYPE = "1" *) 
  (* C_PROBE522_WIDTH = "1" *) 
  (* C_PROBE523_MU_CNT = "1" *) 
  (* C_PROBE523_TYPE = "1" *) 
  (* C_PROBE523_WIDTH = "1" *) 
  (* C_PROBE524_MU_CNT = "1" *) 
  (* C_PROBE524_TYPE = "1" *) 
  (* C_PROBE524_WIDTH = "1" *) 
  (* C_PROBE525_MU_CNT = "1" *) 
  (* C_PROBE525_TYPE = "1" *) 
  (* C_PROBE525_WIDTH = "1" *) 
  (* C_PROBE526_MU_CNT = "1" *) 
  (* C_PROBE526_TYPE = "1" *) 
  (* C_PROBE526_WIDTH = "1" *) 
  (* C_PROBE527_MU_CNT = "1" *) 
  (* C_PROBE527_TYPE = "1" *) 
  (* C_PROBE527_WIDTH = "1" *) 
  (* C_PROBE528_MU_CNT = "1" *) 
  (* C_PROBE528_TYPE = "1" *) 
  (* C_PROBE528_WIDTH = "1" *) 
  (* C_PROBE529_MU_CNT = "1" *) 
  (* C_PROBE529_TYPE = "1" *) 
  (* C_PROBE529_WIDTH = "1" *) 
  (* C_PROBE52_MU_CNT = "1" *) 
  (* C_PROBE52_TYPE = "1" *) 
  (* C_PROBE52_WIDTH = "1" *) 
  (* C_PROBE530_MU_CNT = "1" *) 
  (* C_PROBE530_TYPE = "1" *) 
  (* C_PROBE530_WIDTH = "1" *) 
  (* C_PROBE531_MU_CNT = "1" *) 
  (* C_PROBE531_TYPE = "1" *) 
  (* C_PROBE531_WIDTH = "1" *) 
  (* C_PROBE532_MU_CNT = "1" *) 
  (* C_PROBE532_TYPE = "1" *) 
  (* C_PROBE532_WIDTH = "1" *) 
  (* C_PROBE533_MU_CNT = "1" *) 
  (* C_PROBE533_TYPE = "1" *) 
  (* C_PROBE533_WIDTH = "1" *) 
  (* C_PROBE534_MU_CNT = "1" *) 
  (* C_PROBE534_TYPE = "1" *) 
  (* C_PROBE534_WIDTH = "1" *) 
  (* C_PROBE535_MU_CNT = "1" *) 
  (* C_PROBE535_TYPE = "1" *) 
  (* C_PROBE535_WIDTH = "1" *) 
  (* C_PROBE536_MU_CNT = "1" *) 
  (* C_PROBE536_TYPE = "1" *) 
  (* C_PROBE536_WIDTH = "1" *) 
  (* C_PROBE537_MU_CNT = "1" *) 
  (* C_PROBE537_TYPE = "1" *) 
  (* C_PROBE537_WIDTH = "1" *) 
  (* C_PROBE538_MU_CNT = "1" *) 
  (* C_PROBE538_TYPE = "1" *) 
  (* C_PROBE538_WIDTH = "1" *) 
  (* C_PROBE539_MU_CNT = "1" *) 
  (* C_PROBE539_TYPE = "1" *) 
  (* C_PROBE539_WIDTH = "1" *) 
  (* C_PROBE53_MU_CNT = "1" *) 
  (* C_PROBE53_TYPE = "1" *) 
  (* C_PROBE53_WIDTH = "1" *) 
  (* C_PROBE540_MU_CNT = "1" *) 
  (* C_PROBE540_TYPE = "1" *) 
  (* C_PROBE540_WIDTH = "1" *) 
  (* C_PROBE541_MU_CNT = "1" *) 
  (* C_PROBE541_TYPE = "1" *) 
  (* C_PROBE541_WIDTH = "1" *) 
  (* C_PROBE542_MU_CNT = "1" *) 
  (* C_PROBE542_TYPE = "1" *) 
  (* C_PROBE542_WIDTH = "1" *) 
  (* C_PROBE543_MU_CNT = "1" *) 
  (* C_PROBE543_TYPE = "1" *) 
  (* C_PROBE543_WIDTH = "1" *) 
  (* C_PROBE544_MU_CNT = "1" *) 
  (* C_PROBE544_TYPE = "1" *) 
  (* C_PROBE544_WIDTH = "1" *) 
  (* C_PROBE545_MU_CNT = "1" *) 
  (* C_PROBE545_TYPE = "1" *) 
  (* C_PROBE545_WIDTH = "1" *) 
  (* C_PROBE546_MU_CNT = "1" *) 
  (* C_PROBE546_TYPE = "1" *) 
  (* C_PROBE546_WIDTH = "1" *) 
  (* C_PROBE547_MU_CNT = "1" *) 
  (* C_PROBE547_TYPE = "1" *) 
  (* C_PROBE547_WIDTH = "1" *) 
  (* C_PROBE548_MU_CNT = "1" *) 
  (* C_PROBE548_TYPE = "1" *) 
  (* C_PROBE548_WIDTH = "1" *) 
  (* C_PROBE549_MU_CNT = "1" *) 
  (* C_PROBE549_TYPE = "1" *) 
  (* C_PROBE549_WIDTH = "1" *) 
  (* C_PROBE54_MU_CNT = "1" *) 
  (* C_PROBE54_TYPE = "1" *) 
  (* C_PROBE54_WIDTH = "1" *) 
  (* C_PROBE550_MU_CNT = "1" *) 
  (* C_PROBE550_TYPE = "1" *) 
  (* C_PROBE550_WIDTH = "1" *) 
  (* C_PROBE551_MU_CNT = "1" *) 
  (* C_PROBE551_TYPE = "1" *) 
  (* C_PROBE551_WIDTH = "1" *) 
  (* C_PROBE552_MU_CNT = "1" *) 
  (* C_PROBE552_TYPE = "1" *) 
  (* C_PROBE552_WIDTH = "1" *) 
  (* C_PROBE553_MU_CNT = "1" *) 
  (* C_PROBE553_TYPE = "1" *) 
  (* C_PROBE553_WIDTH = "1" *) 
  (* C_PROBE554_MU_CNT = "1" *) 
  (* C_PROBE554_TYPE = "1" *) 
  (* C_PROBE554_WIDTH = "1" *) 
  (* C_PROBE555_MU_CNT = "1" *) 
  (* C_PROBE555_TYPE = "1" *) 
  (* C_PROBE555_WIDTH = "1" *) 
  (* C_PROBE556_MU_CNT = "1" *) 
  (* C_PROBE556_TYPE = "1" *) 
  (* C_PROBE556_WIDTH = "1" *) 
  (* C_PROBE557_MU_CNT = "1" *) 
  (* C_PROBE557_TYPE = "1" *) 
  (* C_PROBE557_WIDTH = "1" *) 
  (* C_PROBE558_MU_CNT = "1" *) 
  (* C_PROBE558_TYPE = "1" *) 
  (* C_PROBE558_WIDTH = "1" *) 
  (* C_PROBE559_MU_CNT = "1" *) 
  (* C_PROBE559_TYPE = "1" *) 
  (* C_PROBE559_WIDTH = "1" *) 
  (* C_PROBE55_MU_CNT = "1" *) 
  (* C_PROBE55_TYPE = "1" *) 
  (* C_PROBE55_WIDTH = "1" *) 
  (* C_PROBE560_MU_CNT = "1" *) 
  (* C_PROBE560_TYPE = "1" *) 
  (* C_PROBE560_WIDTH = "1" *) 
  (* C_PROBE561_MU_CNT = "1" *) 
  (* C_PROBE561_TYPE = "1" *) 
  (* C_PROBE561_WIDTH = "1" *) 
  (* C_PROBE562_MU_CNT = "1" *) 
  (* C_PROBE562_TYPE = "1" *) 
  (* C_PROBE562_WIDTH = "1" *) 
  (* C_PROBE563_MU_CNT = "1" *) 
  (* C_PROBE563_TYPE = "1" *) 
  (* C_PROBE563_WIDTH = "1" *) 
  (* C_PROBE564_MU_CNT = "1" *) 
  (* C_PROBE564_TYPE = "1" *) 
  (* C_PROBE564_WIDTH = "1" *) 
  (* C_PROBE565_MU_CNT = "1" *) 
  (* C_PROBE565_TYPE = "1" *) 
  (* C_PROBE565_WIDTH = "1" *) 
  (* C_PROBE566_MU_CNT = "1" *) 
  (* C_PROBE566_TYPE = "1" *) 
  (* C_PROBE566_WIDTH = "1" *) 
  (* C_PROBE567_MU_CNT = "1" *) 
  (* C_PROBE567_TYPE = "1" *) 
  (* C_PROBE567_WIDTH = "1" *) 
  (* C_PROBE568_MU_CNT = "1" *) 
  (* C_PROBE568_TYPE = "1" *) 
  (* C_PROBE568_WIDTH = "1" *) 
  (* C_PROBE569_MU_CNT = "1" *) 
  (* C_PROBE569_TYPE = "1" *) 
  (* C_PROBE569_WIDTH = "1" *) 
  (* C_PROBE56_MU_CNT = "1" *) 
  (* C_PROBE56_TYPE = "1" *) 
  (* C_PROBE56_WIDTH = "1" *) 
  (* C_PROBE570_MU_CNT = "1" *) 
  (* C_PROBE570_TYPE = "1" *) 
  (* C_PROBE570_WIDTH = "1" *) 
  (* C_PROBE571_MU_CNT = "1" *) 
  (* C_PROBE571_TYPE = "1" *) 
  (* C_PROBE571_WIDTH = "1" *) 
  (* C_PROBE572_MU_CNT = "1" *) 
  (* C_PROBE572_TYPE = "1" *) 
  (* C_PROBE572_WIDTH = "1" *) 
  (* C_PROBE573_MU_CNT = "1" *) 
  (* C_PROBE573_TYPE = "1" *) 
  (* C_PROBE573_WIDTH = "1" *) 
  (* C_PROBE574_MU_CNT = "1" *) 
  (* C_PROBE574_TYPE = "1" *) 
  (* C_PROBE574_WIDTH = "1" *) 
  (* C_PROBE575_MU_CNT = "1" *) 
  (* C_PROBE575_TYPE = "1" *) 
  (* C_PROBE575_WIDTH = "1" *) 
  (* C_PROBE576_MU_CNT = "1" *) 
  (* C_PROBE576_TYPE = "1" *) 
  (* C_PROBE576_WIDTH = "1" *) 
  (* C_PROBE577_MU_CNT = "1" *) 
  (* C_PROBE577_TYPE = "1" *) 
  (* C_PROBE577_WIDTH = "1" *) 
  (* C_PROBE578_MU_CNT = "1" *) 
  (* C_PROBE578_TYPE = "1" *) 
  (* C_PROBE578_WIDTH = "1" *) 
  (* C_PROBE579_MU_CNT = "1" *) 
  (* C_PROBE579_TYPE = "1" *) 
  (* C_PROBE579_WIDTH = "1" *) 
  (* C_PROBE57_MU_CNT = "1" *) 
  (* C_PROBE57_TYPE = "1" *) 
  (* C_PROBE57_WIDTH = "1" *) 
  (* C_PROBE580_MU_CNT = "1" *) 
  (* C_PROBE580_TYPE = "1" *) 
  (* C_PROBE580_WIDTH = "1" *) 
  (* C_PROBE581_MU_CNT = "1" *) 
  (* C_PROBE581_TYPE = "1" *) 
  (* C_PROBE581_WIDTH = "1" *) 
  (* C_PROBE582_MU_CNT = "1" *) 
  (* C_PROBE582_TYPE = "1" *) 
  (* C_PROBE582_WIDTH = "1" *) 
  (* C_PROBE583_MU_CNT = "1" *) 
  (* C_PROBE583_TYPE = "1" *) 
  (* C_PROBE583_WIDTH = "1" *) 
  (* C_PROBE584_MU_CNT = "1" *) 
  (* C_PROBE584_TYPE = "1" *) 
  (* C_PROBE584_WIDTH = "1" *) 
  (* C_PROBE585_MU_CNT = "1" *) 
  (* C_PROBE585_TYPE = "1" *) 
  (* C_PROBE585_WIDTH = "1" *) 
  (* C_PROBE586_MU_CNT = "1" *) 
  (* C_PROBE586_TYPE = "1" *) 
  (* C_PROBE586_WIDTH = "1" *) 
  (* C_PROBE587_MU_CNT = "1" *) 
  (* C_PROBE587_TYPE = "1" *) 
  (* C_PROBE587_WIDTH = "1" *) 
  (* C_PROBE588_MU_CNT = "1" *) 
  (* C_PROBE588_TYPE = "1" *) 
  (* C_PROBE588_WIDTH = "1" *) 
  (* C_PROBE589_MU_CNT = "1" *) 
  (* C_PROBE589_TYPE = "1" *) 
  (* C_PROBE589_WIDTH = "1" *) 
  (* C_PROBE58_MU_CNT = "1" *) 
  (* C_PROBE58_TYPE = "1" *) 
  (* C_PROBE58_WIDTH = "1" *) 
  (* C_PROBE590_MU_CNT = "1" *) 
  (* C_PROBE590_TYPE = "1" *) 
  (* C_PROBE590_WIDTH = "1" *) 
  (* C_PROBE591_MU_CNT = "1" *) 
  (* C_PROBE591_TYPE = "1" *) 
  (* C_PROBE591_WIDTH = "1" *) 
  (* C_PROBE592_MU_CNT = "1" *) 
  (* C_PROBE592_TYPE = "1" *) 
  (* C_PROBE592_WIDTH = "1" *) 
  (* C_PROBE593_MU_CNT = "1" *) 
  (* C_PROBE593_TYPE = "1" *) 
  (* C_PROBE593_WIDTH = "1" *) 
  (* C_PROBE594_MU_CNT = "1" *) 
  (* C_PROBE594_TYPE = "1" *) 
  (* C_PROBE594_WIDTH = "1" *) 
  (* C_PROBE595_MU_CNT = "1" *) 
  (* C_PROBE595_TYPE = "1" *) 
  (* C_PROBE595_WIDTH = "1" *) 
  (* C_PROBE596_MU_CNT = "1" *) 
  (* C_PROBE596_TYPE = "1" *) 
  (* C_PROBE596_WIDTH = "1" *) 
  (* C_PROBE597_MU_CNT = "1" *) 
  (* C_PROBE597_TYPE = "1" *) 
  (* C_PROBE597_WIDTH = "1" *) 
  (* C_PROBE598_MU_CNT = "1" *) 
  (* C_PROBE598_TYPE = "1" *) 
  (* C_PROBE598_WIDTH = "1" *) 
  (* C_PROBE599_MU_CNT = "1" *) 
  (* C_PROBE599_TYPE = "1" *) 
  (* C_PROBE599_WIDTH = "1" *) 
  (* C_PROBE59_MU_CNT = "1" *) 
  (* C_PROBE59_TYPE = "1" *) 
  (* C_PROBE59_WIDTH = "1" *) 
  (* C_PROBE5_MU_CNT = "1" *) 
  (* C_PROBE5_TYPE = "1" *) 
  (* C_PROBE5_WIDTH = "1" *) 
  (* C_PROBE600_MU_CNT = "1" *) 
  (* C_PROBE600_TYPE = "1" *) 
  (* C_PROBE600_WIDTH = "1" *) 
  (* C_PROBE601_MU_CNT = "1" *) 
  (* C_PROBE601_TYPE = "1" *) 
  (* C_PROBE601_WIDTH = "1" *) 
  (* C_PROBE602_MU_CNT = "1" *) 
  (* C_PROBE602_TYPE = "1" *) 
  (* C_PROBE602_WIDTH = "1" *) 
  (* C_PROBE603_MU_CNT = "1" *) 
  (* C_PROBE603_TYPE = "1" *) 
  (* C_PROBE603_WIDTH = "1" *) 
  (* C_PROBE604_MU_CNT = "1" *) 
  (* C_PROBE604_TYPE = "1" *) 
  (* C_PROBE604_WIDTH = "1" *) 
  (* C_PROBE605_MU_CNT = "1" *) 
  (* C_PROBE605_TYPE = "1" *) 
  (* C_PROBE605_WIDTH = "1" *) 
  (* C_PROBE606_MU_CNT = "1" *) 
  (* C_PROBE606_TYPE = "1" *) 
  (* C_PROBE606_WIDTH = "1" *) 
  (* C_PROBE607_MU_CNT = "1" *) 
  (* C_PROBE607_TYPE = "1" *) 
  (* C_PROBE607_WIDTH = "1" *) 
  (* C_PROBE608_MU_CNT = "1" *) 
  (* C_PROBE608_TYPE = "1" *) 
  (* C_PROBE608_WIDTH = "1" *) 
  (* C_PROBE609_MU_CNT = "1" *) 
  (* C_PROBE609_TYPE = "1" *) 
  (* C_PROBE609_WIDTH = "1" *) 
  (* C_PROBE60_MU_CNT = "1" *) 
  (* C_PROBE60_TYPE = "1" *) 
  (* C_PROBE60_WIDTH = "1" *) 
  (* C_PROBE610_MU_CNT = "1" *) 
  (* C_PROBE610_TYPE = "1" *) 
  (* C_PROBE610_WIDTH = "1" *) 
  (* C_PROBE611_MU_CNT = "1" *) 
  (* C_PROBE611_TYPE = "1" *) 
  (* C_PROBE611_WIDTH = "1" *) 
  (* C_PROBE612_MU_CNT = "1" *) 
  (* C_PROBE612_TYPE = "1" *) 
  (* C_PROBE612_WIDTH = "1" *) 
  (* C_PROBE613_MU_CNT = "1" *) 
  (* C_PROBE613_TYPE = "1" *) 
  (* C_PROBE613_WIDTH = "1" *) 
  (* C_PROBE614_MU_CNT = "1" *) 
  (* C_PROBE614_TYPE = "1" *) 
  (* C_PROBE614_WIDTH = "1" *) 
  (* C_PROBE615_MU_CNT = "1" *) 
  (* C_PROBE615_TYPE = "1" *) 
  (* C_PROBE615_WIDTH = "1" *) 
  (* C_PROBE616_MU_CNT = "1" *) 
  (* C_PROBE616_TYPE = "1" *) 
  (* C_PROBE616_WIDTH = "1" *) 
  (* C_PROBE617_MU_CNT = "1" *) 
  (* C_PROBE617_TYPE = "1" *) 
  (* C_PROBE617_WIDTH = "1" *) 
  (* C_PROBE618_MU_CNT = "1" *) 
  (* C_PROBE618_TYPE = "1" *) 
  (* C_PROBE618_WIDTH = "1" *) 
  (* C_PROBE619_MU_CNT = "1" *) 
  (* C_PROBE619_TYPE = "1" *) 
  (* C_PROBE619_WIDTH = "1" *) 
  (* C_PROBE61_MU_CNT = "1" *) 
  (* C_PROBE61_TYPE = "1" *) 
  (* C_PROBE61_WIDTH = "1" *) 
  (* C_PROBE620_MU_CNT = "1" *) 
  (* C_PROBE620_TYPE = "1" *) 
  (* C_PROBE620_WIDTH = "1" *) 
  (* C_PROBE621_MU_CNT = "1" *) 
  (* C_PROBE621_TYPE = "1" *) 
  (* C_PROBE621_WIDTH = "1" *) 
  (* C_PROBE622_MU_CNT = "1" *) 
  (* C_PROBE622_TYPE = "1" *) 
  (* C_PROBE622_WIDTH = "1" *) 
  (* C_PROBE623_MU_CNT = "1" *) 
  (* C_PROBE623_TYPE = "1" *) 
  (* C_PROBE623_WIDTH = "1" *) 
  (* C_PROBE624_MU_CNT = "1" *) 
  (* C_PROBE624_TYPE = "1" *) 
  (* C_PROBE624_WIDTH = "1" *) 
  (* C_PROBE625_MU_CNT = "1" *) 
  (* C_PROBE625_TYPE = "1" *) 
  (* C_PROBE625_WIDTH = "1" *) 
  (* C_PROBE626_MU_CNT = "1" *) 
  (* C_PROBE626_TYPE = "1" *) 
  (* C_PROBE626_WIDTH = "1" *) 
  (* C_PROBE627_MU_CNT = "1" *) 
  (* C_PROBE627_TYPE = "1" *) 
  (* C_PROBE627_WIDTH = "1" *) 
  (* C_PROBE628_MU_CNT = "1" *) 
  (* C_PROBE628_TYPE = "1" *) 
  (* C_PROBE628_WIDTH = "1" *) 
  (* C_PROBE629_MU_CNT = "1" *) 
  (* C_PROBE629_TYPE = "1" *) 
  (* C_PROBE629_WIDTH = "1" *) 
  (* C_PROBE62_MU_CNT = "1" *) 
  (* C_PROBE62_TYPE = "1" *) 
  (* C_PROBE62_WIDTH = "1" *) 
  (* C_PROBE630_MU_CNT = "1" *) 
  (* C_PROBE630_TYPE = "1" *) 
  (* C_PROBE630_WIDTH = "1" *) 
  (* C_PROBE631_MU_CNT = "1" *) 
  (* C_PROBE631_TYPE = "1" *) 
  (* C_PROBE631_WIDTH = "1" *) 
  (* C_PROBE632_MU_CNT = "1" *) 
  (* C_PROBE632_TYPE = "1" *) 
  (* C_PROBE632_WIDTH = "1" *) 
  (* C_PROBE633_MU_CNT = "1" *) 
  (* C_PROBE633_TYPE = "1" *) 
  (* C_PROBE633_WIDTH = "1" *) 
  (* C_PROBE634_MU_CNT = "1" *) 
  (* C_PROBE634_TYPE = "1" *) 
  (* C_PROBE634_WIDTH = "1" *) 
  (* C_PROBE635_MU_CNT = "1" *) 
  (* C_PROBE635_TYPE = "1" *) 
  (* C_PROBE635_WIDTH = "1" *) 
  (* C_PROBE636_MU_CNT = "1" *) 
  (* C_PROBE636_TYPE = "1" *) 
  (* C_PROBE636_WIDTH = "1" *) 
  (* C_PROBE637_MU_CNT = "1" *) 
  (* C_PROBE637_TYPE = "1" *) 
  (* C_PROBE637_WIDTH = "1" *) 
  (* C_PROBE638_MU_CNT = "1" *) 
  (* C_PROBE638_TYPE = "1" *) 
  (* C_PROBE638_WIDTH = "1" *) 
  (* C_PROBE639_MU_CNT = "1" *) 
  (* C_PROBE639_TYPE = "1" *) 
  (* C_PROBE639_WIDTH = "1" *) 
  (* C_PROBE63_MU_CNT = "1" *) 
  (* C_PROBE63_TYPE = "1" *) 
  (* C_PROBE63_WIDTH = "1" *) 
  (* C_PROBE640_MU_CNT = "1" *) 
  (* C_PROBE640_TYPE = "1" *) 
  (* C_PROBE640_WIDTH = "1" *) 
  (* C_PROBE641_MU_CNT = "1" *) 
  (* C_PROBE641_TYPE = "1" *) 
  (* C_PROBE641_WIDTH = "1" *) 
  (* C_PROBE642_MU_CNT = "1" *) 
  (* C_PROBE642_TYPE = "1" *) 
  (* C_PROBE642_WIDTH = "1" *) 
  (* C_PROBE643_MU_CNT = "1" *) 
  (* C_PROBE643_TYPE = "1" *) 
  (* C_PROBE643_WIDTH = "1" *) 
  (* C_PROBE644_MU_CNT = "1" *) 
  (* C_PROBE644_TYPE = "1" *) 
  (* C_PROBE644_WIDTH = "1" *) 
  (* C_PROBE645_MU_CNT = "1" *) 
  (* C_PROBE645_TYPE = "1" *) 
  (* C_PROBE645_WIDTH = "1" *) 
  (* C_PROBE646_MU_CNT = "1" *) 
  (* C_PROBE646_TYPE = "1" *) 
  (* C_PROBE646_WIDTH = "1" *) 
  (* C_PROBE647_MU_CNT = "1" *) 
  (* C_PROBE647_TYPE = "1" *) 
  (* C_PROBE647_WIDTH = "1" *) 
  (* C_PROBE648_MU_CNT = "1" *) 
  (* C_PROBE648_TYPE = "1" *) 
  (* C_PROBE648_WIDTH = "1" *) 
  (* C_PROBE649_MU_CNT = "1" *) 
  (* C_PROBE649_TYPE = "1" *) 
  (* C_PROBE649_WIDTH = "1" *) 
  (* C_PROBE64_MU_CNT = "1" *) 
  (* C_PROBE64_TYPE = "1" *) 
  (* C_PROBE64_WIDTH = "1" *) 
  (* C_PROBE650_MU_CNT = "1" *) 
  (* C_PROBE650_TYPE = "1" *) 
  (* C_PROBE650_WIDTH = "1" *) 
  (* C_PROBE651_MU_CNT = "1" *) 
  (* C_PROBE651_TYPE = "1" *) 
  (* C_PROBE651_WIDTH = "1" *) 
  (* C_PROBE652_MU_CNT = "1" *) 
  (* C_PROBE652_TYPE = "1" *) 
  (* C_PROBE652_WIDTH = "1" *) 
  (* C_PROBE653_MU_CNT = "1" *) 
  (* C_PROBE653_TYPE = "1" *) 
  (* C_PROBE653_WIDTH = "1" *) 
  (* C_PROBE654_MU_CNT = "1" *) 
  (* C_PROBE654_TYPE = "1" *) 
  (* C_PROBE654_WIDTH = "1" *) 
  (* C_PROBE655_MU_CNT = "1" *) 
  (* C_PROBE655_TYPE = "1" *) 
  (* C_PROBE655_WIDTH = "1" *) 
  (* C_PROBE656_MU_CNT = "1" *) 
  (* C_PROBE656_TYPE = "1" *) 
  (* C_PROBE656_WIDTH = "1" *) 
  (* C_PROBE657_MU_CNT = "1" *) 
  (* C_PROBE657_TYPE = "1" *) 
  (* C_PROBE657_WIDTH = "1" *) 
  (* C_PROBE658_MU_CNT = "1" *) 
  (* C_PROBE658_TYPE = "1" *) 
  (* C_PROBE658_WIDTH = "1" *) 
  (* C_PROBE659_MU_CNT = "1" *) 
  (* C_PROBE659_TYPE = "1" *) 
  (* C_PROBE659_WIDTH = "1" *) 
  (* C_PROBE65_MU_CNT = "1" *) 
  (* C_PROBE65_TYPE = "1" *) 
  (* C_PROBE65_WIDTH = "1" *) 
  (* C_PROBE660_MU_CNT = "1" *) 
  (* C_PROBE660_TYPE = "1" *) 
  (* C_PROBE660_WIDTH = "1" *) 
  (* C_PROBE661_MU_CNT = "1" *) 
  (* C_PROBE661_TYPE = "1" *) 
  (* C_PROBE661_WIDTH = "1" *) 
  (* C_PROBE662_MU_CNT = "1" *) 
  (* C_PROBE662_TYPE = "1" *) 
  (* C_PROBE662_WIDTH = "1" *) 
  (* C_PROBE663_MU_CNT = "1" *) 
  (* C_PROBE663_TYPE = "1" *) 
  (* C_PROBE663_WIDTH = "1" *) 
  (* C_PROBE664_MU_CNT = "1" *) 
  (* C_PROBE664_TYPE = "1" *) 
  (* C_PROBE664_WIDTH = "1" *) 
  (* C_PROBE665_MU_CNT = "1" *) 
  (* C_PROBE665_TYPE = "1" *) 
  (* C_PROBE665_WIDTH = "1" *) 
  (* C_PROBE666_MU_CNT = "1" *) 
  (* C_PROBE666_TYPE = "1" *) 
  (* C_PROBE666_WIDTH = "1" *) 
  (* C_PROBE667_MU_CNT = "1" *) 
  (* C_PROBE667_TYPE = "1" *) 
  (* C_PROBE667_WIDTH = "1" *) 
  (* C_PROBE668_MU_CNT = "1" *) 
  (* C_PROBE668_TYPE = "1" *) 
  (* C_PROBE668_WIDTH = "1" *) 
  (* C_PROBE669_MU_CNT = "1" *) 
  (* C_PROBE669_TYPE = "1" *) 
  (* C_PROBE669_WIDTH = "1" *) 
  (* C_PROBE66_MU_CNT = "1" *) 
  (* C_PROBE66_TYPE = "1" *) 
  (* C_PROBE66_WIDTH = "1" *) 
  (* C_PROBE670_MU_CNT = "1" *) 
  (* C_PROBE670_TYPE = "1" *) 
  (* C_PROBE670_WIDTH = "1" *) 
  (* C_PROBE671_MU_CNT = "1" *) 
  (* C_PROBE671_TYPE = "1" *) 
  (* C_PROBE671_WIDTH = "1" *) 
  (* C_PROBE672_MU_CNT = "1" *) 
  (* C_PROBE672_TYPE = "1" *) 
  (* C_PROBE672_WIDTH = "1" *) 
  (* C_PROBE673_MU_CNT = "1" *) 
  (* C_PROBE673_TYPE = "1" *) 
  (* C_PROBE673_WIDTH = "1" *) 
  (* C_PROBE674_MU_CNT = "1" *) 
  (* C_PROBE674_TYPE = "1" *) 
  (* C_PROBE674_WIDTH = "1" *) 
  (* C_PROBE675_MU_CNT = "1" *) 
  (* C_PROBE675_TYPE = "1" *) 
  (* C_PROBE675_WIDTH = "1" *) 
  (* C_PROBE676_MU_CNT = "1" *) 
  (* C_PROBE676_TYPE = "1" *) 
  (* C_PROBE676_WIDTH = "1" *) 
  (* C_PROBE677_MU_CNT = "1" *) 
  (* C_PROBE677_TYPE = "1" *) 
  (* C_PROBE677_WIDTH = "1" *) 
  (* C_PROBE678_MU_CNT = "1" *) 
  (* C_PROBE678_TYPE = "1" *) 
  (* C_PROBE678_WIDTH = "1" *) 
  (* C_PROBE679_MU_CNT = "1" *) 
  (* C_PROBE679_TYPE = "1" *) 
  (* C_PROBE679_WIDTH = "1" *) 
  (* C_PROBE67_MU_CNT = "1" *) 
  (* C_PROBE67_TYPE = "1" *) 
  (* C_PROBE67_WIDTH = "1" *) 
  (* C_PROBE680_MU_CNT = "1" *) 
  (* C_PROBE680_TYPE = "1" *) 
  (* C_PROBE680_WIDTH = "1" *) 
  (* C_PROBE681_MU_CNT = "1" *) 
  (* C_PROBE681_TYPE = "1" *) 
  (* C_PROBE681_WIDTH = "1" *) 
  (* C_PROBE682_MU_CNT = "1" *) 
  (* C_PROBE682_TYPE = "1" *) 
  (* C_PROBE682_WIDTH = "1" *) 
  (* C_PROBE683_MU_CNT = "1" *) 
  (* C_PROBE683_TYPE = "1" *) 
  (* C_PROBE683_WIDTH = "1" *) 
  (* C_PROBE684_MU_CNT = "1" *) 
  (* C_PROBE684_TYPE = "1" *) 
  (* C_PROBE684_WIDTH = "1" *) 
  (* C_PROBE685_MU_CNT = "1" *) 
  (* C_PROBE685_TYPE = "1" *) 
  (* C_PROBE685_WIDTH = "1" *) 
  (* C_PROBE686_MU_CNT = "1" *) 
  (* C_PROBE686_TYPE = "1" *) 
  (* C_PROBE686_WIDTH = "1" *) 
  (* C_PROBE687_MU_CNT = "1" *) 
  (* C_PROBE687_TYPE = "1" *) 
  (* C_PROBE687_WIDTH = "1" *) 
  (* C_PROBE688_MU_CNT = "1" *) 
  (* C_PROBE688_TYPE = "1" *) 
  (* C_PROBE688_WIDTH = "1" *) 
  (* C_PROBE689_MU_CNT = "1" *) 
  (* C_PROBE689_TYPE = "1" *) 
  (* C_PROBE689_WIDTH = "1" *) 
  (* C_PROBE68_MU_CNT = "1" *) 
  (* C_PROBE68_TYPE = "1" *) 
  (* C_PROBE68_WIDTH = "1" *) 
  (* C_PROBE690_MU_CNT = "1" *) 
  (* C_PROBE690_TYPE = "1" *) 
  (* C_PROBE690_WIDTH = "1" *) 
  (* C_PROBE691_MU_CNT = "1" *) 
  (* C_PROBE691_TYPE = "1" *) 
  (* C_PROBE691_WIDTH = "1" *) 
  (* C_PROBE692_MU_CNT = "1" *) 
  (* C_PROBE692_TYPE = "1" *) 
  (* C_PROBE692_WIDTH = "1" *) 
  (* C_PROBE693_MU_CNT = "1" *) 
  (* C_PROBE693_TYPE = "1" *) 
  (* C_PROBE693_WIDTH = "1" *) 
  (* C_PROBE694_MU_CNT = "1" *) 
  (* C_PROBE694_TYPE = "1" *) 
  (* C_PROBE694_WIDTH = "1" *) 
  (* C_PROBE695_MU_CNT = "1" *) 
  (* C_PROBE695_TYPE = "1" *) 
  (* C_PROBE695_WIDTH = "1" *) 
  (* C_PROBE696_MU_CNT = "1" *) 
  (* C_PROBE696_TYPE = "1" *) 
  (* C_PROBE696_WIDTH = "1" *) 
  (* C_PROBE697_MU_CNT = "1" *) 
  (* C_PROBE697_TYPE = "1" *) 
  (* C_PROBE697_WIDTH = "1" *) 
  (* C_PROBE698_MU_CNT = "1" *) 
  (* C_PROBE698_TYPE = "1" *) 
  (* C_PROBE698_WIDTH = "1" *) 
  (* C_PROBE699_MU_CNT = "1" *) 
  (* C_PROBE699_TYPE = "1" *) 
  (* C_PROBE699_WIDTH = "1" *) 
  (* C_PROBE69_MU_CNT = "1" *) 
  (* C_PROBE69_TYPE = "1" *) 
  (* C_PROBE69_WIDTH = "1" *) 
  (* C_PROBE6_MU_CNT = "1" *) 
  (* C_PROBE6_TYPE = "1" *) 
  (* C_PROBE6_WIDTH = "1" *) 
  (* C_PROBE700_MU_CNT = "1" *) 
  (* C_PROBE700_TYPE = "1" *) 
  (* C_PROBE700_WIDTH = "1" *) 
  (* C_PROBE701_MU_CNT = "1" *) 
  (* C_PROBE701_TYPE = "1" *) 
  (* C_PROBE701_WIDTH = "1" *) 
  (* C_PROBE702_MU_CNT = "1" *) 
  (* C_PROBE702_TYPE = "1" *) 
  (* C_PROBE702_WIDTH = "1" *) 
  (* C_PROBE703_MU_CNT = "1" *) 
  (* C_PROBE703_TYPE = "1" *) 
  (* C_PROBE703_WIDTH = "1" *) 
  (* C_PROBE704_MU_CNT = "1" *) 
  (* C_PROBE704_TYPE = "1" *) 
  (* C_PROBE704_WIDTH = "1" *) 
  (* C_PROBE705_MU_CNT = "1" *) 
  (* C_PROBE705_TYPE = "1" *) 
  (* C_PROBE705_WIDTH = "1" *) 
  (* C_PROBE706_MU_CNT = "1" *) 
  (* C_PROBE706_TYPE = "1" *) 
  (* C_PROBE706_WIDTH = "1" *) 
  (* C_PROBE707_MU_CNT = "1" *) 
  (* C_PROBE707_TYPE = "1" *) 
  (* C_PROBE707_WIDTH = "1" *) 
  (* C_PROBE708_MU_CNT = "1" *) 
  (* C_PROBE708_TYPE = "1" *) 
  (* C_PROBE708_WIDTH = "1" *) 
  (* C_PROBE709_MU_CNT = "1" *) 
  (* C_PROBE709_TYPE = "1" *) 
  (* C_PROBE709_WIDTH = "1" *) 
  (* C_PROBE70_MU_CNT = "1" *) 
  (* C_PROBE70_TYPE = "1" *) 
  (* C_PROBE70_WIDTH = "1" *) 
  (* C_PROBE710_MU_CNT = "1" *) 
  (* C_PROBE710_TYPE = "1" *) 
  (* C_PROBE710_WIDTH = "1" *) 
  (* C_PROBE711_MU_CNT = "1" *) 
  (* C_PROBE711_TYPE = "1" *) 
  (* C_PROBE711_WIDTH = "1" *) 
  (* C_PROBE712_MU_CNT = "1" *) 
  (* C_PROBE712_TYPE = "1" *) 
  (* C_PROBE712_WIDTH = "1" *) 
  (* C_PROBE713_MU_CNT = "1" *) 
  (* C_PROBE713_TYPE = "1" *) 
  (* C_PROBE713_WIDTH = "1" *) 
  (* C_PROBE714_MU_CNT = "1" *) 
  (* C_PROBE714_TYPE = "1" *) 
  (* C_PROBE714_WIDTH = "1" *) 
  (* C_PROBE715_MU_CNT = "1" *) 
  (* C_PROBE715_TYPE = "1" *) 
  (* C_PROBE715_WIDTH = "1" *) 
  (* C_PROBE716_MU_CNT = "1" *) 
  (* C_PROBE716_TYPE = "1" *) 
  (* C_PROBE716_WIDTH = "1" *) 
  (* C_PROBE717_MU_CNT = "1" *) 
  (* C_PROBE717_TYPE = "1" *) 
  (* C_PROBE717_WIDTH = "1" *) 
  (* C_PROBE718_MU_CNT = "1" *) 
  (* C_PROBE718_TYPE = "1" *) 
  (* C_PROBE718_WIDTH = "1" *) 
  (* C_PROBE719_MU_CNT = "1" *) 
  (* C_PROBE719_TYPE = "1" *) 
  (* C_PROBE719_WIDTH = "1" *) 
  (* C_PROBE71_MU_CNT = "1" *) 
  (* C_PROBE71_TYPE = "1" *) 
  (* C_PROBE71_WIDTH = "1" *) 
  (* C_PROBE720_MU_CNT = "1" *) 
  (* C_PROBE720_TYPE = "1" *) 
  (* C_PROBE720_WIDTH = "1" *) 
  (* C_PROBE721_MU_CNT = "1" *) 
  (* C_PROBE721_TYPE = "1" *) 
  (* C_PROBE721_WIDTH = "1" *) 
  (* C_PROBE722_MU_CNT = "1" *) 
  (* C_PROBE722_TYPE = "1" *) 
  (* C_PROBE722_WIDTH = "1" *) 
  (* C_PROBE723_MU_CNT = "1" *) 
  (* C_PROBE723_TYPE = "1" *) 
  (* C_PROBE723_WIDTH = "1" *) 
  (* C_PROBE724_MU_CNT = "1" *) 
  (* C_PROBE724_TYPE = "1" *) 
  (* C_PROBE724_WIDTH = "1" *) 
  (* C_PROBE725_MU_CNT = "1" *) 
  (* C_PROBE725_TYPE = "1" *) 
  (* C_PROBE725_WIDTH = "1" *) 
  (* C_PROBE726_MU_CNT = "1" *) 
  (* C_PROBE726_TYPE = "1" *) 
  (* C_PROBE726_WIDTH = "1" *) 
  (* C_PROBE727_MU_CNT = "1" *) 
  (* C_PROBE727_TYPE = "1" *) 
  (* C_PROBE727_WIDTH = "1" *) 
  (* C_PROBE728_MU_CNT = "1" *) 
  (* C_PROBE728_TYPE = "1" *) 
  (* C_PROBE728_WIDTH = "1" *) 
  (* C_PROBE729_MU_CNT = "1" *) 
  (* C_PROBE729_TYPE = "1" *) 
  (* C_PROBE729_WIDTH = "1" *) 
  (* C_PROBE72_MU_CNT = "1" *) 
  (* C_PROBE72_TYPE = "1" *) 
  (* C_PROBE72_WIDTH = "1" *) 
  (* C_PROBE730_MU_CNT = "1" *) 
  (* C_PROBE730_TYPE = "1" *) 
  (* C_PROBE730_WIDTH = "1" *) 
  (* C_PROBE731_MU_CNT = "1" *) 
  (* C_PROBE731_TYPE = "1" *) 
  (* C_PROBE731_WIDTH = "1" *) 
  (* C_PROBE732_MU_CNT = "1" *) 
  (* C_PROBE732_TYPE = "1" *) 
  (* C_PROBE732_WIDTH = "1" *) 
  (* C_PROBE733_MU_CNT = "1" *) 
  (* C_PROBE733_TYPE = "1" *) 
  (* C_PROBE733_WIDTH = "1" *) 
  (* C_PROBE734_MU_CNT = "1" *) 
  (* C_PROBE734_TYPE = "1" *) 
  (* C_PROBE734_WIDTH = "1" *) 
  (* C_PROBE735_MU_CNT = "1" *) 
  (* C_PROBE735_TYPE = "1" *) 
  (* C_PROBE735_WIDTH = "1" *) 
  (* C_PROBE736_MU_CNT = "1" *) 
  (* C_PROBE736_TYPE = "1" *) 
  (* C_PROBE736_WIDTH = "1" *) 
  (* C_PROBE737_MU_CNT = "1" *) 
  (* C_PROBE737_TYPE = "1" *) 
  (* C_PROBE737_WIDTH = "1" *) 
  (* C_PROBE738_MU_CNT = "1" *) 
  (* C_PROBE738_TYPE = "1" *) 
  (* C_PROBE738_WIDTH = "1" *) 
  (* C_PROBE739_MU_CNT = "1" *) 
  (* C_PROBE739_TYPE = "1" *) 
  (* C_PROBE739_WIDTH = "1" *) 
  (* C_PROBE73_MU_CNT = "1" *) 
  (* C_PROBE73_TYPE = "1" *) 
  (* C_PROBE73_WIDTH = "1" *) 
  (* C_PROBE740_MU_CNT = "1" *) 
  (* C_PROBE740_TYPE = "1" *) 
  (* C_PROBE740_WIDTH = "1" *) 
  (* C_PROBE741_MU_CNT = "1" *) 
  (* C_PROBE741_TYPE = "1" *) 
  (* C_PROBE741_WIDTH = "1" *) 
  (* C_PROBE742_MU_CNT = "1" *) 
  (* C_PROBE742_TYPE = "1" *) 
  (* C_PROBE742_WIDTH = "1" *) 
  (* C_PROBE743_MU_CNT = "1" *) 
  (* C_PROBE743_TYPE = "1" *) 
  (* C_PROBE743_WIDTH = "1" *) 
  (* C_PROBE744_MU_CNT = "1" *) 
  (* C_PROBE744_TYPE = "1" *) 
  (* C_PROBE744_WIDTH = "1" *) 
  (* C_PROBE745_MU_CNT = "1" *) 
  (* C_PROBE745_TYPE = "1" *) 
  (* C_PROBE745_WIDTH = "1" *) 
  (* C_PROBE746_MU_CNT = "1" *) 
  (* C_PROBE746_TYPE = "1" *) 
  (* C_PROBE746_WIDTH = "1" *) 
  (* C_PROBE747_MU_CNT = "1" *) 
  (* C_PROBE747_TYPE = "1" *) 
  (* C_PROBE747_WIDTH = "1" *) 
  (* C_PROBE748_MU_CNT = "1" *) 
  (* C_PROBE748_TYPE = "1" *) 
  (* C_PROBE748_WIDTH = "1" *) 
  (* C_PROBE749_MU_CNT = "1" *) 
  (* C_PROBE749_TYPE = "1" *) 
  (* C_PROBE749_WIDTH = "1" *) 
  (* C_PROBE74_MU_CNT = "1" *) 
  (* C_PROBE74_TYPE = "1" *) 
  (* C_PROBE74_WIDTH = "1" *) 
  (* C_PROBE750_MU_CNT = "1" *) 
  (* C_PROBE750_TYPE = "1" *) 
  (* C_PROBE750_WIDTH = "1" *) 
  (* C_PROBE751_MU_CNT = "1" *) 
  (* C_PROBE751_TYPE = "1" *) 
  (* C_PROBE751_WIDTH = "1" *) 
  (* C_PROBE752_MU_CNT = "1" *) 
  (* C_PROBE752_TYPE = "1" *) 
  (* C_PROBE752_WIDTH = "1" *) 
  (* C_PROBE753_MU_CNT = "1" *) 
  (* C_PROBE753_TYPE = "1" *) 
  (* C_PROBE753_WIDTH = "1" *) 
  (* C_PROBE754_MU_CNT = "1" *) 
  (* C_PROBE754_TYPE = "1" *) 
  (* C_PROBE754_WIDTH = "1" *) 
  (* C_PROBE755_MU_CNT = "1" *) 
  (* C_PROBE755_TYPE = "1" *) 
  (* C_PROBE755_WIDTH = "1" *) 
  (* C_PROBE756_MU_CNT = "1" *) 
  (* C_PROBE756_TYPE = "1" *) 
  (* C_PROBE756_WIDTH = "1" *) 
  (* C_PROBE757_MU_CNT = "1" *) 
  (* C_PROBE757_TYPE = "1" *) 
  (* C_PROBE757_WIDTH = "1" *) 
  (* C_PROBE758_MU_CNT = "1" *) 
  (* C_PROBE758_TYPE = "1" *) 
  (* C_PROBE758_WIDTH = "1" *) 
  (* C_PROBE759_MU_CNT = "1" *) 
  (* C_PROBE759_TYPE = "1" *) 
  (* C_PROBE759_WIDTH = "1" *) 
  (* C_PROBE75_MU_CNT = "1" *) 
  (* C_PROBE75_TYPE = "1" *) 
  (* C_PROBE75_WIDTH = "1" *) 
  (* C_PROBE760_MU_CNT = "1" *) 
  (* C_PROBE760_TYPE = "1" *) 
  (* C_PROBE760_WIDTH = "1" *) 
  (* C_PROBE761_MU_CNT = "1" *) 
  (* C_PROBE761_TYPE = "1" *) 
  (* C_PROBE761_WIDTH = "1" *) 
  (* C_PROBE762_MU_CNT = "1" *) 
  (* C_PROBE762_TYPE = "1" *) 
  (* C_PROBE762_WIDTH = "1" *) 
  (* C_PROBE763_MU_CNT = "1" *) 
  (* C_PROBE763_TYPE = "1" *) 
  (* C_PROBE763_WIDTH = "1" *) 
  (* C_PROBE764_MU_CNT = "1" *) 
  (* C_PROBE764_TYPE = "1" *) 
  (* C_PROBE764_WIDTH = "1" *) 
  (* C_PROBE765_MU_CNT = "1" *) 
  (* C_PROBE765_TYPE = "1" *) 
  (* C_PROBE765_WIDTH = "1" *) 
  (* C_PROBE766_MU_CNT = "1" *) 
  (* C_PROBE766_TYPE = "1" *) 
  (* C_PROBE766_WIDTH = "1" *) 
  (* C_PROBE767_MU_CNT = "1" *) 
  (* C_PROBE767_TYPE = "1" *) 
  (* C_PROBE767_WIDTH = "1" *) 
  (* C_PROBE768_MU_CNT = "1" *) 
  (* C_PROBE768_TYPE = "1" *) 
  (* C_PROBE768_WIDTH = "1" *) 
  (* C_PROBE769_MU_CNT = "1" *) 
  (* C_PROBE769_TYPE = "1" *) 
  (* C_PROBE769_WIDTH = "1" *) 
  (* C_PROBE76_MU_CNT = "1" *) 
  (* C_PROBE76_TYPE = "1" *) 
  (* C_PROBE76_WIDTH = "1" *) 
  (* C_PROBE770_MU_CNT = "1" *) 
  (* C_PROBE770_TYPE = "1" *) 
  (* C_PROBE770_WIDTH = "1" *) 
  (* C_PROBE771_MU_CNT = "1" *) 
  (* C_PROBE771_TYPE = "1" *) 
  (* C_PROBE771_WIDTH = "1" *) 
  (* C_PROBE772_MU_CNT = "1" *) 
  (* C_PROBE772_TYPE = "1" *) 
  (* C_PROBE772_WIDTH = "1" *) 
  (* C_PROBE773_MU_CNT = "1" *) 
  (* C_PROBE773_TYPE = "1" *) 
  (* C_PROBE773_WIDTH = "1" *) 
  (* C_PROBE774_MU_CNT = "1" *) 
  (* C_PROBE774_TYPE = "1" *) 
  (* C_PROBE774_WIDTH = "1" *) 
  (* C_PROBE775_MU_CNT = "1" *) 
  (* C_PROBE775_TYPE = "1" *) 
  (* C_PROBE775_WIDTH = "1" *) 
  (* C_PROBE776_MU_CNT = "1" *) 
  (* C_PROBE776_TYPE = "1" *) 
  (* C_PROBE776_WIDTH = "1" *) 
  (* C_PROBE777_MU_CNT = "1" *) 
  (* C_PROBE777_TYPE = "1" *) 
  (* C_PROBE777_WIDTH = "1" *) 
  (* C_PROBE778_MU_CNT = "1" *) 
  (* C_PROBE778_TYPE = "1" *) 
  (* C_PROBE778_WIDTH = "1" *) 
  (* C_PROBE779_MU_CNT = "1" *) 
  (* C_PROBE779_TYPE = "1" *) 
  (* C_PROBE779_WIDTH = "1" *) 
  (* C_PROBE77_MU_CNT = "1" *) 
  (* C_PROBE77_TYPE = "1" *) 
  (* C_PROBE77_WIDTH = "1" *) 
  (* C_PROBE780_MU_CNT = "1" *) 
  (* C_PROBE780_TYPE = "1" *) 
  (* C_PROBE780_WIDTH = "1" *) 
  (* C_PROBE781_MU_CNT = "1" *) 
  (* C_PROBE781_TYPE = "1" *) 
  (* C_PROBE781_WIDTH = "1" *) 
  (* C_PROBE782_MU_CNT = "1" *) 
  (* C_PROBE782_TYPE = "1" *) 
  (* C_PROBE782_WIDTH = "1" *) 
  (* C_PROBE783_MU_CNT = "1" *) 
  (* C_PROBE783_TYPE = "1" *) 
  (* C_PROBE783_WIDTH = "1" *) 
  (* C_PROBE784_MU_CNT = "1" *) 
  (* C_PROBE784_TYPE = "1" *) 
  (* C_PROBE784_WIDTH = "1" *) 
  (* C_PROBE785_MU_CNT = "1" *) 
  (* C_PROBE785_TYPE = "1" *) 
  (* C_PROBE785_WIDTH = "1" *) 
  (* C_PROBE786_MU_CNT = "1" *) 
  (* C_PROBE786_TYPE = "1" *) 
  (* C_PROBE786_WIDTH = "1" *) 
  (* C_PROBE787_MU_CNT = "1" *) 
  (* C_PROBE787_TYPE = "1" *) 
  (* C_PROBE787_WIDTH = "1" *) 
  (* C_PROBE788_MU_CNT = "1" *) 
  (* C_PROBE788_TYPE = "1" *) 
  (* C_PROBE788_WIDTH = "1" *) 
  (* C_PROBE789_MU_CNT = "1" *) 
  (* C_PROBE789_TYPE = "1" *) 
  (* C_PROBE789_WIDTH = "1" *) 
  (* C_PROBE78_MU_CNT = "1" *) 
  (* C_PROBE78_TYPE = "1" *) 
  (* C_PROBE78_WIDTH = "1" *) 
  (* C_PROBE790_MU_CNT = "1" *) 
  (* C_PROBE790_TYPE = "1" *) 
  (* C_PROBE790_WIDTH = "1" *) 
  (* C_PROBE791_MU_CNT = "1" *) 
  (* C_PROBE791_TYPE = "1" *) 
  (* C_PROBE791_WIDTH = "1" *) 
  (* C_PROBE792_MU_CNT = "1" *) 
  (* C_PROBE792_TYPE = "1" *) 
  (* C_PROBE792_WIDTH = "1" *) 
  (* C_PROBE793_MU_CNT = "1" *) 
  (* C_PROBE793_TYPE = "1" *) 
  (* C_PROBE793_WIDTH = "1" *) 
  (* C_PROBE794_MU_CNT = "1" *) 
  (* C_PROBE794_TYPE = "1" *) 
  (* C_PROBE794_WIDTH = "1" *) 
  (* C_PROBE795_MU_CNT = "1" *) 
  (* C_PROBE795_TYPE = "1" *) 
  (* C_PROBE795_WIDTH = "1" *) 
  (* C_PROBE796_MU_CNT = "1" *) 
  (* C_PROBE796_TYPE = "1" *) 
  (* C_PROBE796_WIDTH = "1" *) 
  (* C_PROBE797_MU_CNT = "1" *) 
  (* C_PROBE797_TYPE = "1" *) 
  (* C_PROBE797_WIDTH = "1" *) 
  (* C_PROBE798_MU_CNT = "1" *) 
  (* C_PROBE798_TYPE = "1" *) 
  (* C_PROBE798_WIDTH = "1" *) 
  (* C_PROBE799_MU_CNT = "1" *) 
  (* C_PROBE799_TYPE = "1" *) 
  (* C_PROBE799_WIDTH = "1" *) 
  (* C_PROBE79_MU_CNT = "1" *) 
  (* C_PROBE79_TYPE = "1" *) 
  (* C_PROBE79_WIDTH = "1" *) 
  (* C_PROBE7_MU_CNT = "1" *) 
  (* C_PROBE7_TYPE = "1" *) 
  (* C_PROBE7_WIDTH = "1" *) 
  (* C_PROBE800_MU_CNT = "1" *) 
  (* C_PROBE800_TYPE = "1" *) 
  (* C_PROBE800_WIDTH = "1" *) 
  (* C_PROBE801_MU_CNT = "1" *) 
  (* C_PROBE801_TYPE = "1" *) 
  (* C_PROBE801_WIDTH = "1" *) 
  (* C_PROBE802_MU_CNT = "1" *) 
  (* C_PROBE802_TYPE = "1" *) 
  (* C_PROBE802_WIDTH = "1" *) 
  (* C_PROBE803_MU_CNT = "1" *) 
  (* C_PROBE803_TYPE = "1" *) 
  (* C_PROBE803_WIDTH = "1" *) 
  (* C_PROBE804_MU_CNT = "1" *) 
  (* C_PROBE804_TYPE = "1" *) 
  (* C_PROBE804_WIDTH = "1" *) 
  (* C_PROBE805_MU_CNT = "1" *) 
  (* C_PROBE805_TYPE = "1" *) 
  (* C_PROBE805_WIDTH = "1" *) 
  (* C_PROBE806_MU_CNT = "1" *) 
  (* C_PROBE806_TYPE = "1" *) 
  (* C_PROBE806_WIDTH = "1" *) 
  (* C_PROBE807_MU_CNT = "1" *) 
  (* C_PROBE807_TYPE = "1" *) 
  (* C_PROBE807_WIDTH = "1" *) 
  (* C_PROBE808_MU_CNT = "1" *) 
  (* C_PROBE808_TYPE = "1" *) 
  (* C_PROBE808_WIDTH = "1" *) 
  (* C_PROBE809_MU_CNT = "1" *) 
  (* C_PROBE809_TYPE = "1" *) 
  (* C_PROBE809_WIDTH = "1" *) 
  (* C_PROBE80_MU_CNT = "1" *) 
  (* C_PROBE80_TYPE = "1" *) 
  (* C_PROBE80_WIDTH = "1" *) 
  (* C_PROBE810_MU_CNT = "1" *) 
  (* C_PROBE810_TYPE = "1" *) 
  (* C_PROBE810_WIDTH = "1" *) 
  (* C_PROBE811_MU_CNT = "1" *) 
  (* C_PROBE811_TYPE = "1" *) 
  (* C_PROBE811_WIDTH = "1" *) 
  (* C_PROBE812_MU_CNT = "1" *) 
  (* C_PROBE812_TYPE = "1" *) 
  (* C_PROBE812_WIDTH = "1" *) 
  (* C_PROBE813_MU_CNT = "1" *) 
  (* C_PROBE813_TYPE = "1" *) 
  (* C_PROBE813_WIDTH = "1" *) 
  (* C_PROBE814_MU_CNT = "1" *) 
  (* C_PROBE814_TYPE = "1" *) 
  (* C_PROBE814_WIDTH = "1" *) 
  (* C_PROBE815_MU_CNT = "1" *) 
  (* C_PROBE815_TYPE = "1" *) 
  (* C_PROBE815_WIDTH = "1" *) 
  (* C_PROBE816_MU_CNT = "1" *) 
  (* C_PROBE816_TYPE = "1" *) 
  (* C_PROBE816_WIDTH = "1" *) 
  (* C_PROBE817_MU_CNT = "1" *) 
  (* C_PROBE817_TYPE = "1" *) 
  (* C_PROBE817_WIDTH = "1" *) 
  (* C_PROBE818_MU_CNT = "1" *) 
  (* C_PROBE818_TYPE = "1" *) 
  (* C_PROBE818_WIDTH = "1" *) 
  (* C_PROBE819_MU_CNT = "1" *) 
  (* C_PROBE819_TYPE = "1" *) 
  (* C_PROBE819_WIDTH = "1" *) 
  (* C_PROBE81_MU_CNT = "1" *) 
  (* C_PROBE81_TYPE = "1" *) 
  (* C_PROBE81_WIDTH = "1" *) 
  (* C_PROBE820_MU_CNT = "1" *) 
  (* C_PROBE820_TYPE = "1" *) 
  (* C_PROBE820_WIDTH = "1" *) 
  (* C_PROBE821_MU_CNT = "1" *) 
  (* C_PROBE821_TYPE = "1" *) 
  (* C_PROBE821_WIDTH = "1" *) 
  (* C_PROBE822_MU_CNT = "1" *) 
  (* C_PROBE822_TYPE = "1" *) 
  (* C_PROBE822_WIDTH = "1" *) 
  (* C_PROBE823_MU_CNT = "1" *) 
  (* C_PROBE823_TYPE = "1" *) 
  (* C_PROBE823_WIDTH = "1" *) 
  (* C_PROBE824_MU_CNT = "1" *) 
  (* C_PROBE824_TYPE = "1" *) 
  (* C_PROBE824_WIDTH = "1" *) 
  (* C_PROBE825_MU_CNT = "1" *) 
  (* C_PROBE825_TYPE = "1" *) 
  (* C_PROBE825_WIDTH = "1" *) 
  (* C_PROBE826_MU_CNT = "1" *) 
  (* C_PROBE826_TYPE = "1" *) 
  (* C_PROBE826_WIDTH = "1" *) 
  (* C_PROBE827_MU_CNT = "1" *) 
  (* C_PROBE827_TYPE = "1" *) 
  (* C_PROBE827_WIDTH = "1" *) 
  (* C_PROBE828_MU_CNT = "1" *) 
  (* C_PROBE828_TYPE = "1" *) 
  (* C_PROBE828_WIDTH = "1" *) 
  (* C_PROBE829_MU_CNT = "1" *) 
  (* C_PROBE829_TYPE = "1" *) 
  (* C_PROBE829_WIDTH = "1" *) 
  (* C_PROBE82_MU_CNT = "1" *) 
  (* C_PROBE82_TYPE = "1" *) 
  (* C_PROBE82_WIDTH = "1" *) 
  (* C_PROBE830_MU_CNT = "1" *) 
  (* C_PROBE830_TYPE = "1" *) 
  (* C_PROBE830_WIDTH = "1" *) 
  (* C_PROBE831_MU_CNT = "1" *) 
  (* C_PROBE831_TYPE = "1" *) 
  (* C_PROBE831_WIDTH = "1" *) 
  (* C_PROBE832_MU_CNT = "1" *) 
  (* C_PROBE832_TYPE = "1" *) 
  (* C_PROBE832_WIDTH = "1" *) 
  (* C_PROBE833_MU_CNT = "1" *) 
  (* C_PROBE833_TYPE = "1" *) 
  (* C_PROBE833_WIDTH = "1" *) 
  (* C_PROBE834_MU_CNT = "1" *) 
  (* C_PROBE834_TYPE = "1" *) 
  (* C_PROBE834_WIDTH = "1" *) 
  (* C_PROBE835_MU_CNT = "1" *) 
  (* C_PROBE835_TYPE = "1" *) 
  (* C_PROBE835_WIDTH = "1" *) 
  (* C_PROBE836_MU_CNT = "1" *) 
  (* C_PROBE836_TYPE = "1" *) 
  (* C_PROBE836_WIDTH = "1" *) 
  (* C_PROBE837_MU_CNT = "1" *) 
  (* C_PROBE837_TYPE = "1" *) 
  (* C_PROBE837_WIDTH = "1" *) 
  (* C_PROBE838_MU_CNT = "1" *) 
  (* C_PROBE838_TYPE = "1" *) 
  (* C_PROBE838_WIDTH = "1" *) 
  (* C_PROBE839_MU_CNT = "1" *) 
  (* C_PROBE839_TYPE = "1" *) 
  (* C_PROBE839_WIDTH = "1" *) 
  (* C_PROBE83_MU_CNT = "1" *) 
  (* C_PROBE83_TYPE = "1" *) 
  (* C_PROBE83_WIDTH = "1" *) 
  (* C_PROBE840_MU_CNT = "1" *) 
  (* C_PROBE840_TYPE = "1" *) 
  (* C_PROBE840_WIDTH = "1" *) 
  (* C_PROBE841_MU_CNT = "1" *) 
  (* C_PROBE841_TYPE = "1" *) 
  (* C_PROBE841_WIDTH = "1" *) 
  (* C_PROBE842_MU_CNT = "1" *) 
  (* C_PROBE842_TYPE = "1" *) 
  (* C_PROBE842_WIDTH = "1" *) 
  (* C_PROBE843_MU_CNT = "1" *) 
  (* C_PROBE843_TYPE = "1" *) 
  (* C_PROBE843_WIDTH = "1" *) 
  (* C_PROBE844_MU_CNT = "1" *) 
  (* C_PROBE844_TYPE = "1" *) 
  (* C_PROBE844_WIDTH = "1" *) 
  (* C_PROBE845_MU_CNT = "1" *) 
  (* C_PROBE845_TYPE = "1" *) 
  (* C_PROBE845_WIDTH = "1" *) 
  (* C_PROBE846_MU_CNT = "1" *) 
  (* C_PROBE846_TYPE = "1" *) 
  (* C_PROBE846_WIDTH = "1" *) 
  (* C_PROBE847_MU_CNT = "1" *) 
  (* C_PROBE847_TYPE = "1" *) 
  (* C_PROBE847_WIDTH = "1" *) 
  (* C_PROBE848_MU_CNT = "1" *) 
  (* C_PROBE848_TYPE = "1" *) 
  (* C_PROBE848_WIDTH = "1" *) 
  (* C_PROBE849_MU_CNT = "1" *) 
  (* C_PROBE849_TYPE = "1" *) 
  (* C_PROBE849_WIDTH = "1" *) 
  (* C_PROBE84_MU_CNT = "1" *) 
  (* C_PROBE84_TYPE = "1" *) 
  (* C_PROBE84_WIDTH = "1" *) 
  (* C_PROBE850_MU_CNT = "1" *) 
  (* C_PROBE850_TYPE = "1" *) 
  (* C_PROBE850_WIDTH = "1" *) 
  (* C_PROBE851_MU_CNT = "1" *) 
  (* C_PROBE851_TYPE = "1" *) 
  (* C_PROBE851_WIDTH = "1" *) 
  (* C_PROBE852_MU_CNT = "1" *) 
  (* C_PROBE852_TYPE = "1" *) 
  (* C_PROBE852_WIDTH = "1" *) 
  (* C_PROBE853_MU_CNT = "1" *) 
  (* C_PROBE853_TYPE = "1" *) 
  (* C_PROBE853_WIDTH = "1" *) 
  (* C_PROBE854_MU_CNT = "1" *) 
  (* C_PROBE854_TYPE = "1" *) 
  (* C_PROBE854_WIDTH = "1" *) 
  (* C_PROBE855_MU_CNT = "1" *) 
  (* C_PROBE855_TYPE = "1" *) 
  (* C_PROBE855_WIDTH = "1" *) 
  (* C_PROBE856_MU_CNT = "1" *) 
  (* C_PROBE856_TYPE = "1" *) 
  (* C_PROBE856_WIDTH = "1" *) 
  (* C_PROBE857_MU_CNT = "1" *) 
  (* C_PROBE857_TYPE = "1" *) 
  (* C_PROBE857_WIDTH = "1" *) 
  (* C_PROBE858_MU_CNT = "1" *) 
  (* C_PROBE858_TYPE = "1" *) 
  (* C_PROBE858_WIDTH = "1" *) 
  (* C_PROBE859_MU_CNT = "1" *) 
  (* C_PROBE859_TYPE = "1" *) 
  (* C_PROBE859_WIDTH = "1" *) 
  (* C_PROBE85_MU_CNT = "1" *) 
  (* C_PROBE85_TYPE = "1" *) 
  (* C_PROBE85_WIDTH = "1" *) 
  (* C_PROBE860_MU_CNT = "1" *) 
  (* C_PROBE860_TYPE = "1" *) 
  (* C_PROBE860_WIDTH = "1" *) 
  (* C_PROBE861_MU_CNT = "1" *) 
  (* C_PROBE861_TYPE = "1" *) 
  (* C_PROBE861_WIDTH = "1" *) 
  (* C_PROBE862_MU_CNT = "1" *) 
  (* C_PROBE862_TYPE = "1" *) 
  (* C_PROBE862_WIDTH = "1" *) 
  (* C_PROBE863_MU_CNT = "1" *) 
  (* C_PROBE863_TYPE = "1" *) 
  (* C_PROBE863_WIDTH = "1" *) 
  (* C_PROBE864_MU_CNT = "1" *) 
  (* C_PROBE864_TYPE = "1" *) 
  (* C_PROBE864_WIDTH = "1" *) 
  (* C_PROBE865_MU_CNT = "1" *) 
  (* C_PROBE865_TYPE = "1" *) 
  (* C_PROBE865_WIDTH = "1" *) 
  (* C_PROBE866_MU_CNT = "1" *) 
  (* C_PROBE866_TYPE = "1" *) 
  (* C_PROBE866_WIDTH = "1" *) 
  (* C_PROBE867_MU_CNT = "1" *) 
  (* C_PROBE867_TYPE = "1" *) 
  (* C_PROBE867_WIDTH = "1" *) 
  (* C_PROBE868_MU_CNT = "1" *) 
  (* C_PROBE868_TYPE = "1" *) 
  (* C_PROBE868_WIDTH = "1" *) 
  (* C_PROBE869_MU_CNT = "1" *) 
  (* C_PROBE869_TYPE = "1" *) 
  (* C_PROBE869_WIDTH = "1" *) 
  (* C_PROBE86_MU_CNT = "1" *) 
  (* C_PROBE86_TYPE = "1" *) 
  (* C_PROBE86_WIDTH = "1" *) 
  (* C_PROBE870_MU_CNT = "1" *) 
  (* C_PROBE870_TYPE = "1" *) 
  (* C_PROBE870_WIDTH = "1" *) 
  (* C_PROBE871_MU_CNT = "1" *) 
  (* C_PROBE871_TYPE = "1" *) 
  (* C_PROBE871_WIDTH = "1" *) 
  (* C_PROBE872_MU_CNT = "1" *) 
  (* C_PROBE872_TYPE = "1" *) 
  (* C_PROBE872_WIDTH = "1" *) 
  (* C_PROBE873_MU_CNT = "1" *) 
  (* C_PROBE873_TYPE = "1" *) 
  (* C_PROBE873_WIDTH = "1" *) 
  (* C_PROBE874_MU_CNT = "1" *) 
  (* C_PROBE874_TYPE = "1" *) 
  (* C_PROBE874_WIDTH = "1" *) 
  (* C_PROBE875_MU_CNT = "1" *) 
  (* C_PROBE875_TYPE = "1" *) 
  (* C_PROBE875_WIDTH = "1" *) 
  (* C_PROBE876_MU_CNT = "1" *) 
  (* C_PROBE876_TYPE = "1" *) 
  (* C_PROBE876_WIDTH = "1" *) 
  (* C_PROBE877_MU_CNT = "1" *) 
  (* C_PROBE877_TYPE = "1" *) 
  (* C_PROBE877_WIDTH = "1" *) 
  (* C_PROBE878_MU_CNT = "1" *) 
  (* C_PROBE878_TYPE = "1" *) 
  (* C_PROBE878_WIDTH = "1" *) 
  (* C_PROBE879_MU_CNT = "1" *) 
  (* C_PROBE879_TYPE = "1" *) 
  (* C_PROBE879_WIDTH = "1" *) 
  (* C_PROBE87_MU_CNT = "1" *) 
  (* C_PROBE87_TYPE = "1" *) 
  (* C_PROBE87_WIDTH = "1" *) 
  (* C_PROBE880_MU_CNT = "1" *) 
  (* C_PROBE880_TYPE = "1" *) 
  (* C_PROBE880_WIDTH = "1" *) 
  (* C_PROBE881_MU_CNT = "1" *) 
  (* C_PROBE881_TYPE = "1" *) 
  (* C_PROBE881_WIDTH = "1" *) 
  (* C_PROBE882_MU_CNT = "1" *) 
  (* C_PROBE882_TYPE = "1" *) 
  (* C_PROBE882_WIDTH = "1" *) 
  (* C_PROBE883_MU_CNT = "1" *) 
  (* C_PROBE883_TYPE = "1" *) 
  (* C_PROBE883_WIDTH = "1" *) 
  (* C_PROBE884_MU_CNT = "1" *) 
  (* C_PROBE884_TYPE = "1" *) 
  (* C_PROBE884_WIDTH = "1" *) 
  (* C_PROBE885_MU_CNT = "1" *) 
  (* C_PROBE885_TYPE = "1" *) 
  (* C_PROBE885_WIDTH = "1" *) 
  (* C_PROBE886_MU_CNT = "1" *) 
  (* C_PROBE886_TYPE = "1" *) 
  (* C_PROBE886_WIDTH = "1" *) 
  (* C_PROBE887_MU_CNT = "1" *) 
  (* C_PROBE887_TYPE = "1" *) 
  (* C_PROBE887_WIDTH = "1" *) 
  (* C_PROBE888_MU_CNT = "1" *) 
  (* C_PROBE888_TYPE = "1" *) 
  (* C_PROBE888_WIDTH = "1" *) 
  (* C_PROBE889_MU_CNT = "1" *) 
  (* C_PROBE889_TYPE = "1" *) 
  (* C_PROBE889_WIDTH = "1" *) 
  (* C_PROBE88_MU_CNT = "1" *) 
  (* C_PROBE88_TYPE = "1" *) 
  (* C_PROBE88_WIDTH = "1" *) 
  (* C_PROBE890_MU_CNT = "1" *) 
  (* C_PROBE890_TYPE = "1" *) 
  (* C_PROBE890_WIDTH = "1" *) 
  (* C_PROBE891_MU_CNT = "1" *) 
  (* C_PROBE891_TYPE = "1" *) 
  (* C_PROBE891_WIDTH = "1" *) 
  (* C_PROBE892_MU_CNT = "1" *) 
  (* C_PROBE892_TYPE = "1" *) 
  (* C_PROBE892_WIDTH = "1" *) 
  (* C_PROBE893_MU_CNT = "1" *) 
  (* C_PROBE893_TYPE = "1" *) 
  (* C_PROBE893_WIDTH = "1" *) 
  (* C_PROBE894_MU_CNT = "1" *) 
  (* C_PROBE894_TYPE = "1" *) 
  (* C_PROBE894_WIDTH = "1" *) 
  (* C_PROBE895_MU_CNT = "1" *) 
  (* C_PROBE895_TYPE = "1" *) 
  (* C_PROBE895_WIDTH = "1" *) 
  (* C_PROBE896_MU_CNT = "1" *) 
  (* C_PROBE896_TYPE = "1" *) 
  (* C_PROBE896_WIDTH = "1" *) 
  (* C_PROBE897_MU_CNT = "1" *) 
  (* C_PROBE897_TYPE = "1" *) 
  (* C_PROBE897_WIDTH = "1" *) 
  (* C_PROBE898_MU_CNT = "1" *) 
  (* C_PROBE898_TYPE = "1" *) 
  (* C_PROBE898_WIDTH = "1" *) 
  (* C_PROBE899_MU_CNT = "1" *) 
  (* C_PROBE899_TYPE = "1" *) 
  (* C_PROBE899_WIDTH = "1" *) 
  (* C_PROBE89_MU_CNT = "1" *) 
  (* C_PROBE89_TYPE = "1" *) 
  (* C_PROBE89_WIDTH = "1" *) 
  (* C_PROBE8_MU_CNT = "1" *) 
  (* C_PROBE8_TYPE = "1" *) 
  (* C_PROBE8_WIDTH = "1" *) 
  (* C_PROBE900_MU_CNT = "1" *) 
  (* C_PROBE900_TYPE = "1" *) 
  (* C_PROBE900_WIDTH = "1" *) 
  (* C_PROBE901_MU_CNT = "1" *) 
  (* C_PROBE901_TYPE = "1" *) 
  (* C_PROBE901_WIDTH = "1" *) 
  (* C_PROBE902_MU_CNT = "1" *) 
  (* C_PROBE902_TYPE = "1" *) 
  (* C_PROBE902_WIDTH = "1" *) 
  (* C_PROBE903_MU_CNT = "1" *) 
  (* C_PROBE903_TYPE = "1" *) 
  (* C_PROBE903_WIDTH = "1" *) 
  (* C_PROBE904_MU_CNT = "1" *) 
  (* C_PROBE904_TYPE = "1" *) 
  (* C_PROBE904_WIDTH = "1" *) 
  (* C_PROBE905_MU_CNT = "1" *) 
  (* C_PROBE905_TYPE = "1" *) 
  (* C_PROBE905_WIDTH = "1" *) 
  (* C_PROBE906_MU_CNT = "1" *) 
  (* C_PROBE906_TYPE = "1" *) 
  (* C_PROBE906_WIDTH = "1" *) 
  (* C_PROBE907_MU_CNT = "1" *) 
  (* C_PROBE907_TYPE = "1" *) 
  (* C_PROBE907_WIDTH = "1" *) 
  (* C_PROBE908_MU_CNT = "1" *) 
  (* C_PROBE908_TYPE = "1" *) 
  (* C_PROBE908_WIDTH = "1" *) 
  (* C_PROBE909_MU_CNT = "1" *) 
  (* C_PROBE909_TYPE = "1" *) 
  (* C_PROBE909_WIDTH = "1" *) 
  (* C_PROBE90_MU_CNT = "1" *) 
  (* C_PROBE90_TYPE = "1" *) 
  (* C_PROBE90_WIDTH = "1" *) 
  (* C_PROBE910_MU_CNT = "1" *) 
  (* C_PROBE910_TYPE = "1" *) 
  (* C_PROBE910_WIDTH = "1" *) 
  (* C_PROBE911_MU_CNT = "1" *) 
  (* C_PROBE911_TYPE = "1" *) 
  (* C_PROBE911_WIDTH = "1" *) 
  (* C_PROBE912_MU_CNT = "1" *) 
  (* C_PROBE912_TYPE = "1" *) 
  (* C_PROBE912_WIDTH = "1" *) 
  (* C_PROBE913_MU_CNT = "1" *) 
  (* C_PROBE913_TYPE = "1" *) 
  (* C_PROBE913_WIDTH = "1" *) 
  (* C_PROBE914_MU_CNT = "1" *) 
  (* C_PROBE914_TYPE = "1" *) 
  (* C_PROBE914_WIDTH = "1" *) 
  (* C_PROBE915_MU_CNT = "1" *) 
  (* C_PROBE915_TYPE = "1" *) 
  (* C_PROBE915_WIDTH = "1" *) 
  (* C_PROBE916_MU_CNT = "1" *) 
  (* C_PROBE916_TYPE = "1" *) 
  (* C_PROBE916_WIDTH = "1" *) 
  (* C_PROBE917_MU_CNT = "1" *) 
  (* C_PROBE917_TYPE = "1" *) 
  (* C_PROBE917_WIDTH = "1" *) 
  (* C_PROBE918_MU_CNT = "1" *) 
  (* C_PROBE918_TYPE = "1" *) 
  (* C_PROBE918_WIDTH = "1" *) 
  (* C_PROBE919_MU_CNT = "1" *) 
  (* C_PROBE919_TYPE = "1" *) 
  (* C_PROBE919_WIDTH = "1" *) 
  (* C_PROBE91_MU_CNT = "1" *) 
  (* C_PROBE91_TYPE = "1" *) 
  (* C_PROBE91_WIDTH = "1" *) 
  (* C_PROBE920_MU_CNT = "1" *) 
  (* C_PROBE920_TYPE = "1" *) 
  (* C_PROBE920_WIDTH = "1" *) 
  (* C_PROBE921_MU_CNT = "1" *) 
  (* C_PROBE921_TYPE = "1" *) 
  (* C_PROBE921_WIDTH = "1" *) 
  (* C_PROBE922_MU_CNT = "1" *) 
  (* C_PROBE922_TYPE = "1" *) 
  (* C_PROBE922_WIDTH = "1" *) 
  (* C_PROBE923_MU_CNT = "1" *) 
  (* C_PROBE923_TYPE = "1" *) 
  (* C_PROBE923_WIDTH = "1" *) 
  (* C_PROBE924_MU_CNT = "1" *) 
  (* C_PROBE924_TYPE = "1" *) 
  (* C_PROBE924_WIDTH = "1" *) 
  (* C_PROBE925_MU_CNT = "1" *) 
  (* C_PROBE925_TYPE = "1" *) 
  (* C_PROBE925_WIDTH = "1" *) 
  (* C_PROBE926_MU_CNT = "1" *) 
  (* C_PROBE926_TYPE = "1" *) 
  (* C_PROBE926_WIDTH = "1" *) 
  (* C_PROBE927_MU_CNT = "1" *) 
  (* C_PROBE927_TYPE = "1" *) 
  (* C_PROBE927_WIDTH = "1" *) 
  (* C_PROBE928_MU_CNT = "1" *) 
  (* C_PROBE928_TYPE = "1" *) 
  (* C_PROBE928_WIDTH = "1" *) 
  (* C_PROBE929_MU_CNT = "1" *) 
  (* C_PROBE929_TYPE = "1" *) 
  (* C_PROBE929_WIDTH = "1" *) 
  (* C_PROBE92_MU_CNT = "1" *) 
  (* C_PROBE92_TYPE = "1" *) 
  (* C_PROBE92_WIDTH = "1" *) 
  (* C_PROBE930_MU_CNT = "1" *) 
  (* C_PROBE930_TYPE = "1" *) 
  (* C_PROBE930_WIDTH = "1" *) 
  (* C_PROBE931_MU_CNT = "1" *) 
  (* C_PROBE931_TYPE = "1" *) 
  (* C_PROBE931_WIDTH = "1" *) 
  (* C_PROBE932_MU_CNT = "1" *) 
  (* C_PROBE932_TYPE = "1" *) 
  (* C_PROBE932_WIDTH = "1" *) 
  (* C_PROBE933_MU_CNT = "1" *) 
  (* C_PROBE933_TYPE = "1" *) 
  (* C_PROBE933_WIDTH = "1" *) 
  (* C_PROBE934_MU_CNT = "1" *) 
  (* C_PROBE934_TYPE = "1" *) 
  (* C_PROBE934_WIDTH = "1" *) 
  (* C_PROBE935_MU_CNT = "1" *) 
  (* C_PROBE935_TYPE = "1" *) 
  (* C_PROBE935_WIDTH = "1" *) 
  (* C_PROBE936_MU_CNT = "1" *) 
  (* C_PROBE936_TYPE = "1" *) 
  (* C_PROBE936_WIDTH = "1" *) 
  (* C_PROBE937_MU_CNT = "1" *) 
  (* C_PROBE937_TYPE = "1" *) 
  (* C_PROBE937_WIDTH = "1" *) 
  (* C_PROBE938_MU_CNT = "1" *) 
  (* C_PROBE938_TYPE = "1" *) 
  (* C_PROBE938_WIDTH = "1" *) 
  (* C_PROBE939_MU_CNT = "1" *) 
  (* C_PROBE939_TYPE = "1" *) 
  (* C_PROBE939_WIDTH = "1" *) 
  (* C_PROBE93_MU_CNT = "1" *) 
  (* C_PROBE93_TYPE = "1" *) 
  (* C_PROBE93_WIDTH = "1" *) 
  (* C_PROBE940_MU_CNT = "1" *) 
  (* C_PROBE940_TYPE = "1" *) 
  (* C_PROBE940_WIDTH = "1" *) 
  (* C_PROBE941_MU_CNT = "1" *) 
  (* C_PROBE941_TYPE = "1" *) 
  (* C_PROBE941_WIDTH = "1" *) 
  (* C_PROBE942_MU_CNT = "1" *) 
  (* C_PROBE942_TYPE = "1" *) 
  (* C_PROBE942_WIDTH = "1" *) 
  (* C_PROBE943_MU_CNT = "1" *) 
  (* C_PROBE943_TYPE = "1" *) 
  (* C_PROBE943_WIDTH = "1" *) 
  (* C_PROBE944_MU_CNT = "1" *) 
  (* C_PROBE944_TYPE = "1" *) 
  (* C_PROBE944_WIDTH = "1" *) 
  (* C_PROBE945_MU_CNT = "1" *) 
  (* C_PROBE945_TYPE = "1" *) 
  (* C_PROBE945_WIDTH = "1" *) 
  (* C_PROBE946_MU_CNT = "1" *) 
  (* C_PROBE946_TYPE = "1" *) 
  (* C_PROBE946_WIDTH = "1" *) 
  (* C_PROBE947_MU_CNT = "1" *) 
  (* C_PROBE947_TYPE = "1" *) 
  (* C_PROBE947_WIDTH = "1" *) 
  (* C_PROBE948_MU_CNT = "1" *) 
  (* C_PROBE948_TYPE = "1" *) 
  (* C_PROBE948_WIDTH = "1" *) 
  (* C_PROBE949_MU_CNT = "1" *) 
  (* C_PROBE949_TYPE = "1" *) 
  (* C_PROBE949_WIDTH = "1" *) 
  (* C_PROBE94_MU_CNT = "1" *) 
  (* C_PROBE94_TYPE = "1" *) 
  (* C_PROBE94_WIDTH = "1" *) 
  (* C_PROBE950_MU_CNT = "1" *) 
  (* C_PROBE950_TYPE = "1" *) 
  (* C_PROBE950_WIDTH = "1" *) 
  (* C_PROBE951_MU_CNT = "1" *) 
  (* C_PROBE951_TYPE = "1" *) 
  (* C_PROBE951_WIDTH = "1" *) 
  (* C_PROBE952_MU_CNT = "1" *) 
  (* C_PROBE952_TYPE = "1" *) 
  (* C_PROBE952_WIDTH = "1" *) 
  (* C_PROBE953_MU_CNT = "1" *) 
  (* C_PROBE953_TYPE = "1" *) 
  (* C_PROBE953_WIDTH = "1" *) 
  (* C_PROBE954_MU_CNT = "1" *) 
  (* C_PROBE954_TYPE = "1" *) 
  (* C_PROBE954_WIDTH = "1" *) 
  (* C_PROBE955_MU_CNT = "1" *) 
  (* C_PROBE955_TYPE = "1" *) 
  (* C_PROBE955_WIDTH = "1" *) 
  (* C_PROBE956_MU_CNT = "1" *) 
  (* C_PROBE956_TYPE = "1" *) 
  (* C_PROBE956_WIDTH = "1" *) 
  (* C_PROBE957_MU_CNT = "1" *) 
  (* C_PROBE957_TYPE = "1" *) 
  (* C_PROBE957_WIDTH = "1" *) 
  (* C_PROBE958_MU_CNT = "1" *) 
  (* C_PROBE958_TYPE = "1" *) 
  (* C_PROBE958_WIDTH = "1" *) 
  (* C_PROBE959_MU_CNT = "1" *) 
  (* C_PROBE959_TYPE = "1" *) 
  (* C_PROBE959_WIDTH = "1" *) 
  (* C_PROBE95_MU_CNT = "1" *) 
  (* C_PROBE95_TYPE = "1" *) 
  (* C_PROBE95_WIDTH = "1" *) 
  (* C_PROBE960_MU_CNT = "1" *) 
  (* C_PROBE960_TYPE = "1" *) 
  (* C_PROBE960_WIDTH = "1" *) 
  (* C_PROBE961_MU_CNT = "1" *) 
  (* C_PROBE961_TYPE = "1" *) 
  (* C_PROBE961_WIDTH = "1" *) 
  (* C_PROBE962_MU_CNT = "1" *) 
  (* C_PROBE962_TYPE = "1" *) 
  (* C_PROBE962_WIDTH = "1" *) 
  (* C_PROBE963_MU_CNT = "1" *) 
  (* C_PROBE963_TYPE = "1" *) 
  (* C_PROBE963_WIDTH = "1" *) 
  (* C_PROBE964_MU_CNT = "1" *) 
  (* C_PROBE964_TYPE = "1" *) 
  (* C_PROBE964_WIDTH = "1" *) 
  (* C_PROBE965_MU_CNT = "1" *) 
  (* C_PROBE965_TYPE = "1" *) 
  (* C_PROBE965_WIDTH = "1" *) 
  (* C_PROBE966_MU_CNT = "1" *) 
  (* C_PROBE966_TYPE = "1" *) 
  (* C_PROBE966_WIDTH = "1" *) 
  (* C_PROBE967_MU_CNT = "1" *) 
  (* C_PROBE967_TYPE = "1" *) 
  (* C_PROBE967_WIDTH = "1" *) 
  (* C_PROBE968_MU_CNT = "1" *) 
  (* C_PROBE968_TYPE = "1" *) 
  (* C_PROBE968_WIDTH = "1" *) 
  (* C_PROBE969_MU_CNT = "1" *) 
  (* C_PROBE969_TYPE = "1" *) 
  (* C_PROBE969_WIDTH = "1" *) 
  (* C_PROBE96_MU_CNT = "1" *) 
  (* C_PROBE96_TYPE = "1" *) 
  (* C_PROBE96_WIDTH = "1" *) 
  (* C_PROBE970_MU_CNT = "1" *) 
  (* C_PROBE970_TYPE = "1" *) 
  (* C_PROBE970_WIDTH = "1" *) 
  (* C_PROBE971_MU_CNT = "1" *) 
  (* C_PROBE971_TYPE = "1" *) 
  (* C_PROBE971_WIDTH = "1" *) 
  (* C_PROBE972_MU_CNT = "1" *) 
  (* C_PROBE972_TYPE = "1" *) 
  (* C_PROBE972_WIDTH = "1" *) 
  (* C_PROBE973_MU_CNT = "1" *) 
  (* C_PROBE973_TYPE = "1" *) 
  (* C_PROBE973_WIDTH = "1" *) 
  (* C_PROBE974_MU_CNT = "1" *) 
  (* C_PROBE974_TYPE = "1" *) 
  (* C_PROBE974_WIDTH = "1" *) 
  (* C_PROBE975_MU_CNT = "1" *) 
  (* C_PROBE975_TYPE = "1" *) 
  (* C_PROBE975_WIDTH = "1" *) 
  (* C_PROBE976_MU_CNT = "1" *) 
  (* C_PROBE976_TYPE = "1" *) 
  (* C_PROBE976_WIDTH = "1" *) 
  (* C_PROBE977_MU_CNT = "1" *) 
  (* C_PROBE977_TYPE = "1" *) 
  (* C_PROBE977_WIDTH = "1" *) 
  (* C_PROBE978_MU_CNT = "1" *) 
  (* C_PROBE978_TYPE = "1" *) 
  (* C_PROBE978_WIDTH = "1" *) 
  (* C_PROBE979_MU_CNT = "1" *) 
  (* C_PROBE979_TYPE = "1" *) 
  (* C_PROBE979_WIDTH = "1" *) 
  (* C_PROBE97_MU_CNT = "1" *) 
  (* C_PROBE97_TYPE = "1" *) 
  (* C_PROBE97_WIDTH = "1" *) 
  (* C_PROBE980_MU_CNT = "1" *) 
  (* C_PROBE980_TYPE = "1" *) 
  (* C_PROBE980_WIDTH = "1" *) 
  (* C_PROBE981_MU_CNT = "1" *) 
  (* C_PROBE981_TYPE = "1" *) 
  (* C_PROBE981_WIDTH = "1" *) 
  (* C_PROBE982_MU_CNT = "1" *) 
  (* C_PROBE982_TYPE = "1" *) 
  (* C_PROBE982_WIDTH = "1" *) 
  (* C_PROBE983_MU_CNT = "1" *) 
  (* C_PROBE983_TYPE = "1" *) 
  (* C_PROBE983_WIDTH = "1" *) 
  (* C_PROBE984_MU_CNT = "1" *) 
  (* C_PROBE984_TYPE = "1" *) 
  (* C_PROBE984_WIDTH = "1" *) 
  (* C_PROBE985_MU_CNT = "1" *) 
  (* C_PROBE985_TYPE = "1" *) 
  (* C_PROBE985_WIDTH = "1" *) 
  (* C_PROBE986_MU_CNT = "1" *) 
  (* C_PROBE986_TYPE = "1" *) 
  (* C_PROBE986_WIDTH = "1" *) 
  (* C_PROBE987_MU_CNT = "1" *) 
  (* C_PROBE987_TYPE = "1" *) 
  (* C_PROBE987_WIDTH = "1" *) 
  (* C_PROBE988_MU_CNT = "1" *) 
  (* C_PROBE988_TYPE = "1" *) 
  (* C_PROBE988_WIDTH = "1" *) 
  (* C_PROBE989_MU_CNT = "1" *) 
  (* C_PROBE989_TYPE = "1" *) 
  (* C_PROBE989_WIDTH = "1" *) 
  (* C_PROBE98_MU_CNT = "1" *) 
  (* C_PROBE98_TYPE = "1" *) 
  (* C_PROBE98_WIDTH = "1" *) 
  (* C_PROBE990_MU_CNT = "1" *) 
  (* C_PROBE990_TYPE = "1" *) 
  (* C_PROBE990_WIDTH = "1" *) 
  (* C_PROBE991_MU_CNT = "1" *) 
  (* C_PROBE991_TYPE = "1" *) 
  (* C_PROBE991_WIDTH = "1" *) 
  (* C_PROBE992_MU_CNT = "1" *) 
  (* C_PROBE992_TYPE = "1" *) 
  (* C_PROBE992_WIDTH = "1" *) 
  (* C_PROBE993_MU_CNT = "1" *) 
  (* C_PROBE993_TYPE = "1" *) 
  (* C_PROBE993_WIDTH = "1" *) 
  (* C_PROBE994_MU_CNT = "1" *) 
  (* C_PROBE994_TYPE = "1" *) 
  (* C_PROBE994_WIDTH = "1" *) 
  (* C_PROBE995_MU_CNT = "1" *) 
  (* C_PROBE995_TYPE = "1" *) 
  (* C_PROBE995_WIDTH = "1" *) 
  (* C_PROBE996_MU_CNT = "1" *) 
  (* C_PROBE996_TYPE = "1" *) 
  (* C_PROBE996_WIDTH = "1" *) 
  (* C_PROBE997_MU_CNT = "1" *) 
  (* C_PROBE997_TYPE = "1" *) 
  (* C_PROBE997_WIDTH = "1" *) 
  (* C_PROBE998_MU_CNT = "1" *) 
  (* C_PROBE998_TYPE = "1" *) 
  (* C_PROBE998_WIDTH = "1" *) 
  (* C_PROBE999_MU_CNT = "1" *) 
  (* C_PROBE999_TYPE = "1" *) 
  (* C_PROBE999_WIDTH = "1" *) 
  (* C_PROBE99_MU_CNT = "1" *) 
  (* C_PROBE99_TYPE = "1" *) 
  (* C_PROBE99_WIDTH = "1" *) 
  (* C_PROBE9_MU_CNT = "1" *) 
  (* C_PROBE9_TYPE = "1" *) 
  (* C_PROBE9_WIDTH = "1" *) 
  (* C_RAM_STYLE = "SUBCORE" *) 
  (* C_SLOT_0_AXIS_TDEST_WIDTH = "1" *) 
  (* C_SLOT_0_AXIS_TID_WIDTH = "1" *) 
  (* C_SLOT_0_AXIS_TUSER_WIDTH = "1" *) 
  (* C_SLOT_0_AXI_ARUSER_WIDTH = "1" *) 
  (* C_SLOT_0_AXI_AWUSER_WIDTH = "1" *) 
  (* C_SLOT_0_AXI_BUSER_WIDTH = "1" *) 
  (* C_SLOT_0_AXI_ID_WIDTH = "1" *) 
  (* C_SLOT_0_AXI_PROTOCOL = "AXI4" *) 
  (* C_SLOT_0_AXI_RUSER_WIDTH = "1" *) 
  (* C_SLOT_0_AXI_WUSER_WIDTH = "1" *) 
  (* C_TC_TYPE = "0" *) 
  (* C_TIME_TAG_WIDTH = "32" *) 
  (* C_TRIGIN_EN = "0" *) 
  (* C_TRIGOUT_EN = "0" *) 
  (* C_USE_TEST_REG = "1" *) 
  (* C_XDEVICEFAMILY = "zynq" *) 
  (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) 
  (* C_XLNX_HW_PROBE_INFO_DUMMY1 = "DEFAULT" *) 
  (* C_XLNX_HW_PROBE_INFO_DUMMY2 = "DEFAULT" *) 
  (* C_XLNX_HW_PROBE_INFO_DUMMY3 = "DEFAULT" *) 
  (* C_XLNX_HW_PROBE_INFO_DUMMY4 = "DEFAULT" *) 
  (* C_XSDB_SLAVE_TYPE = "17" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* IS_DEBUG_CORE = "TRUE" *) 
  (* LC_COMPUTED_DATA_WIDTH = "65" *) 
  (* LC_DATA_WIDTH = "65" *) 
  (* LC_MATCH_TPID_VEC = "3072'b000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000100000000000000010000000000000001000000000000000010000000000000001000000000000000100000000000000010000000000000000000000000000000000000000000000000000000000000000" *) 
  (* LC_MU_CNT_STRING = "4096' " *) 
  (* LC_MU_COUNT = "12" *) 
  (* LC_MU_COUNT_EN = "12" *) 
  (* LC_NUM_OF_PROBES = "3" *) 
  (* LC_NUM_PROBES = "3" *) 
  (* LC_NUM_TRIG_EQS = "32" *) 
  (* LC_PROBE0_IS_DATA = "1'b1" *) 
  (* LC_PROBE0_IS_TRIG = "4'b1111" *) 
  (* LC_PROBE0_MU_CNT = "4" *) 
  (* LC_PROBE0_PID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* LC_PROBE0_TYPE = "0" *) 
  (* LC_PROBE0_WIDTH = "21" *) 
  (* LC_PROBE1000_IS_DATA = "1'b0" *) 
  (* LC_PROBE1000_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1000_MU_CNT = "1" *) 
  (* LC_PROBE1000_PID = "16'b0000001111101000" *) 
  (* LC_PROBE1000_TYPE = "1" *) 
  (* LC_PROBE1000_WIDTH = "1" *) 
  (* LC_PROBE1001_IS_DATA = "1'b0" *) 
  (* LC_PROBE1001_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1001_MU_CNT = "1" *) 
  (* LC_PROBE1001_PID = "16'b0000001111101001" *) 
  (* LC_PROBE1001_TYPE = "1" *) 
  (* LC_PROBE1001_WIDTH = "1" *) 
  (* LC_PROBE1002_IS_DATA = "1'b0" *) 
  (* LC_PROBE1002_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1002_MU_CNT = "1" *) 
  (* LC_PROBE1002_PID = "16'b0000001111101010" *) 
  (* LC_PROBE1002_TYPE = "1" *) 
  (* LC_PROBE1002_WIDTH = "1" *) 
  (* LC_PROBE1003_IS_DATA = "1'b0" *) 
  (* LC_PROBE1003_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1003_MU_CNT = "1" *) 
  (* LC_PROBE1003_PID = "16'b0000001111101011" *) 
  (* LC_PROBE1003_TYPE = "1" *) 
  (* LC_PROBE1003_WIDTH = "1" *) 
  (* LC_PROBE1004_IS_DATA = "1'b0" *) 
  (* LC_PROBE1004_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1004_MU_CNT = "1" *) 
  (* LC_PROBE1004_PID = "16'b0000001111101100" *) 
  (* LC_PROBE1004_TYPE = "1" *) 
  (* LC_PROBE1004_WIDTH = "1" *) 
  (* LC_PROBE1005_IS_DATA = "1'b0" *) 
  (* LC_PROBE1005_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1005_MU_CNT = "1" *) 
  (* LC_PROBE1005_PID = "16'b0000001111101101" *) 
  (* LC_PROBE1005_TYPE = "1" *) 
  (* LC_PROBE1005_WIDTH = "1" *) 
  (* LC_PROBE1006_IS_DATA = "1'b0" *) 
  (* LC_PROBE1006_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1006_MU_CNT = "1" *) 
  (* LC_PROBE1006_PID = "16'b0000001111101110" *) 
  (* LC_PROBE1006_TYPE = "1" *) 
  (* LC_PROBE1006_WIDTH = "1" *) 
  (* LC_PROBE1007_IS_DATA = "1'b0" *) 
  (* LC_PROBE1007_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1007_MU_CNT = "1" *) 
  (* LC_PROBE1007_PID = "16'b0000001111101111" *) 
  (* LC_PROBE1007_TYPE = "1" *) 
  (* LC_PROBE1007_WIDTH = "1" *) 
  (* LC_PROBE1008_IS_DATA = "1'b0" *) 
  (* LC_PROBE1008_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1008_MU_CNT = "1" *) 
  (* LC_PROBE1008_PID = "16'b0000001111110000" *) 
  (* LC_PROBE1008_TYPE = "1" *) 
  (* LC_PROBE1008_WIDTH = "1" *) 
  (* LC_PROBE1009_IS_DATA = "1'b0" *) 
  (* LC_PROBE1009_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1009_MU_CNT = "1" *) 
  (* LC_PROBE1009_PID = "16'b0000001111110001" *) 
  (* LC_PROBE1009_TYPE = "1" *) 
  (* LC_PROBE1009_WIDTH = "1" *) 
  (* LC_PROBE100_IS_DATA = "1'b0" *) 
  (* LC_PROBE100_IS_TRIG = "1'b0" *) 
  (* LC_PROBE100_MU_CNT = "1" *) 
  (* LC_PROBE100_PID = "16'b0000000001100100" *) 
  (* LC_PROBE100_TYPE = "1" *) 
  (* LC_PROBE100_WIDTH = "1" *) 
  (* LC_PROBE1010_IS_DATA = "1'b0" *) 
  (* LC_PROBE1010_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1010_MU_CNT = "1" *) 
  (* LC_PROBE1010_PID = "16'b0000001111110010" *) 
  (* LC_PROBE1010_TYPE = "1" *) 
  (* LC_PROBE1010_WIDTH = "1" *) 
  (* LC_PROBE1011_IS_DATA = "1'b0" *) 
  (* LC_PROBE1011_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1011_MU_CNT = "1" *) 
  (* LC_PROBE1011_PID = "16'b0000001111110011" *) 
  (* LC_PROBE1011_TYPE = "1" *) 
  (* LC_PROBE1011_WIDTH = "1" *) 
  (* LC_PROBE1012_IS_DATA = "1'b0" *) 
  (* LC_PROBE1012_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1012_MU_CNT = "1" *) 
  (* LC_PROBE1012_PID = "16'b0000001111110100" *) 
  (* LC_PROBE1012_TYPE = "1" *) 
  (* LC_PROBE1012_WIDTH = "1" *) 
  (* LC_PROBE1013_IS_DATA = "1'b0" *) 
  (* LC_PROBE1013_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1013_MU_CNT = "1" *) 
  (* LC_PROBE1013_PID = "16'b0000001111110101" *) 
  (* LC_PROBE1013_TYPE = "1" *) 
  (* LC_PROBE1013_WIDTH = "1" *) 
  (* LC_PROBE1014_IS_DATA = "1'b0" *) 
  (* LC_PROBE1014_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1014_MU_CNT = "1" *) 
  (* LC_PROBE1014_PID = "16'b0000001111110110" *) 
  (* LC_PROBE1014_TYPE = "1" *) 
  (* LC_PROBE1014_WIDTH = "1" *) 
  (* LC_PROBE1015_IS_DATA = "1'b0" *) 
  (* LC_PROBE1015_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1015_MU_CNT = "1" *) 
  (* LC_PROBE1015_PID = "16'b0000001111110111" *) 
  (* LC_PROBE1015_TYPE = "1" *) 
  (* LC_PROBE1015_WIDTH = "1" *) 
  (* LC_PROBE1016_IS_DATA = "1'b0" *) 
  (* LC_PROBE1016_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1016_MU_CNT = "1" *) 
  (* LC_PROBE1016_PID = "16'b0000001111111000" *) 
  (* LC_PROBE1016_TYPE = "1" *) 
  (* LC_PROBE1016_WIDTH = "1" *) 
  (* LC_PROBE1017_IS_DATA = "1'b0" *) 
  (* LC_PROBE1017_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1017_MU_CNT = "1" *) 
  (* LC_PROBE1017_PID = "16'b0000001111111001" *) 
  (* LC_PROBE1017_TYPE = "1" *) 
  (* LC_PROBE1017_WIDTH = "1" *) 
  (* LC_PROBE1018_IS_DATA = "1'b0" *) 
  (* LC_PROBE1018_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1018_MU_CNT = "1" *) 
  (* LC_PROBE1018_PID = "16'b0000001111111010" *) 
  (* LC_PROBE1018_TYPE = "1" *) 
  (* LC_PROBE1018_WIDTH = "1" *) 
  (* LC_PROBE1019_IS_DATA = "1'b0" *) 
  (* LC_PROBE1019_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1019_MU_CNT = "1" *) 
  (* LC_PROBE1019_PID = "16'b0000001111111011" *) 
  (* LC_PROBE1019_TYPE = "1" *) 
  (* LC_PROBE1019_WIDTH = "1" *) 
  (* LC_PROBE101_IS_DATA = "1'b0" *) 
  (* LC_PROBE101_IS_TRIG = "1'b0" *) 
  (* LC_PROBE101_MU_CNT = "1" *) 
  (* LC_PROBE101_PID = "16'b0000000001100101" *) 
  (* LC_PROBE101_TYPE = "1" *) 
  (* LC_PROBE101_WIDTH = "1" *) 
  (* LC_PROBE1020_IS_DATA = "1'b0" *) 
  (* LC_PROBE1020_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1020_MU_CNT = "1" *) 
  (* LC_PROBE1020_PID = "16'b0000001111111100" *) 
  (* LC_PROBE1020_TYPE = "1" *) 
  (* LC_PROBE1020_WIDTH = "1" *) 
  (* LC_PROBE1021_IS_DATA = "1'b0" *) 
  (* LC_PROBE1021_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1021_MU_CNT = "1" *) 
  (* LC_PROBE1021_PID = "16'b0000001111111101" *) 
  (* LC_PROBE1021_TYPE = "1" *) 
  (* LC_PROBE1021_WIDTH = "1" *) 
  (* LC_PROBE1022_IS_DATA = "1'b0" *) 
  (* LC_PROBE1022_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1022_MU_CNT = "1" *) 
  (* LC_PROBE1022_PID = "16'b0000001111111110" *) 
  (* LC_PROBE1022_TYPE = "1" *) 
  (* LC_PROBE1022_WIDTH = "1" *) 
  (* LC_PROBE1023_IS_DATA = "1'b0" *) 
  (* LC_PROBE1023_IS_TRIG = "1'b0" *) 
  (* LC_PROBE1023_MU_CNT = "1" *) 
  (* LC_PROBE1023_PID = "16'b0000001111111111" *) 
  (* LC_PROBE1023_TYPE = "1" *) 
  (* LC_PROBE1023_WIDTH = "1" *) 
  (* LC_PROBE102_IS_DATA = "1'b0" *) 
  (* LC_PROBE102_IS_TRIG = "1'b0" *) 
  (* LC_PROBE102_MU_CNT = "1" *) 
  (* LC_PROBE102_PID = "16'b0000000001100110" *) 
  (* LC_PROBE102_TYPE = "1" *) 
  (* LC_PROBE102_WIDTH = "1" *) 
  (* LC_PROBE103_IS_DATA = "1'b0" *) 
  (* LC_PROBE103_IS_TRIG = "1'b0" *) 
  (* LC_PROBE103_MU_CNT = "1" *) 
  (* LC_PROBE103_PID = "16'b0000000001100111" *) 
  (* LC_PROBE103_TYPE = "1" *) 
  (* LC_PROBE103_WIDTH = "1" *) 
  (* LC_PROBE104_IS_DATA = "1'b0" *) 
  (* LC_PROBE104_IS_TRIG = "1'b0" *) 
  (* LC_PROBE104_MU_CNT = "1" *) 
  (* LC_PROBE104_PID = "16'b0000000001101000" *) 
  (* LC_PROBE104_TYPE = "1" *) 
  (* LC_PROBE104_WIDTH = "1" *) 
  (* LC_PROBE105_IS_DATA = "1'b0" *) 
  (* LC_PROBE105_IS_TRIG = "1'b0" *) 
  (* LC_PROBE105_MU_CNT = "1" *) 
  (* LC_PROBE105_PID = "16'b0000000001101001" *) 
  (* LC_PROBE105_TYPE = "1" *) 
  (* LC_PROBE105_WIDTH = "1" *) 
  (* LC_PROBE106_IS_DATA = "1'b0" *) 
  (* LC_PROBE106_IS_TRIG = "1'b0" *) 
  (* LC_PROBE106_MU_CNT = "1" *) 
  (* LC_PROBE106_PID = "16'b0000000001101010" *) 
  (* LC_PROBE106_TYPE = "1" *) 
  (* LC_PROBE106_WIDTH = "1" *) 
  (* LC_PROBE107_IS_DATA = "1'b0" *) 
  (* LC_PROBE107_IS_TRIG = "1'b0" *) 
  (* LC_PROBE107_MU_CNT = "1" *) 
  (* LC_PROBE107_PID = "16'b0000000001101011" *) 
  (* LC_PROBE107_TYPE = "1" *) 
  (* LC_PROBE107_WIDTH = "1" *) 
  (* LC_PROBE108_IS_DATA = "1'b0" *) 
  (* LC_PROBE108_IS_TRIG = "1'b0" *) 
  (* LC_PROBE108_MU_CNT = "1" *) 
  (* LC_PROBE108_PID = "16'b0000000001101100" *) 
  (* LC_PROBE108_TYPE = "1" *) 
  (* LC_PROBE108_WIDTH = "1" *) 
  (* LC_PROBE109_IS_DATA = "1'b0" *) 
  (* LC_PROBE109_IS_TRIG = "1'b0" *) 
  (* LC_PROBE109_MU_CNT = "1" *) 
  (* LC_PROBE109_PID = "16'b0000000001101101" *) 
  (* LC_PROBE109_TYPE = "1" *) 
  (* LC_PROBE109_WIDTH = "1" *) 
  (* LC_PROBE10_IS_DATA = "1'b0" *) 
  (* LC_PROBE10_IS_TRIG = "1'b0" *) 
  (* LC_PROBE10_MU_CNT = "1" *) 
  (* LC_PROBE10_PID = "16'b0000000000001010" *) 
  (* LC_PROBE10_TYPE = "1" *) 
  (* LC_PROBE10_WIDTH = "1" *) 
  (* LC_PROBE110_IS_DATA = "1'b0" *) 
  (* LC_PROBE110_IS_TRIG = "1'b0" *) 
  (* LC_PROBE110_MU_CNT = "1" *) 
  (* LC_PROBE110_PID = "16'b0000000001101110" *) 
  (* LC_PROBE110_TYPE = "1" *) 
  (* LC_PROBE110_WIDTH = "1" *) 
  (* LC_PROBE111_IS_DATA = "1'b0" *) 
  (* LC_PROBE111_IS_TRIG = "1'b0" *) 
  (* LC_PROBE111_MU_CNT = "1" *) 
  (* LC_PROBE111_PID = "16'b0000000001101111" *) 
  (* LC_PROBE111_TYPE = "1" *) 
  (* LC_PROBE111_WIDTH = "1" *) 
  (* LC_PROBE112_IS_DATA = "1'b0" *) 
  (* LC_PROBE112_IS_TRIG = "1'b0" *) 
  (* LC_PROBE112_MU_CNT = "1" *) 
  (* LC_PROBE112_PID = "16'b0000000001110000" *) 
  (* LC_PROBE112_TYPE = "1" *) 
  (* LC_PROBE112_WIDTH = "1" *) 
  (* LC_PROBE113_IS_DATA = "1'b0" *) 
  (* LC_PROBE113_IS_TRIG = "1'b0" *) 
  (* LC_PROBE113_MU_CNT = "1" *) 
  (* LC_PROBE113_PID = "16'b0000000001110001" *) 
  (* LC_PROBE113_TYPE = "1" *) 
  (* LC_PROBE113_WIDTH = "1" *) 
  (* LC_PROBE114_IS_DATA = "1'b0" *) 
  (* LC_PROBE114_IS_TRIG = "1'b0" *) 
  (* LC_PROBE114_MU_CNT = "1" *) 
  (* LC_PROBE114_PID = "16'b0000000001110010" *) 
  (* LC_PROBE114_TYPE = "1" *) 
  (* LC_PROBE114_WIDTH = "1" *) 
  (* LC_PROBE115_IS_DATA = "1'b0" *) 
  (* LC_PROBE115_IS_TRIG = "1'b0" *) 
  (* LC_PROBE115_MU_CNT = "1" *) 
  (* LC_PROBE115_PID = "16'b0000000001110011" *) 
  (* LC_PROBE115_TYPE = "1" *) 
  (* LC_PROBE115_WIDTH = "1" *) 
  (* LC_PROBE116_IS_DATA = "1'b0" *) 
  (* LC_PROBE116_IS_TRIG = "1'b0" *) 
  (* LC_PROBE116_MU_CNT = "1" *) 
  (* LC_PROBE116_PID = "16'b0000000001110100" *) 
  (* LC_PROBE116_TYPE = "1" *) 
  (* LC_PROBE116_WIDTH = "1" *) 
  (* LC_PROBE117_IS_DATA = "1'b0" *) 
  (* LC_PROBE117_IS_TRIG = "1'b0" *) 
  (* LC_PROBE117_MU_CNT = "1" *) 
  (* LC_PROBE117_PID = "16'b0000000001110101" *) 
  (* LC_PROBE117_TYPE = "1" *) 
  (* LC_PROBE117_WIDTH = "1" *) 
  (* LC_PROBE118_IS_DATA = "1'b0" *) 
  (* LC_PROBE118_IS_TRIG = "1'b0" *) 
  (* LC_PROBE118_MU_CNT = "1" *) 
  (* LC_PROBE118_PID = "16'b0000000001110110" *) 
  (* LC_PROBE118_TYPE = "1" *) 
  (* LC_PROBE118_WIDTH = "1" *) 
  (* LC_PROBE119_IS_DATA = "1'b0" *) 
  (* LC_PROBE119_IS_TRIG = "1'b0" *) 
  (* LC_PROBE119_MU_CNT = "1" *) 
  (* LC_PROBE119_PID = "16'b0000000001110111" *) 
  (* LC_PROBE119_TYPE = "1" *) 
  (* LC_PROBE119_WIDTH = "1" *) 
  (* LC_PROBE11_IS_DATA = "1'b0" *) 
  (* LC_PROBE11_IS_TRIG = "1'b0" *) 
  (* LC_PROBE11_MU_CNT = "1" *) 
  (* LC_PROBE11_PID = "16'b0000000000001011" *) 
  (* LC_PROBE11_TYPE = "1" *) 
  (* LC_PROBE11_WIDTH = "1" *) 
  (* LC_PROBE120_IS_DATA = "1'b0" *) 
  (* LC_PROBE120_IS_TRIG = "1'b0" *) 
  (* LC_PROBE120_MU_CNT = "1" *) 
  (* LC_PROBE120_PID = "16'b0000000001111000" *) 
  (* LC_PROBE120_TYPE = "1" *) 
  (* LC_PROBE120_WIDTH = "1" *) 
  (* LC_PROBE121_IS_DATA = "1'b0" *) 
  (* LC_PROBE121_IS_TRIG = "1'b0" *) 
  (* LC_PROBE121_MU_CNT = "1" *) 
  (* LC_PROBE121_PID = "16'b0000000001111001" *) 
  (* LC_PROBE121_TYPE = "1" *) 
  (* LC_PROBE121_WIDTH = "1" *) 
  (* LC_PROBE122_IS_DATA = "1'b0" *) 
  (* LC_PROBE122_IS_TRIG = "1'b0" *) 
  (* LC_PROBE122_MU_CNT = "1" *) 
  (* LC_PROBE122_PID = "16'b0000000001111010" *) 
  (* LC_PROBE122_TYPE = "1" *) 
  (* LC_PROBE122_WIDTH = "1" *) 
  (* LC_PROBE123_IS_DATA = "1'b0" *) 
  (* LC_PROBE123_IS_TRIG = "1'b0" *) 
  (* LC_PROBE123_MU_CNT = "1" *) 
  (* LC_PROBE123_PID = "16'b0000000001111011" *) 
  (* LC_PROBE123_TYPE = "1" *) 
  (* LC_PROBE123_WIDTH = "1" *) 
  (* LC_PROBE124_IS_DATA = "1'b0" *) 
  (* LC_PROBE124_IS_TRIG = "1'b0" *) 
  (* LC_PROBE124_MU_CNT = "1" *) 
  (* LC_PROBE124_PID = "16'b0000000001111100" *) 
  (* LC_PROBE124_TYPE = "1" *) 
  (* LC_PROBE124_WIDTH = "1" *) 
  (* LC_PROBE125_IS_DATA = "1'b0" *) 
  (* LC_PROBE125_IS_TRIG = "1'b0" *) 
  (* LC_PROBE125_MU_CNT = "1" *) 
  (* LC_PROBE125_PID = "16'b0000000001111101" *) 
  (* LC_PROBE125_TYPE = "1" *) 
  (* LC_PROBE125_WIDTH = "1" *) 
  (* LC_PROBE126_IS_DATA = "1'b0" *) 
  (* LC_PROBE126_IS_TRIG = "1'b0" *) 
  (* LC_PROBE126_MU_CNT = "1" *) 
  (* LC_PROBE126_PID = "16'b0000000001111110" *) 
  (* LC_PROBE126_TYPE = "1" *) 
  (* LC_PROBE126_WIDTH = "1" *) 
  (* LC_PROBE127_IS_DATA = "1'b0" *) 
  (* LC_PROBE127_IS_TRIG = "1'b0" *) 
  (* LC_PROBE127_MU_CNT = "1" *) 
  (* LC_PROBE127_PID = "16'b0000000001111111" *) 
  (* LC_PROBE127_TYPE = "1" *) 
  (* LC_PROBE127_WIDTH = "1" *) 
  (* LC_PROBE128_IS_DATA = "1'b0" *) 
  (* LC_PROBE128_IS_TRIG = "1'b0" *) 
  (* LC_PROBE128_MU_CNT = "1" *) 
  (* LC_PROBE128_PID = "16'b0000000010000000" *) 
  (* LC_PROBE128_TYPE = "1" *) 
  (* LC_PROBE128_WIDTH = "1" *) 
  (* LC_PROBE129_IS_DATA = "1'b0" *) 
  (* LC_PROBE129_IS_TRIG = "1'b0" *) 
  (* LC_PROBE129_MU_CNT = "1" *) 
  (* LC_PROBE129_PID = "16'b0000000010000001" *) 
  (* LC_PROBE129_TYPE = "1" *) 
  (* LC_PROBE129_WIDTH = "1" *) 
  (* LC_PROBE12_IS_DATA = "1'b0" *) 
  (* LC_PROBE12_IS_TRIG = "1'b0" *) 
  (* LC_PROBE12_MU_CNT = "1" *) 
  (* LC_PROBE12_PID = "16'b0000000000001100" *) 
  (* LC_PROBE12_TYPE = "1" *) 
  (* LC_PROBE12_WIDTH = "1" *) 
  (* LC_PROBE130_IS_DATA = "1'b0" *) 
  (* LC_PROBE130_IS_TRIG = "1'b0" *) 
  (* LC_PROBE130_MU_CNT = "1" *) 
  (* LC_PROBE130_PID = "16'b0000000010000010" *) 
  (* LC_PROBE130_TYPE = "1" *) 
  (* LC_PROBE130_WIDTH = "1" *) 
  (* LC_PROBE131_IS_DATA = "1'b0" *) 
  (* LC_PROBE131_IS_TRIG = "1'b0" *) 
  (* LC_PROBE131_MU_CNT = "1" *) 
  (* LC_PROBE131_PID = "16'b0000000010000011" *) 
  (* LC_PROBE131_TYPE = "1" *) 
  (* LC_PROBE131_WIDTH = "1" *) 
  (* LC_PROBE132_IS_DATA = "1'b0" *) 
  (* LC_PROBE132_IS_TRIG = "1'b0" *) 
  (* LC_PROBE132_MU_CNT = "1" *) 
  (* LC_PROBE132_PID = "16'b0000000010000100" *) 
  (* LC_PROBE132_TYPE = "1" *) 
  (* LC_PROBE132_WIDTH = "1" *) 
  (* LC_PROBE133_IS_DATA = "1'b0" *) 
  (* LC_PROBE133_IS_TRIG = "1'b0" *) 
  (* LC_PROBE133_MU_CNT = "1" *) 
  (* LC_PROBE133_PID = "16'b0000000010000101" *) 
  (* LC_PROBE133_TYPE = "1" *) 
  (* LC_PROBE133_WIDTH = "1" *) 
  (* LC_PROBE134_IS_DATA = "1'b0" *) 
  (* LC_PROBE134_IS_TRIG = "1'b0" *) 
  (* LC_PROBE134_MU_CNT = "1" *) 
  (* LC_PROBE134_PID = "16'b0000000010000110" *) 
  (* LC_PROBE134_TYPE = "1" *) 
  (* LC_PROBE134_WIDTH = "1" *) 
  (* LC_PROBE135_IS_DATA = "1'b0" *) 
  (* LC_PROBE135_IS_TRIG = "1'b0" *) 
  (* LC_PROBE135_MU_CNT = "1" *) 
  (* LC_PROBE135_PID = "16'b0000000010000111" *) 
  (* LC_PROBE135_TYPE = "1" *) 
  (* LC_PROBE135_WIDTH = "1" *) 
  (* LC_PROBE136_IS_DATA = "1'b0" *) 
  (* LC_PROBE136_IS_TRIG = "1'b0" *) 
  (* LC_PROBE136_MU_CNT = "1" *) 
  (* LC_PROBE136_PID = "16'b0000000010001000" *) 
  (* LC_PROBE136_TYPE = "1" *) 
  (* LC_PROBE136_WIDTH = "1" *) 
  (* LC_PROBE137_IS_DATA = "1'b0" *) 
  (* LC_PROBE137_IS_TRIG = "1'b0" *) 
  (* LC_PROBE137_MU_CNT = "1" *) 
  (* LC_PROBE137_PID = "16'b0000000010001001" *) 
  (* LC_PROBE137_TYPE = "1" *) 
  (* LC_PROBE137_WIDTH = "1" *) 
  (* LC_PROBE138_IS_DATA = "1'b0" *) 
  (* LC_PROBE138_IS_TRIG = "1'b0" *) 
  (* LC_PROBE138_MU_CNT = "1" *) 
  (* LC_PROBE138_PID = "16'b0000000010001010" *) 
  (* LC_PROBE138_TYPE = "1" *) 
  (* LC_PROBE138_WIDTH = "1" *) 
  (* LC_PROBE139_IS_DATA = "1'b0" *) 
  (* LC_PROBE139_IS_TRIG = "1'b0" *) 
  (* LC_PROBE139_MU_CNT = "1" *) 
  (* LC_PROBE139_PID = "16'b0000000010001011" *) 
  (* LC_PROBE139_TYPE = "1" *) 
  (* LC_PROBE139_WIDTH = "1" *) 
  (* LC_PROBE13_IS_DATA = "1'b0" *) 
  (* LC_PROBE13_IS_TRIG = "1'b0" *) 
  (* LC_PROBE13_MU_CNT = "1" *) 
  (* LC_PROBE13_PID = "16'b0000000000001101" *) 
  (* LC_PROBE13_TYPE = "1" *) 
  (* LC_PROBE13_WIDTH = "1" *) 
  (* LC_PROBE140_IS_DATA = "1'b0" *) 
  (* LC_PROBE140_IS_TRIG = "1'b0" *) 
  (* LC_PROBE140_MU_CNT = "1" *) 
  (* LC_PROBE140_PID = "16'b0000000010001100" *) 
  (* LC_PROBE140_TYPE = "1" *) 
  (* LC_PROBE140_WIDTH = "1" *) 
  (* LC_PROBE141_IS_DATA = "1'b0" *) 
  (* LC_PROBE141_IS_TRIG = "1'b0" *) 
  (* LC_PROBE141_MU_CNT = "1" *) 
  (* LC_PROBE141_PID = "16'b0000000010001101" *) 
  (* LC_PROBE141_TYPE = "1" *) 
  (* LC_PROBE141_WIDTH = "1" *) 
  (* LC_PROBE142_IS_DATA = "1'b0" *) 
  (* LC_PROBE142_IS_TRIG = "1'b0" *) 
  (* LC_PROBE142_MU_CNT = "1" *) 
  (* LC_PROBE142_PID = "16'b0000000010001110" *) 
  (* LC_PROBE142_TYPE = "1" *) 
  (* LC_PROBE142_WIDTH = "1" *) 
  (* LC_PROBE143_IS_DATA = "1'b0" *) 
  (* LC_PROBE143_IS_TRIG = "1'b0" *) 
  (* LC_PROBE143_MU_CNT = "1" *) 
  (* LC_PROBE143_PID = "16'b0000000010001111" *) 
  (* LC_PROBE143_TYPE = "1" *) 
  (* LC_PROBE143_WIDTH = "1" *) 
  (* LC_PROBE144_IS_DATA = "1'b0" *) 
  (* LC_PROBE144_IS_TRIG = "1'b0" *) 
  (* LC_PROBE144_MU_CNT = "1" *) 
  (* LC_PROBE144_PID = "16'b0000000010010000" *) 
  (* LC_PROBE144_TYPE = "1" *) 
  (* LC_PROBE144_WIDTH = "1" *) 
  (* LC_PROBE145_IS_DATA = "1'b0" *) 
  (* LC_PROBE145_IS_TRIG = "1'b0" *) 
  (* LC_PROBE145_MU_CNT = "1" *) 
  (* LC_PROBE145_PID = "16'b0000000010010001" *) 
  (* LC_PROBE145_TYPE = "1" *) 
  (* LC_PROBE145_WIDTH = "1" *) 
  (* LC_PROBE146_IS_DATA = "1'b0" *) 
  (* LC_PROBE146_IS_TRIG = "1'b0" *) 
  (* LC_PROBE146_MU_CNT = "1" *) 
  (* LC_PROBE146_PID = "16'b0000000010010010" *) 
  (* LC_PROBE146_TYPE = "1" *) 
  (* LC_PROBE146_WIDTH = "1" *) 
  (* LC_PROBE147_IS_DATA = "1'b0" *) 
  (* LC_PROBE147_IS_TRIG = "1'b0" *) 
  (* LC_PROBE147_MU_CNT = "1" *) 
  (* LC_PROBE147_PID = "16'b0000000010010011" *) 
  (* LC_PROBE147_TYPE = "1" *) 
  (* LC_PROBE147_WIDTH = "1" *) 
  (* LC_PROBE148_IS_DATA = "1'b0" *) 
  (* LC_PROBE148_IS_TRIG = "1'b0" *) 
  (* LC_PROBE148_MU_CNT = "1" *) 
  (* LC_PROBE148_PID = "16'b0000000010010100" *) 
  (* LC_PROBE148_TYPE = "1" *) 
  (* LC_PROBE148_WIDTH = "1" *) 
  (* LC_PROBE149_IS_DATA = "1'b0" *) 
  (* LC_PROBE149_IS_TRIG = "1'b0" *) 
  (* LC_PROBE149_MU_CNT = "1" *) 
  (* LC_PROBE149_PID = "16'b0000000010010101" *) 
  (* LC_PROBE149_TYPE = "1" *) 
  (* LC_PROBE149_WIDTH = "1" *) 
  (* LC_PROBE14_IS_DATA = "1'b0" *) 
  (* LC_PROBE14_IS_TRIG = "1'b0" *) 
  (* LC_PROBE14_MU_CNT = "1" *) 
  (* LC_PROBE14_PID = "16'b0000000000001110" *) 
  (* LC_PROBE14_TYPE = "1" *) 
  (* LC_PROBE14_WIDTH = "1" *) 
  (* LC_PROBE150_IS_DATA = "1'b0" *) 
  (* LC_PROBE150_IS_TRIG = "1'b0" *) 
  (* LC_PROBE150_MU_CNT = "1" *) 
  (* LC_PROBE150_PID = "16'b0000000010010110" *) 
  (* LC_PROBE150_TYPE = "1" *) 
  (* LC_PROBE150_WIDTH = "1" *) 
  (* LC_PROBE151_IS_DATA = "1'b0" *) 
  (* LC_PROBE151_IS_TRIG = "1'b0" *) 
  (* LC_PROBE151_MU_CNT = "1" *) 
  (* LC_PROBE151_PID = "16'b0000000010010111" *) 
  (* LC_PROBE151_TYPE = "1" *) 
  (* LC_PROBE151_WIDTH = "1" *) 
  (* LC_PROBE152_IS_DATA = "1'b0" *) 
  (* LC_PROBE152_IS_TRIG = "1'b0" *) 
  (* LC_PROBE152_MU_CNT = "1" *) 
  (* LC_PROBE152_PID = "16'b0000000010011000" *) 
  (* LC_PROBE152_TYPE = "1" *) 
  (* LC_PROBE152_WIDTH = "1" *) 
  (* LC_PROBE153_IS_DATA = "1'b0" *) 
  (* LC_PROBE153_IS_TRIG = "1'b0" *) 
  (* LC_PROBE153_MU_CNT = "1" *) 
  (* LC_PROBE153_PID = "16'b0000000010011001" *) 
  (* LC_PROBE153_TYPE = "1" *) 
  (* LC_PROBE153_WIDTH = "1" *) 
  (* LC_PROBE154_IS_DATA = "1'b0" *) 
  (* LC_PROBE154_IS_TRIG = "1'b0" *) 
  (* LC_PROBE154_MU_CNT = "1" *) 
  (* LC_PROBE154_PID = "16'b0000000010011010" *) 
  (* LC_PROBE154_TYPE = "1" *) 
  (* LC_PROBE154_WIDTH = "1" *) 
  (* LC_PROBE155_IS_DATA = "1'b0" *) 
  (* LC_PROBE155_IS_TRIG = "1'b0" *) 
  (* LC_PROBE155_MU_CNT = "1" *) 
  (* LC_PROBE155_PID = "16'b0000000010011011" *) 
  (* LC_PROBE155_TYPE = "1" *) 
  (* LC_PROBE155_WIDTH = "1" *) 
  (* LC_PROBE156_IS_DATA = "1'b0" *) 
  (* LC_PROBE156_IS_TRIG = "1'b0" *) 
  (* LC_PROBE156_MU_CNT = "1" *) 
  (* LC_PROBE156_PID = "16'b0000000010011100" *) 
  (* LC_PROBE156_TYPE = "1" *) 
  (* LC_PROBE156_WIDTH = "1" *) 
  (* LC_PROBE157_IS_DATA = "1'b0" *) 
  (* LC_PROBE157_IS_TRIG = "1'b0" *) 
  (* LC_PROBE157_MU_CNT = "1" *) 
  (* LC_PROBE157_PID = "16'b0000000010011101" *) 
  (* LC_PROBE157_TYPE = "1" *) 
  (* LC_PROBE157_WIDTH = "1" *) 
  (* LC_PROBE158_IS_DATA = "1'b0" *) 
  (* LC_PROBE158_IS_TRIG = "1'b0" *) 
  (* LC_PROBE158_MU_CNT = "1" *) 
  (* LC_PROBE158_PID = "16'b0000000010011110" *) 
  (* LC_PROBE158_TYPE = "1" *) 
  (* LC_PROBE158_WIDTH = "1" *) 
  (* LC_PROBE159_IS_DATA = "1'b0" *) 
  (* LC_PROBE159_IS_TRIG = "1'b0" *) 
  (* LC_PROBE159_MU_CNT = "1" *) 
  (* LC_PROBE159_PID = "16'b0000000010011111" *) 
  (* LC_PROBE159_TYPE = "1" *) 
  (* LC_PROBE159_WIDTH = "1" *) 
  (* LC_PROBE15_IS_DATA = "1'b0" *) 
  (* LC_PROBE15_IS_TRIG = "1'b0" *) 
  (* LC_PROBE15_MU_CNT = "1" *) 
  (* LC_PROBE15_PID = "16'b0000000000001111" *) 
  (* LC_PROBE15_TYPE = "1" *) 
  (* LC_PROBE15_WIDTH = "1" *) 
  (* LC_PROBE160_IS_DATA = "1'b0" *) 
  (* LC_PROBE160_IS_TRIG = "1'b0" *) 
  (* LC_PROBE160_MU_CNT = "1" *) 
  (* LC_PROBE160_PID = "16'b0000000010100000" *) 
  (* LC_PROBE160_TYPE = "1" *) 
  (* LC_PROBE160_WIDTH = "1" *) 
  (* LC_PROBE161_IS_DATA = "1'b0" *) 
  (* LC_PROBE161_IS_TRIG = "1'b0" *) 
  (* LC_PROBE161_MU_CNT = "1" *) 
  (* LC_PROBE161_PID = "16'b0000000010100001" *) 
  (* LC_PROBE161_TYPE = "1" *) 
  (* LC_PROBE161_WIDTH = "1" *) 
  (* LC_PROBE162_IS_DATA = "1'b0" *) 
  (* LC_PROBE162_IS_TRIG = "1'b0" *) 
  (* LC_PROBE162_MU_CNT = "1" *) 
  (* LC_PROBE162_PID = "16'b0000000010100010" *) 
  (* LC_PROBE162_TYPE = "1" *) 
  (* LC_PROBE162_WIDTH = "1" *) 
  (* LC_PROBE163_IS_DATA = "1'b0" *) 
  (* LC_PROBE163_IS_TRIG = "1'b0" *) 
  (* LC_PROBE163_MU_CNT = "1" *) 
  (* LC_PROBE163_PID = "16'b0000000010100011" *) 
  (* LC_PROBE163_TYPE = "1" *) 
  (* LC_PROBE163_WIDTH = "1" *) 
  (* LC_PROBE164_IS_DATA = "1'b0" *) 
  (* LC_PROBE164_IS_TRIG = "1'b0" *) 
  (* LC_PROBE164_MU_CNT = "1" *) 
  (* LC_PROBE164_PID = "16'b0000000010100100" *) 
  (* LC_PROBE164_TYPE = "1" *) 
  (* LC_PROBE164_WIDTH = "1" *) 
  (* LC_PROBE165_IS_DATA = "1'b0" *) 
  (* LC_PROBE165_IS_TRIG = "1'b0" *) 
  (* LC_PROBE165_MU_CNT = "1" *) 
  (* LC_PROBE165_PID = "16'b0000000010100101" *) 
  (* LC_PROBE165_TYPE = "1" *) 
  (* LC_PROBE165_WIDTH = "1" *) 
  (* LC_PROBE166_IS_DATA = "1'b0" *) 
  (* LC_PROBE166_IS_TRIG = "1'b0" *) 
  (* LC_PROBE166_MU_CNT = "1" *) 
  (* LC_PROBE166_PID = "16'b0000000010100110" *) 
  (* LC_PROBE166_TYPE = "1" *) 
  (* LC_PROBE166_WIDTH = "1" *) 
  (* LC_PROBE167_IS_DATA = "1'b0" *) 
  (* LC_PROBE167_IS_TRIG = "1'b0" *) 
  (* LC_PROBE167_MU_CNT = "1" *) 
  (* LC_PROBE167_PID = "16'b0000000010100111" *) 
  (* LC_PROBE167_TYPE = "1" *) 
  (* LC_PROBE167_WIDTH = "1" *) 
  (* LC_PROBE168_IS_DATA = "1'b0" *) 
  (* LC_PROBE168_IS_TRIG = "1'b0" *) 
  (* LC_PROBE168_MU_CNT = "1" *) 
  (* LC_PROBE168_PID = "16'b0000000010101000" *) 
  (* LC_PROBE168_TYPE = "1" *) 
  (* LC_PROBE168_WIDTH = "1" *) 
  (* LC_PROBE169_IS_DATA = "1'b0" *) 
  (* LC_PROBE169_IS_TRIG = "1'b0" *) 
  (* LC_PROBE169_MU_CNT = "1" *) 
  (* LC_PROBE169_PID = "16'b0000000010101001" *) 
  (* LC_PROBE169_TYPE = "1" *) 
  (* LC_PROBE169_WIDTH = "1" *) 
  (* LC_PROBE16_IS_DATA = "1'b0" *) 
  (* LC_PROBE16_IS_TRIG = "1'b0" *) 
  (* LC_PROBE16_MU_CNT = "1" *) 
  (* LC_PROBE16_PID = "16'b0000000000010000" *) 
  (* LC_PROBE16_TYPE = "1" *) 
  (* LC_PROBE16_WIDTH = "1" *) 
  (* LC_PROBE170_IS_DATA = "1'b0" *) 
  (* LC_PROBE170_IS_TRIG = "1'b0" *) 
  (* LC_PROBE170_MU_CNT = "1" *) 
  (* LC_PROBE170_PID = "16'b0000000010101010" *) 
  (* LC_PROBE170_TYPE = "1" *) 
  (* LC_PROBE170_WIDTH = "1" *) 
  (* LC_PROBE171_IS_DATA = "1'b0" *) 
  (* LC_PROBE171_IS_TRIG = "1'b0" *) 
  (* LC_PROBE171_MU_CNT = "1" *) 
  (* LC_PROBE171_PID = "16'b0000000010101011" *) 
  (* LC_PROBE171_TYPE = "1" *) 
  (* LC_PROBE171_WIDTH = "1" *) 
  (* LC_PROBE172_IS_DATA = "1'b0" *) 
  (* LC_PROBE172_IS_TRIG = "1'b0" *) 
  (* LC_PROBE172_MU_CNT = "1" *) 
  (* LC_PROBE172_PID = "16'b0000000010101100" *) 
  (* LC_PROBE172_TYPE = "1" *) 
  (* LC_PROBE172_WIDTH = "1" *) 
  (* LC_PROBE173_IS_DATA = "1'b0" *) 
  (* LC_PROBE173_IS_TRIG = "1'b0" *) 
  (* LC_PROBE173_MU_CNT = "1" *) 
  (* LC_PROBE173_PID = "16'b0000000010101101" *) 
  (* LC_PROBE173_TYPE = "1" *) 
  (* LC_PROBE173_WIDTH = "1" *) 
  (* LC_PROBE174_IS_DATA = "1'b0" *) 
  (* LC_PROBE174_IS_TRIG = "1'b0" *) 
  (* LC_PROBE174_MU_CNT = "1" *) 
  (* LC_PROBE174_PID = "16'b0000000010101110" *) 
  (* LC_PROBE174_TYPE = "1" *) 
  (* LC_PROBE174_WIDTH = "1" *) 
  (* LC_PROBE175_IS_DATA = "1'b0" *) 
  (* LC_PROBE175_IS_TRIG = "1'b0" *) 
  (* LC_PROBE175_MU_CNT = "1" *) 
  (* LC_PROBE175_PID = "16'b0000000010101111" *) 
  (* LC_PROBE175_TYPE = "1" *) 
  (* LC_PROBE175_WIDTH = "1" *) 
  (* LC_PROBE176_IS_DATA = "1'b0" *) 
  (* LC_PROBE176_IS_TRIG = "1'b0" *) 
  (* LC_PROBE176_MU_CNT = "1" *) 
  (* LC_PROBE176_PID = "16'b0000000010110000" *) 
  (* LC_PROBE176_TYPE = "1" *) 
  (* LC_PROBE176_WIDTH = "1" *) 
  (* LC_PROBE177_IS_DATA = "1'b0" *) 
  (* LC_PROBE177_IS_TRIG = "1'b0" *) 
  (* LC_PROBE177_MU_CNT = "1" *) 
  (* LC_PROBE177_PID = "16'b0000000010110001" *) 
  (* LC_PROBE177_TYPE = "1" *) 
  (* LC_PROBE177_WIDTH = "1" *) 
  (* LC_PROBE178_IS_DATA = "1'b0" *) 
  (* LC_PROBE178_IS_TRIG = "1'b0" *) 
  (* LC_PROBE178_MU_CNT = "1" *) 
  (* LC_PROBE178_PID = "16'b0000000010110010" *) 
  (* LC_PROBE178_TYPE = "1" *) 
  (* LC_PROBE178_WIDTH = "1" *) 
  (* LC_PROBE179_IS_DATA = "1'b0" *) 
  (* LC_PROBE179_IS_TRIG = "1'b0" *) 
  (* LC_PROBE179_MU_CNT = "1" *) 
  (* LC_PROBE179_PID = "16'b0000000010110011" *) 
  (* LC_PROBE179_TYPE = "1" *) 
  (* LC_PROBE179_WIDTH = "1" *) 
  (* LC_PROBE17_IS_DATA = "1'b0" *) 
  (* LC_PROBE17_IS_TRIG = "1'b0" *) 
  (* LC_PROBE17_MU_CNT = "1" *) 
  (* LC_PROBE17_PID = "16'b0000000000010001" *) 
  (* LC_PROBE17_TYPE = "1" *) 
  (* LC_PROBE17_WIDTH = "1" *) 
  (* LC_PROBE180_IS_DATA = "1'b0" *) 
  (* LC_PROBE180_IS_TRIG = "1'b0" *) 
  (* LC_PROBE180_MU_CNT = "1" *) 
  (* LC_PROBE180_PID = "16'b0000000010110100" *) 
  (* LC_PROBE180_TYPE = "1" *) 
  (* LC_PROBE180_WIDTH = "1" *) 
  (* LC_PROBE181_IS_DATA = "1'b0" *) 
  (* LC_PROBE181_IS_TRIG = "1'b0" *) 
  (* LC_PROBE181_MU_CNT = "1" *) 
  (* LC_PROBE181_PID = "16'b0000000010110101" *) 
  (* LC_PROBE181_TYPE = "1" *) 
  (* LC_PROBE181_WIDTH = "1" *) 
  (* LC_PROBE182_IS_DATA = "1'b0" *) 
  (* LC_PROBE182_IS_TRIG = "1'b0" *) 
  (* LC_PROBE182_MU_CNT = "1" *) 
  (* LC_PROBE182_PID = "16'b0000000010110110" *) 
  (* LC_PROBE182_TYPE = "1" *) 
  (* LC_PROBE182_WIDTH = "1" *) 
  (* LC_PROBE183_IS_DATA = "1'b0" *) 
  (* LC_PROBE183_IS_TRIG = "1'b0" *) 
  (* LC_PROBE183_MU_CNT = "1" *) 
  (* LC_PROBE183_PID = "16'b0000000010110111" *) 
  (* LC_PROBE183_TYPE = "1" *) 
  (* LC_PROBE183_WIDTH = "1" *) 
  (* LC_PROBE184_IS_DATA = "1'b0" *) 
  (* LC_PROBE184_IS_TRIG = "1'b0" *) 
  (* LC_PROBE184_MU_CNT = "1" *) 
  (* LC_PROBE184_PID = "16'b0000000010111000" *) 
  (* LC_PROBE184_TYPE = "1" *) 
  (* LC_PROBE184_WIDTH = "1" *) 
  (* LC_PROBE185_IS_DATA = "1'b0" *) 
  (* LC_PROBE185_IS_TRIG = "1'b0" *) 
  (* LC_PROBE185_MU_CNT = "1" *) 
  (* LC_PROBE185_PID = "16'b0000000010111001" *) 
  (* LC_PROBE185_TYPE = "1" *) 
  (* LC_PROBE185_WIDTH = "1" *) 
  (* LC_PROBE186_IS_DATA = "1'b0" *) 
  (* LC_PROBE186_IS_TRIG = "1'b0" *) 
  (* LC_PROBE186_MU_CNT = "1" *) 
  (* LC_PROBE186_PID = "16'b0000000010111010" *) 
  (* LC_PROBE186_TYPE = "1" *) 
  (* LC_PROBE186_WIDTH = "1" *) 
  (* LC_PROBE187_IS_DATA = "1'b0" *) 
  (* LC_PROBE187_IS_TRIG = "1'b0" *) 
  (* LC_PROBE187_MU_CNT = "1" *) 
  (* LC_PROBE187_PID = "16'b0000000010111011" *) 
  (* LC_PROBE187_TYPE = "1" *) 
  (* LC_PROBE187_WIDTH = "1" *) 
  (* LC_PROBE188_IS_DATA = "1'b0" *) 
  (* LC_PROBE188_IS_TRIG = "1'b0" *) 
  (* LC_PROBE188_MU_CNT = "1" *) 
  (* LC_PROBE188_PID = "16'b0000000010111100" *) 
  (* LC_PROBE188_TYPE = "1" *) 
  (* LC_PROBE188_WIDTH = "1" *) 
  (* LC_PROBE189_IS_DATA = "1'b0" *) 
  (* LC_PROBE189_IS_TRIG = "1'b0" *) 
  (* LC_PROBE189_MU_CNT = "1" *) 
  (* LC_PROBE189_PID = "16'b0000000010111101" *) 
  (* LC_PROBE189_TYPE = "1" *) 
  (* LC_PROBE189_WIDTH = "1" *) 
  (* LC_PROBE18_IS_DATA = "1'b0" *) 
  (* LC_PROBE18_IS_TRIG = "1'b0" *) 
  (* LC_PROBE18_MU_CNT = "1" *) 
  (* LC_PROBE18_PID = "16'b0000000000010010" *) 
  (* LC_PROBE18_TYPE = "1" *) 
  (* LC_PROBE18_WIDTH = "1" *) 
  (* LC_PROBE190_IS_DATA = "1'b0" *) 
  (* LC_PROBE190_IS_TRIG = "1'b0" *) 
  (* LC_PROBE190_MU_CNT = "1" *) 
  (* LC_PROBE190_PID = "16'b0000000010111110" *) 
  (* LC_PROBE190_TYPE = "1" *) 
  (* LC_PROBE190_WIDTH = "1" *) 
  (* LC_PROBE191_IS_DATA = "1'b0" *) 
  (* LC_PROBE191_IS_TRIG = "1'b0" *) 
  (* LC_PROBE191_MU_CNT = "1" *) 
  (* LC_PROBE191_PID = "16'b0000000010111111" *) 
  (* LC_PROBE191_TYPE = "1" *) 
  (* LC_PROBE191_WIDTH = "1" *) 
  (* LC_PROBE192_IS_DATA = "1'b0" *) 
  (* LC_PROBE192_IS_TRIG = "1'b0" *) 
  (* LC_PROBE192_MU_CNT = "1" *) 
  (* LC_PROBE192_PID = "16'b0000000011000000" *) 
  (* LC_PROBE192_TYPE = "1" *) 
  (* LC_PROBE192_WIDTH = "1" *) 
  (* LC_PROBE193_IS_DATA = "1'b0" *) 
  (* LC_PROBE193_IS_TRIG = "1'b0" *) 
  (* LC_PROBE193_MU_CNT = "1" *) 
  (* LC_PROBE193_PID = "16'b0000000011000001" *) 
  (* LC_PROBE193_TYPE = "1" *) 
  (* LC_PROBE193_WIDTH = "1" *) 
  (* LC_PROBE194_IS_DATA = "1'b0" *) 
  (* LC_PROBE194_IS_TRIG = "1'b0" *) 
  (* LC_PROBE194_MU_CNT = "1" *) 
  (* LC_PROBE194_PID = "16'b0000000011000010" *) 
  (* LC_PROBE194_TYPE = "1" *) 
  (* LC_PROBE194_WIDTH = "1" *) 
  (* LC_PROBE195_IS_DATA = "1'b0" *) 
  (* LC_PROBE195_IS_TRIG = "1'b0" *) 
  (* LC_PROBE195_MU_CNT = "1" *) 
  (* LC_PROBE195_PID = "16'b0000000011000011" *) 
  (* LC_PROBE195_TYPE = "1" *) 
  (* LC_PROBE195_WIDTH = "1" *) 
  (* LC_PROBE196_IS_DATA = "1'b0" *) 
  (* LC_PROBE196_IS_TRIG = "1'b0" *) 
  (* LC_PROBE196_MU_CNT = "1" *) 
  (* LC_PROBE196_PID = "16'b0000000011000100" *) 
  (* LC_PROBE196_TYPE = "1" *) 
  (* LC_PROBE196_WIDTH = "1" *) 
  (* LC_PROBE197_IS_DATA = "1'b0" *) 
  (* LC_PROBE197_IS_TRIG = "1'b0" *) 
  (* LC_PROBE197_MU_CNT = "1" *) 
  (* LC_PROBE197_PID = "16'b0000000011000101" *) 
  (* LC_PROBE197_TYPE = "1" *) 
  (* LC_PROBE197_WIDTH = "1" *) 
  (* LC_PROBE198_IS_DATA = "1'b0" *) 
  (* LC_PROBE198_IS_TRIG = "1'b0" *) 
  (* LC_PROBE198_MU_CNT = "1" *) 
  (* LC_PROBE198_PID = "16'b0000000011000110" *) 
  (* LC_PROBE198_TYPE = "1" *) 
  (* LC_PROBE198_WIDTH = "1" *) 
  (* LC_PROBE199_IS_DATA = "1'b0" *) 
  (* LC_PROBE199_IS_TRIG = "1'b0" *) 
  (* LC_PROBE199_MU_CNT = "1" *) 
  (* LC_PROBE199_PID = "16'b0000000011000111" *) 
  (* LC_PROBE199_TYPE = "1" *) 
  (* LC_PROBE199_WIDTH = "1" *) 
  (* LC_PROBE19_IS_DATA = "1'b0" *) 
  (* LC_PROBE19_IS_TRIG = "1'b0" *) 
  (* LC_PROBE19_MU_CNT = "1" *) 
  (* LC_PROBE19_PID = "16'b0000000000010011" *) 
  (* LC_PROBE19_TYPE = "1" *) 
  (* LC_PROBE19_WIDTH = "1" *) 
  (* LC_PROBE1_IS_DATA = "1'b1" *) 
  (* LC_PROBE1_IS_TRIG = "4'b1111" *) 
  (* LC_PROBE1_MU_CNT = "4" *) 
  (* LC_PROBE1_PID = "64'b0000000000000001000000000000000100000000000000010000000000000001" *) 
  (* LC_PROBE1_TYPE = "0" *) 
  (* LC_PROBE1_WIDTH = "22" *) 
  (* LC_PROBE200_IS_DATA = "1'b0" *) 
  (* LC_PROBE200_IS_TRIG = "1'b0" *) 
  (* LC_PROBE200_MU_CNT = "1" *) 
  (* LC_PROBE200_PID = "16'b0000000011001000" *) 
  (* LC_PROBE200_TYPE = "1" *) 
  (* LC_PROBE200_WIDTH = "1" *) 
  (* LC_PROBE201_IS_DATA = "1'b0" *) 
  (* LC_PROBE201_IS_TRIG = "1'b0" *) 
  (* LC_PROBE201_MU_CNT = "1" *) 
  (* LC_PROBE201_PID = "16'b0000000011001001" *) 
  (* LC_PROBE201_TYPE = "1" *) 
  (* LC_PROBE201_WIDTH = "1" *) 
  (* LC_PROBE202_IS_DATA = "1'b0" *) 
  (* LC_PROBE202_IS_TRIG = "1'b0" *) 
  (* LC_PROBE202_MU_CNT = "1" *) 
  (* LC_PROBE202_PID = "16'b0000000011001010" *) 
  (* LC_PROBE202_TYPE = "1" *) 
  (* LC_PROBE202_WIDTH = "1" *) 
  (* LC_PROBE203_IS_DATA = "1'b0" *) 
  (* LC_PROBE203_IS_TRIG = "1'b0" *) 
  (* LC_PROBE203_MU_CNT = "1" *) 
  (* LC_PROBE203_PID = "16'b0000000011001011" *) 
  (* LC_PROBE203_TYPE = "1" *) 
  (* LC_PROBE203_WIDTH = "1" *) 
  (* LC_PROBE204_IS_DATA = "1'b0" *) 
  (* LC_PROBE204_IS_TRIG = "1'b0" *) 
  (* LC_PROBE204_MU_CNT = "1" *) 
  (* LC_PROBE204_PID = "16'b0000000011001100" *) 
  (* LC_PROBE204_TYPE = "1" *) 
  (* LC_PROBE204_WIDTH = "1" *) 
  (* LC_PROBE205_IS_DATA = "1'b0" *) 
  (* LC_PROBE205_IS_TRIG = "1'b0" *) 
  (* LC_PROBE205_MU_CNT = "1" *) 
  (* LC_PROBE205_PID = "16'b0000000011001101" *) 
  (* LC_PROBE205_TYPE = "1" *) 
  (* LC_PROBE205_WIDTH = "1" *) 
  (* LC_PROBE206_IS_DATA = "1'b0" *) 
  (* LC_PROBE206_IS_TRIG = "1'b0" *) 
  (* LC_PROBE206_MU_CNT = "1" *) 
  (* LC_PROBE206_PID = "16'b0000000011001110" *) 
  (* LC_PROBE206_TYPE = "1" *) 
  (* LC_PROBE206_WIDTH = "1" *) 
  (* LC_PROBE207_IS_DATA = "1'b0" *) 
  (* LC_PROBE207_IS_TRIG = "1'b0" *) 
  (* LC_PROBE207_MU_CNT = "1" *) 
  (* LC_PROBE207_PID = "16'b0000000011001111" *) 
  (* LC_PROBE207_TYPE = "1" *) 
  (* LC_PROBE207_WIDTH = "1" *) 
  (* LC_PROBE208_IS_DATA = "1'b0" *) 
  (* LC_PROBE208_IS_TRIG = "1'b0" *) 
  (* LC_PROBE208_MU_CNT = "1" *) 
  (* LC_PROBE208_PID = "16'b0000000011010000" *) 
  (* LC_PROBE208_TYPE = "1" *) 
  (* LC_PROBE208_WIDTH = "1" *) 
  (* LC_PROBE209_IS_DATA = "1'b0" *) 
  (* LC_PROBE209_IS_TRIG = "1'b0" *) 
  (* LC_PROBE209_MU_CNT = "1" *) 
  (* LC_PROBE209_PID = "16'b0000000011010001" *) 
  (* LC_PROBE209_TYPE = "1" *) 
  (* LC_PROBE209_WIDTH = "1" *) 
  (* LC_PROBE20_IS_DATA = "1'b0" *) 
  (* LC_PROBE20_IS_TRIG = "1'b0" *) 
  (* LC_PROBE20_MU_CNT = "1" *) 
  (* LC_PROBE20_PID = "16'b0000000000010100" *) 
  (* LC_PROBE20_TYPE = "1" *) 
  (* LC_PROBE20_WIDTH = "1" *) 
  (* LC_PROBE210_IS_DATA = "1'b0" *) 
  (* LC_PROBE210_IS_TRIG = "1'b0" *) 
  (* LC_PROBE210_MU_CNT = "1" *) 
  (* LC_PROBE210_PID = "16'b0000000011010010" *) 
  (* LC_PROBE210_TYPE = "1" *) 
  (* LC_PROBE210_WIDTH = "1" *) 
  (* LC_PROBE211_IS_DATA = "1'b0" *) 
  (* LC_PROBE211_IS_TRIG = "1'b0" *) 
  (* LC_PROBE211_MU_CNT = "1" *) 
  (* LC_PROBE211_PID = "16'b0000000011010011" *) 
  (* LC_PROBE211_TYPE = "1" *) 
  (* LC_PROBE211_WIDTH = "1" *) 
  (* LC_PROBE212_IS_DATA = "1'b0" *) 
  (* LC_PROBE212_IS_TRIG = "1'b0" *) 
  (* LC_PROBE212_MU_CNT = "1" *) 
  (* LC_PROBE212_PID = "16'b0000000011010100" *) 
  (* LC_PROBE212_TYPE = "1" *) 
  (* LC_PROBE212_WIDTH = "1" *) 
  (* LC_PROBE213_IS_DATA = "1'b0" *) 
  (* LC_PROBE213_IS_TRIG = "1'b0" *) 
  (* LC_PROBE213_MU_CNT = "1" *) 
  (* LC_PROBE213_PID = "16'b0000000011010101" *) 
  (* LC_PROBE213_TYPE = "1" *) 
  (* LC_PROBE213_WIDTH = "1" *) 
  (* LC_PROBE214_IS_DATA = "1'b0" *) 
  (* LC_PROBE214_IS_TRIG = "1'b0" *) 
  (* LC_PROBE214_MU_CNT = "1" *) 
  (* LC_PROBE214_PID = "16'b0000000011010110" *) 
  (* LC_PROBE214_TYPE = "1" *) 
  (* LC_PROBE214_WIDTH = "1" *) 
  (* LC_PROBE215_IS_DATA = "1'b0" *) 
  (* LC_PROBE215_IS_TRIG = "1'b0" *) 
  (* LC_PROBE215_MU_CNT = "1" *) 
  (* LC_PROBE215_PID = "16'b0000000011010111" *) 
  (* LC_PROBE215_TYPE = "1" *) 
  (* LC_PROBE215_WIDTH = "1" *) 
  (* LC_PROBE216_IS_DATA = "1'b0" *) 
  (* LC_PROBE216_IS_TRIG = "1'b0" *) 
  (* LC_PROBE216_MU_CNT = "1" *) 
  (* LC_PROBE216_PID = "16'b0000000011011000" *) 
  (* LC_PROBE216_TYPE = "1" *) 
  (* LC_PROBE216_WIDTH = "1" *) 
  (* LC_PROBE217_IS_DATA = "1'b0" *) 
  (* LC_PROBE217_IS_TRIG = "1'b0" *) 
  (* LC_PROBE217_MU_CNT = "1" *) 
  (* LC_PROBE217_PID = "16'b0000000011011001" *) 
  (* LC_PROBE217_TYPE = "1" *) 
  (* LC_PROBE217_WIDTH = "1" *) 
  (* LC_PROBE218_IS_DATA = "1'b0" *) 
  (* LC_PROBE218_IS_TRIG = "1'b0" *) 
  (* LC_PROBE218_MU_CNT = "1" *) 
  (* LC_PROBE218_PID = "16'b0000000011011010" *) 
  (* LC_PROBE218_TYPE = "1" *) 
  (* LC_PROBE218_WIDTH = "1" *) 
  (* LC_PROBE219_IS_DATA = "1'b0" *) 
  (* LC_PROBE219_IS_TRIG = "1'b0" *) 
  (* LC_PROBE219_MU_CNT = "1" *) 
  (* LC_PROBE219_PID = "16'b0000000011011011" *) 
  (* LC_PROBE219_TYPE = "1" *) 
  (* LC_PROBE219_WIDTH = "1" *) 
  (* LC_PROBE21_IS_DATA = "1'b0" *) 
  (* LC_PROBE21_IS_TRIG = "1'b0" *) 
  (* LC_PROBE21_MU_CNT = "1" *) 
  (* LC_PROBE21_PID = "16'b0000000000010101" *) 
  (* LC_PROBE21_TYPE = "1" *) 
  (* LC_PROBE21_WIDTH = "1" *) 
  (* LC_PROBE220_IS_DATA = "1'b0" *) 
  (* LC_PROBE220_IS_TRIG = "1'b0" *) 
  (* LC_PROBE220_MU_CNT = "1" *) 
  (* LC_PROBE220_PID = "16'b0000000011011100" *) 
  (* LC_PROBE220_TYPE = "1" *) 
  (* LC_PROBE220_WIDTH = "1" *) 
  (* LC_PROBE221_IS_DATA = "1'b0" *) 
  (* LC_PROBE221_IS_TRIG = "1'b0" *) 
  (* LC_PROBE221_MU_CNT = "1" *) 
  (* LC_PROBE221_PID = "16'b0000000011011101" *) 
  (* LC_PROBE221_TYPE = "1" *) 
  (* LC_PROBE221_WIDTH = "1" *) 
  (* LC_PROBE222_IS_DATA = "1'b0" *) 
  (* LC_PROBE222_IS_TRIG = "1'b0" *) 
  (* LC_PROBE222_MU_CNT = "1" *) 
  (* LC_PROBE222_PID = "16'b0000000011011110" *) 
  (* LC_PROBE222_TYPE = "1" *) 
  (* LC_PROBE222_WIDTH = "1" *) 
  (* LC_PROBE223_IS_DATA = "1'b0" *) 
  (* LC_PROBE223_IS_TRIG = "1'b0" *) 
  (* LC_PROBE223_MU_CNT = "1" *) 
  (* LC_PROBE223_PID = "16'b0000000011011111" *) 
  (* LC_PROBE223_TYPE = "1" *) 
  (* LC_PROBE223_WIDTH = "1" *) 
  (* LC_PROBE224_IS_DATA = "1'b0" *) 
  (* LC_PROBE224_IS_TRIG = "1'b0" *) 
  (* LC_PROBE224_MU_CNT = "1" *) 
  (* LC_PROBE224_PID = "16'b0000000011100000" *) 
  (* LC_PROBE224_TYPE = "1" *) 
  (* LC_PROBE224_WIDTH = "1" *) 
  (* LC_PROBE225_IS_DATA = "1'b0" *) 
  (* LC_PROBE225_IS_TRIG = "1'b0" *) 
  (* LC_PROBE225_MU_CNT = "1" *) 
  (* LC_PROBE225_PID = "16'b0000000011100001" *) 
  (* LC_PROBE225_TYPE = "1" *) 
  (* LC_PROBE225_WIDTH = "1" *) 
  (* LC_PROBE226_IS_DATA = "1'b0" *) 
  (* LC_PROBE226_IS_TRIG = "1'b0" *) 
  (* LC_PROBE226_MU_CNT = "1" *) 
  (* LC_PROBE226_PID = "16'b0000000011100010" *) 
  (* LC_PROBE226_TYPE = "1" *) 
  (* LC_PROBE226_WIDTH = "1" *) 
  (* LC_PROBE227_IS_DATA = "1'b0" *) 
  (* LC_PROBE227_IS_TRIG = "1'b0" *) 
  (* LC_PROBE227_MU_CNT = "1" *) 
  (* LC_PROBE227_PID = "16'b0000000011100011" *) 
  (* LC_PROBE227_TYPE = "1" *) 
  (* LC_PROBE227_WIDTH = "1" *) 
  (* LC_PROBE228_IS_DATA = "1'b0" *) 
  (* LC_PROBE228_IS_TRIG = "1'b0" *) 
  (* LC_PROBE228_MU_CNT = "1" *) 
  (* LC_PROBE228_PID = "16'b0000000011100100" *) 
  (* LC_PROBE228_TYPE = "1" *) 
  (* LC_PROBE228_WIDTH = "1" *) 
  (* LC_PROBE229_IS_DATA = "1'b0" *) 
  (* LC_PROBE229_IS_TRIG = "1'b0" *) 
  (* LC_PROBE229_MU_CNT = "1" *) 
  (* LC_PROBE229_PID = "16'b0000000011100101" *) 
  (* LC_PROBE229_TYPE = "1" *) 
  (* LC_PROBE229_WIDTH = "1" *) 
  (* LC_PROBE22_IS_DATA = "1'b0" *) 
  (* LC_PROBE22_IS_TRIG = "1'b0" *) 
  (* LC_PROBE22_MU_CNT = "1" *) 
  (* LC_PROBE22_PID = "16'b0000000000010110" *) 
  (* LC_PROBE22_TYPE = "1" *) 
  (* LC_PROBE22_WIDTH = "1" *) 
  (* LC_PROBE230_IS_DATA = "1'b0" *) 
  (* LC_PROBE230_IS_TRIG = "1'b0" *) 
  (* LC_PROBE230_MU_CNT = "1" *) 
  (* LC_PROBE230_PID = "16'b0000000011100110" *) 
  (* LC_PROBE230_TYPE = "1" *) 
  (* LC_PROBE230_WIDTH = "1" *) 
  (* LC_PROBE231_IS_DATA = "1'b0" *) 
  (* LC_PROBE231_IS_TRIG = "1'b0" *) 
  (* LC_PROBE231_MU_CNT = "1" *) 
  (* LC_PROBE231_PID = "16'b0000000011100111" *) 
  (* LC_PROBE231_TYPE = "1" *) 
  (* LC_PROBE231_WIDTH = "1" *) 
  (* LC_PROBE232_IS_DATA = "1'b0" *) 
  (* LC_PROBE232_IS_TRIG = "1'b0" *) 
  (* LC_PROBE232_MU_CNT = "1" *) 
  (* LC_PROBE232_PID = "16'b0000000011101000" *) 
  (* LC_PROBE232_TYPE = "1" *) 
  (* LC_PROBE232_WIDTH = "1" *) 
  (* LC_PROBE233_IS_DATA = "1'b0" *) 
  (* LC_PROBE233_IS_TRIG = "1'b0" *) 
  (* LC_PROBE233_MU_CNT = "1" *) 
  (* LC_PROBE233_PID = "16'b0000000011101001" *) 
  (* LC_PROBE233_TYPE = "1" *) 
  (* LC_PROBE233_WIDTH = "1" *) 
  (* LC_PROBE234_IS_DATA = "1'b0" *) 
  (* LC_PROBE234_IS_TRIG = "1'b0" *) 
  (* LC_PROBE234_MU_CNT = "1" *) 
  (* LC_PROBE234_PID = "16'b0000000011101010" *) 
  (* LC_PROBE234_TYPE = "1" *) 
  (* LC_PROBE234_WIDTH = "1" *) 
  (* LC_PROBE235_IS_DATA = "1'b0" *) 
  (* LC_PROBE235_IS_TRIG = "1'b0" *) 
  (* LC_PROBE235_MU_CNT = "1" *) 
  (* LC_PROBE235_PID = "16'b0000000011101011" *) 
  (* LC_PROBE235_TYPE = "1" *) 
  (* LC_PROBE235_WIDTH = "1" *) 
  (* LC_PROBE236_IS_DATA = "1'b0" *) 
  (* LC_PROBE236_IS_TRIG = "1'b0" *) 
  (* LC_PROBE236_MU_CNT = "1" *) 
  (* LC_PROBE236_PID = "16'b0000000011101100" *) 
  (* LC_PROBE236_TYPE = "1" *) 
  (* LC_PROBE236_WIDTH = "1" *) 
  (* LC_PROBE237_IS_DATA = "1'b0" *) 
  (* LC_PROBE237_IS_TRIG = "1'b0" *) 
  (* LC_PROBE237_MU_CNT = "1" *) 
  (* LC_PROBE237_PID = "16'b0000000011101101" *) 
  (* LC_PROBE237_TYPE = "1" *) 
  (* LC_PROBE237_WIDTH = "1" *) 
  (* LC_PROBE238_IS_DATA = "1'b0" *) 
  (* LC_PROBE238_IS_TRIG = "1'b0" *) 
  (* LC_PROBE238_MU_CNT = "1" *) 
  (* LC_PROBE238_PID = "16'b0000000011101110" *) 
  (* LC_PROBE238_TYPE = "1" *) 
  (* LC_PROBE238_WIDTH = "1" *) 
  (* LC_PROBE239_IS_DATA = "1'b0" *) 
  (* LC_PROBE239_IS_TRIG = "1'b0" *) 
  (* LC_PROBE239_MU_CNT = "1" *) 
  (* LC_PROBE239_PID = "16'b0000000011101111" *) 
  (* LC_PROBE239_TYPE = "1" *) 
  (* LC_PROBE239_WIDTH = "1" *) 
  (* LC_PROBE23_IS_DATA = "1'b0" *) 
  (* LC_PROBE23_IS_TRIG = "1'b0" *) 
  (* LC_PROBE23_MU_CNT = "1" *) 
  (* LC_PROBE23_PID = "16'b0000000000010111" *) 
  (* LC_PROBE23_TYPE = "1" *) 
  (* LC_PROBE23_WIDTH = "1" *) 
  (* LC_PROBE240_IS_DATA = "1'b0" *) 
  (* LC_PROBE240_IS_TRIG = "1'b0" *) 
  (* LC_PROBE240_MU_CNT = "1" *) 
  (* LC_PROBE240_PID = "16'b0000000011110000" *) 
  (* LC_PROBE240_TYPE = "1" *) 
  (* LC_PROBE240_WIDTH = "1" *) 
  (* LC_PROBE241_IS_DATA = "1'b0" *) 
  (* LC_PROBE241_IS_TRIG = "1'b0" *) 
  (* LC_PROBE241_MU_CNT = "1" *) 
  (* LC_PROBE241_PID = "16'b0000000011110001" *) 
  (* LC_PROBE241_TYPE = "1" *) 
  (* LC_PROBE241_WIDTH = "1" *) 
  (* LC_PROBE242_IS_DATA = "1'b0" *) 
  (* LC_PROBE242_IS_TRIG = "1'b0" *) 
  (* LC_PROBE242_MU_CNT = "1" *) 
  (* LC_PROBE242_PID = "16'b0000000011110010" *) 
  (* LC_PROBE242_TYPE = "1" *) 
  (* LC_PROBE242_WIDTH = "1" *) 
  (* LC_PROBE243_IS_DATA = "1'b0" *) 
  (* LC_PROBE243_IS_TRIG = "1'b0" *) 
  (* LC_PROBE243_MU_CNT = "1" *) 
  (* LC_PROBE243_PID = "16'b0000000011110011" *) 
  (* LC_PROBE243_TYPE = "1" *) 
  (* LC_PROBE243_WIDTH = "1" *) 
  (* LC_PROBE244_IS_DATA = "1'b0" *) 
  (* LC_PROBE244_IS_TRIG = "1'b0" *) 
  (* LC_PROBE244_MU_CNT = "1" *) 
  (* LC_PROBE244_PID = "16'b0000000011110100" *) 
  (* LC_PROBE244_TYPE = "1" *) 
  (* LC_PROBE244_WIDTH = "1" *) 
  (* LC_PROBE245_IS_DATA = "1'b0" *) 
  (* LC_PROBE245_IS_TRIG = "1'b0" *) 
  (* LC_PROBE245_MU_CNT = "1" *) 
  (* LC_PROBE245_PID = "16'b0000000011110101" *) 
  (* LC_PROBE245_TYPE = "1" *) 
  (* LC_PROBE245_WIDTH = "1" *) 
  (* LC_PROBE246_IS_DATA = "1'b0" *) 
  (* LC_PROBE246_IS_TRIG = "1'b0" *) 
  (* LC_PROBE246_MU_CNT = "1" *) 
  (* LC_PROBE246_PID = "16'b0000000011110110" *) 
  (* LC_PROBE246_TYPE = "1" *) 
  (* LC_PROBE246_WIDTH = "1" *) 
  (* LC_PROBE247_IS_DATA = "1'b0" *) 
  (* LC_PROBE247_IS_TRIG = "1'b0" *) 
  (* LC_PROBE247_MU_CNT = "1" *) 
  (* LC_PROBE247_PID = "16'b0000000011110111" *) 
  (* LC_PROBE247_TYPE = "1" *) 
  (* LC_PROBE247_WIDTH = "1" *) 
  (* LC_PROBE248_IS_DATA = "1'b0" *) 
  (* LC_PROBE248_IS_TRIG = "1'b0" *) 
  (* LC_PROBE248_MU_CNT = "1" *) 
  (* LC_PROBE248_PID = "16'b0000000011111000" *) 
  (* LC_PROBE248_TYPE = "1" *) 
  (* LC_PROBE248_WIDTH = "1" *) 
  (* LC_PROBE249_IS_DATA = "1'b0" *) 
  (* LC_PROBE249_IS_TRIG = "1'b0" *) 
  (* LC_PROBE249_MU_CNT = "1" *) 
  (* LC_PROBE249_PID = "16'b0000000011111001" *) 
  (* LC_PROBE249_TYPE = "1" *) 
  (* LC_PROBE249_WIDTH = "1" *) 
  (* LC_PROBE24_IS_DATA = "1'b0" *) 
  (* LC_PROBE24_IS_TRIG = "1'b0" *) 
  (* LC_PROBE24_MU_CNT = "1" *) 
  (* LC_PROBE24_PID = "16'b0000000000011000" *) 
  (* LC_PROBE24_TYPE = "1" *) 
  (* LC_PROBE24_WIDTH = "1" *) 
  (* LC_PROBE250_IS_DATA = "1'b0" *) 
  (* LC_PROBE250_IS_TRIG = "1'b0" *) 
  (* LC_PROBE250_MU_CNT = "1" *) 
  (* LC_PROBE250_PID = "16'b0000000011111010" *) 
  (* LC_PROBE250_TYPE = "1" *) 
  (* LC_PROBE250_WIDTH = "1" *) 
  (* LC_PROBE251_IS_DATA = "1'b0" *) 
  (* LC_PROBE251_IS_TRIG = "1'b0" *) 
  (* LC_PROBE251_MU_CNT = "1" *) 
  (* LC_PROBE251_PID = "16'b0000000011111011" *) 
  (* LC_PROBE251_TYPE = "1" *) 
  (* LC_PROBE251_WIDTH = "1" *) 
  (* LC_PROBE252_IS_DATA = "1'b0" *) 
  (* LC_PROBE252_IS_TRIG = "1'b0" *) 
  (* LC_PROBE252_MU_CNT = "1" *) 
  (* LC_PROBE252_PID = "16'b0000000011111100" *) 
  (* LC_PROBE252_TYPE = "1" *) 
  (* LC_PROBE252_WIDTH = "1" *) 
  (* LC_PROBE253_IS_DATA = "1'b0" *) 
  (* LC_PROBE253_IS_TRIG = "1'b0" *) 
  (* LC_PROBE253_MU_CNT = "1" *) 
  (* LC_PROBE253_PID = "16'b0000000011111101" *) 
  (* LC_PROBE253_TYPE = "1" *) 
  (* LC_PROBE253_WIDTH = "1" *) 
  (* LC_PROBE254_IS_DATA = "1'b0" *) 
  (* LC_PROBE254_IS_TRIG = "1'b0" *) 
  (* LC_PROBE254_MU_CNT = "1" *) 
  (* LC_PROBE254_PID = "16'b0000000011111110" *) 
  (* LC_PROBE254_TYPE = "1" *) 
  (* LC_PROBE254_WIDTH = "1" *) 
  (* LC_PROBE255_IS_DATA = "1'b0" *) 
  (* LC_PROBE255_IS_TRIG = "1'b0" *) 
  (* LC_PROBE255_MU_CNT = "1" *) 
  (* LC_PROBE255_PID = "16'b0000000011111111" *) 
  (* LC_PROBE255_TYPE = "1" *) 
  (* LC_PROBE255_WIDTH = "1" *) 
  (* LC_PROBE256_IS_DATA = "1'b0" *) 
  (* LC_PROBE256_IS_TRIG = "1'b0" *) 
  (* LC_PROBE256_MU_CNT = "1" *) 
  (* LC_PROBE256_PID = "16'b0000000100000000" *) 
  (* LC_PROBE256_TYPE = "1" *) 
  (* LC_PROBE256_WIDTH = "1" *) 
  (* LC_PROBE257_IS_DATA = "1'b0" *) 
  (* LC_PROBE257_IS_TRIG = "1'b0" *) 
  (* LC_PROBE257_MU_CNT = "1" *) 
  (* LC_PROBE257_PID = "16'b0000000100000001" *) 
  (* LC_PROBE257_TYPE = "1" *) 
  (* LC_PROBE257_WIDTH = "1" *) 
  (* LC_PROBE258_IS_DATA = "1'b0" *) 
  (* LC_PROBE258_IS_TRIG = "1'b0" *) 
  (* LC_PROBE258_MU_CNT = "1" *) 
  (* LC_PROBE258_PID = "16'b0000000100000010" *) 
  (* LC_PROBE258_TYPE = "1" *) 
  (* LC_PROBE258_WIDTH = "1" *) 
  (* LC_PROBE259_IS_DATA = "1'b0" *) 
  (* LC_PROBE259_IS_TRIG = "1'b0" *) 
  (* LC_PROBE259_MU_CNT = "1" *) 
  (* LC_PROBE259_PID = "16'b0000000100000011" *) 
  (* LC_PROBE259_TYPE = "1" *) 
  (* LC_PROBE259_WIDTH = "1" *) 
  (* LC_PROBE25_IS_DATA = "1'b0" *) 
  (* LC_PROBE25_IS_TRIG = "1'b0" *) 
  (* LC_PROBE25_MU_CNT = "1" *) 
  (* LC_PROBE25_PID = "16'b0000000000011001" *) 
  (* LC_PROBE25_TYPE = "1" *) 
  (* LC_PROBE25_WIDTH = "1" *) 
  (* LC_PROBE260_IS_DATA = "1'b0" *) 
  (* LC_PROBE260_IS_TRIG = "1'b0" *) 
  (* LC_PROBE260_MU_CNT = "1" *) 
  (* LC_PROBE260_PID = "16'b0000000100000100" *) 
  (* LC_PROBE260_TYPE = "1" *) 
  (* LC_PROBE260_WIDTH = "1" *) 
  (* LC_PROBE261_IS_DATA = "1'b0" *) 
  (* LC_PROBE261_IS_TRIG = "1'b0" *) 
  (* LC_PROBE261_MU_CNT = "1" *) 
  (* LC_PROBE261_PID = "16'b0000000100000101" *) 
  (* LC_PROBE261_TYPE = "1" *) 
  (* LC_PROBE261_WIDTH = "1" *) 
  (* LC_PROBE262_IS_DATA = "1'b0" *) 
  (* LC_PROBE262_IS_TRIG = "1'b0" *) 
  (* LC_PROBE262_MU_CNT = "1" *) 
  (* LC_PROBE262_PID = "16'b0000000100000110" *) 
  (* LC_PROBE262_TYPE = "1" *) 
  (* LC_PROBE262_WIDTH = "1" *) 
  (* LC_PROBE263_IS_DATA = "1'b0" *) 
  (* LC_PROBE263_IS_TRIG = "1'b0" *) 
  (* LC_PROBE263_MU_CNT = "1" *) 
  (* LC_PROBE263_PID = "16'b0000000100000111" *) 
  (* LC_PROBE263_TYPE = "1" *) 
  (* LC_PROBE263_WIDTH = "1" *) 
  (* LC_PROBE264_IS_DATA = "1'b0" *) 
  (* LC_PROBE264_IS_TRIG = "1'b0" *) 
  (* LC_PROBE264_MU_CNT = "1" *) 
  (* LC_PROBE264_PID = "16'b0000000100001000" *) 
  (* LC_PROBE264_TYPE = "1" *) 
  (* LC_PROBE264_WIDTH = "1" *) 
  (* LC_PROBE265_IS_DATA = "1'b0" *) 
  (* LC_PROBE265_IS_TRIG = "1'b0" *) 
  (* LC_PROBE265_MU_CNT = "1" *) 
  (* LC_PROBE265_PID = "16'b0000000100001001" *) 
  (* LC_PROBE265_TYPE = "1" *) 
  (* LC_PROBE265_WIDTH = "1" *) 
  (* LC_PROBE266_IS_DATA = "1'b0" *) 
  (* LC_PROBE266_IS_TRIG = "1'b0" *) 
  (* LC_PROBE266_MU_CNT = "1" *) 
  (* LC_PROBE266_PID = "16'b0000000100001010" *) 
  (* LC_PROBE266_TYPE = "1" *) 
  (* LC_PROBE266_WIDTH = "1" *) 
  (* LC_PROBE267_IS_DATA = "1'b0" *) 
  (* LC_PROBE267_IS_TRIG = "1'b0" *) 
  (* LC_PROBE267_MU_CNT = "1" *) 
  (* LC_PROBE267_PID = "16'b0000000100001011" *) 
  (* LC_PROBE267_TYPE = "1" *) 
  (* LC_PROBE267_WIDTH = "1" *) 
  (* LC_PROBE268_IS_DATA = "1'b0" *) 
  (* LC_PROBE268_IS_TRIG = "1'b0" *) 
  (* LC_PROBE268_MU_CNT = "1" *) 
  (* LC_PROBE268_PID = "16'b0000000100001100" *) 
  (* LC_PROBE268_TYPE = "1" *) 
  (* LC_PROBE268_WIDTH = "1" *) 
  (* LC_PROBE269_IS_DATA = "1'b0" *) 
  (* LC_PROBE269_IS_TRIG = "1'b0" *) 
  (* LC_PROBE269_MU_CNT = "1" *) 
  (* LC_PROBE269_PID = "16'b0000000100001101" *) 
  (* LC_PROBE269_TYPE = "1" *) 
  (* LC_PROBE269_WIDTH = "1" *) 
  (* LC_PROBE26_IS_DATA = "1'b0" *) 
  (* LC_PROBE26_IS_TRIG = "1'b0" *) 
  (* LC_PROBE26_MU_CNT = "1" *) 
  (* LC_PROBE26_PID = "16'b0000000000011010" *) 
  (* LC_PROBE26_TYPE = "1" *) 
  (* LC_PROBE26_WIDTH = "1" *) 
  (* LC_PROBE270_IS_DATA = "1'b0" *) 
  (* LC_PROBE270_IS_TRIG = "1'b0" *) 
  (* LC_PROBE270_MU_CNT = "1" *) 
  (* LC_PROBE270_PID = "16'b0000000100001110" *) 
  (* LC_PROBE270_TYPE = "1" *) 
  (* LC_PROBE270_WIDTH = "1" *) 
  (* LC_PROBE271_IS_DATA = "1'b0" *) 
  (* LC_PROBE271_IS_TRIG = "1'b0" *) 
  (* LC_PROBE271_MU_CNT = "1" *) 
  (* LC_PROBE271_PID = "16'b0000000100001111" *) 
  (* LC_PROBE271_TYPE = "1" *) 
  (* LC_PROBE271_WIDTH = "1" *) 
  (* LC_PROBE272_IS_DATA = "1'b0" *) 
  (* LC_PROBE272_IS_TRIG = "1'b0" *) 
  (* LC_PROBE272_MU_CNT = "1" *) 
  (* LC_PROBE272_PID = "16'b0000000100010000" *) 
  (* LC_PROBE272_TYPE = "1" *) 
  (* LC_PROBE272_WIDTH = "1" *) 
  (* LC_PROBE273_IS_DATA = "1'b0" *) 
  (* LC_PROBE273_IS_TRIG = "1'b0" *) 
  (* LC_PROBE273_MU_CNT = "1" *) 
  (* LC_PROBE273_PID = "16'b0000000100010001" *) 
  (* LC_PROBE273_TYPE = "1" *) 
  (* LC_PROBE273_WIDTH = "1" *) 
  (* LC_PROBE274_IS_DATA = "1'b0" *) 
  (* LC_PROBE274_IS_TRIG = "1'b0" *) 
  (* LC_PROBE274_MU_CNT = "1" *) 
  (* LC_PROBE274_PID = "16'b0000000100010010" *) 
  (* LC_PROBE274_TYPE = "1" *) 
  (* LC_PROBE274_WIDTH = "1" *) 
  (* LC_PROBE275_IS_DATA = "1'b0" *) 
  (* LC_PROBE275_IS_TRIG = "1'b0" *) 
  (* LC_PROBE275_MU_CNT = "1" *) 
  (* LC_PROBE275_PID = "16'b0000000100010011" *) 
  (* LC_PROBE275_TYPE = "1" *) 
  (* LC_PROBE275_WIDTH = "1" *) 
  (* LC_PROBE276_IS_DATA = "1'b0" *) 
  (* LC_PROBE276_IS_TRIG = "1'b0" *) 
  (* LC_PROBE276_MU_CNT = "1" *) 
  (* LC_PROBE276_PID = "16'b0000000100010100" *) 
  (* LC_PROBE276_TYPE = "1" *) 
  (* LC_PROBE276_WIDTH = "1" *) 
  (* LC_PROBE277_IS_DATA = "1'b0" *) 
  (* LC_PROBE277_IS_TRIG = "1'b0" *) 
  (* LC_PROBE277_MU_CNT = "1" *) 
  (* LC_PROBE277_PID = "16'b0000000100010101" *) 
  (* LC_PROBE277_TYPE = "1" *) 
  (* LC_PROBE277_WIDTH = "1" *) 
  (* LC_PROBE278_IS_DATA = "1'b0" *) 
  (* LC_PROBE278_IS_TRIG = "1'b0" *) 
  (* LC_PROBE278_MU_CNT = "1" *) 
  (* LC_PROBE278_PID = "16'b0000000100010110" *) 
  (* LC_PROBE278_TYPE = "1" *) 
  (* LC_PROBE278_WIDTH = "1" *) 
  (* LC_PROBE279_IS_DATA = "1'b0" *) 
  (* LC_PROBE279_IS_TRIG = "1'b0" *) 
  (* LC_PROBE279_MU_CNT = "1" *) 
  (* LC_PROBE279_PID = "16'b0000000100010111" *) 
  (* LC_PROBE279_TYPE = "1" *) 
  (* LC_PROBE279_WIDTH = "1" *) 
  (* LC_PROBE27_IS_DATA = "1'b0" *) 
  (* LC_PROBE27_IS_TRIG = "1'b0" *) 
  (* LC_PROBE27_MU_CNT = "1" *) 
  (* LC_PROBE27_PID = "16'b0000000000011011" *) 
  (* LC_PROBE27_TYPE = "1" *) 
  (* LC_PROBE27_WIDTH = "1" *) 
  (* LC_PROBE280_IS_DATA = "1'b0" *) 
  (* LC_PROBE280_IS_TRIG = "1'b0" *) 
  (* LC_PROBE280_MU_CNT = "1" *) 
  (* LC_PROBE280_PID = "16'b0000000100011000" *) 
  (* LC_PROBE280_TYPE = "1" *) 
  (* LC_PROBE280_WIDTH = "1" *) 
  (* LC_PROBE281_IS_DATA = "1'b0" *) 
  (* LC_PROBE281_IS_TRIG = "1'b0" *) 
  (* LC_PROBE281_MU_CNT = "1" *) 
  (* LC_PROBE281_PID = "16'b0000000100011001" *) 
  (* LC_PROBE281_TYPE = "1" *) 
  (* LC_PROBE281_WIDTH = "1" *) 
  (* LC_PROBE282_IS_DATA = "1'b0" *) 
  (* LC_PROBE282_IS_TRIG = "1'b0" *) 
  (* LC_PROBE282_MU_CNT = "1" *) 
  (* LC_PROBE282_PID = "16'b0000000100011010" *) 
  (* LC_PROBE282_TYPE = "1" *) 
  (* LC_PROBE282_WIDTH = "1" *) 
  (* LC_PROBE283_IS_DATA = "1'b0" *) 
  (* LC_PROBE283_IS_TRIG = "1'b0" *) 
  (* LC_PROBE283_MU_CNT = "1" *) 
  (* LC_PROBE283_PID = "16'b0000000100011011" *) 
  (* LC_PROBE283_TYPE = "1" *) 
  (* LC_PROBE283_WIDTH = "1" *) 
  (* LC_PROBE284_IS_DATA = "1'b0" *) 
  (* LC_PROBE284_IS_TRIG = "1'b0" *) 
  (* LC_PROBE284_MU_CNT = "1" *) 
  (* LC_PROBE284_PID = "16'b0000000100011100" *) 
  (* LC_PROBE284_TYPE = "1" *) 
  (* LC_PROBE284_WIDTH = "1" *) 
  (* LC_PROBE285_IS_DATA = "1'b0" *) 
  (* LC_PROBE285_IS_TRIG = "1'b0" *) 
  (* LC_PROBE285_MU_CNT = "1" *) 
  (* LC_PROBE285_PID = "16'b0000000100011101" *) 
  (* LC_PROBE285_TYPE = "1" *) 
  (* LC_PROBE285_WIDTH = "1" *) 
  (* LC_PROBE286_IS_DATA = "1'b0" *) 
  (* LC_PROBE286_IS_TRIG = "1'b0" *) 
  (* LC_PROBE286_MU_CNT = "1" *) 
  (* LC_PROBE286_PID = "16'b0000000100011110" *) 
  (* LC_PROBE286_TYPE = "1" *) 
  (* LC_PROBE286_WIDTH = "1" *) 
  (* LC_PROBE287_IS_DATA = "1'b0" *) 
  (* LC_PROBE287_IS_TRIG = "1'b0" *) 
  (* LC_PROBE287_MU_CNT = "1" *) 
  (* LC_PROBE287_PID = "16'b0000000100011111" *) 
  (* LC_PROBE287_TYPE = "1" *) 
  (* LC_PROBE287_WIDTH = "1" *) 
  (* LC_PROBE288_IS_DATA = "1'b0" *) 
  (* LC_PROBE288_IS_TRIG = "1'b0" *) 
  (* LC_PROBE288_MU_CNT = "1" *) 
  (* LC_PROBE288_PID = "16'b0000000100100000" *) 
  (* LC_PROBE288_TYPE = "1" *) 
  (* LC_PROBE288_WIDTH = "1" *) 
  (* LC_PROBE289_IS_DATA = "1'b0" *) 
  (* LC_PROBE289_IS_TRIG = "1'b0" *) 
  (* LC_PROBE289_MU_CNT = "1" *) 
  (* LC_PROBE289_PID = "16'b0000000100100001" *) 
  (* LC_PROBE289_TYPE = "1" *) 
  (* LC_PROBE289_WIDTH = "1" *) 
  (* LC_PROBE28_IS_DATA = "1'b0" *) 
  (* LC_PROBE28_IS_TRIG = "1'b0" *) 
  (* LC_PROBE28_MU_CNT = "1" *) 
  (* LC_PROBE28_PID = "16'b0000000000011100" *) 
  (* LC_PROBE28_TYPE = "1" *) 
  (* LC_PROBE28_WIDTH = "1" *) 
  (* LC_PROBE290_IS_DATA = "1'b0" *) 
  (* LC_PROBE290_IS_TRIG = "1'b0" *) 
  (* LC_PROBE290_MU_CNT = "1" *) 
  (* LC_PROBE290_PID = "16'b0000000100100010" *) 
  (* LC_PROBE290_TYPE = "1" *) 
  (* LC_PROBE290_WIDTH = "1" *) 
  (* LC_PROBE291_IS_DATA = "1'b0" *) 
  (* LC_PROBE291_IS_TRIG = "1'b0" *) 
  (* LC_PROBE291_MU_CNT = "1" *) 
  (* LC_PROBE291_PID = "16'b0000000100100011" *) 
  (* LC_PROBE291_TYPE = "1" *) 
  (* LC_PROBE291_WIDTH = "1" *) 
  (* LC_PROBE292_IS_DATA = "1'b0" *) 
  (* LC_PROBE292_IS_TRIG = "1'b0" *) 
  (* LC_PROBE292_MU_CNT = "1" *) 
  (* LC_PROBE292_PID = "16'b0000000100100100" *) 
  (* LC_PROBE292_TYPE = "1" *) 
  (* LC_PROBE292_WIDTH = "1" *) 
  (* LC_PROBE293_IS_DATA = "1'b0" *) 
  (* LC_PROBE293_IS_TRIG = "1'b0" *) 
  (* LC_PROBE293_MU_CNT = "1" *) 
  (* LC_PROBE293_PID = "16'b0000000100100101" *) 
  (* LC_PROBE293_TYPE = "1" *) 
  (* LC_PROBE293_WIDTH = "1" *) 
  (* LC_PROBE294_IS_DATA = "1'b0" *) 
  (* LC_PROBE294_IS_TRIG = "1'b0" *) 
  (* LC_PROBE294_MU_CNT = "1" *) 
  (* LC_PROBE294_PID = "16'b0000000100100110" *) 
  (* LC_PROBE294_TYPE = "1" *) 
  (* LC_PROBE294_WIDTH = "1" *) 
  (* LC_PROBE295_IS_DATA = "1'b0" *) 
  (* LC_PROBE295_IS_TRIG = "1'b0" *) 
  (* LC_PROBE295_MU_CNT = "1" *) 
  (* LC_PROBE295_PID = "16'b0000000100100111" *) 
  (* LC_PROBE295_TYPE = "1" *) 
  (* LC_PROBE295_WIDTH = "1" *) 
  (* LC_PROBE296_IS_DATA = "1'b0" *) 
  (* LC_PROBE296_IS_TRIG = "1'b0" *) 
  (* LC_PROBE296_MU_CNT = "1" *) 
  (* LC_PROBE296_PID = "16'b0000000100101000" *) 
  (* LC_PROBE296_TYPE = "1" *) 
  (* LC_PROBE296_WIDTH = "1" *) 
  (* LC_PROBE297_IS_DATA = "1'b0" *) 
  (* LC_PROBE297_IS_TRIG = "1'b0" *) 
  (* LC_PROBE297_MU_CNT = "1" *) 
  (* LC_PROBE297_PID = "16'b0000000100101001" *) 
  (* LC_PROBE297_TYPE = "1" *) 
  (* LC_PROBE297_WIDTH = "1" *) 
  (* LC_PROBE298_IS_DATA = "1'b0" *) 
  (* LC_PROBE298_IS_TRIG = "1'b0" *) 
  (* LC_PROBE298_MU_CNT = "1" *) 
  (* LC_PROBE298_PID = "16'b0000000100101010" *) 
  (* LC_PROBE298_TYPE = "1" *) 
  (* LC_PROBE298_WIDTH = "1" *) 
  (* LC_PROBE299_IS_DATA = "1'b0" *) 
  (* LC_PROBE299_IS_TRIG = "1'b0" *) 
  (* LC_PROBE299_MU_CNT = "1" *) 
  (* LC_PROBE299_PID = "16'b0000000100101011" *) 
  (* LC_PROBE299_TYPE = "1" *) 
  (* LC_PROBE299_WIDTH = "1" *) 
  (* LC_PROBE29_IS_DATA = "1'b0" *) 
  (* LC_PROBE29_IS_TRIG = "1'b0" *) 
  (* LC_PROBE29_MU_CNT = "1" *) 
  (* LC_PROBE29_PID = "16'b0000000000011101" *) 
  (* LC_PROBE29_TYPE = "1" *) 
  (* LC_PROBE29_WIDTH = "1" *) 
  (* LC_PROBE2_IS_DATA = "1'b1" *) 
  (* LC_PROBE2_IS_TRIG = "4'b1111" *) 
  (* LC_PROBE2_MU_CNT = "4" *) 
  (* LC_PROBE2_PID = "64'b0000000000000010000000000000001000000000000000100000000000000010" *) 
  (* LC_PROBE2_TYPE = "0" *) 
  (* LC_PROBE2_WIDTH = "22" *) 
  (* LC_PROBE300_IS_DATA = "1'b0" *) 
  (* LC_PROBE300_IS_TRIG = "1'b0" *) 
  (* LC_PROBE300_MU_CNT = "1" *) 
  (* LC_PROBE300_PID = "16'b0000000100101100" *) 
  (* LC_PROBE300_TYPE = "1" *) 
  (* LC_PROBE300_WIDTH = "1" *) 
  (* LC_PROBE301_IS_DATA = "1'b0" *) 
  (* LC_PROBE301_IS_TRIG = "1'b0" *) 
  (* LC_PROBE301_MU_CNT = "1" *) 
  (* LC_PROBE301_PID = "16'b0000000100101101" *) 
  (* LC_PROBE301_TYPE = "1" *) 
  (* LC_PROBE301_WIDTH = "1" *) 
  (* LC_PROBE302_IS_DATA = "1'b0" *) 
  (* LC_PROBE302_IS_TRIG = "1'b0" *) 
  (* LC_PROBE302_MU_CNT = "1" *) 
  (* LC_PROBE302_PID = "16'b0000000100101110" *) 
  (* LC_PROBE302_TYPE = "1" *) 
  (* LC_PROBE302_WIDTH = "1" *) 
  (* LC_PROBE303_IS_DATA = "1'b0" *) 
  (* LC_PROBE303_IS_TRIG = "1'b0" *) 
  (* LC_PROBE303_MU_CNT = "1" *) 
  (* LC_PROBE303_PID = "16'b0000000100101111" *) 
  (* LC_PROBE303_TYPE = "1" *) 
  (* LC_PROBE303_WIDTH = "1" *) 
  (* LC_PROBE304_IS_DATA = "1'b0" *) 
  (* LC_PROBE304_IS_TRIG = "1'b0" *) 
  (* LC_PROBE304_MU_CNT = "1" *) 
  (* LC_PROBE304_PID = "16'b0000000100110000" *) 
  (* LC_PROBE304_TYPE = "1" *) 
  (* LC_PROBE304_WIDTH = "1" *) 
  (* LC_PROBE305_IS_DATA = "1'b0" *) 
  (* LC_PROBE305_IS_TRIG = "1'b0" *) 
  (* LC_PROBE305_MU_CNT = "1" *) 
  (* LC_PROBE305_PID = "16'b0000000100110001" *) 
  (* LC_PROBE305_TYPE = "1" *) 
  (* LC_PROBE305_WIDTH = "1" *) 
  (* LC_PROBE306_IS_DATA = "1'b0" *) 
  (* LC_PROBE306_IS_TRIG = "1'b0" *) 
  (* LC_PROBE306_MU_CNT = "1" *) 
  (* LC_PROBE306_PID = "16'b0000000100110010" *) 
  (* LC_PROBE306_TYPE = "1" *) 
  (* LC_PROBE306_WIDTH = "1" *) 
  (* LC_PROBE307_IS_DATA = "1'b0" *) 
  (* LC_PROBE307_IS_TRIG = "1'b0" *) 
  (* LC_PROBE307_MU_CNT = "1" *) 
  (* LC_PROBE307_PID = "16'b0000000100110011" *) 
  (* LC_PROBE307_TYPE = "1" *) 
  (* LC_PROBE307_WIDTH = "1" *) 
  (* LC_PROBE308_IS_DATA = "1'b0" *) 
  (* LC_PROBE308_IS_TRIG = "1'b0" *) 
  (* LC_PROBE308_MU_CNT = "1" *) 
  (* LC_PROBE308_PID = "16'b0000000100110100" *) 
  (* LC_PROBE308_TYPE = "1" *) 
  (* LC_PROBE308_WIDTH = "1" *) 
  (* LC_PROBE309_IS_DATA = "1'b0" *) 
  (* LC_PROBE309_IS_TRIG = "1'b0" *) 
  (* LC_PROBE309_MU_CNT = "1" *) 
  (* LC_PROBE309_PID = "16'b0000000100110101" *) 
  (* LC_PROBE309_TYPE = "1" *) 
  (* LC_PROBE309_WIDTH = "1" *) 
  (* LC_PROBE30_IS_DATA = "1'b0" *) 
  (* LC_PROBE30_IS_TRIG = "1'b0" *) 
  (* LC_PROBE30_MU_CNT = "1" *) 
  (* LC_PROBE30_PID = "16'b0000000000011110" *) 
  (* LC_PROBE30_TYPE = "1" *) 
  (* LC_PROBE30_WIDTH = "1" *) 
  (* LC_PROBE310_IS_DATA = "1'b0" *) 
  (* LC_PROBE310_IS_TRIG = "1'b0" *) 
  (* LC_PROBE310_MU_CNT = "1" *) 
  (* LC_PROBE310_PID = "16'b0000000100110110" *) 
  (* LC_PROBE310_TYPE = "1" *) 
  (* LC_PROBE310_WIDTH = "1" *) 
  (* LC_PROBE311_IS_DATA = "1'b0" *) 
  (* LC_PROBE311_IS_TRIG = "1'b0" *) 
  (* LC_PROBE311_MU_CNT = "1" *) 
  (* LC_PROBE311_PID = "16'b0000000100110111" *) 
  (* LC_PROBE311_TYPE = "1" *) 
  (* LC_PROBE311_WIDTH = "1" *) 
  (* LC_PROBE312_IS_DATA = "1'b0" *) 
  (* LC_PROBE312_IS_TRIG = "1'b0" *) 
  (* LC_PROBE312_MU_CNT = "1" *) 
  (* LC_PROBE312_PID = "16'b0000000100111000" *) 
  (* LC_PROBE312_TYPE = "1" *) 
  (* LC_PROBE312_WIDTH = "1" *) 
  (* LC_PROBE313_IS_DATA = "1'b0" *) 
  (* LC_PROBE313_IS_TRIG = "1'b0" *) 
  (* LC_PROBE313_MU_CNT = "1" *) 
  (* LC_PROBE313_PID = "16'b0000000100111001" *) 
  (* LC_PROBE313_TYPE = "1" *) 
  (* LC_PROBE313_WIDTH = "1" *) 
  (* LC_PROBE314_IS_DATA = "1'b0" *) 
  (* LC_PROBE314_IS_TRIG = "1'b0" *) 
  (* LC_PROBE314_MU_CNT = "1" *) 
  (* LC_PROBE314_PID = "16'b0000000100111010" *) 
  (* LC_PROBE314_TYPE = "1" *) 
  (* LC_PROBE314_WIDTH = "1" *) 
  (* LC_PROBE315_IS_DATA = "1'b0" *) 
  (* LC_PROBE315_IS_TRIG = "1'b0" *) 
  (* LC_PROBE315_MU_CNT = "1" *) 
  (* LC_PROBE315_PID = "16'b0000000100111011" *) 
  (* LC_PROBE315_TYPE = "1" *) 
  (* LC_PROBE315_WIDTH = "1" *) 
  (* LC_PROBE316_IS_DATA = "1'b0" *) 
  (* LC_PROBE316_IS_TRIG = "1'b0" *) 
  (* LC_PROBE316_MU_CNT = "1" *) 
  (* LC_PROBE316_PID = "16'b0000000100111100" *) 
  (* LC_PROBE316_TYPE = "1" *) 
  (* LC_PROBE316_WIDTH = "1" *) 
  (* LC_PROBE317_IS_DATA = "1'b0" *) 
  (* LC_PROBE317_IS_TRIG = "1'b0" *) 
  (* LC_PROBE317_MU_CNT = "1" *) 
  (* LC_PROBE317_PID = "16'b0000000100111101" *) 
  (* LC_PROBE317_TYPE = "1" *) 
  (* LC_PROBE317_WIDTH = "1" *) 
  (* LC_PROBE318_IS_DATA = "1'b0" *) 
  (* LC_PROBE318_IS_TRIG = "1'b0" *) 
  (* LC_PROBE318_MU_CNT = "1" *) 
  (* LC_PROBE318_PID = "16'b0000000100111110" *) 
  (* LC_PROBE318_TYPE = "1" *) 
  (* LC_PROBE318_WIDTH = "1" *) 
  (* LC_PROBE319_IS_DATA = "1'b0" *) 
  (* LC_PROBE319_IS_TRIG = "1'b0" *) 
  (* LC_PROBE319_MU_CNT = "1" *) 
  (* LC_PROBE319_PID = "16'b0000000100111111" *) 
  (* LC_PROBE319_TYPE = "1" *) 
  (* LC_PROBE319_WIDTH = "1" *) 
  (* LC_PROBE31_IS_DATA = "1'b0" *) 
  (* LC_PROBE31_IS_TRIG = "1'b0" *) 
  (* LC_PROBE31_MU_CNT = "1" *) 
  (* LC_PROBE31_PID = "16'b0000000000011111" *) 
  (* LC_PROBE31_TYPE = "1" *) 
  (* LC_PROBE31_WIDTH = "1" *) 
  (* LC_PROBE320_IS_DATA = "1'b0" *) 
  (* LC_PROBE320_IS_TRIG = "1'b0" *) 
  (* LC_PROBE320_MU_CNT = "1" *) 
  (* LC_PROBE320_PID = "16'b0000000101000000" *) 
  (* LC_PROBE320_TYPE = "1" *) 
  (* LC_PROBE320_WIDTH = "1" *) 
  (* LC_PROBE321_IS_DATA = "1'b0" *) 
  (* LC_PROBE321_IS_TRIG = "1'b0" *) 
  (* LC_PROBE321_MU_CNT = "1" *) 
  (* LC_PROBE321_PID = "16'b0000000101000001" *) 
  (* LC_PROBE321_TYPE = "1" *) 
  (* LC_PROBE321_WIDTH = "1" *) 
  (* LC_PROBE322_IS_DATA = "1'b0" *) 
  (* LC_PROBE322_IS_TRIG = "1'b0" *) 
  (* LC_PROBE322_MU_CNT = "1" *) 
  (* LC_PROBE322_PID = "16'b0000000101000010" *) 
  (* LC_PROBE322_TYPE = "1" *) 
  (* LC_PROBE322_WIDTH = "1" *) 
  (* LC_PROBE323_IS_DATA = "1'b0" *) 
  (* LC_PROBE323_IS_TRIG = "1'b0" *) 
  (* LC_PROBE323_MU_CNT = "1" *) 
  (* LC_PROBE323_PID = "16'b0000000101000011" *) 
  (* LC_PROBE323_TYPE = "1" *) 
  (* LC_PROBE323_WIDTH = "1" *) 
  (* LC_PROBE324_IS_DATA = "1'b0" *) 
  (* LC_PROBE324_IS_TRIG = "1'b0" *) 
  (* LC_PROBE324_MU_CNT = "1" *) 
  (* LC_PROBE324_PID = "16'b0000000101000100" *) 
  (* LC_PROBE324_TYPE = "1" *) 
  (* LC_PROBE324_WIDTH = "1" *) 
  (* LC_PROBE325_IS_DATA = "1'b0" *) 
  (* LC_PROBE325_IS_TRIG = "1'b0" *) 
  (* LC_PROBE325_MU_CNT = "1" *) 
  (* LC_PROBE325_PID = "16'b0000000101000101" *) 
  (* LC_PROBE325_TYPE = "1" *) 
  (* LC_PROBE325_WIDTH = "1" *) 
  (* LC_PROBE326_IS_DATA = "1'b0" *) 
  (* LC_PROBE326_IS_TRIG = "1'b0" *) 
  (* LC_PROBE326_MU_CNT = "1" *) 
  (* LC_PROBE326_PID = "16'b0000000101000110" *) 
  (* LC_PROBE326_TYPE = "1" *) 
  (* LC_PROBE326_WIDTH = "1" *) 
  (* LC_PROBE327_IS_DATA = "1'b0" *) 
  (* LC_PROBE327_IS_TRIG = "1'b0" *) 
  (* LC_PROBE327_MU_CNT = "1" *) 
  (* LC_PROBE327_PID = "16'b0000000101000111" *) 
  (* LC_PROBE327_TYPE = "1" *) 
  (* LC_PROBE327_WIDTH = "1" *) 
  (* LC_PROBE328_IS_DATA = "1'b0" *) 
  (* LC_PROBE328_IS_TRIG = "1'b0" *) 
  (* LC_PROBE328_MU_CNT = "1" *) 
  (* LC_PROBE328_PID = "16'b0000000101001000" *) 
  (* LC_PROBE328_TYPE = "1" *) 
  (* LC_PROBE328_WIDTH = "1" *) 
  (* LC_PROBE329_IS_DATA = "1'b0" *) 
  (* LC_PROBE329_IS_TRIG = "1'b0" *) 
  (* LC_PROBE329_MU_CNT = "1" *) 
  (* LC_PROBE329_PID = "16'b0000000101001001" *) 
  (* LC_PROBE329_TYPE = "1" *) 
  (* LC_PROBE329_WIDTH = "1" *) 
  (* LC_PROBE32_IS_DATA = "1'b0" *) 
  (* LC_PROBE32_IS_TRIG = "1'b0" *) 
  (* LC_PROBE32_MU_CNT = "1" *) 
  (* LC_PROBE32_PID = "16'b0000000000100000" *) 
  (* LC_PROBE32_TYPE = "1" *) 
  (* LC_PROBE32_WIDTH = "1" *) 
  (* LC_PROBE330_IS_DATA = "1'b0" *) 
  (* LC_PROBE330_IS_TRIG = "1'b0" *) 
  (* LC_PROBE330_MU_CNT = "1" *) 
  (* LC_PROBE330_PID = "16'b0000000101001010" *) 
  (* LC_PROBE330_TYPE = "1" *) 
  (* LC_PROBE330_WIDTH = "1" *) 
  (* LC_PROBE331_IS_DATA = "1'b0" *) 
  (* LC_PROBE331_IS_TRIG = "1'b0" *) 
  (* LC_PROBE331_MU_CNT = "1" *) 
  (* LC_PROBE331_PID = "16'b0000000101001011" *) 
  (* LC_PROBE331_TYPE = "1" *) 
  (* LC_PROBE331_WIDTH = "1" *) 
  (* LC_PROBE332_IS_DATA = "1'b0" *) 
  (* LC_PROBE332_IS_TRIG = "1'b0" *) 
  (* LC_PROBE332_MU_CNT = "1" *) 
  (* LC_PROBE332_PID = "16'b0000000101001100" *) 
  (* LC_PROBE332_TYPE = "1" *) 
  (* LC_PROBE332_WIDTH = "1" *) 
  (* LC_PROBE333_IS_DATA = "1'b0" *) 
  (* LC_PROBE333_IS_TRIG = "1'b0" *) 
  (* LC_PROBE333_MU_CNT = "1" *) 
  (* LC_PROBE333_PID = "16'b0000000101001101" *) 
  (* LC_PROBE333_TYPE = "1" *) 
  (* LC_PROBE333_WIDTH = "1" *) 
  (* LC_PROBE334_IS_DATA = "1'b0" *) 
  (* LC_PROBE334_IS_TRIG = "1'b0" *) 
  (* LC_PROBE334_MU_CNT = "1" *) 
  (* LC_PROBE334_PID = "16'b0000000101001110" *) 
  (* LC_PROBE334_TYPE = "1" *) 
  (* LC_PROBE334_WIDTH = "1" *) 
  (* LC_PROBE335_IS_DATA = "1'b0" *) 
  (* LC_PROBE335_IS_TRIG = "1'b0" *) 
  (* LC_PROBE335_MU_CNT = "1" *) 
  (* LC_PROBE335_PID = "16'b0000000101001111" *) 
  (* LC_PROBE335_TYPE = "1" *) 
  (* LC_PROBE335_WIDTH = "1" *) 
  (* LC_PROBE336_IS_DATA = "1'b0" *) 
  (* LC_PROBE336_IS_TRIG = "1'b0" *) 
  (* LC_PROBE336_MU_CNT = "1" *) 
  (* LC_PROBE336_PID = "16'b0000000101010000" *) 
  (* LC_PROBE336_TYPE = "1" *) 
  (* LC_PROBE336_WIDTH = "1" *) 
  (* LC_PROBE337_IS_DATA = "1'b0" *) 
  (* LC_PROBE337_IS_TRIG = "1'b0" *) 
  (* LC_PROBE337_MU_CNT = "1" *) 
  (* LC_PROBE337_PID = "16'b0000000101010001" *) 
  (* LC_PROBE337_TYPE = "1" *) 
  (* LC_PROBE337_WIDTH = "1" *) 
  (* LC_PROBE338_IS_DATA = "1'b0" *) 
  (* LC_PROBE338_IS_TRIG = "1'b0" *) 
  (* LC_PROBE338_MU_CNT = "1" *) 
  (* LC_PROBE338_PID = "16'b0000000101010010" *) 
  (* LC_PROBE338_TYPE = "1" *) 
  (* LC_PROBE338_WIDTH = "1" *) 
  (* LC_PROBE339_IS_DATA = "1'b0" *) 
  (* LC_PROBE339_IS_TRIG = "1'b0" *) 
  (* LC_PROBE339_MU_CNT = "1" *) 
  (* LC_PROBE339_PID = "16'b0000000101010011" *) 
  (* LC_PROBE339_TYPE = "1" *) 
  (* LC_PROBE339_WIDTH = "1" *) 
  (* LC_PROBE33_IS_DATA = "1'b0" *) 
  (* LC_PROBE33_IS_TRIG = "1'b0" *) 
  (* LC_PROBE33_MU_CNT = "1" *) 
  (* LC_PROBE33_PID = "16'b0000000000100001" *) 
  (* LC_PROBE33_TYPE = "1" *) 
  (* LC_PROBE33_WIDTH = "1" *) 
  (* LC_PROBE340_IS_DATA = "1'b0" *) 
  (* LC_PROBE340_IS_TRIG = "1'b0" *) 
  (* LC_PROBE340_MU_CNT = "1" *) 
  (* LC_PROBE340_PID = "16'b0000000101010100" *) 
  (* LC_PROBE340_TYPE = "1" *) 
  (* LC_PROBE340_WIDTH = "1" *) 
  (* LC_PROBE341_IS_DATA = "1'b0" *) 
  (* LC_PROBE341_IS_TRIG = "1'b0" *) 
  (* LC_PROBE341_MU_CNT = "1" *) 
  (* LC_PROBE341_PID = "16'b0000000101010101" *) 
  (* LC_PROBE341_TYPE = "1" *) 
  (* LC_PROBE341_WIDTH = "1" *) 
  (* LC_PROBE342_IS_DATA = "1'b0" *) 
  (* LC_PROBE342_IS_TRIG = "1'b0" *) 
  (* LC_PROBE342_MU_CNT = "1" *) 
  (* LC_PROBE342_PID = "16'b0000000101010110" *) 
  (* LC_PROBE342_TYPE = "1" *) 
  (* LC_PROBE342_WIDTH = "1" *) 
  (* LC_PROBE343_IS_DATA = "1'b0" *) 
  (* LC_PROBE343_IS_TRIG = "1'b0" *) 
  (* LC_PROBE343_MU_CNT = "1" *) 
  (* LC_PROBE343_PID = "16'b0000000101010111" *) 
  (* LC_PROBE343_TYPE = "1" *) 
  (* LC_PROBE343_WIDTH = "1" *) 
  (* LC_PROBE344_IS_DATA = "1'b0" *) 
  (* LC_PROBE344_IS_TRIG = "1'b0" *) 
  (* LC_PROBE344_MU_CNT = "1" *) 
  (* LC_PROBE344_PID = "16'b0000000101011000" *) 
  (* LC_PROBE344_TYPE = "1" *) 
  (* LC_PROBE344_WIDTH = "1" *) 
  (* LC_PROBE345_IS_DATA = "1'b0" *) 
  (* LC_PROBE345_IS_TRIG = "1'b0" *) 
  (* LC_PROBE345_MU_CNT = "1" *) 
  (* LC_PROBE345_PID = "16'b0000000101011001" *) 
  (* LC_PROBE345_TYPE = "1" *) 
  (* LC_PROBE345_WIDTH = "1" *) 
  (* LC_PROBE346_IS_DATA = "1'b0" *) 
  (* LC_PROBE346_IS_TRIG = "1'b0" *) 
  (* LC_PROBE346_MU_CNT = "1" *) 
  (* LC_PROBE346_PID = "16'b0000000101011010" *) 
  (* LC_PROBE346_TYPE = "1" *) 
  (* LC_PROBE346_WIDTH = "1" *) 
  (* LC_PROBE347_IS_DATA = "1'b0" *) 
  (* LC_PROBE347_IS_TRIG = "1'b0" *) 
  (* LC_PROBE347_MU_CNT = "1" *) 
  (* LC_PROBE347_PID = "16'b0000000101011011" *) 
  (* LC_PROBE347_TYPE = "1" *) 
  (* LC_PROBE347_WIDTH = "1" *) 
  (* LC_PROBE348_IS_DATA = "1'b0" *) 
  (* LC_PROBE348_IS_TRIG = "1'b0" *) 
  (* LC_PROBE348_MU_CNT = "1" *) 
  (* LC_PROBE348_PID = "16'b0000000101011100" *) 
  (* LC_PROBE348_TYPE = "1" *) 
  (* LC_PROBE348_WIDTH = "1" *) 
  (* LC_PROBE349_IS_DATA = "1'b0" *) 
  (* LC_PROBE349_IS_TRIG = "1'b0" *) 
  (* LC_PROBE349_MU_CNT = "1" *) 
  (* LC_PROBE349_PID = "16'b0000000101011101" *) 
  (* LC_PROBE349_TYPE = "1" *) 
  (* LC_PROBE349_WIDTH = "1" *) 
  (* LC_PROBE34_IS_DATA = "1'b0" *) 
  (* LC_PROBE34_IS_TRIG = "1'b0" *) 
  (* LC_PROBE34_MU_CNT = "1" *) 
  (* LC_PROBE34_PID = "16'b0000000000100010" *) 
  (* LC_PROBE34_TYPE = "1" *) 
  (* LC_PROBE34_WIDTH = "1" *) 
  (* LC_PROBE350_IS_DATA = "1'b0" *) 
  (* LC_PROBE350_IS_TRIG = "1'b0" *) 
  (* LC_PROBE350_MU_CNT = "1" *) 
  (* LC_PROBE350_PID = "16'b0000000101011110" *) 
  (* LC_PROBE350_TYPE = "1" *) 
  (* LC_PROBE350_WIDTH = "1" *) 
  (* LC_PROBE351_IS_DATA = "1'b0" *) 
  (* LC_PROBE351_IS_TRIG = "1'b0" *) 
  (* LC_PROBE351_MU_CNT = "1" *) 
  (* LC_PROBE351_PID = "16'b0000000101011111" *) 
  (* LC_PROBE351_TYPE = "1" *) 
  (* LC_PROBE351_WIDTH = "1" *) 
  (* LC_PROBE352_IS_DATA = "1'b0" *) 
  (* LC_PROBE352_IS_TRIG = "1'b0" *) 
  (* LC_PROBE352_MU_CNT = "1" *) 
  (* LC_PROBE352_PID = "16'b0000000101100000" *) 
  (* LC_PROBE352_TYPE = "1" *) 
  (* LC_PROBE352_WIDTH = "1" *) 
  (* LC_PROBE353_IS_DATA = "1'b0" *) 
  (* LC_PROBE353_IS_TRIG = "1'b0" *) 
  (* LC_PROBE353_MU_CNT = "1" *) 
  (* LC_PROBE353_PID = "16'b0000000101100001" *) 
  (* LC_PROBE353_TYPE = "1" *) 
  (* LC_PROBE353_WIDTH = "1" *) 
  (* LC_PROBE354_IS_DATA = "1'b0" *) 
  (* LC_PROBE354_IS_TRIG = "1'b0" *) 
  (* LC_PROBE354_MU_CNT = "1" *) 
  (* LC_PROBE354_PID = "16'b0000000101100010" *) 
  (* LC_PROBE354_TYPE = "1" *) 
  (* LC_PROBE354_WIDTH = "1" *) 
  (* LC_PROBE355_IS_DATA = "1'b0" *) 
  (* LC_PROBE355_IS_TRIG = "1'b0" *) 
  (* LC_PROBE355_MU_CNT = "1" *) 
  (* LC_PROBE355_PID = "16'b0000000101100011" *) 
  (* LC_PROBE355_TYPE = "1" *) 
  (* LC_PROBE355_WIDTH = "1" *) 
  (* LC_PROBE356_IS_DATA = "1'b0" *) 
  (* LC_PROBE356_IS_TRIG = "1'b0" *) 
  (* LC_PROBE356_MU_CNT = "1" *) 
  (* LC_PROBE356_PID = "16'b0000000101100100" *) 
  (* LC_PROBE356_TYPE = "1" *) 
  (* LC_PROBE356_WIDTH = "1" *) 
  (* LC_PROBE357_IS_DATA = "1'b0" *) 
  (* LC_PROBE357_IS_TRIG = "1'b0" *) 
  (* LC_PROBE357_MU_CNT = "1" *) 
  (* LC_PROBE357_PID = "16'b0000000101100101" *) 
  (* LC_PROBE357_TYPE = "1" *) 
  (* LC_PROBE357_WIDTH = "1" *) 
  (* LC_PROBE358_IS_DATA = "1'b0" *) 
  (* LC_PROBE358_IS_TRIG = "1'b0" *) 
  (* LC_PROBE358_MU_CNT = "1" *) 
  (* LC_PROBE358_PID = "16'b0000000101100110" *) 
  (* LC_PROBE358_TYPE = "1" *) 
  (* LC_PROBE358_WIDTH = "1" *) 
  (* LC_PROBE359_IS_DATA = "1'b0" *) 
  (* LC_PROBE359_IS_TRIG = "1'b0" *) 
  (* LC_PROBE359_MU_CNT = "1" *) 
  (* LC_PROBE359_PID = "16'b0000000101100111" *) 
  (* LC_PROBE359_TYPE = "1" *) 
  (* LC_PROBE359_WIDTH = "1" *) 
  (* LC_PROBE35_IS_DATA = "1'b0" *) 
  (* LC_PROBE35_IS_TRIG = "1'b0" *) 
  (* LC_PROBE35_MU_CNT = "1" *) 
  (* LC_PROBE35_PID = "16'b0000000000100011" *) 
  (* LC_PROBE35_TYPE = "1" *) 
  (* LC_PROBE35_WIDTH = "1" *) 
  (* LC_PROBE360_IS_DATA = "1'b0" *) 
  (* LC_PROBE360_IS_TRIG = "1'b0" *) 
  (* LC_PROBE360_MU_CNT = "1" *) 
  (* LC_PROBE360_PID = "16'b0000000101101000" *) 
  (* LC_PROBE360_TYPE = "1" *) 
  (* LC_PROBE360_WIDTH = "1" *) 
  (* LC_PROBE361_IS_DATA = "1'b0" *) 
  (* LC_PROBE361_IS_TRIG = "1'b0" *) 
  (* LC_PROBE361_MU_CNT = "1" *) 
  (* LC_PROBE361_PID = "16'b0000000101101001" *) 
  (* LC_PROBE361_TYPE = "1" *) 
  (* LC_PROBE361_WIDTH = "1" *) 
  (* LC_PROBE362_IS_DATA = "1'b0" *) 
  (* LC_PROBE362_IS_TRIG = "1'b0" *) 
  (* LC_PROBE362_MU_CNT = "1" *) 
  (* LC_PROBE362_PID = "16'b0000000101101010" *) 
  (* LC_PROBE362_TYPE = "1" *) 
  (* LC_PROBE362_WIDTH = "1" *) 
  (* LC_PROBE363_IS_DATA = "1'b0" *) 
  (* LC_PROBE363_IS_TRIG = "1'b0" *) 
  (* LC_PROBE363_MU_CNT = "1" *) 
  (* LC_PROBE363_PID = "16'b0000000101101011" *) 
  (* LC_PROBE363_TYPE = "1" *) 
  (* LC_PROBE363_WIDTH = "1" *) 
  (* LC_PROBE364_IS_DATA = "1'b0" *) 
  (* LC_PROBE364_IS_TRIG = "1'b0" *) 
  (* LC_PROBE364_MU_CNT = "1" *) 
  (* LC_PROBE364_PID = "16'b0000000101101100" *) 
  (* LC_PROBE364_TYPE = "1" *) 
  (* LC_PROBE364_WIDTH = "1" *) 
  (* LC_PROBE365_IS_DATA = "1'b0" *) 
  (* LC_PROBE365_IS_TRIG = "1'b0" *) 
  (* LC_PROBE365_MU_CNT = "1" *) 
  (* LC_PROBE365_PID = "16'b0000000101101101" *) 
  (* LC_PROBE365_TYPE = "1" *) 
  (* LC_PROBE365_WIDTH = "1" *) 
  (* LC_PROBE366_IS_DATA = "1'b0" *) 
  (* LC_PROBE366_IS_TRIG = "1'b0" *) 
  (* LC_PROBE366_MU_CNT = "1" *) 
  (* LC_PROBE366_PID = "16'b0000000101101110" *) 
  (* LC_PROBE366_TYPE = "1" *) 
  (* LC_PROBE366_WIDTH = "1" *) 
  (* LC_PROBE367_IS_DATA = "1'b0" *) 
  (* LC_PROBE367_IS_TRIG = "1'b0" *) 
  (* LC_PROBE367_MU_CNT = "1" *) 
  (* LC_PROBE367_PID = "16'b0000000101101111" *) 
  (* LC_PROBE367_TYPE = "1" *) 
  (* LC_PROBE367_WIDTH = "1" *) 
  (* LC_PROBE368_IS_DATA = "1'b0" *) 
  (* LC_PROBE368_IS_TRIG = "1'b0" *) 
  (* LC_PROBE368_MU_CNT = "1" *) 
  (* LC_PROBE368_PID = "16'b0000000101110000" *) 
  (* LC_PROBE368_TYPE = "1" *) 
  (* LC_PROBE368_WIDTH = "1" *) 
  (* LC_PROBE369_IS_DATA = "1'b0" *) 
  (* LC_PROBE369_IS_TRIG = "1'b0" *) 
  (* LC_PROBE369_MU_CNT = "1" *) 
  (* LC_PROBE369_PID = "16'b0000000101110001" *) 
  (* LC_PROBE369_TYPE = "1" *) 
  (* LC_PROBE369_WIDTH = "1" *) 
  (* LC_PROBE36_IS_DATA = "1'b0" *) 
  (* LC_PROBE36_IS_TRIG = "1'b0" *) 
  (* LC_PROBE36_MU_CNT = "1" *) 
  (* LC_PROBE36_PID = "16'b0000000000100100" *) 
  (* LC_PROBE36_TYPE = "1" *) 
  (* LC_PROBE36_WIDTH = "1" *) 
  (* LC_PROBE370_IS_DATA = "1'b0" *) 
  (* LC_PROBE370_IS_TRIG = "1'b0" *) 
  (* LC_PROBE370_MU_CNT = "1" *) 
  (* LC_PROBE370_PID = "16'b0000000101110010" *) 
  (* LC_PROBE370_TYPE = "1" *) 
  (* LC_PROBE370_WIDTH = "1" *) 
  (* LC_PROBE371_IS_DATA = "1'b0" *) 
  (* LC_PROBE371_IS_TRIG = "1'b0" *) 
  (* LC_PROBE371_MU_CNT = "1" *) 
  (* LC_PROBE371_PID = "16'b0000000101110011" *) 
  (* LC_PROBE371_TYPE = "1" *) 
  (* LC_PROBE371_WIDTH = "1" *) 
  (* LC_PROBE372_IS_DATA = "1'b0" *) 
  (* LC_PROBE372_IS_TRIG = "1'b0" *) 
  (* LC_PROBE372_MU_CNT = "1" *) 
  (* LC_PROBE372_PID = "16'b0000000101110100" *) 
  (* LC_PROBE372_TYPE = "1" *) 
  (* LC_PROBE372_WIDTH = "1" *) 
  (* LC_PROBE373_IS_DATA = "1'b0" *) 
  (* LC_PROBE373_IS_TRIG = "1'b0" *) 
  (* LC_PROBE373_MU_CNT = "1" *) 
  (* LC_PROBE373_PID = "16'b0000000101110101" *) 
  (* LC_PROBE373_TYPE = "1" *) 
  (* LC_PROBE373_WIDTH = "1" *) 
  (* LC_PROBE374_IS_DATA = "1'b0" *) 
  (* LC_PROBE374_IS_TRIG = "1'b0" *) 
  (* LC_PROBE374_MU_CNT = "1" *) 
  (* LC_PROBE374_PID = "16'b0000000101110110" *) 
  (* LC_PROBE374_TYPE = "1" *) 
  (* LC_PROBE374_WIDTH = "1" *) 
  (* LC_PROBE375_IS_DATA = "1'b0" *) 
  (* LC_PROBE375_IS_TRIG = "1'b0" *) 
  (* LC_PROBE375_MU_CNT = "1" *) 
  (* LC_PROBE375_PID = "16'b0000000101110111" *) 
  (* LC_PROBE375_TYPE = "1" *) 
  (* LC_PROBE375_WIDTH = "1" *) 
  (* LC_PROBE376_IS_DATA = "1'b0" *) 
  (* LC_PROBE376_IS_TRIG = "1'b0" *) 
  (* LC_PROBE376_MU_CNT = "1" *) 
  (* LC_PROBE376_PID = "16'b0000000101111000" *) 
  (* LC_PROBE376_TYPE = "1" *) 
  (* LC_PROBE376_WIDTH = "1" *) 
  (* LC_PROBE377_IS_DATA = "1'b0" *) 
  (* LC_PROBE377_IS_TRIG = "1'b0" *) 
  (* LC_PROBE377_MU_CNT = "1" *) 
  (* LC_PROBE377_PID = "16'b0000000101111001" *) 
  (* LC_PROBE377_TYPE = "1" *) 
  (* LC_PROBE377_WIDTH = "1" *) 
  (* LC_PROBE378_IS_DATA = "1'b0" *) 
  (* LC_PROBE378_IS_TRIG = "1'b0" *) 
  (* LC_PROBE378_MU_CNT = "1" *) 
  (* LC_PROBE378_PID = "16'b0000000101111010" *) 
  (* LC_PROBE378_TYPE = "1" *) 
  (* LC_PROBE378_WIDTH = "1" *) 
  (* LC_PROBE379_IS_DATA = "1'b0" *) 
  (* LC_PROBE379_IS_TRIG = "1'b0" *) 
  (* LC_PROBE379_MU_CNT = "1" *) 
  (* LC_PROBE379_PID = "16'b0000000101111011" *) 
  (* LC_PROBE379_TYPE = "1" *) 
  (* LC_PROBE379_WIDTH = "1" *) 
  (* LC_PROBE37_IS_DATA = "1'b0" *) 
  (* LC_PROBE37_IS_TRIG = "1'b0" *) 
  (* LC_PROBE37_MU_CNT = "1" *) 
  (* LC_PROBE37_PID = "16'b0000000000100101" *) 
  (* LC_PROBE37_TYPE = "1" *) 
  (* LC_PROBE37_WIDTH = "1" *) 
  (* LC_PROBE380_IS_DATA = "1'b0" *) 
  (* LC_PROBE380_IS_TRIG = "1'b0" *) 
  (* LC_PROBE380_MU_CNT = "1" *) 
  (* LC_PROBE380_PID = "16'b0000000101111100" *) 
  (* LC_PROBE380_TYPE = "1" *) 
  (* LC_PROBE380_WIDTH = "1" *) 
  (* LC_PROBE381_IS_DATA = "1'b0" *) 
  (* LC_PROBE381_IS_TRIG = "1'b0" *) 
  (* LC_PROBE381_MU_CNT = "1" *) 
  (* LC_PROBE381_PID = "16'b0000000101111101" *) 
  (* LC_PROBE381_TYPE = "1" *) 
  (* LC_PROBE381_WIDTH = "1" *) 
  (* LC_PROBE382_IS_DATA = "1'b0" *) 
  (* LC_PROBE382_IS_TRIG = "1'b0" *) 
  (* LC_PROBE382_MU_CNT = "1" *) 
  (* LC_PROBE382_PID = "16'b0000000101111110" *) 
  (* LC_PROBE382_TYPE = "1" *) 
  (* LC_PROBE382_WIDTH = "1" *) 
  (* LC_PROBE383_IS_DATA = "1'b0" *) 
  (* LC_PROBE383_IS_TRIG = "1'b0" *) 
  (* LC_PROBE383_MU_CNT = "1" *) 
  (* LC_PROBE383_PID = "16'b0000000101111111" *) 
  (* LC_PROBE383_TYPE = "1" *) 
  (* LC_PROBE383_WIDTH = "1" *) 
  (* LC_PROBE384_IS_DATA = "1'b0" *) 
  (* LC_PROBE384_IS_TRIG = "1'b0" *) 
  (* LC_PROBE384_MU_CNT = "1" *) 
  (* LC_PROBE384_PID = "16'b0000000110000000" *) 
  (* LC_PROBE384_TYPE = "1" *) 
  (* LC_PROBE384_WIDTH = "1" *) 
  (* LC_PROBE385_IS_DATA = "1'b0" *) 
  (* LC_PROBE385_IS_TRIG = "1'b0" *) 
  (* LC_PROBE385_MU_CNT = "1" *) 
  (* LC_PROBE385_PID = "16'b0000000110000001" *) 
  (* LC_PROBE385_TYPE = "1" *) 
  (* LC_PROBE385_WIDTH = "1" *) 
  (* LC_PROBE386_IS_DATA = "1'b0" *) 
  (* LC_PROBE386_IS_TRIG = "1'b0" *) 
  (* LC_PROBE386_MU_CNT = "1" *) 
  (* LC_PROBE386_PID = "16'b0000000110000010" *) 
  (* LC_PROBE386_TYPE = "1" *) 
  (* LC_PROBE386_WIDTH = "1" *) 
  (* LC_PROBE387_IS_DATA = "1'b0" *) 
  (* LC_PROBE387_IS_TRIG = "1'b0" *) 
  (* LC_PROBE387_MU_CNT = "1" *) 
  (* LC_PROBE387_PID = "16'b0000000110000011" *) 
  (* LC_PROBE387_TYPE = "1" *) 
  (* LC_PROBE387_WIDTH = "1" *) 
  (* LC_PROBE388_IS_DATA = "1'b0" *) 
  (* LC_PROBE388_IS_TRIG = "1'b0" *) 
  (* LC_PROBE388_MU_CNT = "1" *) 
  (* LC_PROBE388_PID = "16'b0000000110000100" *) 
  (* LC_PROBE388_TYPE = "1" *) 
  (* LC_PROBE388_WIDTH = "1" *) 
  (* LC_PROBE389_IS_DATA = "1'b0" *) 
  (* LC_PROBE389_IS_TRIG = "1'b0" *) 
  (* LC_PROBE389_MU_CNT = "1" *) 
  (* LC_PROBE389_PID = "16'b0000000110000101" *) 
  (* LC_PROBE389_TYPE = "1" *) 
  (* LC_PROBE389_WIDTH = "1" *) 
  (* LC_PROBE38_IS_DATA = "1'b0" *) 
  (* LC_PROBE38_IS_TRIG = "1'b0" *) 
  (* LC_PROBE38_MU_CNT = "1" *) 
  (* LC_PROBE38_PID = "16'b0000000000100110" *) 
  (* LC_PROBE38_TYPE = "1" *) 
  (* LC_PROBE38_WIDTH = "1" *) 
  (* LC_PROBE390_IS_DATA = "1'b0" *) 
  (* LC_PROBE390_IS_TRIG = "1'b0" *) 
  (* LC_PROBE390_MU_CNT = "1" *) 
  (* LC_PROBE390_PID = "16'b0000000110000110" *) 
  (* LC_PROBE390_TYPE = "1" *) 
  (* LC_PROBE390_WIDTH = "1" *) 
  (* LC_PROBE391_IS_DATA = "1'b0" *) 
  (* LC_PROBE391_IS_TRIG = "1'b0" *) 
  (* LC_PROBE391_MU_CNT = "1" *) 
  (* LC_PROBE391_PID = "16'b0000000110000111" *) 
  (* LC_PROBE391_TYPE = "1" *) 
  (* LC_PROBE391_WIDTH = "1" *) 
  (* LC_PROBE392_IS_DATA = "1'b0" *) 
  (* LC_PROBE392_IS_TRIG = "1'b0" *) 
  (* LC_PROBE392_MU_CNT = "1" *) 
  (* LC_PROBE392_PID = "16'b0000000110001000" *) 
  (* LC_PROBE392_TYPE = "1" *) 
  (* LC_PROBE392_WIDTH = "1" *) 
  (* LC_PROBE393_IS_DATA = "1'b0" *) 
  (* LC_PROBE393_IS_TRIG = "1'b0" *) 
  (* LC_PROBE393_MU_CNT = "1" *) 
  (* LC_PROBE393_PID = "16'b0000000110001001" *) 
  (* LC_PROBE393_TYPE = "1" *) 
  (* LC_PROBE393_WIDTH = "1" *) 
  (* LC_PROBE394_IS_DATA = "1'b0" *) 
  (* LC_PROBE394_IS_TRIG = "1'b0" *) 
  (* LC_PROBE394_MU_CNT = "1" *) 
  (* LC_PROBE394_PID = "16'b0000000110001010" *) 
  (* LC_PROBE394_TYPE = "1" *) 
  (* LC_PROBE394_WIDTH = "1" *) 
  (* LC_PROBE395_IS_DATA = "1'b0" *) 
  (* LC_PROBE395_IS_TRIG = "1'b0" *) 
  (* LC_PROBE395_MU_CNT = "1" *) 
  (* LC_PROBE395_PID = "16'b0000000110001011" *) 
  (* LC_PROBE395_TYPE = "1" *) 
  (* LC_PROBE395_WIDTH = "1" *) 
  (* LC_PROBE396_IS_DATA = "1'b0" *) 
  (* LC_PROBE396_IS_TRIG = "1'b0" *) 
  (* LC_PROBE396_MU_CNT = "1" *) 
  (* LC_PROBE396_PID = "16'b0000000110001100" *) 
  (* LC_PROBE396_TYPE = "1" *) 
  (* LC_PROBE396_WIDTH = "1" *) 
  (* LC_PROBE397_IS_DATA = "1'b0" *) 
  (* LC_PROBE397_IS_TRIG = "1'b0" *) 
  (* LC_PROBE397_MU_CNT = "1" *) 
  (* LC_PROBE397_PID = "16'b0000000110001101" *) 
  (* LC_PROBE397_TYPE = "1" *) 
  (* LC_PROBE397_WIDTH = "1" *) 
  (* LC_PROBE398_IS_DATA = "1'b0" *) 
  (* LC_PROBE398_IS_TRIG = "1'b0" *) 
  (* LC_PROBE398_MU_CNT = "1" *) 
  (* LC_PROBE398_PID = "16'b0000000110001110" *) 
  (* LC_PROBE398_TYPE = "1" *) 
  (* LC_PROBE398_WIDTH = "1" *) 
  (* LC_PROBE399_IS_DATA = "1'b0" *) 
  (* LC_PROBE399_IS_TRIG = "1'b0" *) 
  (* LC_PROBE399_MU_CNT = "1" *) 
  (* LC_PROBE399_PID = "16'b0000000110001111" *) 
  (* LC_PROBE399_TYPE = "1" *) 
  (* LC_PROBE399_WIDTH = "1" *) 
  (* LC_PROBE39_IS_DATA = "1'b0" *) 
  (* LC_PROBE39_IS_TRIG = "1'b0" *) 
  (* LC_PROBE39_MU_CNT = "1" *) 
  (* LC_PROBE39_PID = "16'b0000000000100111" *) 
  (* LC_PROBE39_TYPE = "1" *) 
  (* LC_PROBE39_WIDTH = "1" *) 
  (* LC_PROBE3_IS_DATA = "1'b0" *) 
  (* LC_PROBE3_IS_TRIG = "1'b0" *) 
  (* LC_PROBE3_MU_CNT = "1" *) 
  (* LC_PROBE3_PID = "16'b0000000000000011" *) 
  (* LC_PROBE3_TYPE = "1" *) 
  (* LC_PROBE3_WIDTH = "1" *) 
  (* LC_PROBE400_IS_DATA = "1'b0" *) 
  (* LC_PROBE400_IS_TRIG = "1'b0" *) 
  (* LC_PROBE400_MU_CNT = "1" *) 
  (* LC_PROBE400_PID = "16'b0000000110010000" *) 
  (* LC_PROBE400_TYPE = "1" *) 
  (* LC_PROBE400_WIDTH = "1" *) 
  (* LC_PROBE401_IS_DATA = "1'b0" *) 
  (* LC_PROBE401_IS_TRIG = "1'b0" *) 
  (* LC_PROBE401_MU_CNT = "1" *) 
  (* LC_PROBE401_PID = "16'b0000000110010001" *) 
  (* LC_PROBE401_TYPE = "1" *) 
  (* LC_PROBE401_WIDTH = "1" *) 
  (* LC_PROBE402_IS_DATA = "1'b0" *) 
  (* LC_PROBE402_IS_TRIG = "1'b0" *) 
  (* LC_PROBE402_MU_CNT = "1" *) 
  (* LC_PROBE402_PID = "16'b0000000110010010" *) 
  (* LC_PROBE402_TYPE = "1" *) 
  (* LC_PROBE402_WIDTH = "1" *) 
  (* LC_PROBE403_IS_DATA = "1'b0" *) 
  (* LC_PROBE403_IS_TRIG = "1'b0" *) 
  (* LC_PROBE403_MU_CNT = "1" *) 
  (* LC_PROBE403_PID = "16'b0000000110010011" *) 
  (* LC_PROBE403_TYPE = "1" *) 
  (* LC_PROBE403_WIDTH = "1" *) 
  (* LC_PROBE404_IS_DATA = "1'b0" *) 
  (* LC_PROBE404_IS_TRIG = "1'b0" *) 
  (* LC_PROBE404_MU_CNT = "1" *) 
  (* LC_PROBE404_PID = "16'b0000000110010100" *) 
  (* LC_PROBE404_TYPE = "1" *) 
  (* LC_PROBE404_WIDTH = "1" *) 
  (* LC_PROBE405_IS_DATA = "1'b0" *) 
  (* LC_PROBE405_IS_TRIG = "1'b0" *) 
  (* LC_PROBE405_MU_CNT = "1" *) 
  (* LC_PROBE405_PID = "16'b0000000110010101" *) 
  (* LC_PROBE405_TYPE = "1" *) 
  (* LC_PROBE405_WIDTH = "1" *) 
  (* LC_PROBE406_IS_DATA = "1'b0" *) 
  (* LC_PROBE406_IS_TRIG = "1'b0" *) 
  (* LC_PROBE406_MU_CNT = "1" *) 
  (* LC_PROBE406_PID = "16'b0000000110010110" *) 
  (* LC_PROBE406_TYPE = "1" *) 
  (* LC_PROBE406_WIDTH = "1" *) 
  (* LC_PROBE407_IS_DATA = "1'b0" *) 
  (* LC_PROBE407_IS_TRIG = "1'b0" *) 
  (* LC_PROBE407_MU_CNT = "1" *) 
  (* LC_PROBE407_PID = "16'b0000000110010111" *) 
  (* LC_PROBE407_TYPE = "1" *) 
  (* LC_PROBE407_WIDTH = "1" *) 
  (* LC_PROBE408_IS_DATA = "1'b0" *) 
  (* LC_PROBE408_IS_TRIG = "1'b0" *) 
  (* LC_PROBE408_MU_CNT = "1" *) 
  (* LC_PROBE408_PID = "16'b0000000110011000" *) 
  (* LC_PROBE408_TYPE = "1" *) 
  (* LC_PROBE408_WIDTH = "1" *) 
  (* LC_PROBE409_IS_DATA = "1'b0" *) 
  (* LC_PROBE409_IS_TRIG = "1'b0" *) 
  (* LC_PROBE409_MU_CNT = "1" *) 
  (* LC_PROBE409_PID = "16'b0000000110011001" *) 
  (* LC_PROBE409_TYPE = "1" *) 
  (* LC_PROBE409_WIDTH = "1" *) 
  (* LC_PROBE40_IS_DATA = "1'b0" *) 
  (* LC_PROBE40_IS_TRIG = "1'b0" *) 
  (* LC_PROBE40_MU_CNT = "1" *) 
  (* LC_PROBE40_PID = "16'b0000000000101000" *) 
  (* LC_PROBE40_TYPE = "1" *) 
  (* LC_PROBE40_WIDTH = "1" *) 
  (* LC_PROBE410_IS_DATA = "1'b0" *) 
  (* LC_PROBE410_IS_TRIG = "1'b0" *) 
  (* LC_PROBE410_MU_CNT = "1" *) 
  (* LC_PROBE410_PID = "16'b0000000110011010" *) 
  (* LC_PROBE410_TYPE = "1" *) 
  (* LC_PROBE410_WIDTH = "1" *) 
  (* LC_PROBE411_IS_DATA = "1'b0" *) 
  (* LC_PROBE411_IS_TRIG = "1'b0" *) 
  (* LC_PROBE411_MU_CNT = "1" *) 
  (* LC_PROBE411_PID = "16'b0000000110011011" *) 
  (* LC_PROBE411_TYPE = "1" *) 
  (* LC_PROBE411_WIDTH = "1" *) 
  (* LC_PROBE412_IS_DATA = "1'b0" *) 
  (* LC_PROBE412_IS_TRIG = "1'b0" *) 
  (* LC_PROBE412_MU_CNT = "1" *) 
  (* LC_PROBE412_PID = "16'b0000000110011100" *) 
  (* LC_PROBE412_TYPE = "1" *) 
  (* LC_PROBE412_WIDTH = "1" *) 
  (* LC_PROBE413_IS_DATA = "1'b0" *) 
  (* LC_PROBE413_IS_TRIG = "1'b0" *) 
  (* LC_PROBE413_MU_CNT = "1" *) 
  (* LC_PROBE413_PID = "16'b0000000110011101" *) 
  (* LC_PROBE413_TYPE = "1" *) 
  (* LC_PROBE413_WIDTH = "1" *) 
  (* LC_PROBE414_IS_DATA = "1'b0" *) 
  (* LC_PROBE414_IS_TRIG = "1'b0" *) 
  (* LC_PROBE414_MU_CNT = "1" *) 
  (* LC_PROBE414_PID = "16'b0000000110011110" *) 
  (* LC_PROBE414_TYPE = "1" *) 
  (* LC_PROBE414_WIDTH = "1" *) 
  (* LC_PROBE415_IS_DATA = "1'b0" *) 
  (* LC_PROBE415_IS_TRIG = "1'b0" *) 
  (* LC_PROBE415_MU_CNT = "1" *) 
  (* LC_PROBE415_PID = "16'b0000000110011111" *) 
  (* LC_PROBE415_TYPE = "1" *) 
  (* LC_PROBE415_WIDTH = "1" *) 
  (* LC_PROBE416_IS_DATA = "1'b0" *) 
  (* LC_PROBE416_IS_TRIG = "1'b0" *) 
  (* LC_PROBE416_MU_CNT = "1" *) 
  (* LC_PROBE416_PID = "16'b0000000110100000" *) 
  (* LC_PROBE416_TYPE = "1" *) 
  (* LC_PROBE416_WIDTH = "1" *) 
  (* LC_PROBE417_IS_DATA = "1'b0" *) 
  (* LC_PROBE417_IS_TRIG = "1'b0" *) 
  (* LC_PROBE417_MU_CNT = "1" *) 
  (* LC_PROBE417_PID = "16'b0000000110100001" *) 
  (* LC_PROBE417_TYPE = "1" *) 
  (* LC_PROBE417_WIDTH = "1" *) 
  (* LC_PROBE418_IS_DATA = "1'b0" *) 
  (* LC_PROBE418_IS_TRIG = "1'b0" *) 
  (* LC_PROBE418_MU_CNT = "1" *) 
  (* LC_PROBE418_PID = "16'b0000000110100010" *) 
  (* LC_PROBE418_TYPE = "1" *) 
  (* LC_PROBE418_WIDTH = "1" *) 
  (* LC_PROBE419_IS_DATA = "1'b0" *) 
  (* LC_PROBE419_IS_TRIG = "1'b0" *) 
  (* LC_PROBE419_MU_CNT = "1" *) 
  (* LC_PROBE419_PID = "16'b0000000110100011" *) 
  (* LC_PROBE419_TYPE = "1" *) 
  (* LC_PROBE419_WIDTH = "1" *) 
  (* LC_PROBE41_IS_DATA = "1'b0" *) 
  (* LC_PROBE41_IS_TRIG = "1'b0" *) 
  (* LC_PROBE41_MU_CNT = "1" *) 
  (* LC_PROBE41_PID = "16'b0000000000101001" *) 
  (* LC_PROBE41_TYPE = "1" *) 
  (* LC_PROBE41_WIDTH = "1" *) 
  (* LC_PROBE420_IS_DATA = "1'b0" *) 
  (* LC_PROBE420_IS_TRIG = "1'b0" *) 
  (* LC_PROBE420_MU_CNT = "1" *) 
  (* LC_PROBE420_PID = "16'b0000000110100100" *) 
  (* LC_PROBE420_TYPE = "1" *) 
  (* LC_PROBE420_WIDTH = "1" *) 
  (* LC_PROBE421_IS_DATA = "1'b0" *) 
  (* LC_PROBE421_IS_TRIG = "1'b0" *) 
  (* LC_PROBE421_MU_CNT = "1" *) 
  (* LC_PROBE421_PID = "16'b0000000110100101" *) 
  (* LC_PROBE421_TYPE = "1" *) 
  (* LC_PROBE421_WIDTH = "1" *) 
  (* LC_PROBE422_IS_DATA = "1'b0" *) 
  (* LC_PROBE422_IS_TRIG = "1'b0" *) 
  (* LC_PROBE422_MU_CNT = "1" *) 
  (* LC_PROBE422_PID = "16'b0000000110100110" *) 
  (* LC_PROBE422_TYPE = "1" *) 
  (* LC_PROBE422_WIDTH = "1" *) 
  (* LC_PROBE423_IS_DATA = "1'b0" *) 
  (* LC_PROBE423_IS_TRIG = "1'b0" *) 
  (* LC_PROBE423_MU_CNT = "1" *) 
  (* LC_PROBE423_PID = "16'b0000000110100111" *) 
  (* LC_PROBE423_TYPE = "1" *) 
  (* LC_PROBE423_WIDTH = "1" *) 
  (* LC_PROBE424_IS_DATA = "1'b0" *) 
  (* LC_PROBE424_IS_TRIG = "1'b0" *) 
  (* LC_PROBE424_MU_CNT = "1" *) 
  (* LC_PROBE424_PID = "16'b0000000110101000" *) 
  (* LC_PROBE424_TYPE = "1" *) 
  (* LC_PROBE424_WIDTH = "1" *) 
  (* LC_PROBE425_IS_DATA = "1'b0" *) 
  (* LC_PROBE425_IS_TRIG = "1'b0" *) 
  (* LC_PROBE425_MU_CNT = "1" *) 
  (* LC_PROBE425_PID = "16'b0000000110101001" *) 
  (* LC_PROBE425_TYPE = "1" *) 
  (* LC_PROBE425_WIDTH = "1" *) 
  (* LC_PROBE426_IS_DATA = "1'b0" *) 
  (* LC_PROBE426_IS_TRIG = "1'b0" *) 
  (* LC_PROBE426_MU_CNT = "1" *) 
  (* LC_PROBE426_PID = "16'b0000000110101010" *) 
  (* LC_PROBE426_TYPE = "1" *) 
  (* LC_PROBE426_WIDTH = "1" *) 
  (* LC_PROBE427_IS_DATA = "1'b0" *) 
  (* LC_PROBE427_IS_TRIG = "1'b0" *) 
  (* LC_PROBE427_MU_CNT = "1" *) 
  (* LC_PROBE427_PID = "16'b0000000110101011" *) 
  (* LC_PROBE427_TYPE = "1" *) 
  (* LC_PROBE427_WIDTH = "1" *) 
  (* LC_PROBE428_IS_DATA = "1'b0" *) 
  (* LC_PROBE428_IS_TRIG = "1'b0" *) 
  (* LC_PROBE428_MU_CNT = "1" *) 
  (* LC_PROBE428_PID = "16'b0000000110101100" *) 
  (* LC_PROBE428_TYPE = "1" *) 
  (* LC_PROBE428_WIDTH = "1" *) 
  (* LC_PROBE429_IS_DATA = "1'b0" *) 
  (* LC_PROBE429_IS_TRIG = "1'b0" *) 
  (* LC_PROBE429_MU_CNT = "1" *) 
  (* LC_PROBE429_PID = "16'b0000000110101101" *) 
  (* LC_PROBE429_TYPE = "1" *) 
  (* LC_PROBE429_WIDTH = "1" *) 
  (* LC_PROBE42_IS_DATA = "1'b0" *) 
  (* LC_PROBE42_IS_TRIG = "1'b0" *) 
  (* LC_PROBE42_MU_CNT = "1" *) 
  (* LC_PROBE42_PID = "16'b0000000000101010" *) 
  (* LC_PROBE42_TYPE = "1" *) 
  (* LC_PROBE42_WIDTH = "1" *) 
  (* LC_PROBE430_IS_DATA = "1'b0" *) 
  (* LC_PROBE430_IS_TRIG = "1'b0" *) 
  (* LC_PROBE430_MU_CNT = "1" *) 
  (* LC_PROBE430_PID = "16'b0000000110101110" *) 
  (* LC_PROBE430_TYPE = "1" *) 
  (* LC_PROBE430_WIDTH = "1" *) 
  (* LC_PROBE431_IS_DATA = "1'b0" *) 
  (* LC_PROBE431_IS_TRIG = "1'b0" *) 
  (* LC_PROBE431_MU_CNT = "1" *) 
  (* LC_PROBE431_PID = "16'b0000000110101111" *) 
  (* LC_PROBE431_TYPE = "1" *) 
  (* LC_PROBE431_WIDTH = "1" *) 
  (* LC_PROBE432_IS_DATA = "1'b0" *) 
  (* LC_PROBE432_IS_TRIG = "1'b0" *) 
  (* LC_PROBE432_MU_CNT = "1" *) 
  (* LC_PROBE432_PID = "16'b0000000110110000" *) 
  (* LC_PROBE432_TYPE = "1" *) 
  (* LC_PROBE432_WIDTH = "1" *) 
  (* LC_PROBE433_IS_DATA = "1'b0" *) 
  (* LC_PROBE433_IS_TRIG = "1'b0" *) 
  (* LC_PROBE433_MU_CNT = "1" *) 
  (* LC_PROBE433_PID = "16'b0000000110110001" *) 
  (* LC_PROBE433_TYPE = "1" *) 
  (* LC_PROBE433_WIDTH = "1" *) 
  (* LC_PROBE434_IS_DATA = "1'b0" *) 
  (* LC_PROBE434_IS_TRIG = "1'b0" *) 
  (* LC_PROBE434_MU_CNT = "1" *) 
  (* LC_PROBE434_PID = "16'b0000000110110010" *) 
  (* LC_PROBE434_TYPE = "1" *) 
  (* LC_PROBE434_WIDTH = "1" *) 
  (* LC_PROBE435_IS_DATA = "1'b0" *) 
  (* LC_PROBE435_IS_TRIG = "1'b0" *) 
  (* LC_PROBE435_MU_CNT = "1" *) 
  (* LC_PROBE435_PID = "16'b0000000110110011" *) 
  (* LC_PROBE435_TYPE = "1" *) 
  (* LC_PROBE435_WIDTH = "1" *) 
  (* LC_PROBE436_IS_DATA = "1'b0" *) 
  (* LC_PROBE436_IS_TRIG = "1'b0" *) 
  (* LC_PROBE436_MU_CNT = "1" *) 
  (* LC_PROBE436_PID = "16'b0000000110110100" *) 
  (* LC_PROBE436_TYPE = "1" *) 
  (* LC_PROBE436_WIDTH = "1" *) 
  (* LC_PROBE437_IS_DATA = "1'b0" *) 
  (* LC_PROBE437_IS_TRIG = "1'b0" *) 
  (* LC_PROBE437_MU_CNT = "1" *) 
  (* LC_PROBE437_PID = "16'b0000000110110101" *) 
  (* LC_PROBE437_TYPE = "1" *) 
  (* LC_PROBE437_WIDTH = "1" *) 
  (* LC_PROBE438_IS_DATA = "1'b0" *) 
  (* LC_PROBE438_IS_TRIG = "1'b0" *) 
  (* LC_PROBE438_MU_CNT = "1" *) 
  (* LC_PROBE438_PID = "16'b0000000110110110" *) 
  (* LC_PROBE438_TYPE = "1" *) 
  (* LC_PROBE438_WIDTH = "1" *) 
  (* LC_PROBE439_IS_DATA = "1'b0" *) 
  (* LC_PROBE439_IS_TRIG = "1'b0" *) 
  (* LC_PROBE439_MU_CNT = "1" *) 
  (* LC_PROBE439_PID = "16'b0000000110110111" *) 
  (* LC_PROBE439_TYPE = "1" *) 
  (* LC_PROBE439_WIDTH = "1" *) 
  (* LC_PROBE43_IS_DATA = "1'b0" *) 
  (* LC_PROBE43_IS_TRIG = "1'b0" *) 
  (* LC_PROBE43_MU_CNT = "1" *) 
  (* LC_PROBE43_PID = "16'b0000000000101011" *) 
  (* LC_PROBE43_TYPE = "1" *) 
  (* LC_PROBE43_WIDTH = "1" *) 
  (* LC_PROBE440_IS_DATA = "1'b0" *) 
  (* LC_PROBE440_IS_TRIG = "1'b0" *) 
  (* LC_PROBE440_MU_CNT = "1" *) 
  (* LC_PROBE440_PID = "16'b0000000110111000" *) 
  (* LC_PROBE440_TYPE = "1" *) 
  (* LC_PROBE440_WIDTH = "1" *) 
  (* LC_PROBE441_IS_DATA = "1'b0" *) 
  (* LC_PROBE441_IS_TRIG = "1'b0" *) 
  (* LC_PROBE441_MU_CNT = "1" *) 
  (* LC_PROBE441_PID = "16'b0000000110111001" *) 
  (* LC_PROBE441_TYPE = "1" *) 
  (* LC_PROBE441_WIDTH = "1" *) 
  (* LC_PROBE442_IS_DATA = "1'b0" *) 
  (* LC_PROBE442_IS_TRIG = "1'b0" *) 
  (* LC_PROBE442_MU_CNT = "1" *) 
  (* LC_PROBE442_PID = "16'b0000000110111010" *) 
  (* LC_PROBE442_TYPE = "1" *) 
  (* LC_PROBE442_WIDTH = "1" *) 
  (* LC_PROBE443_IS_DATA = "1'b0" *) 
  (* LC_PROBE443_IS_TRIG = "1'b0" *) 
  (* LC_PROBE443_MU_CNT = "1" *) 
  (* LC_PROBE443_PID = "16'b0000000110111011" *) 
  (* LC_PROBE443_TYPE = "1" *) 
  (* LC_PROBE443_WIDTH = "1" *) 
  (* LC_PROBE444_IS_DATA = "1'b0" *) 
  (* LC_PROBE444_IS_TRIG = "1'b0" *) 
  (* LC_PROBE444_MU_CNT = "1" *) 
  (* LC_PROBE444_PID = "16'b0000000110111100" *) 
  (* LC_PROBE444_TYPE = "1" *) 
  (* LC_PROBE444_WIDTH = "1" *) 
  (* LC_PROBE445_IS_DATA = "1'b0" *) 
  (* LC_PROBE445_IS_TRIG = "1'b0" *) 
  (* LC_PROBE445_MU_CNT = "1" *) 
  (* LC_PROBE445_PID = "16'b0000000110111101" *) 
  (* LC_PROBE445_TYPE = "1" *) 
  (* LC_PROBE445_WIDTH = "1" *) 
  (* LC_PROBE446_IS_DATA = "1'b0" *) 
  (* LC_PROBE446_IS_TRIG = "1'b0" *) 
  (* LC_PROBE446_MU_CNT = "1" *) 
  (* LC_PROBE446_PID = "16'b0000000110111110" *) 
  (* LC_PROBE446_TYPE = "1" *) 
  (* LC_PROBE446_WIDTH = "1" *) 
  (* LC_PROBE447_IS_DATA = "1'b0" *) 
  (* LC_PROBE447_IS_TRIG = "1'b0" *) 
  (* LC_PROBE447_MU_CNT = "1" *) 
  (* LC_PROBE447_PID = "16'b0000000110111111" *) 
  (* LC_PROBE447_TYPE = "1" *) 
  (* LC_PROBE447_WIDTH = "1" *) 
  (* LC_PROBE448_IS_DATA = "1'b0" *) 
  (* LC_PROBE448_IS_TRIG = "1'b0" *) 
  (* LC_PROBE448_MU_CNT = "1" *) 
  (* LC_PROBE448_PID = "16'b0000000111000000" *) 
  (* LC_PROBE448_TYPE = "1" *) 
  (* LC_PROBE448_WIDTH = "1" *) 
  (* LC_PROBE449_IS_DATA = "1'b0" *) 
  (* LC_PROBE449_IS_TRIG = "1'b0" *) 
  (* LC_PROBE449_MU_CNT = "1" *) 
  (* LC_PROBE449_PID = "16'b0000000111000001" *) 
  (* LC_PROBE449_TYPE = "1" *) 
  (* LC_PROBE449_WIDTH = "1" *) 
  (* LC_PROBE44_IS_DATA = "1'b0" *) 
  (* LC_PROBE44_IS_TRIG = "1'b0" *) 
  (* LC_PROBE44_MU_CNT = "1" *) 
  (* LC_PROBE44_PID = "16'b0000000000101100" *) 
  (* LC_PROBE44_TYPE = "1" *) 
  (* LC_PROBE44_WIDTH = "1" *) 
  (* LC_PROBE450_IS_DATA = "1'b0" *) 
  (* LC_PROBE450_IS_TRIG = "1'b0" *) 
  (* LC_PROBE450_MU_CNT = "1" *) 
  (* LC_PROBE450_PID = "16'b0000000111000010" *) 
  (* LC_PROBE450_TYPE = "1" *) 
  (* LC_PROBE450_WIDTH = "1" *) 
  (* LC_PROBE451_IS_DATA = "1'b0" *) 
  (* LC_PROBE451_IS_TRIG = "1'b0" *) 
  (* LC_PROBE451_MU_CNT = "1" *) 
  (* LC_PROBE451_PID = "16'b0000000111000011" *) 
  (* LC_PROBE451_TYPE = "1" *) 
  (* LC_PROBE451_WIDTH = "1" *) 
  (* LC_PROBE452_IS_DATA = "1'b0" *) 
  (* LC_PROBE452_IS_TRIG = "1'b0" *) 
  (* LC_PROBE452_MU_CNT = "1" *) 
  (* LC_PROBE452_PID = "16'b0000000111000100" *) 
  (* LC_PROBE452_TYPE = "1" *) 
  (* LC_PROBE452_WIDTH = "1" *) 
  (* LC_PROBE453_IS_DATA = "1'b0" *) 
  (* LC_PROBE453_IS_TRIG = "1'b0" *) 
  (* LC_PROBE453_MU_CNT = "1" *) 
  (* LC_PROBE453_PID = "16'b0000000111000101" *) 
  (* LC_PROBE453_TYPE = "1" *) 
  (* LC_PROBE453_WIDTH = "1" *) 
  (* LC_PROBE454_IS_DATA = "1'b0" *) 
  (* LC_PROBE454_IS_TRIG = "1'b0" *) 
  (* LC_PROBE454_MU_CNT = "1" *) 
  (* LC_PROBE454_PID = "16'b0000000111000110" *) 
  (* LC_PROBE454_TYPE = "1" *) 
  (* LC_PROBE454_WIDTH = "1" *) 
  (* LC_PROBE455_IS_DATA = "1'b0" *) 
  (* LC_PROBE455_IS_TRIG = "1'b0" *) 
  (* LC_PROBE455_MU_CNT = "1" *) 
  (* LC_PROBE455_PID = "16'b0000000111000111" *) 
  (* LC_PROBE455_TYPE = "1" *) 
  (* LC_PROBE455_WIDTH = "1" *) 
  (* LC_PROBE456_IS_DATA = "1'b0" *) 
  (* LC_PROBE456_IS_TRIG = "1'b0" *) 
  (* LC_PROBE456_MU_CNT = "1" *) 
  (* LC_PROBE456_PID = "16'b0000000111001000" *) 
  (* LC_PROBE456_TYPE = "1" *) 
  (* LC_PROBE456_WIDTH = "1" *) 
  (* LC_PROBE457_IS_DATA = "1'b0" *) 
  (* LC_PROBE457_IS_TRIG = "1'b0" *) 
  (* LC_PROBE457_MU_CNT = "1" *) 
  (* LC_PROBE457_PID = "16'b0000000111001001" *) 
  (* LC_PROBE457_TYPE = "1" *) 
  (* LC_PROBE457_WIDTH = "1" *) 
  (* LC_PROBE458_IS_DATA = "1'b0" *) 
  (* LC_PROBE458_IS_TRIG = "1'b0" *) 
  (* LC_PROBE458_MU_CNT = "1" *) 
  (* LC_PROBE458_PID = "16'b0000000111001010" *) 
  (* LC_PROBE458_TYPE = "1" *) 
  (* LC_PROBE458_WIDTH = "1" *) 
  (* LC_PROBE459_IS_DATA = "1'b0" *) 
  (* LC_PROBE459_IS_TRIG = "1'b0" *) 
  (* LC_PROBE459_MU_CNT = "1" *) 
  (* LC_PROBE459_PID = "16'b0000000111001011" *) 
  (* LC_PROBE459_TYPE = "1" *) 
  (* LC_PROBE459_WIDTH = "1" *) 
  (* LC_PROBE45_IS_DATA = "1'b0" *) 
  (* LC_PROBE45_IS_TRIG = "1'b0" *) 
  (* LC_PROBE45_MU_CNT = "1" *) 
  (* LC_PROBE45_PID = "16'b0000000000101101" *) 
  (* LC_PROBE45_TYPE = "1" *) 
  (* LC_PROBE45_WIDTH = "1" *) 
  (* LC_PROBE460_IS_DATA = "1'b0" *) 
  (* LC_PROBE460_IS_TRIG = "1'b0" *) 
  (* LC_PROBE460_MU_CNT = "1" *) 
  (* LC_PROBE460_PID = "16'b0000000111001100" *) 
  (* LC_PROBE460_TYPE = "1" *) 
  (* LC_PROBE460_WIDTH = "1" *) 
  (* LC_PROBE461_IS_DATA = "1'b0" *) 
  (* LC_PROBE461_IS_TRIG = "1'b0" *) 
  (* LC_PROBE461_MU_CNT = "1" *) 
  (* LC_PROBE461_PID = "16'b0000000111001101" *) 
  (* LC_PROBE461_TYPE = "1" *) 
  (* LC_PROBE461_WIDTH = "1" *) 
  (* LC_PROBE462_IS_DATA = "1'b0" *) 
  (* LC_PROBE462_IS_TRIG = "1'b0" *) 
  (* LC_PROBE462_MU_CNT = "1" *) 
  (* LC_PROBE462_PID = "16'b0000000111001110" *) 
  (* LC_PROBE462_TYPE = "1" *) 
  (* LC_PROBE462_WIDTH = "1" *) 
  (* LC_PROBE463_IS_DATA = "1'b0" *) 
  (* LC_PROBE463_IS_TRIG = "1'b0" *) 
  (* LC_PROBE463_MU_CNT = "1" *) 
  (* LC_PROBE463_PID = "16'b0000000111001111" *) 
  (* LC_PROBE463_TYPE = "1" *) 
  (* LC_PROBE463_WIDTH = "1" *) 
  (* LC_PROBE464_IS_DATA = "1'b0" *) 
  (* LC_PROBE464_IS_TRIG = "1'b0" *) 
  (* LC_PROBE464_MU_CNT = "1" *) 
  (* LC_PROBE464_PID = "16'b0000000111010000" *) 
  (* LC_PROBE464_TYPE = "1" *) 
  (* LC_PROBE464_WIDTH = "1" *) 
  (* LC_PROBE465_IS_DATA = "1'b0" *) 
  (* LC_PROBE465_IS_TRIG = "1'b0" *) 
  (* LC_PROBE465_MU_CNT = "1" *) 
  (* LC_PROBE465_PID = "16'b0000000111010001" *) 
  (* LC_PROBE465_TYPE = "1" *) 
  (* LC_PROBE465_WIDTH = "1" *) 
  (* LC_PROBE466_IS_DATA = "1'b0" *) 
  (* LC_PROBE466_IS_TRIG = "1'b0" *) 
  (* LC_PROBE466_MU_CNT = "1" *) 
  (* LC_PROBE466_PID = "16'b0000000111010010" *) 
  (* LC_PROBE466_TYPE = "1" *) 
  (* LC_PROBE466_WIDTH = "1" *) 
  (* LC_PROBE467_IS_DATA = "1'b0" *) 
  (* LC_PROBE467_IS_TRIG = "1'b0" *) 
  (* LC_PROBE467_MU_CNT = "1" *) 
  (* LC_PROBE467_PID = "16'b0000000111010011" *) 
  (* LC_PROBE467_TYPE = "1" *) 
  (* LC_PROBE467_WIDTH = "1" *) 
  (* LC_PROBE468_IS_DATA = "1'b0" *) 
  (* LC_PROBE468_IS_TRIG = "1'b0" *) 
  (* LC_PROBE468_MU_CNT = "1" *) 
  (* LC_PROBE468_PID = "16'b0000000111010100" *) 
  (* LC_PROBE468_TYPE = "1" *) 
  (* LC_PROBE468_WIDTH = "1" *) 
  (* LC_PROBE469_IS_DATA = "1'b0" *) 
  (* LC_PROBE469_IS_TRIG = "1'b0" *) 
  (* LC_PROBE469_MU_CNT = "1" *) 
  (* LC_PROBE469_PID = "16'b0000000111010101" *) 
  (* LC_PROBE469_TYPE = "1" *) 
  (* LC_PROBE469_WIDTH = "1" *) 
  (* LC_PROBE46_IS_DATA = "1'b0" *) 
  (* LC_PROBE46_IS_TRIG = "1'b0" *) 
  (* LC_PROBE46_MU_CNT = "1" *) 
  (* LC_PROBE46_PID = "16'b0000000000101110" *) 
  (* LC_PROBE46_TYPE = "1" *) 
  (* LC_PROBE46_WIDTH = "1" *) 
  (* LC_PROBE470_IS_DATA = "1'b0" *) 
  (* LC_PROBE470_IS_TRIG = "1'b0" *) 
  (* LC_PROBE470_MU_CNT = "1" *) 
  (* LC_PROBE470_PID = "16'b0000000111010110" *) 
  (* LC_PROBE470_TYPE = "1" *) 
  (* LC_PROBE470_WIDTH = "1" *) 
  (* LC_PROBE471_IS_DATA = "1'b0" *) 
  (* LC_PROBE471_IS_TRIG = "1'b0" *) 
  (* LC_PROBE471_MU_CNT = "1" *) 
  (* LC_PROBE471_PID = "16'b0000000111010111" *) 
  (* LC_PROBE471_TYPE = "1" *) 
  (* LC_PROBE471_WIDTH = "1" *) 
  (* LC_PROBE472_IS_DATA = "1'b0" *) 
  (* LC_PROBE472_IS_TRIG = "1'b0" *) 
  (* LC_PROBE472_MU_CNT = "1" *) 
  (* LC_PROBE472_PID = "16'b0000000111011000" *) 
  (* LC_PROBE472_TYPE = "1" *) 
  (* LC_PROBE472_WIDTH = "1" *) 
  (* LC_PROBE473_IS_DATA = "1'b0" *) 
  (* LC_PROBE473_IS_TRIG = "1'b0" *) 
  (* LC_PROBE473_MU_CNT = "1" *) 
  (* LC_PROBE473_PID = "16'b0000000111011001" *) 
  (* LC_PROBE473_TYPE = "1" *) 
  (* LC_PROBE473_WIDTH = "1" *) 
  (* LC_PROBE474_IS_DATA = "1'b0" *) 
  (* LC_PROBE474_IS_TRIG = "1'b0" *) 
  (* LC_PROBE474_MU_CNT = "1" *) 
  (* LC_PROBE474_PID = "16'b0000000111011010" *) 
  (* LC_PROBE474_TYPE = "1" *) 
  (* LC_PROBE474_WIDTH = "1" *) 
  (* LC_PROBE475_IS_DATA = "1'b0" *) 
  (* LC_PROBE475_IS_TRIG = "1'b0" *) 
  (* LC_PROBE475_MU_CNT = "1" *) 
  (* LC_PROBE475_PID = "16'b0000000111011011" *) 
  (* LC_PROBE475_TYPE = "1" *) 
  (* LC_PROBE475_WIDTH = "1" *) 
  (* LC_PROBE476_IS_DATA = "1'b0" *) 
  (* LC_PROBE476_IS_TRIG = "1'b0" *) 
  (* LC_PROBE476_MU_CNT = "1" *) 
  (* LC_PROBE476_PID = "16'b0000000111011100" *) 
  (* LC_PROBE476_TYPE = "1" *) 
  (* LC_PROBE476_WIDTH = "1" *) 
  (* LC_PROBE477_IS_DATA = "1'b0" *) 
  (* LC_PROBE477_IS_TRIG = "1'b0" *) 
  (* LC_PROBE477_MU_CNT = "1" *) 
  (* LC_PROBE477_PID = "16'b0000000111011101" *) 
  (* LC_PROBE477_TYPE = "1" *) 
  (* LC_PROBE477_WIDTH = "1" *) 
  (* LC_PROBE478_IS_DATA = "1'b0" *) 
  (* LC_PROBE478_IS_TRIG = "1'b0" *) 
  (* LC_PROBE478_MU_CNT = "1" *) 
  (* LC_PROBE478_PID = "16'b0000000111011110" *) 
  (* LC_PROBE478_TYPE = "1" *) 
  (* LC_PROBE478_WIDTH = "1" *) 
  (* LC_PROBE479_IS_DATA = "1'b0" *) 
  (* LC_PROBE479_IS_TRIG = "1'b0" *) 
  (* LC_PROBE479_MU_CNT = "1" *) 
  (* LC_PROBE479_PID = "16'b0000000111011111" *) 
  (* LC_PROBE479_TYPE = "1" *) 
  (* LC_PROBE479_WIDTH = "1" *) 
  (* LC_PROBE47_IS_DATA = "1'b0" *) 
  (* LC_PROBE47_IS_TRIG = "1'b0" *) 
  (* LC_PROBE47_MU_CNT = "1" *) 
  (* LC_PROBE47_PID = "16'b0000000000101111" *) 
  (* LC_PROBE47_TYPE = "1" *) 
  (* LC_PROBE47_WIDTH = "1" *) 
  (* LC_PROBE480_IS_DATA = "1'b0" *) 
  (* LC_PROBE480_IS_TRIG = "1'b0" *) 
  (* LC_PROBE480_MU_CNT = "1" *) 
  (* LC_PROBE480_PID = "16'b0000000111100000" *) 
  (* LC_PROBE480_TYPE = "1" *) 
  (* LC_PROBE480_WIDTH = "1" *) 
  (* LC_PROBE481_IS_DATA = "1'b0" *) 
  (* LC_PROBE481_IS_TRIG = "1'b0" *) 
  (* LC_PROBE481_MU_CNT = "1" *) 
  (* LC_PROBE481_PID = "16'b0000000111100001" *) 
  (* LC_PROBE481_TYPE = "1" *) 
  (* LC_PROBE481_WIDTH = "1" *) 
  (* LC_PROBE482_IS_DATA = "1'b0" *) 
  (* LC_PROBE482_IS_TRIG = "1'b0" *) 
  (* LC_PROBE482_MU_CNT = "1" *) 
  (* LC_PROBE482_PID = "16'b0000000111100010" *) 
  (* LC_PROBE482_TYPE = "1" *) 
  (* LC_PROBE482_WIDTH = "1" *) 
  (* LC_PROBE483_IS_DATA = "1'b0" *) 
  (* LC_PROBE483_IS_TRIG = "1'b0" *) 
  (* LC_PROBE483_MU_CNT = "1" *) 
  (* LC_PROBE483_PID = "16'b0000000111100011" *) 
  (* LC_PROBE483_TYPE = "1" *) 
  (* LC_PROBE483_WIDTH = "1" *) 
  (* LC_PROBE484_IS_DATA = "1'b0" *) 
  (* LC_PROBE484_IS_TRIG = "1'b0" *) 
  (* LC_PROBE484_MU_CNT = "1" *) 
  (* LC_PROBE484_PID = "16'b0000000111100100" *) 
  (* LC_PROBE484_TYPE = "1" *) 
  (* LC_PROBE484_WIDTH = "1" *) 
  (* LC_PROBE485_IS_DATA = "1'b0" *) 
  (* LC_PROBE485_IS_TRIG = "1'b0" *) 
  (* LC_PROBE485_MU_CNT = "1" *) 
  (* LC_PROBE485_PID = "16'b0000000111100101" *) 
  (* LC_PROBE485_TYPE = "1" *) 
  (* LC_PROBE485_WIDTH = "1" *) 
  (* LC_PROBE486_IS_DATA = "1'b0" *) 
  (* LC_PROBE486_IS_TRIG = "1'b0" *) 
  (* LC_PROBE486_MU_CNT = "1" *) 
  (* LC_PROBE486_PID = "16'b0000000111100110" *) 
  (* LC_PROBE486_TYPE = "1" *) 
  (* LC_PROBE486_WIDTH = "1" *) 
  (* LC_PROBE487_IS_DATA = "1'b0" *) 
  (* LC_PROBE487_IS_TRIG = "1'b0" *) 
  (* LC_PROBE487_MU_CNT = "1" *) 
  (* LC_PROBE487_PID = "16'b0000000111100111" *) 
  (* LC_PROBE487_TYPE = "1" *) 
  (* LC_PROBE487_WIDTH = "1" *) 
  (* LC_PROBE488_IS_DATA = "1'b0" *) 
  (* LC_PROBE488_IS_TRIG = "1'b0" *) 
  (* LC_PROBE488_MU_CNT = "1" *) 
  (* LC_PROBE488_PID = "16'b0000000111101000" *) 
  (* LC_PROBE488_TYPE = "1" *) 
  (* LC_PROBE488_WIDTH = "1" *) 
  (* LC_PROBE489_IS_DATA = "1'b0" *) 
  (* LC_PROBE489_IS_TRIG = "1'b0" *) 
  (* LC_PROBE489_MU_CNT = "1" *) 
  (* LC_PROBE489_PID = "16'b0000000111101001" *) 
  (* LC_PROBE489_TYPE = "1" *) 
  (* LC_PROBE489_WIDTH = "1" *) 
  (* LC_PROBE48_IS_DATA = "1'b0" *) 
  (* LC_PROBE48_IS_TRIG = "1'b0" *) 
  (* LC_PROBE48_MU_CNT = "1" *) 
  (* LC_PROBE48_PID = "16'b0000000000110000" *) 
  (* LC_PROBE48_TYPE = "1" *) 
  (* LC_PROBE48_WIDTH = "1" *) 
  (* LC_PROBE490_IS_DATA = "1'b0" *) 
  (* LC_PROBE490_IS_TRIG = "1'b0" *) 
  (* LC_PROBE490_MU_CNT = "1" *) 
  (* LC_PROBE490_PID = "16'b0000000111101010" *) 
  (* LC_PROBE490_TYPE = "1" *) 
  (* LC_PROBE490_WIDTH = "1" *) 
  (* LC_PROBE491_IS_DATA = "1'b0" *) 
  (* LC_PROBE491_IS_TRIG = "1'b0" *) 
  (* LC_PROBE491_MU_CNT = "1" *) 
  (* LC_PROBE491_PID = "16'b0000000111101011" *) 
  (* LC_PROBE491_TYPE = "1" *) 
  (* LC_PROBE491_WIDTH = "1" *) 
  (* LC_PROBE492_IS_DATA = "1'b0" *) 
  (* LC_PROBE492_IS_TRIG = "1'b0" *) 
  (* LC_PROBE492_MU_CNT = "1" *) 
  (* LC_PROBE492_PID = "16'b0000000111101100" *) 
  (* LC_PROBE492_TYPE = "1" *) 
  (* LC_PROBE492_WIDTH = "1" *) 
  (* LC_PROBE493_IS_DATA = "1'b0" *) 
  (* LC_PROBE493_IS_TRIG = "1'b0" *) 
  (* LC_PROBE493_MU_CNT = "1" *) 
  (* LC_PROBE493_PID = "16'b0000000111101101" *) 
  (* LC_PROBE493_TYPE = "1" *) 
  (* LC_PROBE493_WIDTH = "1" *) 
  (* LC_PROBE494_IS_DATA = "1'b0" *) 
  (* LC_PROBE494_IS_TRIG = "1'b0" *) 
  (* LC_PROBE494_MU_CNT = "1" *) 
  (* LC_PROBE494_PID = "16'b0000000111101110" *) 
  (* LC_PROBE494_TYPE = "1" *) 
  (* LC_PROBE494_WIDTH = "1" *) 
  (* LC_PROBE495_IS_DATA = "1'b0" *) 
  (* LC_PROBE495_IS_TRIG = "1'b0" *) 
  (* LC_PROBE495_MU_CNT = "1" *) 
  (* LC_PROBE495_PID = "16'b0000000111101111" *) 
  (* LC_PROBE495_TYPE = "1" *) 
  (* LC_PROBE495_WIDTH = "1" *) 
  (* LC_PROBE496_IS_DATA = "1'b0" *) 
  (* LC_PROBE496_IS_TRIG = "1'b0" *) 
  (* LC_PROBE496_MU_CNT = "1" *) 
  (* LC_PROBE496_PID = "16'b0000000111110000" *) 
  (* LC_PROBE496_TYPE = "1" *) 
  (* LC_PROBE496_WIDTH = "1" *) 
  (* LC_PROBE497_IS_DATA = "1'b0" *) 
  (* LC_PROBE497_IS_TRIG = "1'b0" *) 
  (* LC_PROBE497_MU_CNT = "1" *) 
  (* LC_PROBE497_PID = "16'b0000000111110001" *) 
  (* LC_PROBE497_TYPE = "1" *) 
  (* LC_PROBE497_WIDTH = "1" *) 
  (* LC_PROBE498_IS_DATA = "1'b0" *) 
  (* LC_PROBE498_IS_TRIG = "1'b0" *) 
  (* LC_PROBE498_MU_CNT = "1" *) 
  (* LC_PROBE498_PID = "16'b0000000111110010" *) 
  (* LC_PROBE498_TYPE = "1" *) 
  (* LC_PROBE498_WIDTH = "1" *) 
  (* LC_PROBE499_IS_DATA = "1'b0" *) 
  (* LC_PROBE499_IS_TRIG = "1'b0" *) 
  (* LC_PROBE499_MU_CNT = "1" *) 
  (* LC_PROBE499_PID = "16'b0000000111110011" *) 
  (* LC_PROBE499_TYPE = "1" *) 
  (* LC_PROBE499_WIDTH = "1" *) 
  (* LC_PROBE49_IS_DATA = "1'b0" *) 
  (* LC_PROBE49_IS_TRIG = "1'b0" *) 
  (* LC_PROBE49_MU_CNT = "1" *) 
  (* LC_PROBE49_PID = "16'b0000000000110001" *) 
  (* LC_PROBE49_TYPE = "1" *) 
  (* LC_PROBE49_WIDTH = "1" *) 
  (* LC_PROBE4_IS_DATA = "1'b0" *) 
  (* LC_PROBE4_IS_TRIG = "1'b0" *) 
  (* LC_PROBE4_MU_CNT = "1" *) 
  (* LC_PROBE4_PID = "16'b0000000000000100" *) 
  (* LC_PROBE4_TYPE = "1" *) 
  (* LC_PROBE4_WIDTH = "1" *) 
  (* LC_PROBE500_IS_DATA = "1'b0" *) 
  (* LC_PROBE500_IS_TRIG = "1'b0" *) 
  (* LC_PROBE500_MU_CNT = "1" *) 
  (* LC_PROBE500_PID = "16'b0000000111110100" *) 
  (* LC_PROBE500_TYPE = "1" *) 
  (* LC_PROBE500_WIDTH = "1" *) 
  (* LC_PROBE501_IS_DATA = "1'b0" *) 
  (* LC_PROBE501_IS_TRIG = "1'b0" *) 
  (* LC_PROBE501_MU_CNT = "1" *) 
  (* LC_PROBE501_PID = "16'b0000000111110101" *) 
  (* LC_PROBE501_TYPE = "1" *) 
  (* LC_PROBE501_WIDTH = "1" *) 
  (* LC_PROBE502_IS_DATA = "1'b0" *) 
  (* LC_PROBE502_IS_TRIG = "1'b0" *) 
  (* LC_PROBE502_MU_CNT = "1" *) 
  (* LC_PROBE502_PID = "16'b0000000111110110" *) 
  (* LC_PROBE502_TYPE = "1" *) 
  (* LC_PROBE502_WIDTH = "1" *) 
  (* LC_PROBE503_IS_DATA = "1'b0" *) 
  (* LC_PROBE503_IS_TRIG = "1'b0" *) 
  (* LC_PROBE503_MU_CNT = "1" *) 
  (* LC_PROBE503_PID = "16'b0000000111110111" *) 
  (* LC_PROBE503_TYPE = "1" *) 
  (* LC_PROBE503_WIDTH = "1" *) 
  (* LC_PROBE504_IS_DATA = "1'b0" *) 
  (* LC_PROBE504_IS_TRIG = "1'b0" *) 
  (* LC_PROBE504_MU_CNT = "1" *) 
  (* LC_PROBE504_PID = "16'b0000000111111000" *) 
  (* LC_PROBE504_TYPE = "1" *) 
  (* LC_PROBE504_WIDTH = "1" *) 
  (* LC_PROBE505_IS_DATA = "1'b0" *) 
  (* LC_PROBE505_IS_TRIG = "1'b0" *) 
  (* LC_PROBE505_MU_CNT = "1" *) 
  (* LC_PROBE505_PID = "16'b0000000111111001" *) 
  (* LC_PROBE505_TYPE = "1" *) 
  (* LC_PROBE505_WIDTH = "1" *) 
  (* LC_PROBE506_IS_DATA = "1'b0" *) 
  (* LC_PROBE506_IS_TRIG = "1'b0" *) 
  (* LC_PROBE506_MU_CNT = "1" *) 
  (* LC_PROBE506_PID = "16'b0000000111111010" *) 
  (* LC_PROBE506_TYPE = "1" *) 
  (* LC_PROBE506_WIDTH = "1" *) 
  (* LC_PROBE507_IS_DATA = "1'b0" *) 
  (* LC_PROBE507_IS_TRIG = "1'b0" *) 
  (* LC_PROBE507_MU_CNT = "1" *) 
  (* LC_PROBE507_PID = "16'b0000000111111011" *) 
  (* LC_PROBE507_TYPE = "1" *) 
  (* LC_PROBE507_WIDTH = "1" *) 
  (* LC_PROBE508_IS_DATA = "1'b0" *) 
  (* LC_PROBE508_IS_TRIG = "1'b0" *) 
  (* LC_PROBE508_MU_CNT = "1" *) 
  (* LC_PROBE508_PID = "16'b0000000111111100" *) 
  (* LC_PROBE508_TYPE = "1" *) 
  (* LC_PROBE508_WIDTH = "1" *) 
  (* LC_PROBE509_IS_DATA = "1'b0" *) 
  (* LC_PROBE509_IS_TRIG = "1'b0" *) 
  (* LC_PROBE509_MU_CNT = "1" *) 
  (* LC_PROBE509_PID = "16'b0000000111111101" *) 
  (* LC_PROBE509_TYPE = "1" *) 
  (* LC_PROBE509_WIDTH = "1" *) 
  (* LC_PROBE50_IS_DATA = "1'b0" *) 
  (* LC_PROBE50_IS_TRIG = "1'b0" *) 
  (* LC_PROBE50_MU_CNT = "1" *) 
  (* LC_PROBE50_PID = "16'b0000000000110010" *) 
  (* LC_PROBE50_TYPE = "1" *) 
  (* LC_PROBE50_WIDTH = "1" *) 
  (* LC_PROBE510_IS_DATA = "1'b0" *) 
  (* LC_PROBE510_IS_TRIG = "1'b0" *) 
  (* LC_PROBE510_MU_CNT = "1" *) 
  (* LC_PROBE510_PID = "16'b0000000111111110" *) 
  (* LC_PROBE510_TYPE = "1" *) 
  (* LC_PROBE510_WIDTH = "1" *) 
  (* LC_PROBE511_IS_DATA = "1'b0" *) 
  (* LC_PROBE511_IS_TRIG = "1'b0" *) 
  (* LC_PROBE511_MU_CNT = "1" *) 
  (* LC_PROBE511_PID = "16'b0000000111111111" *) 
  (* LC_PROBE511_TYPE = "1" *) 
  (* LC_PROBE511_WIDTH = "1" *) 
  (* LC_PROBE512_IS_DATA = "1'b0" *) 
  (* LC_PROBE512_IS_TRIG = "1'b0" *) 
  (* LC_PROBE512_MU_CNT = "1" *) 
  (* LC_PROBE512_PID = "16'b0000001000000000" *) 
  (* LC_PROBE512_TYPE = "1" *) 
  (* LC_PROBE512_WIDTH = "1" *) 
  (* LC_PROBE513_IS_DATA = "1'b0" *) 
  (* LC_PROBE513_IS_TRIG = "1'b0" *) 
  (* LC_PROBE513_MU_CNT = "1" *) 
  (* LC_PROBE513_PID = "16'b0000001000000001" *) 
  (* LC_PROBE513_TYPE = "1" *) 
  (* LC_PROBE513_WIDTH = "1" *) 
  (* LC_PROBE514_IS_DATA = "1'b0" *) 
  (* LC_PROBE514_IS_TRIG = "1'b0" *) 
  (* LC_PROBE514_MU_CNT = "1" *) 
  (* LC_PROBE514_PID = "16'b0000001000000010" *) 
  (* LC_PROBE514_TYPE = "1" *) 
  (* LC_PROBE514_WIDTH = "1" *) 
  (* LC_PROBE515_IS_DATA = "1'b0" *) 
  (* LC_PROBE515_IS_TRIG = "1'b0" *) 
  (* LC_PROBE515_MU_CNT = "1" *) 
  (* LC_PROBE515_PID = "16'b0000001000000011" *) 
  (* LC_PROBE515_TYPE = "1" *) 
  (* LC_PROBE515_WIDTH = "1" *) 
  (* LC_PROBE516_IS_DATA = "1'b0" *) 
  (* LC_PROBE516_IS_TRIG = "1'b0" *) 
  (* LC_PROBE516_MU_CNT = "1" *) 
  (* LC_PROBE516_PID = "16'b0000001000000100" *) 
  (* LC_PROBE516_TYPE = "1" *) 
  (* LC_PROBE516_WIDTH = "1" *) 
  (* LC_PROBE517_IS_DATA = "1'b0" *) 
  (* LC_PROBE517_IS_TRIG = "1'b0" *) 
  (* LC_PROBE517_MU_CNT = "1" *) 
  (* LC_PROBE517_PID = "16'b0000001000000101" *) 
  (* LC_PROBE517_TYPE = "1" *) 
  (* LC_PROBE517_WIDTH = "1" *) 
  (* LC_PROBE518_IS_DATA = "1'b0" *) 
  (* LC_PROBE518_IS_TRIG = "1'b0" *) 
  (* LC_PROBE518_MU_CNT = "1" *) 
  (* LC_PROBE518_PID = "16'b0000001000000110" *) 
  (* LC_PROBE518_TYPE = "1" *) 
  (* LC_PROBE518_WIDTH = "1" *) 
  (* LC_PROBE519_IS_DATA = "1'b0" *) 
  (* LC_PROBE519_IS_TRIG = "1'b0" *) 
  (* LC_PROBE519_MU_CNT = "1" *) 
  (* LC_PROBE519_PID = "16'b0000001000000111" *) 
  (* LC_PROBE519_TYPE = "1" *) 
  (* LC_PROBE519_WIDTH = "1" *) 
  (* LC_PROBE51_IS_DATA = "1'b0" *) 
  (* LC_PROBE51_IS_TRIG = "1'b0" *) 
  (* LC_PROBE51_MU_CNT = "1" *) 
  (* LC_PROBE51_PID = "16'b0000000000110011" *) 
  (* LC_PROBE51_TYPE = "1" *) 
  (* LC_PROBE51_WIDTH = "1" *) 
  (* LC_PROBE520_IS_DATA = "1'b0" *) 
  (* LC_PROBE520_IS_TRIG = "1'b0" *) 
  (* LC_PROBE520_MU_CNT = "1" *) 
  (* LC_PROBE520_PID = "16'b0000001000001000" *) 
  (* LC_PROBE520_TYPE = "1" *) 
  (* LC_PROBE520_WIDTH = "1" *) 
  (* LC_PROBE521_IS_DATA = "1'b0" *) 
  (* LC_PROBE521_IS_TRIG = "1'b0" *) 
  (* LC_PROBE521_MU_CNT = "1" *) 
  (* LC_PROBE521_PID = "16'b0000001000001001" *) 
  (* LC_PROBE521_TYPE = "1" *) 
  (* LC_PROBE521_WIDTH = "1" *) 
  (* LC_PROBE522_IS_DATA = "1'b0" *) 
  (* LC_PROBE522_IS_TRIG = "1'b0" *) 
  (* LC_PROBE522_MU_CNT = "1" *) 
  (* LC_PROBE522_PID = "16'b0000001000001010" *) 
  (* LC_PROBE522_TYPE = "1" *) 
  (* LC_PROBE522_WIDTH = "1" *) 
  (* LC_PROBE523_IS_DATA = "1'b0" *) 
  (* LC_PROBE523_IS_TRIG = "1'b0" *) 
  (* LC_PROBE523_MU_CNT = "1" *) 
  (* LC_PROBE523_PID = "16'b0000001000001011" *) 
  (* LC_PROBE523_TYPE = "1" *) 
  (* LC_PROBE523_WIDTH = "1" *) 
  (* LC_PROBE524_IS_DATA = "1'b0" *) 
  (* LC_PROBE524_IS_TRIG = "1'b0" *) 
  (* LC_PROBE524_MU_CNT = "1" *) 
  (* LC_PROBE524_PID = "16'b0000001000001100" *) 
  (* LC_PROBE524_TYPE = "1" *) 
  (* LC_PROBE524_WIDTH = "1" *) 
  (* LC_PROBE525_IS_DATA = "1'b0" *) 
  (* LC_PROBE525_IS_TRIG = "1'b0" *) 
  (* LC_PROBE525_MU_CNT = "1" *) 
  (* LC_PROBE525_PID = "16'b0000001000001101" *) 
  (* LC_PROBE525_TYPE = "1" *) 
  (* LC_PROBE525_WIDTH = "1" *) 
  (* LC_PROBE526_IS_DATA = "1'b0" *) 
  (* LC_PROBE526_IS_TRIG = "1'b0" *) 
  (* LC_PROBE526_MU_CNT = "1" *) 
  (* LC_PROBE526_PID = "16'b0000001000001110" *) 
  (* LC_PROBE526_TYPE = "1" *) 
  (* LC_PROBE526_WIDTH = "1" *) 
  (* LC_PROBE527_IS_DATA = "1'b0" *) 
  (* LC_PROBE527_IS_TRIG = "1'b0" *) 
  (* LC_PROBE527_MU_CNT = "1" *) 
  (* LC_PROBE527_PID = "16'b0000001000001111" *) 
  (* LC_PROBE527_TYPE = "1" *) 
  (* LC_PROBE527_WIDTH = "1" *) 
  (* LC_PROBE528_IS_DATA = "1'b0" *) 
  (* LC_PROBE528_IS_TRIG = "1'b0" *) 
  (* LC_PROBE528_MU_CNT = "1" *) 
  (* LC_PROBE528_PID = "16'b0000001000010000" *) 
  (* LC_PROBE528_TYPE = "1" *) 
  (* LC_PROBE528_WIDTH = "1" *) 
  (* LC_PROBE529_IS_DATA = "1'b0" *) 
  (* LC_PROBE529_IS_TRIG = "1'b0" *) 
  (* LC_PROBE529_MU_CNT = "1" *) 
  (* LC_PROBE529_PID = "16'b0000001000010001" *) 
  (* LC_PROBE529_TYPE = "1" *) 
  (* LC_PROBE529_WIDTH = "1" *) 
  (* LC_PROBE52_IS_DATA = "1'b0" *) 
  (* LC_PROBE52_IS_TRIG = "1'b0" *) 
  (* LC_PROBE52_MU_CNT = "1" *) 
  (* LC_PROBE52_PID = "16'b0000000000110100" *) 
  (* LC_PROBE52_TYPE = "1" *) 
  (* LC_PROBE52_WIDTH = "1" *) 
  (* LC_PROBE530_IS_DATA = "1'b0" *) 
  (* LC_PROBE530_IS_TRIG = "1'b0" *) 
  (* LC_PROBE530_MU_CNT = "1" *) 
  (* LC_PROBE530_PID = "16'b0000001000010010" *) 
  (* LC_PROBE530_TYPE = "1" *) 
  (* LC_PROBE530_WIDTH = "1" *) 
  (* LC_PROBE531_IS_DATA = "1'b0" *) 
  (* LC_PROBE531_IS_TRIG = "1'b0" *) 
  (* LC_PROBE531_MU_CNT = "1" *) 
  (* LC_PROBE531_PID = "16'b0000001000010011" *) 
  (* LC_PROBE531_TYPE = "1" *) 
  (* LC_PROBE531_WIDTH = "1" *) 
  (* LC_PROBE532_IS_DATA = "1'b0" *) 
  (* LC_PROBE532_IS_TRIG = "1'b0" *) 
  (* LC_PROBE532_MU_CNT = "1" *) 
  (* LC_PROBE532_PID = "16'b0000001000010100" *) 
  (* LC_PROBE532_TYPE = "1" *) 
  (* LC_PROBE532_WIDTH = "1" *) 
  (* LC_PROBE533_IS_DATA = "1'b0" *) 
  (* LC_PROBE533_IS_TRIG = "1'b0" *) 
  (* LC_PROBE533_MU_CNT = "1" *) 
  (* LC_PROBE533_PID = "16'b0000001000010101" *) 
  (* LC_PROBE533_TYPE = "1" *) 
  (* LC_PROBE533_WIDTH = "1" *) 
  (* LC_PROBE534_IS_DATA = "1'b0" *) 
  (* LC_PROBE534_IS_TRIG = "1'b0" *) 
  (* LC_PROBE534_MU_CNT = "1" *) 
  (* LC_PROBE534_PID = "16'b0000001000010110" *) 
  (* LC_PROBE534_TYPE = "1" *) 
  (* LC_PROBE534_WIDTH = "1" *) 
  (* LC_PROBE535_IS_DATA = "1'b0" *) 
  (* LC_PROBE535_IS_TRIG = "1'b0" *) 
  (* LC_PROBE535_MU_CNT = "1" *) 
  (* LC_PROBE535_PID = "16'b0000001000010111" *) 
  (* LC_PROBE535_TYPE = "1" *) 
  (* LC_PROBE535_WIDTH = "1" *) 
  (* LC_PROBE536_IS_DATA = "1'b0" *) 
  (* LC_PROBE536_IS_TRIG = "1'b0" *) 
  (* LC_PROBE536_MU_CNT = "1" *) 
  (* LC_PROBE536_PID = "16'b0000001000011000" *) 
  (* LC_PROBE536_TYPE = "1" *) 
  (* LC_PROBE536_WIDTH = "1" *) 
  (* LC_PROBE537_IS_DATA = "1'b0" *) 
  (* LC_PROBE537_IS_TRIG = "1'b0" *) 
  (* LC_PROBE537_MU_CNT = "1" *) 
  (* LC_PROBE537_PID = "16'b0000001000011001" *) 
  (* LC_PROBE537_TYPE = "1" *) 
  (* LC_PROBE537_WIDTH = "1" *) 
  (* LC_PROBE538_IS_DATA = "1'b0" *) 
  (* LC_PROBE538_IS_TRIG = "1'b0" *) 
  (* LC_PROBE538_MU_CNT = "1" *) 
  (* LC_PROBE538_PID = "16'b0000001000011010" *) 
  (* LC_PROBE538_TYPE = "1" *) 
  (* LC_PROBE538_WIDTH = "1" *) 
  (* LC_PROBE539_IS_DATA = "1'b0" *) 
  (* LC_PROBE539_IS_TRIG = "1'b0" *) 
  (* LC_PROBE539_MU_CNT = "1" *) 
  (* LC_PROBE539_PID = "16'b0000001000011011" *) 
  (* LC_PROBE539_TYPE = "1" *) 
  (* LC_PROBE539_WIDTH = "1" *) 
  (* LC_PROBE53_IS_DATA = "1'b0" *) 
  (* LC_PROBE53_IS_TRIG = "1'b0" *) 
  (* LC_PROBE53_MU_CNT = "1" *) 
  (* LC_PROBE53_PID = "16'b0000000000110101" *) 
  (* LC_PROBE53_TYPE = "1" *) 
  (* LC_PROBE53_WIDTH = "1" *) 
  (* LC_PROBE540_IS_DATA = "1'b0" *) 
  (* LC_PROBE540_IS_TRIG = "1'b0" *) 
  (* LC_PROBE540_MU_CNT = "1" *) 
  (* LC_PROBE540_PID = "16'b0000001000011100" *) 
  (* LC_PROBE540_TYPE = "1" *) 
  (* LC_PROBE540_WIDTH = "1" *) 
  (* LC_PROBE541_IS_DATA = "1'b0" *) 
  (* LC_PROBE541_IS_TRIG = "1'b0" *) 
  (* LC_PROBE541_MU_CNT = "1" *) 
  (* LC_PROBE541_PID = "16'b0000001000011101" *) 
  (* LC_PROBE541_TYPE = "1" *) 
  (* LC_PROBE541_WIDTH = "1" *) 
  (* LC_PROBE542_IS_DATA = "1'b0" *) 
  (* LC_PROBE542_IS_TRIG = "1'b0" *) 
  (* LC_PROBE542_MU_CNT = "1" *) 
  (* LC_PROBE542_PID = "16'b0000001000011110" *) 
  (* LC_PROBE542_TYPE = "1" *) 
  (* LC_PROBE542_WIDTH = "1" *) 
  (* LC_PROBE543_IS_DATA = "1'b0" *) 
  (* LC_PROBE543_IS_TRIG = "1'b0" *) 
  (* LC_PROBE543_MU_CNT = "1" *) 
  (* LC_PROBE543_PID = "16'b0000001000011111" *) 
  (* LC_PROBE543_TYPE = "1" *) 
  (* LC_PROBE543_WIDTH = "1" *) 
  (* LC_PROBE544_IS_DATA = "1'b0" *) 
  (* LC_PROBE544_IS_TRIG = "1'b0" *) 
  (* LC_PROBE544_MU_CNT = "1" *) 
  (* LC_PROBE544_PID = "16'b0000001000100000" *) 
  (* LC_PROBE544_TYPE = "1" *) 
  (* LC_PROBE544_WIDTH = "1" *) 
  (* LC_PROBE545_IS_DATA = "1'b0" *) 
  (* LC_PROBE545_IS_TRIG = "1'b0" *) 
  (* LC_PROBE545_MU_CNT = "1" *) 
  (* LC_PROBE545_PID = "16'b0000001000100001" *) 
  (* LC_PROBE545_TYPE = "1" *) 
  (* LC_PROBE545_WIDTH = "1" *) 
  (* LC_PROBE546_IS_DATA = "1'b0" *) 
  (* LC_PROBE546_IS_TRIG = "1'b0" *) 
  (* LC_PROBE546_MU_CNT = "1" *) 
  (* LC_PROBE546_PID = "16'b0000001000100010" *) 
  (* LC_PROBE546_TYPE = "1" *) 
  (* LC_PROBE546_WIDTH = "1" *) 
  (* LC_PROBE547_IS_DATA = "1'b0" *) 
  (* LC_PROBE547_IS_TRIG = "1'b0" *) 
  (* LC_PROBE547_MU_CNT = "1" *) 
  (* LC_PROBE547_PID = "16'b0000001000100011" *) 
  (* LC_PROBE547_TYPE = "1" *) 
  (* LC_PROBE547_WIDTH = "1" *) 
  (* LC_PROBE548_IS_DATA = "1'b0" *) 
  (* LC_PROBE548_IS_TRIG = "1'b0" *) 
  (* LC_PROBE548_MU_CNT = "1" *) 
  (* LC_PROBE548_PID = "16'b0000001000100100" *) 
  (* LC_PROBE548_TYPE = "1" *) 
  (* LC_PROBE548_WIDTH = "1" *) 
  (* LC_PROBE549_IS_DATA = "1'b0" *) 
  (* LC_PROBE549_IS_TRIG = "1'b0" *) 
  (* LC_PROBE549_MU_CNT = "1" *) 
  (* LC_PROBE549_PID = "16'b0000001000100101" *) 
  (* LC_PROBE549_TYPE = "1" *) 
  (* LC_PROBE549_WIDTH = "1" *) 
  (* LC_PROBE54_IS_DATA = "1'b0" *) 
  (* LC_PROBE54_IS_TRIG = "1'b0" *) 
  (* LC_PROBE54_MU_CNT = "1" *) 
  (* LC_PROBE54_PID = "16'b0000000000110110" *) 
  (* LC_PROBE54_TYPE = "1" *) 
  (* LC_PROBE54_WIDTH = "1" *) 
  (* LC_PROBE550_IS_DATA = "1'b0" *) 
  (* LC_PROBE550_IS_TRIG = "1'b0" *) 
  (* LC_PROBE550_MU_CNT = "1" *) 
  (* LC_PROBE550_PID = "16'b0000001000100110" *) 
  (* LC_PROBE550_TYPE = "1" *) 
  (* LC_PROBE550_WIDTH = "1" *) 
  (* LC_PROBE551_IS_DATA = "1'b0" *) 
  (* LC_PROBE551_IS_TRIG = "1'b0" *) 
  (* LC_PROBE551_MU_CNT = "1" *) 
  (* LC_PROBE551_PID = "16'b0000001000100111" *) 
  (* LC_PROBE551_TYPE = "1" *) 
  (* LC_PROBE551_WIDTH = "1" *) 
  (* LC_PROBE552_IS_DATA = "1'b0" *) 
  (* LC_PROBE552_IS_TRIG = "1'b0" *) 
  (* LC_PROBE552_MU_CNT = "1" *) 
  (* LC_PROBE552_PID = "16'b0000001000101000" *) 
  (* LC_PROBE552_TYPE = "1" *) 
  (* LC_PROBE552_WIDTH = "1" *) 
  (* LC_PROBE553_IS_DATA = "1'b0" *) 
  (* LC_PROBE553_IS_TRIG = "1'b0" *) 
  (* LC_PROBE553_MU_CNT = "1" *) 
  (* LC_PROBE553_PID = "16'b0000001000101001" *) 
  (* LC_PROBE553_TYPE = "1" *) 
  (* LC_PROBE553_WIDTH = "1" *) 
  (* LC_PROBE554_IS_DATA = "1'b0" *) 
  (* LC_PROBE554_IS_TRIG = "1'b0" *) 
  (* LC_PROBE554_MU_CNT = "1" *) 
  (* LC_PROBE554_PID = "16'b0000001000101010" *) 
  (* LC_PROBE554_TYPE = "1" *) 
  (* LC_PROBE554_WIDTH = "1" *) 
  (* LC_PROBE555_IS_DATA = "1'b0" *) 
  (* LC_PROBE555_IS_TRIG = "1'b0" *) 
  (* LC_PROBE555_MU_CNT = "1" *) 
  (* LC_PROBE555_PID = "16'b0000001000101011" *) 
  (* LC_PROBE555_TYPE = "1" *) 
  (* LC_PROBE555_WIDTH = "1" *) 
  (* LC_PROBE556_IS_DATA = "1'b0" *) 
  (* LC_PROBE556_IS_TRIG = "1'b0" *) 
  (* LC_PROBE556_MU_CNT = "1" *) 
  (* LC_PROBE556_PID = "16'b0000001000101100" *) 
  (* LC_PROBE556_TYPE = "1" *) 
  (* LC_PROBE556_WIDTH = "1" *) 
  (* LC_PROBE557_IS_DATA = "1'b0" *) 
  (* LC_PROBE557_IS_TRIG = "1'b0" *) 
  (* LC_PROBE557_MU_CNT = "1" *) 
  (* LC_PROBE557_PID = "16'b0000001000101101" *) 
  (* LC_PROBE557_TYPE = "1" *) 
  (* LC_PROBE557_WIDTH = "1" *) 
  (* LC_PROBE558_IS_DATA = "1'b0" *) 
  (* LC_PROBE558_IS_TRIG = "1'b0" *) 
  (* LC_PROBE558_MU_CNT = "1" *) 
  (* LC_PROBE558_PID = "16'b0000001000101110" *) 
  (* LC_PROBE558_TYPE = "1" *) 
  (* LC_PROBE558_WIDTH = "1" *) 
  (* LC_PROBE559_IS_DATA = "1'b0" *) 
  (* LC_PROBE559_IS_TRIG = "1'b0" *) 
  (* LC_PROBE559_MU_CNT = "1" *) 
  (* LC_PROBE559_PID = "16'b0000001000101111" *) 
  (* LC_PROBE559_TYPE = "1" *) 
  (* LC_PROBE559_WIDTH = "1" *) 
  (* LC_PROBE55_IS_DATA = "1'b0" *) 
  (* LC_PROBE55_IS_TRIG = "1'b0" *) 
  (* LC_PROBE55_MU_CNT = "1" *) 
  (* LC_PROBE55_PID = "16'b0000000000110111" *) 
  (* LC_PROBE55_TYPE = "1" *) 
  (* LC_PROBE55_WIDTH = "1" *) 
  (* LC_PROBE560_IS_DATA = "1'b0" *) 
  (* LC_PROBE560_IS_TRIG = "1'b0" *) 
  (* LC_PROBE560_MU_CNT = "1" *) 
  (* LC_PROBE560_PID = "16'b0000001000110000" *) 
  (* LC_PROBE560_TYPE = "1" *) 
  (* LC_PROBE560_WIDTH = "1" *) 
  (* LC_PROBE561_IS_DATA = "1'b0" *) 
  (* LC_PROBE561_IS_TRIG = "1'b0" *) 
  (* LC_PROBE561_MU_CNT = "1" *) 
  (* LC_PROBE561_PID = "16'b0000001000110001" *) 
  (* LC_PROBE561_TYPE = "1" *) 
  (* LC_PROBE561_WIDTH = "1" *) 
  (* LC_PROBE562_IS_DATA = "1'b0" *) 
  (* LC_PROBE562_IS_TRIG = "1'b0" *) 
  (* LC_PROBE562_MU_CNT = "1" *) 
  (* LC_PROBE562_PID = "16'b0000001000110010" *) 
  (* LC_PROBE562_TYPE = "1" *) 
  (* LC_PROBE562_WIDTH = "1" *) 
  (* LC_PROBE563_IS_DATA = "1'b0" *) 
  (* LC_PROBE563_IS_TRIG = "1'b0" *) 
  (* LC_PROBE563_MU_CNT = "1" *) 
  (* LC_PROBE563_PID = "16'b0000001000110011" *) 
  (* LC_PROBE563_TYPE = "1" *) 
  (* LC_PROBE563_WIDTH = "1" *) 
  (* LC_PROBE564_IS_DATA = "1'b0" *) 
  (* LC_PROBE564_IS_TRIG = "1'b0" *) 
  (* LC_PROBE564_MU_CNT = "1" *) 
  (* LC_PROBE564_PID = "16'b0000001000110100" *) 
  (* LC_PROBE564_TYPE = "1" *) 
  (* LC_PROBE564_WIDTH = "1" *) 
  (* LC_PROBE565_IS_DATA = "1'b0" *) 
  (* LC_PROBE565_IS_TRIG = "1'b0" *) 
  (* LC_PROBE565_MU_CNT = "1" *) 
  (* LC_PROBE565_PID = "16'b0000001000110101" *) 
  (* LC_PROBE565_TYPE = "1" *) 
  (* LC_PROBE565_WIDTH = "1" *) 
  (* LC_PROBE566_IS_DATA = "1'b0" *) 
  (* LC_PROBE566_IS_TRIG = "1'b0" *) 
  (* LC_PROBE566_MU_CNT = "1" *) 
  (* LC_PROBE566_PID = "16'b0000001000110110" *) 
  (* LC_PROBE566_TYPE = "1" *) 
  (* LC_PROBE566_WIDTH = "1" *) 
  (* LC_PROBE567_IS_DATA = "1'b0" *) 
  (* LC_PROBE567_IS_TRIG = "1'b0" *) 
  (* LC_PROBE567_MU_CNT = "1" *) 
  (* LC_PROBE567_PID = "16'b0000001000110111" *) 
  (* LC_PROBE567_TYPE = "1" *) 
  (* LC_PROBE567_WIDTH = "1" *) 
  (* LC_PROBE568_IS_DATA = "1'b0" *) 
  (* LC_PROBE568_IS_TRIG = "1'b0" *) 
  (* LC_PROBE568_MU_CNT = "1" *) 
  (* LC_PROBE568_PID = "16'b0000001000111000" *) 
  (* LC_PROBE568_TYPE = "1" *) 
  (* LC_PROBE568_WIDTH = "1" *) 
  (* LC_PROBE569_IS_DATA = "1'b0" *) 
  (* LC_PROBE569_IS_TRIG = "1'b0" *) 
  (* LC_PROBE569_MU_CNT = "1" *) 
  (* LC_PROBE569_PID = "16'b0000001000111001" *) 
  (* LC_PROBE569_TYPE = "1" *) 
  (* LC_PROBE569_WIDTH = "1" *) 
  (* LC_PROBE56_IS_DATA = "1'b0" *) 
  (* LC_PROBE56_IS_TRIG = "1'b0" *) 
  (* LC_PROBE56_MU_CNT = "1" *) 
  (* LC_PROBE56_PID = "16'b0000000000111000" *) 
  (* LC_PROBE56_TYPE = "1" *) 
  (* LC_PROBE56_WIDTH = "1" *) 
  (* LC_PROBE570_IS_DATA = "1'b0" *) 
  (* LC_PROBE570_IS_TRIG = "1'b0" *) 
  (* LC_PROBE570_MU_CNT = "1" *) 
  (* LC_PROBE570_PID = "16'b0000001000111010" *) 
  (* LC_PROBE570_TYPE = "1" *) 
  (* LC_PROBE570_WIDTH = "1" *) 
  (* LC_PROBE571_IS_DATA = "1'b0" *) 
  (* LC_PROBE571_IS_TRIG = "1'b0" *) 
  (* LC_PROBE571_MU_CNT = "1" *) 
  (* LC_PROBE571_PID = "16'b0000001000111011" *) 
  (* LC_PROBE571_TYPE = "1" *) 
  (* LC_PROBE571_WIDTH = "1" *) 
  (* LC_PROBE572_IS_DATA = "1'b0" *) 
  (* LC_PROBE572_IS_TRIG = "1'b0" *) 
  (* LC_PROBE572_MU_CNT = "1" *) 
  (* LC_PROBE572_PID = "16'b0000001000111100" *) 
  (* LC_PROBE572_TYPE = "1" *) 
  (* LC_PROBE572_WIDTH = "1" *) 
  (* LC_PROBE573_IS_DATA = "1'b0" *) 
  (* LC_PROBE573_IS_TRIG = "1'b0" *) 
  (* LC_PROBE573_MU_CNT = "1" *) 
  (* LC_PROBE573_PID = "16'b0000001000111101" *) 
  (* LC_PROBE573_TYPE = "1" *) 
  (* LC_PROBE573_WIDTH = "1" *) 
  (* LC_PROBE574_IS_DATA = "1'b0" *) 
  (* LC_PROBE574_IS_TRIG = "1'b0" *) 
  (* LC_PROBE574_MU_CNT = "1" *) 
  (* LC_PROBE574_PID = "16'b0000001000111110" *) 
  (* LC_PROBE574_TYPE = "1" *) 
  (* LC_PROBE574_WIDTH = "1" *) 
  (* LC_PROBE575_IS_DATA = "1'b0" *) 
  (* LC_PROBE575_IS_TRIG = "1'b0" *) 
  (* LC_PROBE575_MU_CNT = "1" *) 
  (* LC_PROBE575_PID = "16'b0000001000111111" *) 
  (* LC_PROBE575_TYPE = "1" *) 
  (* LC_PROBE575_WIDTH = "1" *) 
  (* LC_PROBE576_IS_DATA = "1'b0" *) 
  (* LC_PROBE576_IS_TRIG = "1'b0" *) 
  (* LC_PROBE576_MU_CNT = "1" *) 
  (* LC_PROBE576_PID = "16'b0000001001000000" *) 
  (* LC_PROBE576_TYPE = "1" *) 
  (* LC_PROBE576_WIDTH = "1" *) 
  (* LC_PROBE577_IS_DATA = "1'b0" *) 
  (* LC_PROBE577_IS_TRIG = "1'b0" *) 
  (* LC_PROBE577_MU_CNT = "1" *) 
  (* LC_PROBE577_PID = "16'b0000001001000001" *) 
  (* LC_PROBE577_TYPE = "1" *) 
  (* LC_PROBE577_WIDTH = "1" *) 
  (* LC_PROBE578_IS_DATA = "1'b0" *) 
  (* LC_PROBE578_IS_TRIG = "1'b0" *) 
  (* LC_PROBE578_MU_CNT = "1" *) 
  (* LC_PROBE578_PID = "16'b0000001001000010" *) 
  (* LC_PROBE578_TYPE = "1" *) 
  (* LC_PROBE578_WIDTH = "1" *) 
  (* LC_PROBE579_IS_DATA = "1'b0" *) 
  (* LC_PROBE579_IS_TRIG = "1'b0" *) 
  (* LC_PROBE579_MU_CNT = "1" *) 
  (* LC_PROBE579_PID = "16'b0000001001000011" *) 
  (* LC_PROBE579_TYPE = "1" *) 
  (* LC_PROBE579_WIDTH = "1" *) 
  (* LC_PROBE57_IS_DATA = "1'b0" *) 
  (* LC_PROBE57_IS_TRIG = "1'b0" *) 
  (* LC_PROBE57_MU_CNT = "1" *) 
  (* LC_PROBE57_PID = "16'b0000000000111001" *) 
  (* LC_PROBE57_TYPE = "1" *) 
  (* LC_PROBE57_WIDTH = "1" *) 
  (* LC_PROBE580_IS_DATA = "1'b0" *) 
  (* LC_PROBE580_IS_TRIG = "1'b0" *) 
  (* LC_PROBE580_MU_CNT = "1" *) 
  (* LC_PROBE580_PID = "16'b0000001001000100" *) 
  (* LC_PROBE580_TYPE = "1" *) 
  (* LC_PROBE580_WIDTH = "1" *) 
  (* LC_PROBE581_IS_DATA = "1'b0" *) 
  (* LC_PROBE581_IS_TRIG = "1'b0" *) 
  (* LC_PROBE581_MU_CNT = "1" *) 
  (* LC_PROBE581_PID = "16'b0000001001000101" *) 
  (* LC_PROBE581_TYPE = "1" *) 
  (* LC_PROBE581_WIDTH = "1" *) 
  (* LC_PROBE582_IS_DATA = "1'b0" *) 
  (* LC_PROBE582_IS_TRIG = "1'b0" *) 
  (* LC_PROBE582_MU_CNT = "1" *) 
  (* LC_PROBE582_PID = "16'b0000001001000110" *) 
  (* LC_PROBE582_TYPE = "1" *) 
  (* LC_PROBE582_WIDTH = "1" *) 
  (* LC_PROBE583_IS_DATA = "1'b0" *) 
  (* LC_PROBE583_IS_TRIG = "1'b0" *) 
  (* LC_PROBE583_MU_CNT = "1" *) 
  (* LC_PROBE583_PID = "16'b0000001001000111" *) 
  (* LC_PROBE583_TYPE = "1" *) 
  (* LC_PROBE583_WIDTH = "1" *) 
  (* LC_PROBE584_IS_DATA = "1'b0" *) 
  (* LC_PROBE584_IS_TRIG = "1'b0" *) 
  (* LC_PROBE584_MU_CNT = "1" *) 
  (* LC_PROBE584_PID = "16'b0000001001001000" *) 
  (* LC_PROBE584_TYPE = "1" *) 
  (* LC_PROBE584_WIDTH = "1" *) 
  (* LC_PROBE585_IS_DATA = "1'b0" *) 
  (* LC_PROBE585_IS_TRIG = "1'b0" *) 
  (* LC_PROBE585_MU_CNT = "1" *) 
  (* LC_PROBE585_PID = "16'b0000001001001001" *) 
  (* LC_PROBE585_TYPE = "1" *) 
  (* LC_PROBE585_WIDTH = "1" *) 
  (* LC_PROBE586_IS_DATA = "1'b0" *) 
  (* LC_PROBE586_IS_TRIG = "1'b0" *) 
  (* LC_PROBE586_MU_CNT = "1" *) 
  (* LC_PROBE586_PID = "16'b0000001001001010" *) 
  (* LC_PROBE586_TYPE = "1" *) 
  (* LC_PROBE586_WIDTH = "1" *) 
  (* LC_PROBE587_IS_DATA = "1'b0" *) 
  (* LC_PROBE587_IS_TRIG = "1'b0" *) 
  (* LC_PROBE587_MU_CNT = "1" *) 
  (* LC_PROBE587_PID = "16'b0000001001001011" *) 
  (* LC_PROBE587_TYPE = "1" *) 
  (* LC_PROBE587_WIDTH = "1" *) 
  (* LC_PROBE588_IS_DATA = "1'b0" *) 
  (* LC_PROBE588_IS_TRIG = "1'b0" *) 
  (* LC_PROBE588_MU_CNT = "1" *) 
  (* LC_PROBE588_PID = "16'b0000001001001100" *) 
  (* LC_PROBE588_TYPE = "1" *) 
  (* LC_PROBE588_WIDTH = "1" *) 
  (* LC_PROBE589_IS_DATA = "1'b0" *) 
  (* LC_PROBE589_IS_TRIG = "1'b0" *) 
  (* LC_PROBE589_MU_CNT = "1" *) 
  (* LC_PROBE589_PID = "16'b0000001001001101" *) 
  (* LC_PROBE589_TYPE = "1" *) 
  (* LC_PROBE589_WIDTH = "1" *) 
  (* LC_PROBE58_IS_DATA = "1'b0" *) 
  (* LC_PROBE58_IS_TRIG = "1'b0" *) 
  (* LC_PROBE58_MU_CNT = "1" *) 
  (* LC_PROBE58_PID = "16'b0000000000111010" *) 
  (* LC_PROBE58_TYPE = "1" *) 
  (* LC_PROBE58_WIDTH = "1" *) 
  (* LC_PROBE590_IS_DATA = "1'b0" *) 
  (* LC_PROBE590_IS_TRIG = "1'b0" *) 
  (* LC_PROBE590_MU_CNT = "1" *) 
  (* LC_PROBE590_PID = "16'b0000001001001110" *) 
  (* LC_PROBE590_TYPE = "1" *) 
  (* LC_PROBE590_WIDTH = "1" *) 
  (* LC_PROBE591_IS_DATA = "1'b0" *) 
  (* LC_PROBE591_IS_TRIG = "1'b0" *) 
  (* LC_PROBE591_MU_CNT = "1" *) 
  (* LC_PROBE591_PID = "16'b0000001001001111" *) 
  (* LC_PROBE591_TYPE = "1" *) 
  (* LC_PROBE591_WIDTH = "1" *) 
  (* LC_PROBE592_IS_DATA = "1'b0" *) 
  (* LC_PROBE592_IS_TRIG = "1'b0" *) 
  (* LC_PROBE592_MU_CNT = "1" *) 
  (* LC_PROBE592_PID = "16'b0000001001010000" *) 
  (* LC_PROBE592_TYPE = "1" *) 
  (* LC_PROBE592_WIDTH = "1" *) 
  (* LC_PROBE593_IS_DATA = "1'b0" *) 
  (* LC_PROBE593_IS_TRIG = "1'b0" *) 
  (* LC_PROBE593_MU_CNT = "1" *) 
  (* LC_PROBE593_PID = "16'b0000001001010001" *) 
  (* LC_PROBE593_TYPE = "1" *) 
  (* LC_PROBE593_WIDTH = "1" *) 
  (* LC_PROBE594_IS_DATA = "1'b0" *) 
  (* LC_PROBE594_IS_TRIG = "1'b0" *) 
  (* LC_PROBE594_MU_CNT = "1" *) 
  (* LC_PROBE594_PID = "16'b0000001001010010" *) 
  (* LC_PROBE594_TYPE = "1" *) 
  (* LC_PROBE594_WIDTH = "1" *) 
  (* LC_PROBE595_IS_DATA = "1'b0" *) 
  (* LC_PROBE595_IS_TRIG = "1'b0" *) 
  (* LC_PROBE595_MU_CNT = "1" *) 
  (* LC_PROBE595_PID = "16'b0000001001010011" *) 
  (* LC_PROBE595_TYPE = "1" *) 
  (* LC_PROBE595_WIDTH = "1" *) 
  (* LC_PROBE596_IS_DATA = "1'b0" *) 
  (* LC_PROBE596_IS_TRIG = "1'b0" *) 
  (* LC_PROBE596_MU_CNT = "1" *) 
  (* LC_PROBE596_PID = "16'b0000001001010100" *) 
  (* LC_PROBE596_TYPE = "1" *) 
  (* LC_PROBE596_WIDTH = "1" *) 
  (* LC_PROBE597_IS_DATA = "1'b0" *) 
  (* LC_PROBE597_IS_TRIG = "1'b0" *) 
  (* LC_PROBE597_MU_CNT = "1" *) 
  (* LC_PROBE597_PID = "16'b0000001001010101" *) 
  (* LC_PROBE597_TYPE = "1" *) 
  (* LC_PROBE597_WIDTH = "1" *) 
  (* LC_PROBE598_IS_DATA = "1'b0" *) 
  (* LC_PROBE598_IS_TRIG = "1'b0" *) 
  (* LC_PROBE598_MU_CNT = "1" *) 
  (* LC_PROBE598_PID = "16'b0000001001010110" *) 
  (* LC_PROBE598_TYPE = "1" *) 
  (* LC_PROBE598_WIDTH = "1" *) 
  (* LC_PROBE599_IS_DATA = "1'b0" *) 
  (* LC_PROBE599_IS_TRIG = "1'b0" *) 
  (* LC_PROBE599_MU_CNT = "1" *) 
  (* LC_PROBE599_PID = "16'b0000001001010111" *) 
  (* LC_PROBE599_TYPE = "1" *) 
  (* LC_PROBE599_WIDTH = "1" *) 
  (* LC_PROBE59_IS_DATA = "1'b0" *) 
  (* LC_PROBE59_IS_TRIG = "1'b0" *) 
  (* LC_PROBE59_MU_CNT = "1" *) 
  (* LC_PROBE59_PID = "16'b0000000000111011" *) 
  (* LC_PROBE59_TYPE = "1" *) 
  (* LC_PROBE59_WIDTH = "1" *) 
  (* LC_PROBE5_IS_DATA = "1'b0" *) 
  (* LC_PROBE5_IS_TRIG = "1'b0" *) 
  (* LC_PROBE5_MU_CNT = "1" *) 
  (* LC_PROBE5_PID = "16'b0000000000000101" *) 
  (* LC_PROBE5_TYPE = "1" *) 
  (* LC_PROBE5_WIDTH = "1" *) 
  (* LC_PROBE600_IS_DATA = "1'b0" *) 
  (* LC_PROBE600_IS_TRIG = "1'b0" *) 
  (* LC_PROBE600_MU_CNT = "1" *) 
  (* LC_PROBE600_PID = "16'b0000001001011000" *) 
  (* LC_PROBE600_TYPE = "1" *) 
  (* LC_PROBE600_WIDTH = "1" *) 
  (* LC_PROBE601_IS_DATA = "1'b0" *) 
  (* LC_PROBE601_IS_TRIG = "1'b0" *) 
  (* LC_PROBE601_MU_CNT = "1" *) 
  (* LC_PROBE601_PID = "16'b0000001001011001" *) 
  (* LC_PROBE601_TYPE = "1" *) 
  (* LC_PROBE601_WIDTH = "1" *) 
  (* LC_PROBE602_IS_DATA = "1'b0" *) 
  (* LC_PROBE602_IS_TRIG = "1'b0" *) 
  (* LC_PROBE602_MU_CNT = "1" *) 
  (* LC_PROBE602_PID = "16'b0000001001011010" *) 
  (* LC_PROBE602_TYPE = "1" *) 
  (* LC_PROBE602_WIDTH = "1" *) 
  (* LC_PROBE603_IS_DATA = "1'b0" *) 
  (* LC_PROBE603_IS_TRIG = "1'b0" *) 
  (* LC_PROBE603_MU_CNT = "1" *) 
  (* LC_PROBE603_PID = "16'b0000001001011011" *) 
  (* LC_PROBE603_TYPE = "1" *) 
  (* LC_PROBE603_WIDTH = "1" *) 
  (* LC_PROBE604_IS_DATA = "1'b0" *) 
  (* LC_PROBE604_IS_TRIG = "1'b0" *) 
  (* LC_PROBE604_MU_CNT = "1" *) 
  (* LC_PROBE604_PID = "16'b0000001001011100" *) 
  (* LC_PROBE604_TYPE = "1" *) 
  (* LC_PROBE604_WIDTH = "1" *) 
  (* LC_PROBE605_IS_DATA = "1'b0" *) 
  (* LC_PROBE605_IS_TRIG = "1'b0" *) 
  (* LC_PROBE605_MU_CNT = "1" *) 
  (* LC_PROBE605_PID = "16'b0000001001011101" *) 
  (* LC_PROBE605_TYPE = "1" *) 
  (* LC_PROBE605_WIDTH = "1" *) 
  (* LC_PROBE606_IS_DATA = "1'b0" *) 
  (* LC_PROBE606_IS_TRIG = "1'b0" *) 
  (* LC_PROBE606_MU_CNT = "1" *) 
  (* LC_PROBE606_PID = "16'b0000001001011110" *) 
  (* LC_PROBE606_TYPE = "1" *) 
  (* LC_PROBE606_WIDTH = "1" *) 
  (* LC_PROBE607_IS_DATA = "1'b0" *) 
  (* LC_PROBE607_IS_TRIG = "1'b0" *) 
  (* LC_PROBE607_MU_CNT = "1" *) 
  (* LC_PROBE607_PID = "16'b0000001001011111" *) 
  (* LC_PROBE607_TYPE = "1" *) 
  (* LC_PROBE607_WIDTH = "1" *) 
  (* LC_PROBE608_IS_DATA = "1'b0" *) 
  (* LC_PROBE608_IS_TRIG = "1'b0" *) 
  (* LC_PROBE608_MU_CNT = "1" *) 
  (* LC_PROBE608_PID = "16'b0000001001100000" *) 
  (* LC_PROBE608_TYPE = "1" *) 
  (* LC_PROBE608_WIDTH = "1" *) 
  (* LC_PROBE609_IS_DATA = "1'b0" *) 
  (* LC_PROBE609_IS_TRIG = "1'b0" *) 
  (* LC_PROBE609_MU_CNT = "1" *) 
  (* LC_PROBE609_PID = "16'b0000001001100001" *) 
  (* LC_PROBE609_TYPE = "1" *) 
  (* LC_PROBE609_WIDTH = "1" *) 
  (* LC_PROBE60_IS_DATA = "1'b0" *) 
  (* LC_PROBE60_IS_TRIG = "1'b0" *) 
  (* LC_PROBE60_MU_CNT = "1" *) 
  (* LC_PROBE60_PID = "16'b0000000000111100" *) 
  (* LC_PROBE60_TYPE = "1" *) 
  (* LC_PROBE60_WIDTH = "1" *) 
  (* LC_PROBE610_IS_DATA = "1'b0" *) 
  (* LC_PROBE610_IS_TRIG = "1'b0" *) 
  (* LC_PROBE610_MU_CNT = "1" *) 
  (* LC_PROBE610_PID = "16'b0000001001100010" *) 
  (* LC_PROBE610_TYPE = "1" *) 
  (* LC_PROBE610_WIDTH = "1" *) 
  (* LC_PROBE611_IS_DATA = "1'b0" *) 
  (* LC_PROBE611_IS_TRIG = "1'b0" *) 
  (* LC_PROBE611_MU_CNT = "1" *) 
  (* LC_PROBE611_PID = "16'b0000001001100011" *) 
  (* LC_PROBE611_TYPE = "1" *) 
  (* LC_PROBE611_WIDTH = "1" *) 
  (* LC_PROBE612_IS_DATA = "1'b0" *) 
  (* LC_PROBE612_IS_TRIG = "1'b0" *) 
  (* LC_PROBE612_MU_CNT = "1" *) 
  (* LC_PROBE612_PID = "16'b0000001001100100" *) 
  (* LC_PROBE612_TYPE = "1" *) 
  (* LC_PROBE612_WIDTH = "1" *) 
  (* LC_PROBE613_IS_DATA = "1'b0" *) 
  (* LC_PROBE613_IS_TRIG = "1'b0" *) 
  (* LC_PROBE613_MU_CNT = "1" *) 
  (* LC_PROBE613_PID = "16'b0000001001100101" *) 
  (* LC_PROBE613_TYPE = "1" *) 
  (* LC_PROBE613_WIDTH = "1" *) 
  (* LC_PROBE614_IS_DATA = "1'b0" *) 
  (* LC_PROBE614_IS_TRIG = "1'b0" *) 
  (* LC_PROBE614_MU_CNT = "1" *) 
  (* LC_PROBE614_PID = "16'b0000001001100110" *) 
  (* LC_PROBE614_TYPE = "1" *) 
  (* LC_PROBE614_WIDTH = "1" *) 
  (* LC_PROBE615_IS_DATA = "1'b0" *) 
  (* LC_PROBE615_IS_TRIG = "1'b0" *) 
  (* LC_PROBE615_MU_CNT = "1" *) 
  (* LC_PROBE615_PID = "16'b0000001001100111" *) 
  (* LC_PROBE615_TYPE = "1" *) 
  (* LC_PROBE615_WIDTH = "1" *) 
  (* LC_PROBE616_IS_DATA = "1'b0" *) 
  (* LC_PROBE616_IS_TRIG = "1'b0" *) 
  (* LC_PROBE616_MU_CNT = "1" *) 
  (* LC_PROBE616_PID = "16'b0000001001101000" *) 
  (* LC_PROBE616_TYPE = "1" *) 
  (* LC_PROBE616_WIDTH = "1" *) 
  (* LC_PROBE617_IS_DATA = "1'b0" *) 
  (* LC_PROBE617_IS_TRIG = "1'b0" *) 
  (* LC_PROBE617_MU_CNT = "1" *) 
  (* LC_PROBE617_PID = "16'b0000001001101001" *) 
  (* LC_PROBE617_TYPE = "1" *) 
  (* LC_PROBE617_WIDTH = "1" *) 
  (* LC_PROBE618_IS_DATA = "1'b0" *) 
  (* LC_PROBE618_IS_TRIG = "1'b0" *) 
  (* LC_PROBE618_MU_CNT = "1" *) 
  (* LC_PROBE618_PID = "16'b0000001001101010" *) 
  (* LC_PROBE618_TYPE = "1" *) 
  (* LC_PROBE618_WIDTH = "1" *) 
  (* LC_PROBE619_IS_DATA = "1'b0" *) 
  (* LC_PROBE619_IS_TRIG = "1'b0" *) 
  (* LC_PROBE619_MU_CNT = "1" *) 
  (* LC_PROBE619_PID = "16'b0000001001101011" *) 
  (* LC_PROBE619_TYPE = "1" *) 
  (* LC_PROBE619_WIDTH = "1" *) 
  (* LC_PROBE61_IS_DATA = "1'b0" *) 
  (* LC_PROBE61_IS_TRIG = "1'b0" *) 
  (* LC_PROBE61_MU_CNT = "1" *) 
  (* LC_PROBE61_PID = "16'b0000000000111101" *) 
  (* LC_PROBE61_TYPE = "1" *) 
  (* LC_PROBE61_WIDTH = "1" *) 
  (* LC_PROBE620_IS_DATA = "1'b0" *) 
  (* LC_PROBE620_IS_TRIG = "1'b0" *) 
  (* LC_PROBE620_MU_CNT = "1" *) 
  (* LC_PROBE620_PID = "16'b0000001001101100" *) 
  (* LC_PROBE620_TYPE = "1" *) 
  (* LC_PROBE620_WIDTH = "1" *) 
  (* LC_PROBE621_IS_DATA = "1'b0" *) 
  (* LC_PROBE621_IS_TRIG = "1'b0" *) 
  (* LC_PROBE621_MU_CNT = "1" *) 
  (* LC_PROBE621_PID = "16'b0000001001101101" *) 
  (* LC_PROBE621_TYPE = "1" *) 
  (* LC_PROBE621_WIDTH = "1" *) 
  (* LC_PROBE622_IS_DATA = "1'b0" *) 
  (* LC_PROBE622_IS_TRIG = "1'b0" *) 
  (* LC_PROBE622_MU_CNT = "1" *) 
  (* LC_PROBE622_PID = "16'b0000001001101110" *) 
  (* LC_PROBE622_TYPE = "1" *) 
  (* LC_PROBE622_WIDTH = "1" *) 
  (* LC_PROBE623_IS_DATA = "1'b0" *) 
  (* LC_PROBE623_IS_TRIG = "1'b0" *) 
  (* LC_PROBE623_MU_CNT = "1" *) 
  (* LC_PROBE623_PID = "16'b0000001001101111" *) 
  (* LC_PROBE623_TYPE = "1" *) 
  (* LC_PROBE623_WIDTH = "1" *) 
  (* LC_PROBE624_IS_DATA = "1'b0" *) 
  (* LC_PROBE624_IS_TRIG = "1'b0" *) 
  (* LC_PROBE624_MU_CNT = "1" *) 
  (* LC_PROBE624_PID = "16'b0000001001110000" *) 
  (* LC_PROBE624_TYPE = "1" *) 
  (* LC_PROBE624_WIDTH = "1" *) 
  (* LC_PROBE625_IS_DATA = "1'b0" *) 
  (* LC_PROBE625_IS_TRIG = "1'b0" *) 
  (* LC_PROBE625_MU_CNT = "1" *) 
  (* LC_PROBE625_PID = "16'b0000001001110001" *) 
  (* LC_PROBE625_TYPE = "1" *) 
  (* LC_PROBE625_WIDTH = "1" *) 
  (* LC_PROBE626_IS_DATA = "1'b0" *) 
  (* LC_PROBE626_IS_TRIG = "1'b0" *) 
  (* LC_PROBE626_MU_CNT = "1" *) 
  (* LC_PROBE626_PID = "16'b0000001001110010" *) 
  (* LC_PROBE626_TYPE = "1" *) 
  (* LC_PROBE626_WIDTH = "1" *) 
  (* LC_PROBE627_IS_DATA = "1'b0" *) 
  (* LC_PROBE627_IS_TRIG = "1'b0" *) 
  (* LC_PROBE627_MU_CNT = "1" *) 
  (* LC_PROBE627_PID = "16'b0000001001110011" *) 
  (* LC_PROBE627_TYPE = "1" *) 
  (* LC_PROBE627_WIDTH = "1" *) 
  (* LC_PROBE628_IS_DATA = "1'b0" *) 
  (* LC_PROBE628_IS_TRIG = "1'b0" *) 
  (* LC_PROBE628_MU_CNT = "1" *) 
  (* LC_PROBE628_PID = "16'b0000001001110100" *) 
  (* LC_PROBE628_TYPE = "1" *) 
  (* LC_PROBE628_WIDTH = "1" *) 
  (* LC_PROBE629_IS_DATA = "1'b0" *) 
  (* LC_PROBE629_IS_TRIG = "1'b0" *) 
  (* LC_PROBE629_MU_CNT = "1" *) 
  (* LC_PROBE629_PID = "16'b0000001001110101" *) 
  (* LC_PROBE629_TYPE = "1" *) 
  (* LC_PROBE629_WIDTH = "1" *) 
  (* LC_PROBE62_IS_DATA = "1'b0" *) 
  (* LC_PROBE62_IS_TRIG = "1'b0" *) 
  (* LC_PROBE62_MU_CNT = "1" *) 
  (* LC_PROBE62_PID = "16'b0000000000111110" *) 
  (* LC_PROBE62_TYPE = "1" *) 
  (* LC_PROBE62_WIDTH = "1" *) 
  (* LC_PROBE630_IS_DATA = "1'b0" *) 
  (* LC_PROBE630_IS_TRIG = "1'b0" *) 
  (* LC_PROBE630_MU_CNT = "1" *) 
  (* LC_PROBE630_PID = "16'b0000001001110110" *) 
  (* LC_PROBE630_TYPE = "1" *) 
  (* LC_PROBE630_WIDTH = "1" *) 
  (* LC_PROBE631_IS_DATA = "1'b0" *) 
  (* LC_PROBE631_IS_TRIG = "1'b0" *) 
  (* LC_PROBE631_MU_CNT = "1" *) 
  (* LC_PROBE631_PID = "16'b0000001001110111" *) 
  (* LC_PROBE631_TYPE = "1" *) 
  (* LC_PROBE631_WIDTH = "1" *) 
  (* LC_PROBE632_IS_DATA = "1'b0" *) 
  (* LC_PROBE632_IS_TRIG = "1'b0" *) 
  (* LC_PROBE632_MU_CNT = "1" *) 
  (* LC_PROBE632_PID = "16'b0000001001111000" *) 
  (* LC_PROBE632_TYPE = "1" *) 
  (* LC_PROBE632_WIDTH = "1" *) 
  (* LC_PROBE633_IS_DATA = "1'b0" *) 
  (* LC_PROBE633_IS_TRIG = "1'b0" *) 
  (* LC_PROBE633_MU_CNT = "1" *) 
  (* LC_PROBE633_PID = "16'b0000001001111001" *) 
  (* LC_PROBE633_TYPE = "1" *) 
  (* LC_PROBE633_WIDTH = "1" *) 
  (* LC_PROBE634_IS_DATA = "1'b0" *) 
  (* LC_PROBE634_IS_TRIG = "1'b0" *) 
  (* LC_PROBE634_MU_CNT = "1" *) 
  (* LC_PROBE634_PID = "16'b0000001001111010" *) 
  (* LC_PROBE634_TYPE = "1" *) 
  (* LC_PROBE634_WIDTH = "1" *) 
  (* LC_PROBE635_IS_DATA = "1'b0" *) 
  (* LC_PROBE635_IS_TRIG = "1'b0" *) 
  (* LC_PROBE635_MU_CNT = "1" *) 
  (* LC_PROBE635_PID = "16'b0000001001111011" *) 
  (* LC_PROBE635_TYPE = "1" *) 
  (* LC_PROBE635_WIDTH = "1" *) 
  (* LC_PROBE636_IS_DATA = "1'b0" *) 
  (* LC_PROBE636_IS_TRIG = "1'b0" *) 
  (* LC_PROBE636_MU_CNT = "1" *) 
  (* LC_PROBE636_PID = "16'b0000001001111100" *) 
  (* LC_PROBE636_TYPE = "1" *) 
  (* LC_PROBE636_WIDTH = "1" *) 
  (* LC_PROBE637_IS_DATA = "1'b0" *) 
  (* LC_PROBE637_IS_TRIG = "1'b0" *) 
  (* LC_PROBE637_MU_CNT = "1" *) 
  (* LC_PROBE637_PID = "16'b0000001001111101" *) 
  (* LC_PROBE637_TYPE = "1" *) 
  (* LC_PROBE637_WIDTH = "1" *) 
  (* LC_PROBE638_IS_DATA = "1'b0" *) 
  (* LC_PROBE638_IS_TRIG = "1'b0" *) 
  (* LC_PROBE638_MU_CNT = "1" *) 
  (* LC_PROBE638_PID = "16'b0000001001111110" *) 
  (* LC_PROBE638_TYPE = "1" *) 
  (* LC_PROBE638_WIDTH = "1" *) 
  (* LC_PROBE639_IS_DATA = "1'b0" *) 
  (* LC_PROBE639_IS_TRIG = "1'b0" *) 
  (* LC_PROBE639_MU_CNT = "1" *) 
  (* LC_PROBE639_PID = "16'b0000001001111111" *) 
  (* LC_PROBE639_TYPE = "1" *) 
  (* LC_PROBE639_WIDTH = "1" *) 
  (* LC_PROBE63_IS_DATA = "1'b0" *) 
  (* LC_PROBE63_IS_TRIG = "1'b0" *) 
  (* LC_PROBE63_MU_CNT = "1" *) 
  (* LC_PROBE63_PID = "16'b0000000000111111" *) 
  (* LC_PROBE63_TYPE = "1" *) 
  (* LC_PROBE63_WIDTH = "1" *) 
  (* LC_PROBE640_IS_DATA = "1'b0" *) 
  (* LC_PROBE640_IS_TRIG = "1'b0" *) 
  (* LC_PROBE640_MU_CNT = "1" *) 
  (* LC_PROBE640_PID = "16'b0000001010000000" *) 
  (* LC_PROBE640_TYPE = "1" *) 
  (* LC_PROBE640_WIDTH = "1" *) 
  (* LC_PROBE641_IS_DATA = "1'b0" *) 
  (* LC_PROBE641_IS_TRIG = "1'b0" *) 
  (* LC_PROBE641_MU_CNT = "1" *) 
  (* LC_PROBE641_PID = "16'b0000001010000001" *) 
  (* LC_PROBE641_TYPE = "1" *) 
  (* LC_PROBE641_WIDTH = "1" *) 
  (* LC_PROBE642_IS_DATA = "1'b0" *) 
  (* LC_PROBE642_IS_TRIG = "1'b0" *) 
  (* LC_PROBE642_MU_CNT = "1" *) 
  (* LC_PROBE642_PID = "16'b0000001010000010" *) 
  (* LC_PROBE642_TYPE = "1" *) 
  (* LC_PROBE642_WIDTH = "1" *) 
  (* LC_PROBE643_IS_DATA = "1'b0" *) 
  (* LC_PROBE643_IS_TRIG = "1'b0" *) 
  (* LC_PROBE643_MU_CNT = "1" *) 
  (* LC_PROBE643_PID = "16'b0000001010000011" *) 
  (* LC_PROBE643_TYPE = "1" *) 
  (* LC_PROBE643_WIDTH = "1" *) 
  (* LC_PROBE644_IS_DATA = "1'b0" *) 
  (* LC_PROBE644_IS_TRIG = "1'b0" *) 
  (* LC_PROBE644_MU_CNT = "1" *) 
  (* LC_PROBE644_PID = "16'b0000001010000100" *) 
  (* LC_PROBE644_TYPE = "1" *) 
  (* LC_PROBE644_WIDTH = "1" *) 
  (* LC_PROBE645_IS_DATA = "1'b0" *) 
  (* LC_PROBE645_IS_TRIG = "1'b0" *) 
  (* LC_PROBE645_MU_CNT = "1" *) 
  (* LC_PROBE645_PID = "16'b0000001010000101" *) 
  (* LC_PROBE645_TYPE = "1" *) 
  (* LC_PROBE645_WIDTH = "1" *) 
  (* LC_PROBE646_IS_DATA = "1'b0" *) 
  (* LC_PROBE646_IS_TRIG = "1'b0" *) 
  (* LC_PROBE646_MU_CNT = "1" *) 
  (* LC_PROBE646_PID = "16'b0000001010000110" *) 
  (* LC_PROBE646_TYPE = "1" *) 
  (* LC_PROBE646_WIDTH = "1" *) 
  (* LC_PROBE647_IS_DATA = "1'b0" *) 
  (* LC_PROBE647_IS_TRIG = "1'b0" *) 
  (* LC_PROBE647_MU_CNT = "1" *) 
  (* LC_PROBE647_PID = "16'b0000001010000111" *) 
  (* LC_PROBE647_TYPE = "1" *) 
  (* LC_PROBE647_WIDTH = "1" *) 
  (* LC_PROBE648_IS_DATA = "1'b0" *) 
  (* LC_PROBE648_IS_TRIG = "1'b0" *) 
  (* LC_PROBE648_MU_CNT = "1" *) 
  (* LC_PROBE648_PID = "16'b0000001010001000" *) 
  (* LC_PROBE648_TYPE = "1" *) 
  (* LC_PROBE648_WIDTH = "1" *) 
  (* LC_PROBE649_IS_DATA = "1'b0" *) 
  (* LC_PROBE649_IS_TRIG = "1'b0" *) 
  (* LC_PROBE649_MU_CNT = "1" *) 
  (* LC_PROBE649_PID = "16'b0000001010001001" *) 
  (* LC_PROBE649_TYPE = "1" *) 
  (* LC_PROBE649_WIDTH = "1" *) 
  (* LC_PROBE64_IS_DATA = "1'b0" *) 
  (* LC_PROBE64_IS_TRIG = "1'b0" *) 
  (* LC_PROBE64_MU_CNT = "1" *) 
  (* LC_PROBE64_PID = "16'b0000000001000000" *) 
  (* LC_PROBE64_TYPE = "1" *) 
  (* LC_PROBE64_WIDTH = "1" *) 
  (* LC_PROBE650_IS_DATA = "1'b0" *) 
  (* LC_PROBE650_IS_TRIG = "1'b0" *) 
  (* LC_PROBE650_MU_CNT = "1" *) 
  (* LC_PROBE650_PID = "16'b0000001010001010" *) 
  (* LC_PROBE650_TYPE = "1" *) 
  (* LC_PROBE650_WIDTH = "1" *) 
  (* LC_PROBE651_IS_DATA = "1'b0" *) 
  (* LC_PROBE651_IS_TRIG = "1'b0" *) 
  (* LC_PROBE651_MU_CNT = "1" *) 
  (* LC_PROBE651_PID = "16'b0000001010001011" *) 
  (* LC_PROBE651_TYPE = "1" *) 
  (* LC_PROBE651_WIDTH = "1" *) 
  (* LC_PROBE652_IS_DATA = "1'b0" *) 
  (* LC_PROBE652_IS_TRIG = "1'b0" *) 
  (* LC_PROBE652_MU_CNT = "1" *) 
  (* LC_PROBE652_PID = "16'b0000001010001100" *) 
  (* LC_PROBE652_TYPE = "1" *) 
  (* LC_PROBE652_WIDTH = "1" *) 
  (* LC_PROBE653_IS_DATA = "1'b0" *) 
  (* LC_PROBE653_IS_TRIG = "1'b0" *) 
  (* LC_PROBE653_MU_CNT = "1" *) 
  (* LC_PROBE653_PID = "16'b0000001010001101" *) 
  (* LC_PROBE653_TYPE = "1" *) 
  (* LC_PROBE653_WIDTH = "1" *) 
  (* LC_PROBE654_IS_DATA = "1'b0" *) 
  (* LC_PROBE654_IS_TRIG = "1'b0" *) 
  (* LC_PROBE654_MU_CNT = "1" *) 
  (* LC_PROBE654_PID = "16'b0000001010001110" *) 
  (* LC_PROBE654_TYPE = "1" *) 
  (* LC_PROBE654_WIDTH = "1" *) 
  (* LC_PROBE655_IS_DATA = "1'b0" *) 
  (* LC_PROBE655_IS_TRIG = "1'b0" *) 
  (* LC_PROBE655_MU_CNT = "1" *) 
  (* LC_PROBE655_PID = "16'b0000001010001111" *) 
  (* LC_PROBE655_TYPE = "1" *) 
  (* LC_PROBE655_WIDTH = "1" *) 
  (* LC_PROBE656_IS_DATA = "1'b0" *) 
  (* LC_PROBE656_IS_TRIG = "1'b0" *) 
  (* LC_PROBE656_MU_CNT = "1" *) 
  (* LC_PROBE656_PID = "16'b0000001010010000" *) 
  (* LC_PROBE656_TYPE = "1" *) 
  (* LC_PROBE656_WIDTH = "1" *) 
  (* LC_PROBE657_IS_DATA = "1'b0" *) 
  (* LC_PROBE657_IS_TRIG = "1'b0" *) 
  (* LC_PROBE657_MU_CNT = "1" *) 
  (* LC_PROBE657_PID = "16'b0000001010010001" *) 
  (* LC_PROBE657_TYPE = "1" *) 
  (* LC_PROBE657_WIDTH = "1" *) 
  (* LC_PROBE658_IS_DATA = "1'b0" *) 
  (* LC_PROBE658_IS_TRIG = "1'b0" *) 
  (* LC_PROBE658_MU_CNT = "1" *) 
  (* LC_PROBE658_PID = "16'b0000001010010010" *) 
  (* LC_PROBE658_TYPE = "1" *) 
  (* LC_PROBE658_WIDTH = "1" *) 
  (* LC_PROBE659_IS_DATA = "1'b0" *) 
  (* LC_PROBE659_IS_TRIG = "1'b0" *) 
  (* LC_PROBE659_MU_CNT = "1" *) 
  (* LC_PROBE659_PID = "16'b0000001010010011" *) 
  (* LC_PROBE659_TYPE = "1" *) 
  (* LC_PROBE659_WIDTH = "1" *) 
  (* LC_PROBE65_IS_DATA = "1'b0" *) 
  (* LC_PROBE65_IS_TRIG = "1'b0" *) 
  (* LC_PROBE65_MU_CNT = "1" *) 
  (* LC_PROBE65_PID = "16'b0000000001000001" *) 
  (* LC_PROBE65_TYPE = "1" *) 
  (* LC_PROBE65_WIDTH = "1" *) 
  (* LC_PROBE660_IS_DATA = "1'b0" *) 
  (* LC_PROBE660_IS_TRIG = "1'b0" *) 
  (* LC_PROBE660_MU_CNT = "1" *) 
  (* LC_PROBE660_PID = "16'b0000001010010100" *) 
  (* LC_PROBE660_TYPE = "1" *) 
  (* LC_PROBE660_WIDTH = "1" *) 
  (* LC_PROBE661_IS_DATA = "1'b0" *) 
  (* LC_PROBE661_IS_TRIG = "1'b0" *) 
  (* LC_PROBE661_MU_CNT = "1" *) 
  (* LC_PROBE661_PID = "16'b0000001010010101" *) 
  (* LC_PROBE661_TYPE = "1" *) 
  (* LC_PROBE661_WIDTH = "1" *) 
  (* LC_PROBE662_IS_DATA = "1'b0" *) 
  (* LC_PROBE662_IS_TRIG = "1'b0" *) 
  (* LC_PROBE662_MU_CNT = "1" *) 
  (* LC_PROBE662_PID = "16'b0000001010010110" *) 
  (* LC_PROBE662_TYPE = "1" *) 
  (* LC_PROBE662_WIDTH = "1" *) 
  (* LC_PROBE663_IS_DATA = "1'b0" *) 
  (* LC_PROBE663_IS_TRIG = "1'b0" *) 
  (* LC_PROBE663_MU_CNT = "1" *) 
  (* LC_PROBE663_PID = "16'b0000001010010111" *) 
  (* LC_PROBE663_TYPE = "1" *) 
  (* LC_PROBE663_WIDTH = "1" *) 
  (* LC_PROBE664_IS_DATA = "1'b0" *) 
  (* LC_PROBE664_IS_TRIG = "1'b0" *) 
  (* LC_PROBE664_MU_CNT = "1" *) 
  (* LC_PROBE664_PID = "16'b0000001010011000" *) 
  (* LC_PROBE664_TYPE = "1" *) 
  (* LC_PROBE664_WIDTH = "1" *) 
  (* LC_PROBE665_IS_DATA = "1'b0" *) 
  (* LC_PROBE665_IS_TRIG = "1'b0" *) 
  (* LC_PROBE665_MU_CNT = "1" *) 
  (* LC_PROBE665_PID = "16'b0000001010011001" *) 
  (* LC_PROBE665_TYPE = "1" *) 
  (* LC_PROBE665_WIDTH = "1" *) 
  (* LC_PROBE666_IS_DATA = "1'b0" *) 
  (* LC_PROBE666_IS_TRIG = "1'b0" *) 
  (* LC_PROBE666_MU_CNT = "1" *) 
  (* LC_PROBE666_PID = "16'b0000001010011010" *) 
  (* LC_PROBE666_TYPE = "1" *) 
  (* LC_PROBE666_WIDTH = "1" *) 
  (* LC_PROBE667_IS_DATA = "1'b0" *) 
  (* LC_PROBE667_IS_TRIG = "1'b0" *) 
  (* LC_PROBE667_MU_CNT = "1" *) 
  (* LC_PROBE667_PID = "16'b0000001010011011" *) 
  (* LC_PROBE667_TYPE = "1" *) 
  (* LC_PROBE667_WIDTH = "1" *) 
  (* LC_PROBE668_IS_DATA = "1'b0" *) 
  (* LC_PROBE668_IS_TRIG = "1'b0" *) 
  (* LC_PROBE668_MU_CNT = "1" *) 
  (* LC_PROBE668_PID = "16'b0000001010011100" *) 
  (* LC_PROBE668_TYPE = "1" *) 
  (* LC_PROBE668_WIDTH = "1" *) 
  (* LC_PROBE669_IS_DATA = "1'b0" *) 
  (* LC_PROBE669_IS_TRIG = "1'b0" *) 
  (* LC_PROBE669_MU_CNT = "1" *) 
  (* LC_PROBE669_PID = "16'b0000001010011101" *) 
  (* LC_PROBE669_TYPE = "1" *) 
  (* LC_PROBE669_WIDTH = "1" *) 
  (* LC_PROBE66_IS_DATA = "1'b0" *) 
  (* LC_PROBE66_IS_TRIG = "1'b0" *) 
  (* LC_PROBE66_MU_CNT = "1" *) 
  (* LC_PROBE66_PID = "16'b0000000001000010" *) 
  (* LC_PROBE66_TYPE = "1" *) 
  (* LC_PROBE66_WIDTH = "1" *) 
  (* LC_PROBE670_IS_DATA = "1'b0" *) 
  (* LC_PROBE670_IS_TRIG = "1'b0" *) 
  (* LC_PROBE670_MU_CNT = "1" *) 
  (* LC_PROBE670_PID = "16'b0000001010011110" *) 
  (* LC_PROBE670_TYPE = "1" *) 
  (* LC_PROBE670_WIDTH = "1" *) 
  (* LC_PROBE671_IS_DATA = "1'b0" *) 
  (* LC_PROBE671_IS_TRIG = "1'b0" *) 
  (* LC_PROBE671_MU_CNT = "1" *) 
  (* LC_PROBE671_PID = "16'b0000001010011111" *) 
  (* LC_PROBE671_TYPE = "1" *) 
  (* LC_PROBE671_WIDTH = "1" *) 
  (* LC_PROBE672_IS_DATA = "1'b0" *) 
  (* LC_PROBE672_IS_TRIG = "1'b0" *) 
  (* LC_PROBE672_MU_CNT = "1" *) 
  (* LC_PROBE672_PID = "16'b0000001010100000" *) 
  (* LC_PROBE672_TYPE = "1" *) 
  (* LC_PROBE672_WIDTH = "1" *) 
  (* LC_PROBE673_IS_DATA = "1'b0" *) 
  (* LC_PROBE673_IS_TRIG = "1'b0" *) 
  (* LC_PROBE673_MU_CNT = "1" *) 
  (* LC_PROBE673_PID = "16'b0000001010100001" *) 
  (* LC_PROBE673_TYPE = "1" *) 
  (* LC_PROBE673_WIDTH = "1" *) 
  (* LC_PROBE674_IS_DATA = "1'b0" *) 
  (* LC_PROBE674_IS_TRIG = "1'b0" *) 
  (* LC_PROBE674_MU_CNT = "1" *) 
  (* LC_PROBE674_PID = "16'b0000001010100010" *) 
  (* LC_PROBE674_TYPE = "1" *) 
  (* LC_PROBE674_WIDTH = "1" *) 
  (* LC_PROBE675_IS_DATA = "1'b0" *) 
  (* LC_PROBE675_IS_TRIG = "1'b0" *) 
  (* LC_PROBE675_MU_CNT = "1" *) 
  (* LC_PROBE675_PID = "16'b0000001010100011" *) 
  (* LC_PROBE675_TYPE = "1" *) 
  (* LC_PROBE675_WIDTH = "1" *) 
  (* LC_PROBE676_IS_DATA = "1'b0" *) 
  (* LC_PROBE676_IS_TRIG = "1'b0" *) 
  (* LC_PROBE676_MU_CNT = "1" *) 
  (* LC_PROBE676_PID = "16'b0000001010100100" *) 
  (* LC_PROBE676_TYPE = "1" *) 
  (* LC_PROBE676_WIDTH = "1" *) 
  (* LC_PROBE677_IS_DATA = "1'b0" *) 
  (* LC_PROBE677_IS_TRIG = "1'b0" *) 
  (* LC_PROBE677_MU_CNT = "1" *) 
  (* LC_PROBE677_PID = "16'b0000001010100101" *) 
  (* LC_PROBE677_TYPE = "1" *) 
  (* LC_PROBE677_WIDTH = "1" *) 
  (* LC_PROBE678_IS_DATA = "1'b0" *) 
  (* LC_PROBE678_IS_TRIG = "1'b0" *) 
  (* LC_PROBE678_MU_CNT = "1" *) 
  (* LC_PROBE678_PID = "16'b0000001010100110" *) 
  (* LC_PROBE678_TYPE = "1" *) 
  (* LC_PROBE678_WIDTH = "1" *) 
  (* LC_PROBE679_IS_DATA = "1'b0" *) 
  (* LC_PROBE679_IS_TRIG = "1'b0" *) 
  (* LC_PROBE679_MU_CNT = "1" *) 
  (* LC_PROBE679_PID = "16'b0000001010100111" *) 
  (* LC_PROBE679_TYPE = "1" *) 
  (* LC_PROBE679_WIDTH = "1" *) 
  (* LC_PROBE67_IS_DATA = "1'b0" *) 
  (* LC_PROBE67_IS_TRIG = "1'b0" *) 
  (* LC_PROBE67_MU_CNT = "1" *) 
  (* LC_PROBE67_PID = "16'b0000000001000011" *) 
  (* LC_PROBE67_TYPE = "1" *) 
  (* LC_PROBE67_WIDTH = "1" *) 
  (* LC_PROBE680_IS_DATA = "1'b0" *) 
  (* LC_PROBE680_IS_TRIG = "1'b0" *) 
  (* LC_PROBE680_MU_CNT = "1" *) 
  (* LC_PROBE680_PID = "16'b0000001010101000" *) 
  (* LC_PROBE680_TYPE = "1" *) 
  (* LC_PROBE680_WIDTH = "1" *) 
  (* LC_PROBE681_IS_DATA = "1'b0" *) 
  (* LC_PROBE681_IS_TRIG = "1'b0" *) 
  (* LC_PROBE681_MU_CNT = "1" *) 
  (* LC_PROBE681_PID = "16'b0000001010101001" *) 
  (* LC_PROBE681_TYPE = "1" *) 
  (* LC_PROBE681_WIDTH = "1" *) 
  (* LC_PROBE682_IS_DATA = "1'b0" *) 
  (* LC_PROBE682_IS_TRIG = "1'b0" *) 
  (* LC_PROBE682_MU_CNT = "1" *) 
  (* LC_PROBE682_PID = "16'b0000001010101010" *) 
  (* LC_PROBE682_TYPE = "1" *) 
  (* LC_PROBE682_WIDTH = "1" *) 
  (* LC_PROBE683_IS_DATA = "1'b0" *) 
  (* LC_PROBE683_IS_TRIG = "1'b0" *) 
  (* LC_PROBE683_MU_CNT = "1" *) 
  (* LC_PROBE683_PID = "16'b0000001010101011" *) 
  (* LC_PROBE683_TYPE = "1" *) 
  (* LC_PROBE683_WIDTH = "1" *) 
  (* LC_PROBE684_IS_DATA = "1'b0" *) 
  (* LC_PROBE684_IS_TRIG = "1'b0" *) 
  (* LC_PROBE684_MU_CNT = "1" *) 
  (* LC_PROBE684_PID = "16'b0000001010101100" *) 
  (* LC_PROBE684_TYPE = "1" *) 
  (* LC_PROBE684_WIDTH = "1" *) 
  (* LC_PROBE685_IS_DATA = "1'b0" *) 
  (* LC_PROBE685_IS_TRIG = "1'b0" *) 
  (* LC_PROBE685_MU_CNT = "1" *) 
  (* LC_PROBE685_PID = "16'b0000001010101101" *) 
  (* LC_PROBE685_TYPE = "1" *) 
  (* LC_PROBE685_WIDTH = "1" *) 
  (* LC_PROBE686_IS_DATA = "1'b0" *) 
  (* LC_PROBE686_IS_TRIG = "1'b0" *) 
  (* LC_PROBE686_MU_CNT = "1" *) 
  (* LC_PROBE686_PID = "16'b0000001010101110" *) 
  (* LC_PROBE686_TYPE = "1" *) 
  (* LC_PROBE686_WIDTH = "1" *) 
  (* LC_PROBE687_IS_DATA = "1'b0" *) 
  (* LC_PROBE687_IS_TRIG = "1'b0" *) 
  (* LC_PROBE687_MU_CNT = "1" *) 
  (* LC_PROBE687_PID = "16'b0000001010101111" *) 
  (* LC_PROBE687_TYPE = "1" *) 
  (* LC_PROBE687_WIDTH = "1" *) 
  (* LC_PROBE688_IS_DATA = "1'b0" *) 
  (* LC_PROBE688_IS_TRIG = "1'b0" *) 
  (* LC_PROBE688_MU_CNT = "1" *) 
  (* LC_PROBE688_PID = "16'b0000001010110000" *) 
  (* LC_PROBE688_TYPE = "1" *) 
  (* LC_PROBE688_WIDTH = "1" *) 
  (* LC_PROBE689_IS_DATA = "1'b0" *) 
  (* LC_PROBE689_IS_TRIG = "1'b0" *) 
  (* LC_PROBE689_MU_CNT = "1" *) 
  (* LC_PROBE689_PID = "16'b0000001010110001" *) 
  (* LC_PROBE689_TYPE = "1" *) 
  (* LC_PROBE689_WIDTH = "1" *) 
  (* LC_PROBE68_IS_DATA = "1'b0" *) 
  (* LC_PROBE68_IS_TRIG = "1'b0" *) 
  (* LC_PROBE68_MU_CNT = "1" *) 
  (* LC_PROBE68_PID = "16'b0000000001000100" *) 
  (* LC_PROBE68_TYPE = "1" *) 
  (* LC_PROBE68_WIDTH = "1" *) 
  (* LC_PROBE690_IS_DATA = "1'b0" *) 
  (* LC_PROBE690_IS_TRIG = "1'b0" *) 
  (* LC_PROBE690_MU_CNT = "1" *) 
  (* LC_PROBE690_PID = "16'b0000001010110010" *) 
  (* LC_PROBE690_TYPE = "1" *) 
  (* LC_PROBE690_WIDTH = "1" *) 
  (* LC_PROBE691_IS_DATA = "1'b0" *) 
  (* LC_PROBE691_IS_TRIG = "1'b0" *) 
  (* LC_PROBE691_MU_CNT = "1" *) 
  (* LC_PROBE691_PID = "16'b0000001010110011" *) 
  (* LC_PROBE691_TYPE = "1" *) 
  (* LC_PROBE691_WIDTH = "1" *) 
  (* LC_PROBE692_IS_DATA = "1'b0" *) 
  (* LC_PROBE692_IS_TRIG = "1'b0" *) 
  (* LC_PROBE692_MU_CNT = "1" *) 
  (* LC_PROBE692_PID = "16'b0000001010110100" *) 
  (* LC_PROBE692_TYPE = "1" *) 
  (* LC_PROBE692_WIDTH = "1" *) 
  (* LC_PROBE693_IS_DATA = "1'b0" *) 
  (* LC_PROBE693_IS_TRIG = "1'b0" *) 
  (* LC_PROBE693_MU_CNT = "1" *) 
  (* LC_PROBE693_PID = "16'b0000001010110101" *) 
  (* LC_PROBE693_TYPE = "1" *) 
  (* LC_PROBE693_WIDTH = "1" *) 
  (* LC_PROBE694_IS_DATA = "1'b0" *) 
  (* LC_PROBE694_IS_TRIG = "1'b0" *) 
  (* LC_PROBE694_MU_CNT = "1" *) 
  (* LC_PROBE694_PID = "16'b0000001010110110" *) 
  (* LC_PROBE694_TYPE = "1" *) 
  (* LC_PROBE694_WIDTH = "1" *) 
  (* LC_PROBE695_IS_DATA = "1'b0" *) 
  (* LC_PROBE695_IS_TRIG = "1'b0" *) 
  (* LC_PROBE695_MU_CNT = "1" *) 
  (* LC_PROBE695_PID = "16'b0000001010110111" *) 
  (* LC_PROBE695_TYPE = "1" *) 
  (* LC_PROBE695_WIDTH = "1" *) 
  (* LC_PROBE696_IS_DATA = "1'b0" *) 
  (* LC_PROBE696_IS_TRIG = "1'b0" *) 
  (* LC_PROBE696_MU_CNT = "1" *) 
  (* LC_PROBE696_PID = "16'b0000001010111000" *) 
  (* LC_PROBE696_TYPE = "1" *) 
  (* LC_PROBE696_WIDTH = "1" *) 
  (* LC_PROBE697_IS_DATA = "1'b0" *) 
  (* LC_PROBE697_IS_TRIG = "1'b0" *) 
  (* LC_PROBE697_MU_CNT = "1" *) 
  (* LC_PROBE697_PID = "16'b0000001010111001" *) 
  (* LC_PROBE697_TYPE = "1" *) 
  (* LC_PROBE697_WIDTH = "1" *) 
  (* LC_PROBE698_IS_DATA = "1'b0" *) 
  (* LC_PROBE698_IS_TRIG = "1'b0" *) 
  (* LC_PROBE698_MU_CNT = "1" *) 
  (* LC_PROBE698_PID = "16'b0000001010111010" *) 
  (* LC_PROBE698_TYPE = "1" *) 
  (* LC_PROBE698_WIDTH = "1" *) 
  (* LC_PROBE699_IS_DATA = "1'b0" *) 
  (* LC_PROBE699_IS_TRIG = "1'b0" *) 
  (* LC_PROBE699_MU_CNT = "1" *) 
  (* LC_PROBE699_PID = "16'b0000001010111011" *) 
  (* LC_PROBE699_TYPE = "1" *) 
  (* LC_PROBE699_WIDTH = "1" *) 
  (* LC_PROBE69_IS_DATA = "1'b0" *) 
  (* LC_PROBE69_IS_TRIG = "1'b0" *) 
  (* LC_PROBE69_MU_CNT = "1" *) 
  (* LC_PROBE69_PID = "16'b0000000001000101" *) 
  (* LC_PROBE69_TYPE = "1" *) 
  (* LC_PROBE69_WIDTH = "1" *) 
  (* LC_PROBE6_IS_DATA = "1'b0" *) 
  (* LC_PROBE6_IS_TRIG = "1'b0" *) 
  (* LC_PROBE6_MU_CNT = "1" *) 
  (* LC_PROBE6_PID = "16'b0000000000000110" *) 
  (* LC_PROBE6_TYPE = "1" *) 
  (* LC_PROBE6_WIDTH = "1" *) 
  (* LC_PROBE700_IS_DATA = "1'b0" *) 
  (* LC_PROBE700_IS_TRIG = "1'b0" *) 
  (* LC_PROBE700_MU_CNT = "1" *) 
  (* LC_PROBE700_PID = "16'b0000001010111100" *) 
  (* LC_PROBE700_TYPE = "1" *) 
  (* LC_PROBE700_WIDTH = "1" *) 
  (* LC_PROBE701_IS_DATA = "1'b0" *) 
  (* LC_PROBE701_IS_TRIG = "1'b0" *) 
  (* LC_PROBE701_MU_CNT = "1" *) 
  (* LC_PROBE701_PID = "16'b0000001010111101" *) 
  (* LC_PROBE701_TYPE = "1" *) 
  (* LC_PROBE701_WIDTH = "1" *) 
  (* LC_PROBE702_IS_DATA = "1'b0" *) 
  (* LC_PROBE702_IS_TRIG = "1'b0" *) 
  (* LC_PROBE702_MU_CNT = "1" *) 
  (* LC_PROBE702_PID = "16'b0000001010111110" *) 
  (* LC_PROBE702_TYPE = "1" *) 
  (* LC_PROBE702_WIDTH = "1" *) 
  (* LC_PROBE703_IS_DATA = "1'b0" *) 
  (* LC_PROBE703_IS_TRIG = "1'b0" *) 
  (* LC_PROBE703_MU_CNT = "1" *) 
  (* LC_PROBE703_PID = "16'b0000001010111111" *) 
  (* LC_PROBE703_TYPE = "1" *) 
  (* LC_PROBE703_WIDTH = "1" *) 
  (* LC_PROBE704_IS_DATA = "1'b0" *) 
  (* LC_PROBE704_IS_TRIG = "1'b0" *) 
  (* LC_PROBE704_MU_CNT = "1" *) 
  (* LC_PROBE704_PID = "16'b0000001011000000" *) 
  (* LC_PROBE704_TYPE = "1" *) 
  (* LC_PROBE704_WIDTH = "1" *) 
  (* LC_PROBE705_IS_DATA = "1'b0" *) 
  (* LC_PROBE705_IS_TRIG = "1'b0" *) 
  (* LC_PROBE705_MU_CNT = "1" *) 
  (* LC_PROBE705_PID = "16'b0000001011000001" *) 
  (* LC_PROBE705_TYPE = "1" *) 
  (* LC_PROBE705_WIDTH = "1" *) 
  (* LC_PROBE706_IS_DATA = "1'b0" *) 
  (* LC_PROBE706_IS_TRIG = "1'b0" *) 
  (* LC_PROBE706_MU_CNT = "1" *) 
  (* LC_PROBE706_PID = "16'b0000001011000010" *) 
  (* LC_PROBE706_TYPE = "1" *) 
  (* LC_PROBE706_WIDTH = "1" *) 
  (* LC_PROBE707_IS_DATA = "1'b0" *) 
  (* LC_PROBE707_IS_TRIG = "1'b0" *) 
  (* LC_PROBE707_MU_CNT = "1" *) 
  (* LC_PROBE707_PID = "16'b0000001011000011" *) 
  (* LC_PROBE707_TYPE = "1" *) 
  (* LC_PROBE707_WIDTH = "1" *) 
  (* LC_PROBE708_IS_DATA = "1'b0" *) 
  (* LC_PROBE708_IS_TRIG = "1'b0" *) 
  (* LC_PROBE708_MU_CNT = "1" *) 
  (* LC_PROBE708_PID = "16'b0000001011000100" *) 
  (* LC_PROBE708_TYPE = "1" *) 
  (* LC_PROBE708_WIDTH = "1" *) 
  (* LC_PROBE709_IS_DATA = "1'b0" *) 
  (* LC_PROBE709_IS_TRIG = "1'b0" *) 
  (* LC_PROBE709_MU_CNT = "1" *) 
  (* LC_PROBE709_PID = "16'b0000001011000101" *) 
  (* LC_PROBE709_TYPE = "1" *) 
  (* LC_PROBE709_WIDTH = "1" *) 
  (* LC_PROBE70_IS_DATA = "1'b0" *) 
  (* LC_PROBE70_IS_TRIG = "1'b0" *) 
  (* LC_PROBE70_MU_CNT = "1" *) 
  (* LC_PROBE70_PID = "16'b0000000001000110" *) 
  (* LC_PROBE70_TYPE = "1" *) 
  (* LC_PROBE70_WIDTH = "1" *) 
  (* LC_PROBE710_IS_DATA = "1'b0" *) 
  (* LC_PROBE710_IS_TRIG = "1'b0" *) 
  (* LC_PROBE710_MU_CNT = "1" *) 
  (* LC_PROBE710_PID = "16'b0000001011000110" *) 
  (* LC_PROBE710_TYPE = "1" *) 
  (* LC_PROBE710_WIDTH = "1" *) 
  (* LC_PROBE711_IS_DATA = "1'b0" *) 
  (* LC_PROBE711_IS_TRIG = "1'b0" *) 
  (* LC_PROBE711_MU_CNT = "1" *) 
  (* LC_PROBE711_PID = "16'b0000001011000111" *) 
  (* LC_PROBE711_TYPE = "1" *) 
  (* LC_PROBE711_WIDTH = "1" *) 
  (* LC_PROBE712_IS_DATA = "1'b0" *) 
  (* LC_PROBE712_IS_TRIG = "1'b0" *) 
  (* LC_PROBE712_MU_CNT = "1" *) 
  (* LC_PROBE712_PID = "16'b0000001011001000" *) 
  (* LC_PROBE712_TYPE = "1" *) 
  (* LC_PROBE712_WIDTH = "1" *) 
  (* LC_PROBE713_IS_DATA = "1'b0" *) 
  (* LC_PROBE713_IS_TRIG = "1'b0" *) 
  (* LC_PROBE713_MU_CNT = "1" *) 
  (* LC_PROBE713_PID = "16'b0000001011001001" *) 
  (* LC_PROBE713_TYPE = "1" *) 
  (* LC_PROBE713_WIDTH = "1" *) 
  (* LC_PROBE714_IS_DATA = "1'b0" *) 
  (* LC_PROBE714_IS_TRIG = "1'b0" *) 
  (* LC_PROBE714_MU_CNT = "1" *) 
  (* LC_PROBE714_PID = "16'b0000001011001010" *) 
  (* LC_PROBE714_TYPE = "1" *) 
  (* LC_PROBE714_WIDTH = "1" *) 
  (* LC_PROBE715_IS_DATA = "1'b0" *) 
  (* LC_PROBE715_IS_TRIG = "1'b0" *) 
  (* LC_PROBE715_MU_CNT = "1" *) 
  (* LC_PROBE715_PID = "16'b0000001011001011" *) 
  (* LC_PROBE715_TYPE = "1" *) 
  (* LC_PROBE715_WIDTH = "1" *) 
  (* LC_PROBE716_IS_DATA = "1'b0" *) 
  (* LC_PROBE716_IS_TRIG = "1'b0" *) 
  (* LC_PROBE716_MU_CNT = "1" *) 
  (* LC_PROBE716_PID = "16'b0000001011001100" *) 
  (* LC_PROBE716_TYPE = "1" *) 
  (* LC_PROBE716_WIDTH = "1" *) 
  (* LC_PROBE717_IS_DATA = "1'b0" *) 
  (* LC_PROBE717_IS_TRIG = "1'b0" *) 
  (* LC_PROBE717_MU_CNT = "1" *) 
  (* LC_PROBE717_PID = "16'b0000001011001101" *) 
  (* LC_PROBE717_TYPE = "1" *) 
  (* LC_PROBE717_WIDTH = "1" *) 
  (* LC_PROBE718_IS_DATA = "1'b0" *) 
  (* LC_PROBE718_IS_TRIG = "1'b0" *) 
  (* LC_PROBE718_MU_CNT = "1" *) 
  (* LC_PROBE718_PID = "16'b0000001011001110" *) 
  (* LC_PROBE718_TYPE = "1" *) 
  (* LC_PROBE718_WIDTH = "1" *) 
  (* LC_PROBE719_IS_DATA = "1'b0" *) 
  (* LC_PROBE719_IS_TRIG = "1'b0" *) 
  (* LC_PROBE719_MU_CNT = "1" *) 
  (* LC_PROBE719_PID = "16'b0000001011001111" *) 
  (* LC_PROBE719_TYPE = "1" *) 
  (* LC_PROBE719_WIDTH = "1" *) 
  (* LC_PROBE71_IS_DATA = "1'b0" *) 
  (* LC_PROBE71_IS_TRIG = "1'b0" *) 
  (* LC_PROBE71_MU_CNT = "1" *) 
  (* LC_PROBE71_PID = "16'b0000000001000111" *) 
  (* LC_PROBE71_TYPE = "1" *) 
  (* LC_PROBE71_WIDTH = "1" *) 
  (* LC_PROBE720_IS_DATA = "1'b0" *) 
  (* LC_PROBE720_IS_TRIG = "1'b0" *) 
  (* LC_PROBE720_MU_CNT = "1" *) 
  (* LC_PROBE720_PID = "16'b0000001011010000" *) 
  (* LC_PROBE720_TYPE = "1" *) 
  (* LC_PROBE720_WIDTH = "1" *) 
  (* LC_PROBE721_IS_DATA = "1'b0" *) 
  (* LC_PROBE721_IS_TRIG = "1'b0" *) 
  (* LC_PROBE721_MU_CNT = "1" *) 
  (* LC_PROBE721_PID = "16'b0000001011010001" *) 
  (* LC_PROBE721_TYPE = "1" *) 
  (* LC_PROBE721_WIDTH = "1" *) 
  (* LC_PROBE722_IS_DATA = "1'b0" *) 
  (* LC_PROBE722_IS_TRIG = "1'b0" *) 
  (* LC_PROBE722_MU_CNT = "1" *) 
  (* LC_PROBE722_PID = "16'b0000001011010010" *) 
  (* LC_PROBE722_TYPE = "1" *) 
  (* LC_PROBE722_WIDTH = "1" *) 
  (* LC_PROBE723_IS_DATA = "1'b0" *) 
  (* LC_PROBE723_IS_TRIG = "1'b0" *) 
  (* LC_PROBE723_MU_CNT = "1" *) 
  (* LC_PROBE723_PID = "16'b0000001011010011" *) 
  (* LC_PROBE723_TYPE = "1" *) 
  (* LC_PROBE723_WIDTH = "1" *) 
  (* LC_PROBE724_IS_DATA = "1'b0" *) 
  (* LC_PROBE724_IS_TRIG = "1'b0" *) 
  (* LC_PROBE724_MU_CNT = "1" *) 
  (* LC_PROBE724_PID = "16'b0000001011010100" *) 
  (* LC_PROBE724_TYPE = "1" *) 
  (* LC_PROBE724_WIDTH = "1" *) 
  (* LC_PROBE725_IS_DATA = "1'b0" *) 
  (* LC_PROBE725_IS_TRIG = "1'b0" *) 
  (* LC_PROBE725_MU_CNT = "1" *) 
  (* LC_PROBE725_PID = "16'b0000001011010101" *) 
  (* LC_PROBE725_TYPE = "1" *) 
  (* LC_PROBE725_WIDTH = "1" *) 
  (* LC_PROBE726_IS_DATA = "1'b0" *) 
  (* LC_PROBE726_IS_TRIG = "1'b0" *) 
  (* LC_PROBE726_MU_CNT = "1" *) 
  (* LC_PROBE726_PID = "16'b0000001011010110" *) 
  (* LC_PROBE726_TYPE = "1" *) 
  (* LC_PROBE726_WIDTH = "1" *) 
  (* LC_PROBE727_IS_DATA = "1'b0" *) 
  (* LC_PROBE727_IS_TRIG = "1'b0" *) 
  (* LC_PROBE727_MU_CNT = "1" *) 
  (* LC_PROBE727_PID = "16'b0000001011010111" *) 
  (* LC_PROBE727_TYPE = "1" *) 
  (* LC_PROBE727_WIDTH = "1" *) 
  (* LC_PROBE728_IS_DATA = "1'b0" *) 
  (* LC_PROBE728_IS_TRIG = "1'b0" *) 
  (* LC_PROBE728_MU_CNT = "1" *) 
  (* LC_PROBE728_PID = "16'b0000001011011000" *) 
  (* LC_PROBE728_TYPE = "1" *) 
  (* LC_PROBE728_WIDTH = "1" *) 
  (* LC_PROBE729_IS_DATA = "1'b0" *) 
  (* LC_PROBE729_IS_TRIG = "1'b0" *) 
  (* LC_PROBE729_MU_CNT = "1" *) 
  (* LC_PROBE729_PID = "16'b0000001011011001" *) 
  (* LC_PROBE729_TYPE = "1" *) 
  (* LC_PROBE729_WIDTH = "1" *) 
  (* LC_PROBE72_IS_DATA = "1'b0" *) 
  (* LC_PROBE72_IS_TRIG = "1'b0" *) 
  (* LC_PROBE72_MU_CNT = "1" *) 
  (* LC_PROBE72_PID = "16'b0000000001001000" *) 
  (* LC_PROBE72_TYPE = "1" *) 
  (* LC_PROBE72_WIDTH = "1" *) 
  (* LC_PROBE730_IS_DATA = "1'b0" *) 
  (* LC_PROBE730_IS_TRIG = "1'b0" *) 
  (* LC_PROBE730_MU_CNT = "1" *) 
  (* LC_PROBE730_PID = "16'b0000001011011010" *) 
  (* LC_PROBE730_TYPE = "1" *) 
  (* LC_PROBE730_WIDTH = "1" *) 
  (* LC_PROBE731_IS_DATA = "1'b0" *) 
  (* LC_PROBE731_IS_TRIG = "1'b0" *) 
  (* LC_PROBE731_MU_CNT = "1" *) 
  (* LC_PROBE731_PID = "16'b0000001011011011" *) 
  (* LC_PROBE731_TYPE = "1" *) 
  (* LC_PROBE731_WIDTH = "1" *) 
  (* LC_PROBE732_IS_DATA = "1'b0" *) 
  (* LC_PROBE732_IS_TRIG = "1'b0" *) 
  (* LC_PROBE732_MU_CNT = "1" *) 
  (* LC_PROBE732_PID = "16'b0000001011011100" *) 
  (* LC_PROBE732_TYPE = "1" *) 
  (* LC_PROBE732_WIDTH = "1" *) 
  (* LC_PROBE733_IS_DATA = "1'b0" *) 
  (* LC_PROBE733_IS_TRIG = "1'b0" *) 
  (* LC_PROBE733_MU_CNT = "1" *) 
  (* LC_PROBE733_PID = "16'b0000001011011101" *) 
  (* LC_PROBE733_TYPE = "1" *) 
  (* LC_PROBE733_WIDTH = "1" *) 
  (* LC_PROBE734_IS_DATA = "1'b0" *) 
  (* LC_PROBE734_IS_TRIG = "1'b0" *) 
  (* LC_PROBE734_MU_CNT = "1" *) 
  (* LC_PROBE734_PID = "16'b0000001011011110" *) 
  (* LC_PROBE734_TYPE = "1" *) 
  (* LC_PROBE734_WIDTH = "1" *) 
  (* LC_PROBE735_IS_DATA = "1'b0" *) 
  (* LC_PROBE735_IS_TRIG = "1'b0" *) 
  (* LC_PROBE735_MU_CNT = "1" *) 
  (* LC_PROBE735_PID = "16'b0000001011011111" *) 
  (* LC_PROBE735_TYPE = "1" *) 
  (* LC_PROBE735_WIDTH = "1" *) 
  (* LC_PROBE736_IS_DATA = "1'b0" *) 
  (* LC_PROBE736_IS_TRIG = "1'b0" *) 
  (* LC_PROBE736_MU_CNT = "1" *) 
  (* LC_PROBE736_PID = "16'b0000001011100000" *) 
  (* LC_PROBE736_TYPE = "1" *) 
  (* LC_PROBE736_WIDTH = "1" *) 
  (* LC_PROBE737_IS_DATA = "1'b0" *) 
  (* LC_PROBE737_IS_TRIG = "1'b0" *) 
  (* LC_PROBE737_MU_CNT = "1" *) 
  (* LC_PROBE737_PID = "16'b0000001011100001" *) 
  (* LC_PROBE737_TYPE = "1" *) 
  (* LC_PROBE737_WIDTH = "1" *) 
  (* LC_PROBE738_IS_DATA = "1'b0" *) 
  (* LC_PROBE738_IS_TRIG = "1'b0" *) 
  (* LC_PROBE738_MU_CNT = "1" *) 
  (* LC_PROBE738_PID = "16'b0000001011100010" *) 
  (* LC_PROBE738_TYPE = "1" *) 
  (* LC_PROBE738_WIDTH = "1" *) 
  (* LC_PROBE739_IS_DATA = "1'b0" *) 
  (* LC_PROBE739_IS_TRIG = "1'b0" *) 
  (* LC_PROBE739_MU_CNT = "1" *) 
  (* LC_PROBE739_PID = "16'b0000001011100011" *) 
  (* LC_PROBE739_TYPE = "1" *) 
  (* LC_PROBE739_WIDTH = "1" *) 
  (* LC_PROBE73_IS_DATA = "1'b0" *) 
  (* LC_PROBE73_IS_TRIG = "1'b0" *) 
  (* LC_PROBE73_MU_CNT = "1" *) 
  (* LC_PROBE73_PID = "16'b0000000001001001" *) 
  (* LC_PROBE73_TYPE = "1" *) 
  (* LC_PROBE73_WIDTH = "1" *) 
  (* LC_PROBE740_IS_DATA = "1'b0" *) 
  (* LC_PROBE740_IS_TRIG = "1'b0" *) 
  (* LC_PROBE740_MU_CNT = "1" *) 
  (* LC_PROBE740_PID = "16'b0000001011100100" *) 
  (* LC_PROBE740_TYPE = "1" *) 
  (* LC_PROBE740_WIDTH = "1" *) 
  (* LC_PROBE741_IS_DATA = "1'b0" *) 
  (* LC_PROBE741_IS_TRIG = "1'b0" *) 
  (* LC_PROBE741_MU_CNT = "1" *) 
  (* LC_PROBE741_PID = "16'b0000001011100101" *) 
  (* LC_PROBE741_TYPE = "1" *) 
  (* LC_PROBE741_WIDTH = "1" *) 
  (* LC_PROBE742_IS_DATA = "1'b0" *) 
  (* LC_PROBE742_IS_TRIG = "1'b0" *) 
  (* LC_PROBE742_MU_CNT = "1" *) 
  (* LC_PROBE742_PID = "16'b0000001011100110" *) 
  (* LC_PROBE742_TYPE = "1" *) 
  (* LC_PROBE742_WIDTH = "1" *) 
  (* LC_PROBE743_IS_DATA = "1'b0" *) 
  (* LC_PROBE743_IS_TRIG = "1'b0" *) 
  (* LC_PROBE743_MU_CNT = "1" *) 
  (* LC_PROBE743_PID = "16'b0000001011100111" *) 
  (* LC_PROBE743_TYPE = "1" *) 
  (* LC_PROBE743_WIDTH = "1" *) 
  (* LC_PROBE744_IS_DATA = "1'b0" *) 
  (* LC_PROBE744_IS_TRIG = "1'b0" *) 
  (* LC_PROBE744_MU_CNT = "1" *) 
  (* LC_PROBE744_PID = "16'b0000001011101000" *) 
  (* LC_PROBE744_TYPE = "1" *) 
  (* LC_PROBE744_WIDTH = "1" *) 
  (* LC_PROBE745_IS_DATA = "1'b0" *) 
  (* LC_PROBE745_IS_TRIG = "1'b0" *) 
  (* LC_PROBE745_MU_CNT = "1" *) 
  (* LC_PROBE745_PID = "16'b0000001011101001" *) 
  (* LC_PROBE745_TYPE = "1" *) 
  (* LC_PROBE745_WIDTH = "1" *) 
  (* LC_PROBE746_IS_DATA = "1'b0" *) 
  (* LC_PROBE746_IS_TRIG = "1'b0" *) 
  (* LC_PROBE746_MU_CNT = "1" *) 
  (* LC_PROBE746_PID = "16'b0000001011101010" *) 
  (* LC_PROBE746_TYPE = "1" *) 
  (* LC_PROBE746_WIDTH = "1" *) 
  (* LC_PROBE747_IS_DATA = "1'b0" *) 
  (* LC_PROBE747_IS_TRIG = "1'b0" *) 
  (* LC_PROBE747_MU_CNT = "1" *) 
  (* LC_PROBE747_PID = "16'b0000001011101011" *) 
  (* LC_PROBE747_TYPE = "1" *) 
  (* LC_PROBE747_WIDTH = "1" *) 
  (* LC_PROBE748_IS_DATA = "1'b0" *) 
  (* LC_PROBE748_IS_TRIG = "1'b0" *) 
  (* LC_PROBE748_MU_CNT = "1" *) 
  (* LC_PROBE748_PID = "16'b0000001011101100" *) 
  (* LC_PROBE748_TYPE = "1" *) 
  (* LC_PROBE748_WIDTH = "1" *) 
  (* LC_PROBE749_IS_DATA = "1'b0" *) 
  (* LC_PROBE749_IS_TRIG = "1'b0" *) 
  (* LC_PROBE749_MU_CNT = "1" *) 
  (* LC_PROBE749_PID = "16'b0000001011101101" *) 
  (* LC_PROBE749_TYPE = "1" *) 
  (* LC_PROBE749_WIDTH = "1" *) 
  (* LC_PROBE74_IS_DATA = "1'b0" *) 
  (* LC_PROBE74_IS_TRIG = "1'b0" *) 
  (* LC_PROBE74_MU_CNT = "1" *) 
  (* LC_PROBE74_PID = "16'b0000000001001010" *) 
  (* LC_PROBE74_TYPE = "1" *) 
  (* LC_PROBE74_WIDTH = "1" *) 
  (* LC_PROBE750_IS_DATA = "1'b0" *) 
  (* LC_PROBE750_IS_TRIG = "1'b0" *) 
  (* LC_PROBE750_MU_CNT = "1" *) 
  (* LC_PROBE750_PID = "16'b0000001011101110" *) 
  (* LC_PROBE750_TYPE = "1" *) 
  (* LC_PROBE750_WIDTH = "1" *) 
  (* LC_PROBE751_IS_DATA = "1'b0" *) 
  (* LC_PROBE751_IS_TRIG = "1'b0" *) 
  (* LC_PROBE751_MU_CNT = "1" *) 
  (* LC_PROBE751_PID = "16'b0000001011101111" *) 
  (* LC_PROBE751_TYPE = "1" *) 
  (* LC_PROBE751_WIDTH = "1" *) 
  (* LC_PROBE752_IS_DATA = "1'b0" *) 
  (* LC_PROBE752_IS_TRIG = "1'b0" *) 
  (* LC_PROBE752_MU_CNT = "1" *) 
  (* LC_PROBE752_PID = "16'b0000001011110000" *) 
  (* LC_PROBE752_TYPE = "1" *) 
  (* LC_PROBE752_WIDTH = "1" *) 
  (* LC_PROBE753_IS_DATA = "1'b0" *) 
  (* LC_PROBE753_IS_TRIG = "1'b0" *) 
  (* LC_PROBE753_MU_CNT = "1" *) 
  (* LC_PROBE753_PID = "16'b0000001011110001" *) 
  (* LC_PROBE753_TYPE = "1" *) 
  (* LC_PROBE753_WIDTH = "1" *) 
  (* LC_PROBE754_IS_DATA = "1'b0" *) 
  (* LC_PROBE754_IS_TRIG = "1'b0" *) 
  (* LC_PROBE754_MU_CNT = "1" *) 
  (* LC_PROBE754_PID = "16'b0000001011110010" *) 
  (* LC_PROBE754_TYPE = "1" *) 
  (* LC_PROBE754_WIDTH = "1" *) 
  (* LC_PROBE755_IS_DATA = "1'b0" *) 
  (* LC_PROBE755_IS_TRIG = "1'b0" *) 
  (* LC_PROBE755_MU_CNT = "1" *) 
  (* LC_PROBE755_PID = "16'b0000001011110011" *) 
  (* LC_PROBE755_TYPE = "1" *) 
  (* LC_PROBE755_WIDTH = "1" *) 
  (* LC_PROBE756_IS_DATA = "1'b0" *) 
  (* LC_PROBE756_IS_TRIG = "1'b0" *) 
  (* LC_PROBE756_MU_CNT = "1" *) 
  (* LC_PROBE756_PID = "16'b0000001011110100" *) 
  (* LC_PROBE756_TYPE = "1" *) 
  (* LC_PROBE756_WIDTH = "1" *) 
  (* LC_PROBE757_IS_DATA = "1'b0" *) 
  (* LC_PROBE757_IS_TRIG = "1'b0" *) 
  (* LC_PROBE757_MU_CNT = "1" *) 
  (* LC_PROBE757_PID = "16'b0000001011110101" *) 
  (* LC_PROBE757_TYPE = "1" *) 
  (* LC_PROBE757_WIDTH = "1" *) 
  (* LC_PROBE758_IS_DATA = "1'b0" *) 
  (* LC_PROBE758_IS_TRIG = "1'b0" *) 
  (* LC_PROBE758_MU_CNT = "1" *) 
  (* LC_PROBE758_PID = "16'b0000001011110110" *) 
  (* LC_PROBE758_TYPE = "1" *) 
  (* LC_PROBE758_WIDTH = "1" *) 
  (* LC_PROBE759_IS_DATA = "1'b0" *) 
  (* LC_PROBE759_IS_TRIG = "1'b0" *) 
  (* LC_PROBE759_MU_CNT = "1" *) 
  (* LC_PROBE759_PID = "16'b0000001011110111" *) 
  (* LC_PROBE759_TYPE = "1" *) 
  (* LC_PROBE759_WIDTH = "1" *) 
  (* LC_PROBE75_IS_DATA = "1'b0" *) 
  (* LC_PROBE75_IS_TRIG = "1'b0" *) 
  (* LC_PROBE75_MU_CNT = "1" *) 
  (* LC_PROBE75_PID = "16'b0000000001001011" *) 
  (* LC_PROBE75_TYPE = "1" *) 
  (* LC_PROBE75_WIDTH = "1" *) 
  (* LC_PROBE760_IS_DATA = "1'b0" *) 
  (* LC_PROBE760_IS_TRIG = "1'b0" *) 
  (* LC_PROBE760_MU_CNT = "1" *) 
  (* LC_PROBE760_PID = "16'b0000001011111000" *) 
  (* LC_PROBE760_TYPE = "1" *) 
  (* LC_PROBE760_WIDTH = "1" *) 
  (* LC_PROBE761_IS_DATA = "1'b0" *) 
  (* LC_PROBE761_IS_TRIG = "1'b0" *) 
  (* LC_PROBE761_MU_CNT = "1" *) 
  (* LC_PROBE761_PID = "16'b0000001011111001" *) 
  (* LC_PROBE761_TYPE = "1" *) 
  (* LC_PROBE761_WIDTH = "1" *) 
  (* LC_PROBE762_IS_DATA = "1'b0" *) 
  (* LC_PROBE762_IS_TRIG = "1'b0" *) 
  (* LC_PROBE762_MU_CNT = "1" *) 
  (* LC_PROBE762_PID = "16'b0000001011111010" *) 
  (* LC_PROBE762_TYPE = "1" *) 
  (* LC_PROBE762_WIDTH = "1" *) 
  (* LC_PROBE763_IS_DATA = "1'b0" *) 
  (* LC_PROBE763_IS_TRIG = "1'b0" *) 
  (* LC_PROBE763_MU_CNT = "1" *) 
  (* LC_PROBE763_PID = "16'b0000001011111011" *) 
  (* LC_PROBE763_TYPE = "1" *) 
  (* LC_PROBE763_WIDTH = "1" *) 
  (* LC_PROBE764_IS_DATA = "1'b0" *) 
  (* LC_PROBE764_IS_TRIG = "1'b0" *) 
  (* LC_PROBE764_MU_CNT = "1" *) 
  (* LC_PROBE764_PID = "16'b0000001011111100" *) 
  (* LC_PROBE764_TYPE = "1" *) 
  (* LC_PROBE764_WIDTH = "1" *) 
  (* LC_PROBE765_IS_DATA = "1'b0" *) 
  (* LC_PROBE765_IS_TRIG = "1'b0" *) 
  (* LC_PROBE765_MU_CNT = "1" *) 
  (* LC_PROBE765_PID = "16'b0000001011111101" *) 
  (* LC_PROBE765_TYPE = "1" *) 
  (* LC_PROBE765_WIDTH = "1" *) 
  (* LC_PROBE766_IS_DATA = "1'b0" *) 
  (* LC_PROBE766_IS_TRIG = "1'b0" *) 
  (* LC_PROBE766_MU_CNT = "1" *) 
  (* LC_PROBE766_PID = "16'b0000001011111110" *) 
  (* LC_PROBE766_TYPE = "1" *) 
  (* LC_PROBE766_WIDTH = "1" *) 
  (* LC_PROBE767_IS_DATA = "1'b0" *) 
  (* LC_PROBE767_IS_TRIG = "1'b0" *) 
  (* LC_PROBE767_MU_CNT = "1" *) 
  (* LC_PROBE767_PID = "16'b0000001011111111" *) 
  (* LC_PROBE767_TYPE = "1" *) 
  (* LC_PROBE767_WIDTH = "1" *) 
  (* LC_PROBE768_IS_DATA = "1'b0" *) 
  (* LC_PROBE768_IS_TRIG = "1'b0" *) 
  (* LC_PROBE768_MU_CNT = "1" *) 
  (* LC_PROBE768_PID = "16'b0000001100000000" *) 
  (* LC_PROBE768_TYPE = "1" *) 
  (* LC_PROBE768_WIDTH = "1" *) 
  (* LC_PROBE769_IS_DATA = "1'b0" *) 
  (* LC_PROBE769_IS_TRIG = "1'b0" *) 
  (* LC_PROBE769_MU_CNT = "1" *) 
  (* LC_PROBE769_PID = "16'b0000001100000001" *) 
  (* LC_PROBE769_TYPE = "1" *) 
  (* LC_PROBE769_WIDTH = "1" *) 
  (* LC_PROBE76_IS_DATA = "1'b0" *) 
  (* LC_PROBE76_IS_TRIG = "1'b0" *) 
  (* LC_PROBE76_MU_CNT = "1" *) 
  (* LC_PROBE76_PID = "16'b0000000001001100" *) 
  (* LC_PROBE76_TYPE = "1" *) 
  (* LC_PROBE76_WIDTH = "1" *) 
  (* LC_PROBE770_IS_DATA = "1'b0" *) 
  (* LC_PROBE770_IS_TRIG = "1'b0" *) 
  (* LC_PROBE770_MU_CNT = "1" *) 
  (* LC_PROBE770_PID = "16'b0000001100000010" *) 
  (* LC_PROBE770_TYPE = "1" *) 
  (* LC_PROBE770_WIDTH = "1" *) 
  (* LC_PROBE771_IS_DATA = "1'b0" *) 
  (* LC_PROBE771_IS_TRIG = "1'b0" *) 
  (* LC_PROBE771_MU_CNT = "1" *) 
  (* LC_PROBE771_PID = "16'b0000001100000011" *) 
  (* LC_PROBE771_TYPE = "1" *) 
  (* LC_PROBE771_WIDTH = "1" *) 
  (* LC_PROBE772_IS_DATA = "1'b0" *) 
  (* LC_PROBE772_IS_TRIG = "1'b0" *) 
  (* LC_PROBE772_MU_CNT = "1" *) 
  (* LC_PROBE772_PID = "16'b0000001100000100" *) 
  (* LC_PROBE772_TYPE = "1" *) 
  (* LC_PROBE772_WIDTH = "1" *) 
  (* LC_PROBE773_IS_DATA = "1'b0" *) 
  (* LC_PROBE773_IS_TRIG = "1'b0" *) 
  (* LC_PROBE773_MU_CNT = "1" *) 
  (* LC_PROBE773_PID = "16'b0000001100000101" *) 
  (* LC_PROBE773_TYPE = "1" *) 
  (* LC_PROBE773_WIDTH = "1" *) 
  (* LC_PROBE774_IS_DATA = "1'b0" *) 
  (* LC_PROBE774_IS_TRIG = "1'b0" *) 
  (* LC_PROBE774_MU_CNT = "1" *) 
  (* LC_PROBE774_PID = "16'b0000001100000110" *) 
  (* LC_PROBE774_TYPE = "1" *) 
  (* LC_PROBE774_WIDTH = "1" *) 
  (* LC_PROBE775_IS_DATA = "1'b0" *) 
  (* LC_PROBE775_IS_TRIG = "1'b0" *) 
  (* LC_PROBE775_MU_CNT = "1" *) 
  (* LC_PROBE775_PID = "16'b0000001100000111" *) 
  (* LC_PROBE775_TYPE = "1" *) 
  (* LC_PROBE775_WIDTH = "1" *) 
  (* LC_PROBE776_IS_DATA = "1'b0" *) 
  (* LC_PROBE776_IS_TRIG = "1'b0" *) 
  (* LC_PROBE776_MU_CNT = "1" *) 
  (* LC_PROBE776_PID = "16'b0000001100001000" *) 
  (* LC_PROBE776_TYPE = "1" *) 
  (* LC_PROBE776_WIDTH = "1" *) 
  (* LC_PROBE777_IS_DATA = "1'b0" *) 
  (* LC_PROBE777_IS_TRIG = "1'b0" *) 
  (* LC_PROBE777_MU_CNT = "1" *) 
  (* LC_PROBE777_PID = "16'b0000001100001001" *) 
  (* LC_PROBE777_TYPE = "1" *) 
  (* LC_PROBE777_WIDTH = "1" *) 
  (* LC_PROBE778_IS_DATA = "1'b0" *) 
  (* LC_PROBE778_IS_TRIG = "1'b0" *) 
  (* LC_PROBE778_MU_CNT = "1" *) 
  (* LC_PROBE778_PID = "16'b0000001100001010" *) 
  (* LC_PROBE778_TYPE = "1" *) 
  (* LC_PROBE778_WIDTH = "1" *) 
  (* LC_PROBE779_IS_DATA = "1'b0" *) 
  (* LC_PROBE779_IS_TRIG = "1'b0" *) 
  (* LC_PROBE779_MU_CNT = "1" *) 
  (* LC_PROBE779_PID = "16'b0000001100001011" *) 
  (* LC_PROBE779_TYPE = "1" *) 
  (* LC_PROBE779_WIDTH = "1" *) 
  (* LC_PROBE77_IS_DATA = "1'b0" *) 
  (* LC_PROBE77_IS_TRIG = "1'b0" *) 
  (* LC_PROBE77_MU_CNT = "1" *) 
  (* LC_PROBE77_PID = "16'b0000000001001101" *) 
  (* LC_PROBE77_TYPE = "1" *) 
  (* LC_PROBE77_WIDTH = "1" *) 
  (* LC_PROBE780_IS_DATA = "1'b0" *) 
  (* LC_PROBE780_IS_TRIG = "1'b0" *) 
  (* LC_PROBE780_MU_CNT = "1" *) 
  (* LC_PROBE780_PID = "16'b0000001100001100" *) 
  (* LC_PROBE780_TYPE = "1" *) 
  (* LC_PROBE780_WIDTH = "1" *) 
  (* LC_PROBE781_IS_DATA = "1'b0" *) 
  (* LC_PROBE781_IS_TRIG = "1'b0" *) 
  (* LC_PROBE781_MU_CNT = "1" *) 
  (* LC_PROBE781_PID = "16'b0000001100001101" *) 
  (* LC_PROBE781_TYPE = "1" *) 
  (* LC_PROBE781_WIDTH = "1" *) 
  (* LC_PROBE782_IS_DATA = "1'b0" *) 
  (* LC_PROBE782_IS_TRIG = "1'b0" *) 
  (* LC_PROBE782_MU_CNT = "1" *) 
  (* LC_PROBE782_PID = "16'b0000001100001110" *) 
  (* LC_PROBE782_TYPE = "1" *) 
  (* LC_PROBE782_WIDTH = "1" *) 
  (* LC_PROBE783_IS_DATA = "1'b0" *) 
  (* LC_PROBE783_IS_TRIG = "1'b0" *) 
  (* LC_PROBE783_MU_CNT = "1" *) 
  (* LC_PROBE783_PID = "16'b0000001100001111" *) 
  (* LC_PROBE783_TYPE = "1" *) 
  (* LC_PROBE783_WIDTH = "1" *) 
  (* LC_PROBE784_IS_DATA = "1'b0" *) 
  (* LC_PROBE784_IS_TRIG = "1'b0" *) 
  (* LC_PROBE784_MU_CNT = "1" *) 
  (* LC_PROBE784_PID = "16'b0000001100010000" *) 
  (* LC_PROBE784_TYPE = "1" *) 
  (* LC_PROBE784_WIDTH = "1" *) 
  (* LC_PROBE785_IS_DATA = "1'b0" *) 
  (* LC_PROBE785_IS_TRIG = "1'b0" *) 
  (* LC_PROBE785_MU_CNT = "1" *) 
  (* LC_PROBE785_PID = "16'b0000001100010001" *) 
  (* LC_PROBE785_TYPE = "1" *) 
  (* LC_PROBE785_WIDTH = "1" *) 
  (* LC_PROBE786_IS_DATA = "1'b0" *) 
  (* LC_PROBE786_IS_TRIG = "1'b0" *) 
  (* LC_PROBE786_MU_CNT = "1" *) 
  (* LC_PROBE786_PID = "16'b0000001100010010" *) 
  (* LC_PROBE786_TYPE = "1" *) 
  (* LC_PROBE786_WIDTH = "1" *) 
  (* LC_PROBE787_IS_DATA = "1'b0" *) 
  (* LC_PROBE787_IS_TRIG = "1'b0" *) 
  (* LC_PROBE787_MU_CNT = "1" *) 
  (* LC_PROBE787_PID = "16'b0000001100010011" *) 
  (* LC_PROBE787_TYPE = "1" *) 
  (* LC_PROBE787_WIDTH = "1" *) 
  (* LC_PROBE788_IS_DATA = "1'b0" *) 
  (* LC_PROBE788_IS_TRIG = "1'b0" *) 
  (* LC_PROBE788_MU_CNT = "1" *) 
  (* LC_PROBE788_PID = "16'b0000001100010100" *) 
  (* LC_PROBE788_TYPE = "1" *) 
  (* LC_PROBE788_WIDTH = "1" *) 
  (* LC_PROBE789_IS_DATA = "1'b0" *) 
  (* LC_PROBE789_IS_TRIG = "1'b0" *) 
  (* LC_PROBE789_MU_CNT = "1" *) 
  (* LC_PROBE789_PID = "16'b0000001100010101" *) 
  (* LC_PROBE789_TYPE = "1" *) 
  (* LC_PROBE789_WIDTH = "1" *) 
  (* LC_PROBE78_IS_DATA = "1'b0" *) 
  (* LC_PROBE78_IS_TRIG = "1'b0" *) 
  (* LC_PROBE78_MU_CNT = "1" *) 
  (* LC_PROBE78_PID = "16'b0000000001001110" *) 
  (* LC_PROBE78_TYPE = "1" *) 
  (* LC_PROBE78_WIDTH = "1" *) 
  (* LC_PROBE790_IS_DATA = "1'b0" *) 
  (* LC_PROBE790_IS_TRIG = "1'b0" *) 
  (* LC_PROBE790_MU_CNT = "1" *) 
  (* LC_PROBE790_PID = "16'b0000001100010110" *) 
  (* LC_PROBE790_TYPE = "1" *) 
  (* LC_PROBE790_WIDTH = "1" *) 
  (* LC_PROBE791_IS_DATA = "1'b0" *) 
  (* LC_PROBE791_IS_TRIG = "1'b0" *) 
  (* LC_PROBE791_MU_CNT = "1" *) 
  (* LC_PROBE791_PID = "16'b0000001100010111" *) 
  (* LC_PROBE791_TYPE = "1" *) 
  (* LC_PROBE791_WIDTH = "1" *) 
  (* LC_PROBE792_IS_DATA = "1'b0" *) 
  (* LC_PROBE792_IS_TRIG = "1'b0" *) 
  (* LC_PROBE792_MU_CNT = "1" *) 
  (* LC_PROBE792_PID = "16'b0000001100011000" *) 
  (* LC_PROBE792_TYPE = "1" *) 
  (* LC_PROBE792_WIDTH = "1" *) 
  (* LC_PROBE793_IS_DATA = "1'b0" *) 
  (* LC_PROBE793_IS_TRIG = "1'b0" *) 
  (* LC_PROBE793_MU_CNT = "1" *) 
  (* LC_PROBE793_PID = "16'b0000001100011001" *) 
  (* LC_PROBE793_TYPE = "1" *) 
  (* LC_PROBE793_WIDTH = "1" *) 
  (* LC_PROBE794_IS_DATA = "1'b0" *) 
  (* LC_PROBE794_IS_TRIG = "1'b0" *) 
  (* LC_PROBE794_MU_CNT = "1" *) 
  (* LC_PROBE794_PID = "16'b0000001100011010" *) 
  (* LC_PROBE794_TYPE = "1" *) 
  (* LC_PROBE794_WIDTH = "1" *) 
  (* LC_PROBE795_IS_DATA = "1'b0" *) 
  (* LC_PROBE795_IS_TRIG = "1'b0" *) 
  (* LC_PROBE795_MU_CNT = "1" *) 
  (* LC_PROBE795_PID = "16'b0000001100011011" *) 
  (* LC_PROBE795_TYPE = "1" *) 
  (* LC_PROBE795_WIDTH = "1" *) 
  (* LC_PROBE796_IS_DATA = "1'b0" *) 
  (* LC_PROBE796_IS_TRIG = "1'b0" *) 
  (* LC_PROBE796_MU_CNT = "1" *) 
  (* LC_PROBE796_PID = "16'b0000001100011100" *) 
  (* LC_PROBE796_TYPE = "1" *) 
  (* LC_PROBE796_WIDTH = "1" *) 
  (* LC_PROBE797_IS_DATA = "1'b0" *) 
  (* LC_PROBE797_IS_TRIG = "1'b0" *) 
  (* LC_PROBE797_MU_CNT = "1" *) 
  (* LC_PROBE797_PID = "16'b0000001100011101" *) 
  (* LC_PROBE797_TYPE = "1" *) 
  (* LC_PROBE797_WIDTH = "1" *) 
  (* LC_PROBE798_IS_DATA = "1'b0" *) 
  (* LC_PROBE798_IS_TRIG = "1'b0" *) 
  (* LC_PROBE798_MU_CNT = "1" *) 
  (* LC_PROBE798_PID = "16'b0000001100011110" *) 
  (* LC_PROBE798_TYPE = "1" *) 
  (* LC_PROBE798_WIDTH = "1" *) 
  (* LC_PROBE799_IS_DATA = "1'b0" *) 
  (* LC_PROBE799_IS_TRIG = "1'b0" *) 
  (* LC_PROBE799_MU_CNT = "1" *) 
  (* LC_PROBE799_PID = "16'b0000001100011111" *) 
  (* LC_PROBE799_TYPE = "1" *) 
  (* LC_PROBE799_WIDTH = "1" *) 
  (* LC_PROBE79_IS_DATA = "1'b0" *) 
  (* LC_PROBE79_IS_TRIG = "1'b0" *) 
  (* LC_PROBE79_MU_CNT = "1" *) 
  (* LC_PROBE79_PID = "16'b0000000001001111" *) 
  (* LC_PROBE79_TYPE = "1" *) 
  (* LC_PROBE79_WIDTH = "1" *) 
  (* LC_PROBE7_IS_DATA = "1'b0" *) 
  (* LC_PROBE7_IS_TRIG = "1'b0" *) 
  (* LC_PROBE7_MU_CNT = "1" *) 
  (* LC_PROBE7_PID = "16'b0000000000000111" *) 
  (* LC_PROBE7_TYPE = "1" *) 
  (* LC_PROBE7_WIDTH = "1" *) 
  (* LC_PROBE800_IS_DATA = "1'b0" *) 
  (* LC_PROBE800_IS_TRIG = "1'b0" *) 
  (* LC_PROBE800_MU_CNT = "1" *) 
  (* LC_PROBE800_PID = "16'b0000001100100000" *) 
  (* LC_PROBE800_TYPE = "1" *) 
  (* LC_PROBE800_WIDTH = "1" *) 
  (* LC_PROBE801_IS_DATA = "1'b0" *) 
  (* LC_PROBE801_IS_TRIG = "1'b0" *) 
  (* LC_PROBE801_MU_CNT = "1" *) 
  (* LC_PROBE801_PID = "16'b0000001100100001" *) 
  (* LC_PROBE801_TYPE = "1" *) 
  (* LC_PROBE801_WIDTH = "1" *) 
  (* LC_PROBE802_IS_DATA = "1'b0" *) 
  (* LC_PROBE802_IS_TRIG = "1'b0" *) 
  (* LC_PROBE802_MU_CNT = "1" *) 
  (* LC_PROBE802_PID = "16'b0000001100100010" *) 
  (* LC_PROBE802_TYPE = "1" *) 
  (* LC_PROBE802_WIDTH = "1" *) 
  (* LC_PROBE803_IS_DATA = "1'b0" *) 
  (* LC_PROBE803_IS_TRIG = "1'b0" *) 
  (* LC_PROBE803_MU_CNT = "1" *) 
  (* LC_PROBE803_PID = "16'b0000001100100011" *) 
  (* LC_PROBE803_TYPE = "1" *) 
  (* LC_PROBE803_WIDTH = "1" *) 
  (* LC_PROBE804_IS_DATA = "1'b0" *) 
  (* LC_PROBE804_IS_TRIG = "1'b0" *) 
  (* LC_PROBE804_MU_CNT = "1" *) 
  (* LC_PROBE804_PID = "16'b0000001100100100" *) 
  (* LC_PROBE804_TYPE = "1" *) 
  (* LC_PROBE804_WIDTH = "1" *) 
  (* LC_PROBE805_IS_DATA = "1'b0" *) 
  (* LC_PROBE805_IS_TRIG = "1'b0" *) 
  (* LC_PROBE805_MU_CNT = "1" *) 
  (* LC_PROBE805_PID = "16'b0000001100100101" *) 
  (* LC_PROBE805_TYPE = "1" *) 
  (* LC_PROBE805_WIDTH = "1" *) 
  (* LC_PROBE806_IS_DATA = "1'b0" *) 
  (* LC_PROBE806_IS_TRIG = "1'b0" *) 
  (* LC_PROBE806_MU_CNT = "1" *) 
  (* LC_PROBE806_PID = "16'b0000001100100110" *) 
  (* LC_PROBE806_TYPE = "1" *) 
  (* LC_PROBE806_WIDTH = "1" *) 
  (* LC_PROBE807_IS_DATA = "1'b0" *) 
  (* LC_PROBE807_IS_TRIG = "1'b0" *) 
  (* LC_PROBE807_MU_CNT = "1" *) 
  (* LC_PROBE807_PID = "16'b0000001100100111" *) 
  (* LC_PROBE807_TYPE = "1" *) 
  (* LC_PROBE807_WIDTH = "1" *) 
  (* LC_PROBE808_IS_DATA = "1'b0" *) 
  (* LC_PROBE808_IS_TRIG = "1'b0" *) 
  (* LC_PROBE808_MU_CNT = "1" *) 
  (* LC_PROBE808_PID = "16'b0000001100101000" *) 
  (* LC_PROBE808_TYPE = "1" *) 
  (* LC_PROBE808_WIDTH = "1" *) 
  (* LC_PROBE809_IS_DATA = "1'b0" *) 
  (* LC_PROBE809_IS_TRIG = "1'b0" *) 
  (* LC_PROBE809_MU_CNT = "1" *) 
  (* LC_PROBE809_PID = "16'b0000001100101001" *) 
  (* LC_PROBE809_TYPE = "1" *) 
  (* LC_PROBE809_WIDTH = "1" *) 
  (* LC_PROBE80_IS_DATA = "1'b0" *) 
  (* LC_PROBE80_IS_TRIG = "1'b0" *) 
  (* LC_PROBE80_MU_CNT = "1" *) 
  (* LC_PROBE80_PID = "16'b0000000001010000" *) 
  (* LC_PROBE80_TYPE = "1" *) 
  (* LC_PROBE80_WIDTH = "1" *) 
  (* LC_PROBE810_IS_DATA = "1'b0" *) 
  (* LC_PROBE810_IS_TRIG = "1'b0" *) 
  (* LC_PROBE810_MU_CNT = "1" *) 
  (* LC_PROBE810_PID = "16'b0000001100101010" *) 
  (* LC_PROBE810_TYPE = "1" *) 
  (* LC_PROBE810_WIDTH = "1" *) 
  (* LC_PROBE811_IS_DATA = "1'b0" *) 
  (* LC_PROBE811_IS_TRIG = "1'b0" *) 
  (* LC_PROBE811_MU_CNT = "1" *) 
  (* LC_PROBE811_PID = "16'b0000001100101011" *) 
  (* LC_PROBE811_TYPE = "1" *) 
  (* LC_PROBE811_WIDTH = "1" *) 
  (* LC_PROBE812_IS_DATA = "1'b0" *) 
  (* LC_PROBE812_IS_TRIG = "1'b0" *) 
  (* LC_PROBE812_MU_CNT = "1" *) 
  (* LC_PROBE812_PID = "16'b0000001100101100" *) 
  (* LC_PROBE812_TYPE = "1" *) 
  (* LC_PROBE812_WIDTH = "1" *) 
  (* LC_PROBE813_IS_DATA = "1'b0" *) 
  (* LC_PROBE813_IS_TRIG = "1'b0" *) 
  (* LC_PROBE813_MU_CNT = "1" *) 
  (* LC_PROBE813_PID = "16'b0000001100101101" *) 
  (* LC_PROBE813_TYPE = "1" *) 
  (* LC_PROBE813_WIDTH = "1" *) 
  (* LC_PROBE814_IS_DATA = "1'b0" *) 
  (* LC_PROBE814_IS_TRIG = "1'b0" *) 
  (* LC_PROBE814_MU_CNT = "1" *) 
  (* LC_PROBE814_PID = "16'b0000001100101110" *) 
  (* LC_PROBE814_TYPE = "1" *) 
  (* LC_PROBE814_WIDTH = "1" *) 
  (* LC_PROBE815_IS_DATA = "1'b0" *) 
  (* LC_PROBE815_IS_TRIG = "1'b0" *) 
  (* LC_PROBE815_MU_CNT = "1" *) 
  (* LC_PROBE815_PID = "16'b0000001100101111" *) 
  (* LC_PROBE815_TYPE = "1" *) 
  (* LC_PROBE815_WIDTH = "1" *) 
  (* LC_PROBE816_IS_DATA = "1'b0" *) 
  (* LC_PROBE816_IS_TRIG = "1'b0" *) 
  (* LC_PROBE816_MU_CNT = "1" *) 
  (* LC_PROBE816_PID = "16'b0000001100110000" *) 
  (* LC_PROBE816_TYPE = "1" *) 
  (* LC_PROBE816_WIDTH = "1" *) 
  (* LC_PROBE817_IS_DATA = "1'b0" *) 
  (* LC_PROBE817_IS_TRIG = "1'b0" *) 
  (* LC_PROBE817_MU_CNT = "1" *) 
  (* LC_PROBE817_PID = "16'b0000001100110001" *) 
  (* LC_PROBE817_TYPE = "1" *) 
  (* LC_PROBE817_WIDTH = "1" *) 
  (* LC_PROBE818_IS_DATA = "1'b0" *) 
  (* LC_PROBE818_IS_TRIG = "1'b0" *) 
  (* LC_PROBE818_MU_CNT = "1" *) 
  (* LC_PROBE818_PID = "16'b0000001100110010" *) 
  (* LC_PROBE818_TYPE = "1" *) 
  (* LC_PROBE818_WIDTH = "1" *) 
  (* LC_PROBE819_IS_DATA = "1'b0" *) 
  (* LC_PROBE819_IS_TRIG = "1'b0" *) 
  (* LC_PROBE819_MU_CNT = "1" *) 
  (* LC_PROBE819_PID = "16'b0000001100110011" *) 
  (* LC_PROBE819_TYPE = "1" *) 
  (* LC_PROBE819_WIDTH = "1" *) 
  (* LC_PROBE81_IS_DATA = "1'b0" *) 
  (* LC_PROBE81_IS_TRIG = "1'b0" *) 
  (* LC_PROBE81_MU_CNT = "1" *) 
  (* LC_PROBE81_PID = "16'b0000000001010001" *) 
  (* LC_PROBE81_TYPE = "1" *) 
  (* LC_PROBE81_WIDTH = "1" *) 
  (* LC_PROBE820_IS_DATA = "1'b0" *) 
  (* LC_PROBE820_IS_TRIG = "1'b0" *) 
  (* LC_PROBE820_MU_CNT = "1" *) 
  (* LC_PROBE820_PID = "16'b0000001100110100" *) 
  (* LC_PROBE820_TYPE = "1" *) 
  (* LC_PROBE820_WIDTH = "1" *) 
  (* LC_PROBE821_IS_DATA = "1'b0" *) 
  (* LC_PROBE821_IS_TRIG = "1'b0" *) 
  (* LC_PROBE821_MU_CNT = "1" *) 
  (* LC_PROBE821_PID = "16'b0000001100110101" *) 
  (* LC_PROBE821_TYPE = "1" *) 
  (* LC_PROBE821_WIDTH = "1" *) 
  (* LC_PROBE822_IS_DATA = "1'b0" *) 
  (* LC_PROBE822_IS_TRIG = "1'b0" *) 
  (* LC_PROBE822_MU_CNT = "1" *) 
  (* LC_PROBE822_PID = "16'b0000001100110110" *) 
  (* LC_PROBE822_TYPE = "1" *) 
  (* LC_PROBE822_WIDTH = "1" *) 
  (* LC_PROBE823_IS_DATA = "1'b0" *) 
  (* LC_PROBE823_IS_TRIG = "1'b0" *) 
  (* LC_PROBE823_MU_CNT = "1" *) 
  (* LC_PROBE823_PID = "16'b0000001100110111" *) 
  (* LC_PROBE823_TYPE = "1" *) 
  (* LC_PROBE823_WIDTH = "1" *) 
  (* LC_PROBE824_IS_DATA = "1'b0" *) 
  (* LC_PROBE824_IS_TRIG = "1'b0" *) 
  (* LC_PROBE824_MU_CNT = "1" *) 
  (* LC_PROBE824_PID = "16'b0000001100111000" *) 
  (* LC_PROBE824_TYPE = "1" *) 
  (* LC_PROBE824_WIDTH = "1" *) 
  (* LC_PROBE825_IS_DATA = "1'b0" *) 
  (* LC_PROBE825_IS_TRIG = "1'b0" *) 
  (* LC_PROBE825_MU_CNT = "1" *) 
  (* LC_PROBE825_PID = "16'b0000001100111001" *) 
  (* LC_PROBE825_TYPE = "1" *) 
  (* LC_PROBE825_WIDTH = "1" *) 
  (* LC_PROBE826_IS_DATA = "1'b0" *) 
  (* LC_PROBE826_IS_TRIG = "1'b0" *) 
  (* LC_PROBE826_MU_CNT = "1" *) 
  (* LC_PROBE826_PID = "16'b0000001100111010" *) 
  (* LC_PROBE826_TYPE = "1" *) 
  (* LC_PROBE826_WIDTH = "1" *) 
  (* LC_PROBE827_IS_DATA = "1'b0" *) 
  (* LC_PROBE827_IS_TRIG = "1'b0" *) 
  (* LC_PROBE827_MU_CNT = "1" *) 
  (* LC_PROBE827_PID = "16'b0000001100111011" *) 
  (* LC_PROBE827_TYPE = "1" *) 
  (* LC_PROBE827_WIDTH = "1" *) 
  (* LC_PROBE828_IS_DATA = "1'b0" *) 
  (* LC_PROBE828_IS_TRIG = "1'b0" *) 
  (* LC_PROBE828_MU_CNT = "1" *) 
  (* LC_PROBE828_PID = "16'b0000001100111100" *) 
  (* LC_PROBE828_TYPE = "1" *) 
  (* LC_PROBE828_WIDTH = "1" *) 
  (* LC_PROBE829_IS_DATA = "1'b0" *) 
  (* LC_PROBE829_IS_TRIG = "1'b0" *) 
  (* LC_PROBE829_MU_CNT = "1" *) 
  (* LC_PROBE829_PID = "16'b0000001100111101" *) 
  (* LC_PROBE829_TYPE = "1" *) 
  (* LC_PROBE829_WIDTH = "1" *) 
  (* LC_PROBE82_IS_DATA = "1'b0" *) 
  (* LC_PROBE82_IS_TRIG = "1'b0" *) 
  (* LC_PROBE82_MU_CNT = "1" *) 
  (* LC_PROBE82_PID = "16'b0000000001010010" *) 
  (* LC_PROBE82_TYPE = "1" *) 
  (* LC_PROBE82_WIDTH = "1" *) 
  (* LC_PROBE830_IS_DATA = "1'b0" *) 
  (* LC_PROBE830_IS_TRIG = "1'b0" *) 
  (* LC_PROBE830_MU_CNT = "1" *) 
  (* LC_PROBE830_PID = "16'b0000001100111110" *) 
  (* LC_PROBE830_TYPE = "1" *) 
  (* LC_PROBE830_WIDTH = "1" *) 
  (* LC_PROBE831_IS_DATA = "1'b0" *) 
  (* LC_PROBE831_IS_TRIG = "1'b0" *) 
  (* LC_PROBE831_MU_CNT = "1" *) 
  (* LC_PROBE831_PID = "16'b0000001100111111" *) 
  (* LC_PROBE831_TYPE = "1" *) 
  (* LC_PROBE831_WIDTH = "1" *) 
  (* LC_PROBE832_IS_DATA = "1'b0" *) 
  (* LC_PROBE832_IS_TRIG = "1'b0" *) 
  (* LC_PROBE832_MU_CNT = "1" *) 
  (* LC_PROBE832_PID = "16'b0000001101000000" *) 
  (* LC_PROBE832_TYPE = "1" *) 
  (* LC_PROBE832_WIDTH = "1" *) 
  (* LC_PROBE833_IS_DATA = "1'b0" *) 
  (* LC_PROBE833_IS_TRIG = "1'b0" *) 
  (* LC_PROBE833_MU_CNT = "1" *) 
  (* LC_PROBE833_PID = "16'b0000001101000001" *) 
  (* LC_PROBE833_TYPE = "1" *) 
  (* LC_PROBE833_WIDTH = "1" *) 
  (* LC_PROBE834_IS_DATA = "1'b0" *) 
  (* LC_PROBE834_IS_TRIG = "1'b0" *) 
  (* LC_PROBE834_MU_CNT = "1" *) 
  (* LC_PROBE834_PID = "16'b0000001101000010" *) 
  (* LC_PROBE834_TYPE = "1" *) 
  (* LC_PROBE834_WIDTH = "1" *) 
  (* LC_PROBE835_IS_DATA = "1'b0" *) 
  (* LC_PROBE835_IS_TRIG = "1'b0" *) 
  (* LC_PROBE835_MU_CNT = "1" *) 
  (* LC_PROBE835_PID = "16'b0000001101000011" *) 
  (* LC_PROBE835_TYPE = "1" *) 
  (* LC_PROBE835_WIDTH = "1" *) 
  (* LC_PROBE836_IS_DATA = "1'b0" *) 
  (* LC_PROBE836_IS_TRIG = "1'b0" *) 
  (* LC_PROBE836_MU_CNT = "1" *) 
  (* LC_PROBE836_PID = "16'b0000001101000100" *) 
  (* LC_PROBE836_TYPE = "1" *) 
  (* LC_PROBE836_WIDTH = "1" *) 
  (* LC_PROBE837_IS_DATA = "1'b0" *) 
  (* LC_PROBE837_IS_TRIG = "1'b0" *) 
  (* LC_PROBE837_MU_CNT = "1" *) 
  (* LC_PROBE837_PID = "16'b0000001101000101" *) 
  (* LC_PROBE837_TYPE = "1" *) 
  (* LC_PROBE837_WIDTH = "1" *) 
  (* LC_PROBE838_IS_DATA = "1'b0" *) 
  (* LC_PROBE838_IS_TRIG = "1'b0" *) 
  (* LC_PROBE838_MU_CNT = "1" *) 
  (* LC_PROBE838_PID = "16'b0000001101000110" *) 
  (* LC_PROBE838_TYPE = "1" *) 
  (* LC_PROBE838_WIDTH = "1" *) 
  (* LC_PROBE839_IS_DATA = "1'b0" *) 
  (* LC_PROBE839_IS_TRIG = "1'b0" *) 
  (* LC_PROBE839_MU_CNT = "1" *) 
  (* LC_PROBE839_PID = "16'b0000001101000111" *) 
  (* LC_PROBE839_TYPE = "1" *) 
  (* LC_PROBE839_WIDTH = "1" *) 
  (* LC_PROBE83_IS_DATA = "1'b0" *) 
  (* LC_PROBE83_IS_TRIG = "1'b0" *) 
  (* LC_PROBE83_MU_CNT = "1" *) 
  (* LC_PROBE83_PID = "16'b0000000001010011" *) 
  (* LC_PROBE83_TYPE = "1" *) 
  (* LC_PROBE83_WIDTH = "1" *) 
  (* LC_PROBE840_IS_DATA = "1'b0" *) 
  (* LC_PROBE840_IS_TRIG = "1'b0" *) 
  (* LC_PROBE840_MU_CNT = "1" *) 
  (* LC_PROBE840_PID = "16'b0000001101001000" *) 
  (* LC_PROBE840_TYPE = "1" *) 
  (* LC_PROBE840_WIDTH = "1" *) 
  (* LC_PROBE841_IS_DATA = "1'b0" *) 
  (* LC_PROBE841_IS_TRIG = "1'b0" *) 
  (* LC_PROBE841_MU_CNT = "1" *) 
  (* LC_PROBE841_PID = "16'b0000001101001001" *) 
  (* LC_PROBE841_TYPE = "1" *) 
  (* LC_PROBE841_WIDTH = "1" *) 
  (* LC_PROBE842_IS_DATA = "1'b0" *) 
  (* LC_PROBE842_IS_TRIG = "1'b0" *) 
  (* LC_PROBE842_MU_CNT = "1" *) 
  (* LC_PROBE842_PID = "16'b0000001101001010" *) 
  (* LC_PROBE842_TYPE = "1" *) 
  (* LC_PROBE842_WIDTH = "1" *) 
  (* LC_PROBE843_IS_DATA = "1'b0" *) 
  (* LC_PROBE843_IS_TRIG = "1'b0" *) 
  (* LC_PROBE843_MU_CNT = "1" *) 
  (* LC_PROBE843_PID = "16'b0000001101001011" *) 
  (* LC_PROBE843_TYPE = "1" *) 
  (* LC_PROBE843_WIDTH = "1" *) 
  (* LC_PROBE844_IS_DATA = "1'b0" *) 
  (* LC_PROBE844_IS_TRIG = "1'b0" *) 
  (* LC_PROBE844_MU_CNT = "1" *) 
  (* LC_PROBE844_PID = "16'b0000001101001100" *) 
  (* LC_PROBE844_TYPE = "1" *) 
  (* LC_PROBE844_WIDTH = "1" *) 
  (* LC_PROBE845_IS_DATA = "1'b0" *) 
  (* LC_PROBE845_IS_TRIG = "1'b0" *) 
  (* LC_PROBE845_MU_CNT = "1" *) 
  (* LC_PROBE845_PID = "16'b0000001101001101" *) 
  (* LC_PROBE845_TYPE = "1" *) 
  (* LC_PROBE845_WIDTH = "1" *) 
  (* LC_PROBE846_IS_DATA = "1'b0" *) 
  (* LC_PROBE846_IS_TRIG = "1'b0" *) 
  (* LC_PROBE846_MU_CNT = "1" *) 
  (* LC_PROBE846_PID = "16'b0000001101001110" *) 
  (* LC_PROBE846_TYPE = "1" *) 
  (* LC_PROBE846_WIDTH = "1" *) 
  (* LC_PROBE847_IS_DATA = "1'b0" *) 
  (* LC_PROBE847_IS_TRIG = "1'b0" *) 
  (* LC_PROBE847_MU_CNT = "1" *) 
  (* LC_PROBE847_PID = "16'b0000001101001111" *) 
  (* LC_PROBE847_TYPE = "1" *) 
  (* LC_PROBE847_WIDTH = "1" *) 
  (* LC_PROBE848_IS_DATA = "1'b0" *) 
  (* LC_PROBE848_IS_TRIG = "1'b0" *) 
  (* LC_PROBE848_MU_CNT = "1" *) 
  (* LC_PROBE848_PID = "16'b0000001101010000" *) 
  (* LC_PROBE848_TYPE = "1" *) 
  (* LC_PROBE848_WIDTH = "1" *) 
  (* LC_PROBE849_IS_DATA = "1'b0" *) 
  (* LC_PROBE849_IS_TRIG = "1'b0" *) 
  (* LC_PROBE849_MU_CNT = "1" *) 
  (* LC_PROBE849_PID = "16'b0000001101010001" *) 
  (* LC_PROBE849_TYPE = "1" *) 
  (* LC_PROBE849_WIDTH = "1" *) 
  (* LC_PROBE84_IS_DATA = "1'b0" *) 
  (* LC_PROBE84_IS_TRIG = "1'b0" *) 
  (* LC_PROBE84_MU_CNT = "1" *) 
  (* LC_PROBE84_PID = "16'b0000000001010100" *) 
  (* LC_PROBE84_TYPE = "1" *) 
  (* LC_PROBE84_WIDTH = "1" *) 
  (* LC_PROBE850_IS_DATA = "1'b0" *) 
  (* LC_PROBE850_IS_TRIG = "1'b0" *) 
  (* LC_PROBE850_MU_CNT = "1" *) 
  (* LC_PROBE850_PID = "16'b0000001101010010" *) 
  (* LC_PROBE850_TYPE = "1" *) 
  (* LC_PROBE850_WIDTH = "1" *) 
  (* LC_PROBE851_IS_DATA = "1'b0" *) 
  (* LC_PROBE851_IS_TRIG = "1'b0" *) 
  (* LC_PROBE851_MU_CNT = "1" *) 
  (* LC_PROBE851_PID = "16'b0000001101010011" *) 
  (* LC_PROBE851_TYPE = "1" *) 
  (* LC_PROBE851_WIDTH = "1" *) 
  (* LC_PROBE852_IS_DATA = "1'b0" *) 
  (* LC_PROBE852_IS_TRIG = "1'b0" *) 
  (* LC_PROBE852_MU_CNT = "1" *) 
  (* LC_PROBE852_PID = "16'b0000001101010100" *) 
  (* LC_PROBE852_TYPE = "1" *) 
  (* LC_PROBE852_WIDTH = "1" *) 
  (* LC_PROBE853_IS_DATA = "1'b0" *) 
  (* LC_PROBE853_IS_TRIG = "1'b0" *) 
  (* LC_PROBE853_MU_CNT = "1" *) 
  (* LC_PROBE853_PID = "16'b0000001101010101" *) 
  (* LC_PROBE853_TYPE = "1" *) 
  (* LC_PROBE853_WIDTH = "1" *) 
  (* LC_PROBE854_IS_DATA = "1'b0" *) 
  (* LC_PROBE854_IS_TRIG = "1'b0" *) 
  (* LC_PROBE854_MU_CNT = "1" *) 
  (* LC_PROBE854_PID = "16'b0000001101010110" *) 
  (* LC_PROBE854_TYPE = "1" *) 
  (* LC_PROBE854_WIDTH = "1" *) 
  (* LC_PROBE855_IS_DATA = "1'b0" *) 
  (* LC_PROBE855_IS_TRIG = "1'b0" *) 
  (* LC_PROBE855_MU_CNT = "1" *) 
  (* LC_PROBE855_PID = "16'b0000001101010111" *) 
  (* LC_PROBE855_TYPE = "1" *) 
  (* LC_PROBE855_WIDTH = "1" *) 
  (* LC_PROBE856_IS_DATA = "1'b0" *) 
  (* LC_PROBE856_IS_TRIG = "1'b0" *) 
  (* LC_PROBE856_MU_CNT = "1" *) 
  (* LC_PROBE856_PID = "16'b0000001101011000" *) 
  (* LC_PROBE856_TYPE = "1" *) 
  (* LC_PROBE856_WIDTH = "1" *) 
  (* LC_PROBE857_IS_DATA = "1'b0" *) 
  (* LC_PROBE857_IS_TRIG = "1'b0" *) 
  (* LC_PROBE857_MU_CNT = "1" *) 
  (* LC_PROBE857_PID = "16'b0000001101011001" *) 
  (* LC_PROBE857_TYPE = "1" *) 
  (* LC_PROBE857_WIDTH = "1" *) 
  (* LC_PROBE858_IS_DATA = "1'b0" *) 
  (* LC_PROBE858_IS_TRIG = "1'b0" *) 
  (* LC_PROBE858_MU_CNT = "1" *) 
  (* LC_PROBE858_PID = "16'b0000001101011010" *) 
  (* LC_PROBE858_TYPE = "1" *) 
  (* LC_PROBE858_WIDTH = "1" *) 
  (* LC_PROBE859_IS_DATA = "1'b0" *) 
  (* LC_PROBE859_IS_TRIG = "1'b0" *) 
  (* LC_PROBE859_MU_CNT = "1" *) 
  (* LC_PROBE859_PID = "16'b0000001101011011" *) 
  (* LC_PROBE859_TYPE = "1" *) 
  (* LC_PROBE859_WIDTH = "1" *) 
  (* LC_PROBE85_IS_DATA = "1'b0" *) 
  (* LC_PROBE85_IS_TRIG = "1'b0" *) 
  (* LC_PROBE85_MU_CNT = "1" *) 
  (* LC_PROBE85_PID = "16'b0000000001010101" *) 
  (* LC_PROBE85_TYPE = "1" *) 
  (* LC_PROBE85_WIDTH = "1" *) 
  (* LC_PROBE860_IS_DATA = "1'b0" *) 
  (* LC_PROBE860_IS_TRIG = "1'b0" *) 
  (* LC_PROBE860_MU_CNT = "1" *) 
  (* LC_PROBE860_PID = "16'b0000001101011100" *) 
  (* LC_PROBE860_TYPE = "1" *) 
  (* LC_PROBE860_WIDTH = "1" *) 
  (* LC_PROBE861_IS_DATA = "1'b0" *) 
  (* LC_PROBE861_IS_TRIG = "1'b0" *) 
  (* LC_PROBE861_MU_CNT = "1" *) 
  (* LC_PROBE861_PID = "16'b0000001101011101" *) 
  (* LC_PROBE861_TYPE = "1" *) 
  (* LC_PROBE861_WIDTH = "1" *) 
  (* LC_PROBE862_IS_DATA = "1'b0" *) 
  (* LC_PROBE862_IS_TRIG = "1'b0" *) 
  (* LC_PROBE862_MU_CNT = "1" *) 
  (* LC_PROBE862_PID = "16'b0000001101011110" *) 
  (* LC_PROBE862_TYPE = "1" *) 
  (* LC_PROBE862_WIDTH = "1" *) 
  (* LC_PROBE863_IS_DATA = "1'b0" *) 
  (* LC_PROBE863_IS_TRIG = "1'b0" *) 
  (* LC_PROBE863_MU_CNT = "1" *) 
  (* LC_PROBE863_PID = "16'b0000001101011111" *) 
  (* LC_PROBE863_TYPE = "1" *) 
  (* LC_PROBE863_WIDTH = "1" *) 
  (* LC_PROBE864_IS_DATA = "1'b0" *) 
  (* LC_PROBE864_IS_TRIG = "1'b0" *) 
  (* LC_PROBE864_MU_CNT = "1" *) 
  (* LC_PROBE864_PID = "16'b0000001101100000" *) 
  (* LC_PROBE864_TYPE = "1" *) 
  (* LC_PROBE864_WIDTH = "1" *) 
  (* LC_PROBE865_IS_DATA = "1'b0" *) 
  (* LC_PROBE865_IS_TRIG = "1'b0" *) 
  (* LC_PROBE865_MU_CNT = "1" *) 
  (* LC_PROBE865_PID = "16'b0000001101100001" *) 
  (* LC_PROBE865_TYPE = "1" *) 
  (* LC_PROBE865_WIDTH = "1" *) 
  (* LC_PROBE866_IS_DATA = "1'b0" *) 
  (* LC_PROBE866_IS_TRIG = "1'b0" *) 
  (* LC_PROBE866_MU_CNT = "1" *) 
  (* LC_PROBE866_PID = "16'b0000001101100010" *) 
  (* LC_PROBE866_TYPE = "1" *) 
  (* LC_PROBE866_WIDTH = "1" *) 
  (* LC_PROBE867_IS_DATA = "1'b0" *) 
  (* LC_PROBE867_IS_TRIG = "1'b0" *) 
  (* LC_PROBE867_MU_CNT = "1" *) 
  (* LC_PROBE867_PID = "16'b0000001101100011" *) 
  (* LC_PROBE867_TYPE = "1" *) 
  (* LC_PROBE867_WIDTH = "1" *) 
  (* LC_PROBE868_IS_DATA = "1'b0" *) 
  (* LC_PROBE868_IS_TRIG = "1'b0" *) 
  (* LC_PROBE868_MU_CNT = "1" *) 
  (* LC_PROBE868_PID = "16'b0000001101100100" *) 
  (* LC_PROBE868_TYPE = "1" *) 
  (* LC_PROBE868_WIDTH = "1" *) 
  (* LC_PROBE869_IS_DATA = "1'b0" *) 
  (* LC_PROBE869_IS_TRIG = "1'b0" *) 
  (* LC_PROBE869_MU_CNT = "1" *) 
  (* LC_PROBE869_PID = "16'b0000001101100101" *) 
  (* LC_PROBE869_TYPE = "1" *) 
  (* LC_PROBE869_WIDTH = "1" *) 
  (* LC_PROBE86_IS_DATA = "1'b0" *) 
  (* LC_PROBE86_IS_TRIG = "1'b0" *) 
  (* LC_PROBE86_MU_CNT = "1" *) 
  (* LC_PROBE86_PID = "16'b0000000001010110" *) 
  (* LC_PROBE86_TYPE = "1" *) 
  (* LC_PROBE86_WIDTH = "1" *) 
  (* LC_PROBE870_IS_DATA = "1'b0" *) 
  (* LC_PROBE870_IS_TRIG = "1'b0" *) 
  (* LC_PROBE870_MU_CNT = "1" *) 
  (* LC_PROBE870_PID = "16'b0000001101100110" *) 
  (* LC_PROBE870_TYPE = "1" *) 
  (* LC_PROBE870_WIDTH = "1" *) 
  (* LC_PROBE871_IS_DATA = "1'b0" *) 
  (* LC_PROBE871_IS_TRIG = "1'b0" *) 
  (* LC_PROBE871_MU_CNT = "1" *) 
  (* LC_PROBE871_PID = "16'b0000001101100111" *) 
  (* LC_PROBE871_TYPE = "1" *) 
  (* LC_PROBE871_WIDTH = "1" *) 
  (* LC_PROBE872_IS_DATA = "1'b0" *) 
  (* LC_PROBE872_IS_TRIG = "1'b0" *) 
  (* LC_PROBE872_MU_CNT = "1" *) 
  (* LC_PROBE872_PID = "16'b0000001101101000" *) 
  (* LC_PROBE872_TYPE = "1" *) 
  (* LC_PROBE872_WIDTH = "1" *) 
  (* LC_PROBE873_IS_DATA = "1'b0" *) 
  (* LC_PROBE873_IS_TRIG = "1'b0" *) 
  (* LC_PROBE873_MU_CNT = "1" *) 
  (* LC_PROBE873_PID = "16'b0000001101101001" *) 
  (* LC_PROBE873_TYPE = "1" *) 
  (* LC_PROBE873_WIDTH = "1" *) 
  (* LC_PROBE874_IS_DATA = "1'b0" *) 
  (* LC_PROBE874_IS_TRIG = "1'b0" *) 
  (* LC_PROBE874_MU_CNT = "1" *) 
  (* LC_PROBE874_PID = "16'b0000001101101010" *) 
  (* LC_PROBE874_TYPE = "1" *) 
  (* LC_PROBE874_WIDTH = "1" *) 
  (* LC_PROBE875_IS_DATA = "1'b0" *) 
  (* LC_PROBE875_IS_TRIG = "1'b0" *) 
  (* LC_PROBE875_MU_CNT = "1" *) 
  (* LC_PROBE875_PID = "16'b0000001101101011" *) 
  (* LC_PROBE875_TYPE = "1" *) 
  (* LC_PROBE875_WIDTH = "1" *) 
  (* LC_PROBE876_IS_DATA = "1'b0" *) 
  (* LC_PROBE876_IS_TRIG = "1'b0" *) 
  (* LC_PROBE876_MU_CNT = "1" *) 
  (* LC_PROBE876_PID = "16'b0000001101101100" *) 
  (* LC_PROBE876_TYPE = "1" *) 
  (* LC_PROBE876_WIDTH = "1" *) 
  (* LC_PROBE877_IS_DATA = "1'b0" *) 
  (* LC_PROBE877_IS_TRIG = "1'b0" *) 
  (* LC_PROBE877_MU_CNT = "1" *) 
  (* LC_PROBE877_PID = "16'b0000001101101101" *) 
  (* LC_PROBE877_TYPE = "1" *) 
  (* LC_PROBE877_WIDTH = "1" *) 
  (* LC_PROBE878_IS_DATA = "1'b0" *) 
  (* LC_PROBE878_IS_TRIG = "1'b0" *) 
  (* LC_PROBE878_MU_CNT = "1" *) 
  (* LC_PROBE878_PID = "16'b0000001101101110" *) 
  (* LC_PROBE878_TYPE = "1" *) 
  (* LC_PROBE878_WIDTH = "1" *) 
  (* LC_PROBE879_IS_DATA = "1'b0" *) 
  (* LC_PROBE879_IS_TRIG = "1'b0" *) 
  (* LC_PROBE879_MU_CNT = "1" *) 
  (* LC_PROBE879_PID = "16'b0000001101101111" *) 
  (* LC_PROBE879_TYPE = "1" *) 
  (* LC_PROBE879_WIDTH = "1" *) 
  (* LC_PROBE87_IS_DATA = "1'b0" *) 
  (* LC_PROBE87_IS_TRIG = "1'b0" *) 
  (* LC_PROBE87_MU_CNT = "1" *) 
  (* LC_PROBE87_PID = "16'b0000000001010111" *) 
  (* LC_PROBE87_TYPE = "1" *) 
  (* LC_PROBE87_WIDTH = "1" *) 
  (* LC_PROBE880_IS_DATA = "1'b0" *) 
  (* LC_PROBE880_IS_TRIG = "1'b0" *) 
  (* LC_PROBE880_MU_CNT = "1" *) 
  (* LC_PROBE880_PID = "16'b0000001101110000" *) 
  (* LC_PROBE880_TYPE = "1" *) 
  (* LC_PROBE880_WIDTH = "1" *) 
  (* LC_PROBE881_IS_DATA = "1'b0" *) 
  (* LC_PROBE881_IS_TRIG = "1'b0" *) 
  (* LC_PROBE881_MU_CNT = "1" *) 
  (* LC_PROBE881_PID = "16'b0000001101110001" *) 
  (* LC_PROBE881_TYPE = "1" *) 
  (* LC_PROBE881_WIDTH = "1" *) 
  (* LC_PROBE882_IS_DATA = "1'b0" *) 
  (* LC_PROBE882_IS_TRIG = "1'b0" *) 
  (* LC_PROBE882_MU_CNT = "1" *) 
  (* LC_PROBE882_PID = "16'b0000001101110010" *) 
  (* LC_PROBE882_TYPE = "1" *) 
  (* LC_PROBE882_WIDTH = "1" *) 
  (* LC_PROBE883_IS_DATA = "1'b0" *) 
  (* LC_PROBE883_IS_TRIG = "1'b0" *) 
  (* LC_PROBE883_MU_CNT = "1" *) 
  (* LC_PROBE883_PID = "16'b0000001101110011" *) 
  (* LC_PROBE883_TYPE = "1" *) 
  (* LC_PROBE883_WIDTH = "1" *) 
  (* LC_PROBE884_IS_DATA = "1'b0" *) 
  (* LC_PROBE884_IS_TRIG = "1'b0" *) 
  (* LC_PROBE884_MU_CNT = "1" *) 
  (* LC_PROBE884_PID = "16'b0000001101110100" *) 
  (* LC_PROBE884_TYPE = "1" *) 
  (* LC_PROBE884_WIDTH = "1" *) 
  (* LC_PROBE885_IS_DATA = "1'b0" *) 
  (* LC_PROBE885_IS_TRIG = "1'b0" *) 
  (* LC_PROBE885_MU_CNT = "1" *) 
  (* LC_PROBE885_PID = "16'b0000001101110101" *) 
  (* LC_PROBE885_TYPE = "1" *) 
  (* LC_PROBE885_WIDTH = "1" *) 
  (* LC_PROBE886_IS_DATA = "1'b0" *) 
  (* LC_PROBE886_IS_TRIG = "1'b0" *) 
  (* LC_PROBE886_MU_CNT = "1" *) 
  (* LC_PROBE886_PID = "16'b0000001101110110" *) 
  (* LC_PROBE886_TYPE = "1" *) 
  (* LC_PROBE886_WIDTH = "1" *) 
  (* LC_PROBE887_IS_DATA = "1'b0" *) 
  (* LC_PROBE887_IS_TRIG = "1'b0" *) 
  (* LC_PROBE887_MU_CNT = "1" *) 
  (* LC_PROBE887_PID = "16'b0000001101110111" *) 
  (* LC_PROBE887_TYPE = "1" *) 
  (* LC_PROBE887_WIDTH = "1" *) 
  (* LC_PROBE888_IS_DATA = "1'b0" *) 
  (* LC_PROBE888_IS_TRIG = "1'b0" *) 
  (* LC_PROBE888_MU_CNT = "1" *) 
  (* LC_PROBE888_PID = "16'b0000001101111000" *) 
  (* LC_PROBE888_TYPE = "1" *) 
  (* LC_PROBE888_WIDTH = "1" *) 
  (* LC_PROBE889_IS_DATA = "1'b0" *) 
  (* LC_PROBE889_IS_TRIG = "1'b0" *) 
  (* LC_PROBE889_MU_CNT = "1" *) 
  (* LC_PROBE889_PID = "16'b0000001101111001" *) 
  (* LC_PROBE889_TYPE = "1" *) 
  (* LC_PROBE889_WIDTH = "1" *) 
  (* LC_PROBE88_IS_DATA = "1'b0" *) 
  (* LC_PROBE88_IS_TRIG = "1'b0" *) 
  (* LC_PROBE88_MU_CNT = "1" *) 
  (* LC_PROBE88_PID = "16'b0000000001011000" *) 
  (* LC_PROBE88_TYPE = "1" *) 
  (* LC_PROBE88_WIDTH = "1" *) 
  (* LC_PROBE890_IS_DATA = "1'b0" *) 
  (* LC_PROBE890_IS_TRIG = "1'b0" *) 
  (* LC_PROBE890_MU_CNT = "1" *) 
  (* LC_PROBE890_PID = "16'b0000001101111010" *) 
  (* LC_PROBE890_TYPE = "1" *) 
  (* LC_PROBE890_WIDTH = "1" *) 
  (* LC_PROBE891_IS_DATA = "1'b0" *) 
  (* LC_PROBE891_IS_TRIG = "1'b0" *) 
  (* LC_PROBE891_MU_CNT = "1" *) 
  (* LC_PROBE891_PID = "16'b0000001101111011" *) 
  (* LC_PROBE891_TYPE = "1" *) 
  (* LC_PROBE891_WIDTH = "1" *) 
  (* LC_PROBE892_IS_DATA = "1'b0" *) 
  (* LC_PROBE892_IS_TRIG = "1'b0" *) 
  (* LC_PROBE892_MU_CNT = "1" *) 
  (* LC_PROBE892_PID = "16'b0000001101111100" *) 
  (* LC_PROBE892_TYPE = "1" *) 
  (* LC_PROBE892_WIDTH = "1" *) 
  (* LC_PROBE893_IS_DATA = "1'b0" *) 
  (* LC_PROBE893_IS_TRIG = "1'b0" *) 
  (* LC_PROBE893_MU_CNT = "1" *) 
  (* LC_PROBE893_PID = "16'b0000001101111101" *) 
  (* LC_PROBE893_TYPE = "1" *) 
  (* LC_PROBE893_WIDTH = "1" *) 
  (* LC_PROBE894_IS_DATA = "1'b0" *) 
  (* LC_PROBE894_IS_TRIG = "1'b0" *) 
  (* LC_PROBE894_MU_CNT = "1" *) 
  (* LC_PROBE894_PID = "16'b0000001101111110" *) 
  (* LC_PROBE894_TYPE = "1" *) 
  (* LC_PROBE894_WIDTH = "1" *) 
  (* LC_PROBE895_IS_DATA = "1'b0" *) 
  (* LC_PROBE895_IS_TRIG = "1'b0" *) 
  (* LC_PROBE895_MU_CNT = "1" *) 
  (* LC_PROBE895_PID = "16'b0000001101111111" *) 
  (* LC_PROBE895_TYPE = "1" *) 
  (* LC_PROBE895_WIDTH = "1" *) 
  (* LC_PROBE896_IS_DATA = "1'b0" *) 
  (* LC_PROBE896_IS_TRIG = "1'b0" *) 
  (* LC_PROBE896_MU_CNT = "1" *) 
  (* LC_PROBE896_PID = "16'b0000001110000000" *) 
  (* LC_PROBE896_TYPE = "1" *) 
  (* LC_PROBE896_WIDTH = "1" *) 
  (* LC_PROBE897_IS_DATA = "1'b0" *) 
  (* LC_PROBE897_IS_TRIG = "1'b0" *) 
  (* LC_PROBE897_MU_CNT = "1" *) 
  (* LC_PROBE897_PID = "16'b0000001110000001" *) 
  (* LC_PROBE897_TYPE = "1" *) 
  (* LC_PROBE897_WIDTH = "1" *) 
  (* LC_PROBE898_IS_DATA = "1'b0" *) 
  (* LC_PROBE898_IS_TRIG = "1'b0" *) 
  (* LC_PROBE898_MU_CNT = "1" *) 
  (* LC_PROBE898_PID = "16'b0000001110000010" *) 
  (* LC_PROBE898_TYPE = "1" *) 
  (* LC_PROBE898_WIDTH = "1" *) 
  (* LC_PROBE899_IS_DATA = "1'b0" *) 
  (* LC_PROBE899_IS_TRIG = "1'b0" *) 
  (* LC_PROBE899_MU_CNT = "1" *) 
  (* LC_PROBE899_PID = "16'b0000001110000011" *) 
  (* LC_PROBE899_TYPE = "1" *) 
  (* LC_PROBE899_WIDTH = "1" *) 
  (* LC_PROBE89_IS_DATA = "1'b0" *) 
  (* LC_PROBE89_IS_TRIG = "1'b0" *) 
  (* LC_PROBE89_MU_CNT = "1" *) 
  (* LC_PROBE89_PID = "16'b0000000001011001" *) 
  (* LC_PROBE89_TYPE = "1" *) 
  (* LC_PROBE89_WIDTH = "1" *) 
  (* LC_PROBE8_IS_DATA = "1'b0" *) 
  (* LC_PROBE8_IS_TRIG = "1'b0" *) 
  (* LC_PROBE8_MU_CNT = "1" *) 
  (* LC_PROBE8_PID = "16'b0000000000001000" *) 
  (* LC_PROBE8_TYPE = "1" *) 
  (* LC_PROBE8_WIDTH = "1" *) 
  (* LC_PROBE900_IS_DATA = "1'b0" *) 
  (* LC_PROBE900_IS_TRIG = "1'b0" *) 
  (* LC_PROBE900_MU_CNT = "1" *) 
  (* LC_PROBE900_PID = "16'b0000001110000100" *) 
  (* LC_PROBE900_TYPE = "1" *) 
  (* LC_PROBE900_WIDTH = "1" *) 
  (* LC_PROBE901_IS_DATA = "1'b0" *) 
  (* LC_PROBE901_IS_TRIG = "1'b0" *) 
  (* LC_PROBE901_MU_CNT = "1" *) 
  (* LC_PROBE901_PID = "16'b0000001110000101" *) 
  (* LC_PROBE901_TYPE = "1" *) 
  (* LC_PROBE901_WIDTH = "1" *) 
  (* LC_PROBE902_IS_DATA = "1'b0" *) 
  (* LC_PROBE902_IS_TRIG = "1'b0" *) 
  (* LC_PROBE902_MU_CNT = "1" *) 
  (* LC_PROBE902_PID = "16'b0000001110000110" *) 
  (* LC_PROBE902_TYPE = "1" *) 
  (* LC_PROBE902_WIDTH = "1" *) 
  (* LC_PROBE903_IS_DATA = "1'b0" *) 
  (* LC_PROBE903_IS_TRIG = "1'b0" *) 
  (* LC_PROBE903_MU_CNT = "1" *) 
  (* LC_PROBE903_PID = "16'b0000001110000111" *) 
  (* LC_PROBE903_TYPE = "1" *) 
  (* LC_PROBE903_WIDTH = "1" *) 
  (* LC_PROBE904_IS_DATA = "1'b0" *) 
  (* LC_PROBE904_IS_TRIG = "1'b0" *) 
  (* LC_PROBE904_MU_CNT = "1" *) 
  (* LC_PROBE904_PID = "16'b0000001110001000" *) 
  (* LC_PROBE904_TYPE = "1" *) 
  (* LC_PROBE904_WIDTH = "1" *) 
  (* LC_PROBE905_IS_DATA = "1'b0" *) 
  (* LC_PROBE905_IS_TRIG = "1'b0" *) 
  (* LC_PROBE905_MU_CNT = "1" *) 
  (* LC_PROBE905_PID = "16'b0000001110001001" *) 
  (* LC_PROBE905_TYPE = "1" *) 
  (* LC_PROBE905_WIDTH = "1" *) 
  (* LC_PROBE906_IS_DATA = "1'b0" *) 
  (* LC_PROBE906_IS_TRIG = "1'b0" *) 
  (* LC_PROBE906_MU_CNT = "1" *) 
  (* LC_PROBE906_PID = "16'b0000001110001010" *) 
  (* LC_PROBE906_TYPE = "1" *) 
  (* LC_PROBE906_WIDTH = "1" *) 
  (* LC_PROBE907_IS_DATA = "1'b0" *) 
  (* LC_PROBE907_IS_TRIG = "1'b0" *) 
  (* LC_PROBE907_MU_CNT = "1" *) 
  (* LC_PROBE907_PID = "16'b0000001110001011" *) 
  (* LC_PROBE907_TYPE = "1" *) 
  (* LC_PROBE907_WIDTH = "1" *) 
  (* LC_PROBE908_IS_DATA = "1'b0" *) 
  (* LC_PROBE908_IS_TRIG = "1'b0" *) 
  (* LC_PROBE908_MU_CNT = "1" *) 
  (* LC_PROBE908_PID = "16'b0000001110001100" *) 
  (* LC_PROBE908_TYPE = "1" *) 
  (* LC_PROBE908_WIDTH = "1" *) 
  (* LC_PROBE909_IS_DATA = "1'b0" *) 
  (* LC_PROBE909_IS_TRIG = "1'b0" *) 
  (* LC_PROBE909_MU_CNT = "1" *) 
  (* LC_PROBE909_PID = "16'b0000001110001101" *) 
  (* LC_PROBE909_TYPE = "1" *) 
  (* LC_PROBE909_WIDTH = "1" *) 
  (* LC_PROBE90_IS_DATA = "1'b0" *) 
  (* LC_PROBE90_IS_TRIG = "1'b0" *) 
  (* LC_PROBE90_MU_CNT = "1" *) 
  (* LC_PROBE90_PID = "16'b0000000001011010" *) 
  (* LC_PROBE90_TYPE = "1" *) 
  (* LC_PROBE90_WIDTH = "1" *) 
  (* LC_PROBE910_IS_DATA = "1'b0" *) 
  (* LC_PROBE910_IS_TRIG = "1'b0" *) 
  (* LC_PROBE910_MU_CNT = "1" *) 
  (* LC_PROBE910_PID = "16'b0000001110001110" *) 
  (* LC_PROBE910_TYPE = "1" *) 
  (* LC_PROBE910_WIDTH = "1" *) 
  (* LC_PROBE911_IS_DATA = "1'b0" *) 
  (* LC_PROBE911_IS_TRIG = "1'b0" *) 
  (* LC_PROBE911_MU_CNT = "1" *) 
  (* LC_PROBE911_PID = "16'b0000001110001111" *) 
  (* LC_PROBE911_TYPE = "1" *) 
  (* LC_PROBE911_WIDTH = "1" *) 
  (* LC_PROBE912_IS_DATA = "1'b0" *) 
  (* LC_PROBE912_IS_TRIG = "1'b0" *) 
  (* LC_PROBE912_MU_CNT = "1" *) 
  (* LC_PROBE912_PID = "16'b0000001110010000" *) 
  (* LC_PROBE912_TYPE = "1" *) 
  (* LC_PROBE912_WIDTH = "1" *) 
  (* LC_PROBE913_IS_DATA = "1'b0" *) 
  (* LC_PROBE913_IS_TRIG = "1'b0" *) 
  (* LC_PROBE913_MU_CNT = "1" *) 
  (* LC_PROBE913_PID = "16'b0000001110010001" *) 
  (* LC_PROBE913_TYPE = "1" *) 
  (* LC_PROBE913_WIDTH = "1" *) 
  (* LC_PROBE914_IS_DATA = "1'b0" *) 
  (* LC_PROBE914_IS_TRIG = "1'b0" *) 
  (* LC_PROBE914_MU_CNT = "1" *) 
  (* LC_PROBE914_PID = "16'b0000001110010010" *) 
  (* LC_PROBE914_TYPE = "1" *) 
  (* LC_PROBE914_WIDTH = "1" *) 
  (* LC_PROBE915_IS_DATA = "1'b0" *) 
  (* LC_PROBE915_IS_TRIG = "1'b0" *) 
  (* LC_PROBE915_MU_CNT = "1" *) 
  (* LC_PROBE915_PID = "16'b0000001110010011" *) 
  (* LC_PROBE915_TYPE = "1" *) 
  (* LC_PROBE915_WIDTH = "1" *) 
  (* LC_PROBE916_IS_DATA = "1'b0" *) 
  (* LC_PROBE916_IS_TRIG = "1'b0" *) 
  (* LC_PROBE916_MU_CNT = "1" *) 
  (* LC_PROBE916_PID = "16'b0000001110010100" *) 
  (* LC_PROBE916_TYPE = "1" *) 
  (* LC_PROBE916_WIDTH = "1" *) 
  (* LC_PROBE917_IS_DATA = "1'b0" *) 
  (* LC_PROBE917_IS_TRIG = "1'b0" *) 
  (* LC_PROBE917_MU_CNT = "1" *) 
  (* LC_PROBE917_PID = "16'b0000001110010101" *) 
  (* LC_PROBE917_TYPE = "1" *) 
  (* LC_PROBE917_WIDTH = "1" *) 
  (* LC_PROBE918_IS_DATA = "1'b0" *) 
  (* LC_PROBE918_IS_TRIG = "1'b0" *) 
  (* LC_PROBE918_MU_CNT = "1" *) 
  (* LC_PROBE918_PID = "16'b0000001110010110" *) 
  (* LC_PROBE918_TYPE = "1" *) 
  (* LC_PROBE918_WIDTH = "1" *) 
  (* LC_PROBE919_IS_DATA = "1'b0" *) 
  (* LC_PROBE919_IS_TRIG = "1'b0" *) 
  (* LC_PROBE919_MU_CNT = "1" *) 
  (* LC_PROBE919_PID = "16'b0000001110010111" *) 
  (* LC_PROBE919_TYPE = "1" *) 
  (* LC_PROBE919_WIDTH = "1" *) 
  (* LC_PROBE91_IS_DATA = "1'b0" *) 
  (* LC_PROBE91_IS_TRIG = "1'b0" *) 
  (* LC_PROBE91_MU_CNT = "1" *) 
  (* LC_PROBE91_PID = "16'b0000000001011011" *) 
  (* LC_PROBE91_TYPE = "1" *) 
  (* LC_PROBE91_WIDTH = "1" *) 
  (* LC_PROBE920_IS_DATA = "1'b0" *) 
  (* LC_PROBE920_IS_TRIG = "1'b0" *) 
  (* LC_PROBE920_MU_CNT = "1" *) 
  (* LC_PROBE920_PID = "16'b0000001110011000" *) 
  (* LC_PROBE920_TYPE = "1" *) 
  (* LC_PROBE920_WIDTH = "1" *) 
  (* LC_PROBE921_IS_DATA = "1'b0" *) 
  (* LC_PROBE921_IS_TRIG = "1'b0" *) 
  (* LC_PROBE921_MU_CNT = "1" *) 
  (* LC_PROBE921_PID = "16'b0000001110011001" *) 
  (* LC_PROBE921_TYPE = "1" *) 
  (* LC_PROBE921_WIDTH = "1" *) 
  (* LC_PROBE922_IS_DATA = "1'b0" *) 
  (* LC_PROBE922_IS_TRIG = "1'b0" *) 
  (* LC_PROBE922_MU_CNT = "1" *) 
  (* LC_PROBE922_PID = "16'b0000001110011010" *) 
  (* LC_PROBE922_TYPE = "1" *) 
  (* LC_PROBE922_WIDTH = "1" *) 
  (* LC_PROBE923_IS_DATA = "1'b0" *) 
  (* LC_PROBE923_IS_TRIG = "1'b0" *) 
  (* LC_PROBE923_MU_CNT = "1" *) 
  (* LC_PROBE923_PID = "16'b0000001110011011" *) 
  (* LC_PROBE923_TYPE = "1" *) 
  (* LC_PROBE923_WIDTH = "1" *) 
  (* LC_PROBE924_IS_DATA = "1'b0" *) 
  (* LC_PROBE924_IS_TRIG = "1'b0" *) 
  (* LC_PROBE924_MU_CNT = "1" *) 
  (* LC_PROBE924_PID = "16'b0000001110011100" *) 
  (* LC_PROBE924_TYPE = "1" *) 
  (* LC_PROBE924_WIDTH = "1" *) 
  (* LC_PROBE925_IS_DATA = "1'b0" *) 
  (* LC_PROBE925_IS_TRIG = "1'b0" *) 
  (* LC_PROBE925_MU_CNT = "1" *) 
  (* LC_PROBE925_PID = "16'b0000001110011101" *) 
  (* LC_PROBE925_TYPE = "1" *) 
  (* LC_PROBE925_WIDTH = "1" *) 
  (* LC_PROBE926_IS_DATA = "1'b0" *) 
  (* LC_PROBE926_IS_TRIG = "1'b0" *) 
  (* LC_PROBE926_MU_CNT = "1" *) 
  (* LC_PROBE926_PID = "16'b0000001110011110" *) 
  (* LC_PROBE926_TYPE = "1" *) 
  (* LC_PROBE926_WIDTH = "1" *) 
  (* LC_PROBE927_IS_DATA = "1'b0" *) 
  (* LC_PROBE927_IS_TRIG = "1'b0" *) 
  (* LC_PROBE927_MU_CNT = "1" *) 
  (* LC_PROBE927_PID = "16'b0000001110011111" *) 
  (* LC_PROBE927_TYPE = "1" *) 
  (* LC_PROBE927_WIDTH = "1" *) 
  (* LC_PROBE928_IS_DATA = "1'b0" *) 
  (* LC_PROBE928_IS_TRIG = "1'b0" *) 
  (* LC_PROBE928_MU_CNT = "1" *) 
  (* LC_PROBE928_PID = "16'b0000001110100000" *) 
  (* LC_PROBE928_TYPE = "1" *) 
  (* LC_PROBE928_WIDTH = "1" *) 
  (* LC_PROBE929_IS_DATA = "1'b0" *) 
  (* LC_PROBE929_IS_TRIG = "1'b0" *) 
  (* LC_PROBE929_MU_CNT = "1" *) 
  (* LC_PROBE929_PID = "16'b0000001110100001" *) 
  (* LC_PROBE929_TYPE = "1" *) 
  (* LC_PROBE929_WIDTH = "1" *) 
  (* LC_PROBE92_IS_DATA = "1'b0" *) 
  (* LC_PROBE92_IS_TRIG = "1'b0" *) 
  (* LC_PROBE92_MU_CNT = "1" *) 
  (* LC_PROBE92_PID = "16'b0000000001011100" *) 
  (* LC_PROBE92_TYPE = "1" *) 
  (* LC_PROBE92_WIDTH = "1" *) 
  (* LC_PROBE930_IS_DATA = "1'b0" *) 
  (* LC_PROBE930_IS_TRIG = "1'b0" *) 
  (* LC_PROBE930_MU_CNT = "1" *) 
  (* LC_PROBE930_PID = "16'b0000001110100010" *) 
  (* LC_PROBE930_TYPE = "1" *) 
  (* LC_PROBE930_WIDTH = "1" *) 
  (* LC_PROBE931_IS_DATA = "1'b0" *) 
  (* LC_PROBE931_IS_TRIG = "1'b0" *) 
  (* LC_PROBE931_MU_CNT = "1" *) 
  (* LC_PROBE931_PID = "16'b0000001110100011" *) 
  (* LC_PROBE931_TYPE = "1" *) 
  (* LC_PROBE931_WIDTH = "1" *) 
  (* LC_PROBE932_IS_DATA = "1'b0" *) 
  (* LC_PROBE932_IS_TRIG = "1'b0" *) 
  (* LC_PROBE932_MU_CNT = "1" *) 
  (* LC_PROBE932_PID = "16'b0000001110100100" *) 
  (* LC_PROBE932_TYPE = "1" *) 
  (* LC_PROBE932_WIDTH = "1" *) 
  (* LC_PROBE933_IS_DATA = "1'b0" *) 
  (* LC_PROBE933_IS_TRIG = "1'b0" *) 
  (* LC_PROBE933_MU_CNT = "1" *) 
  (* LC_PROBE933_PID = "16'b0000001110100101" *) 
  (* LC_PROBE933_TYPE = "1" *) 
  (* LC_PROBE933_WIDTH = "1" *) 
  (* LC_PROBE934_IS_DATA = "1'b0" *) 
  (* LC_PROBE934_IS_TRIG = "1'b0" *) 
  (* LC_PROBE934_MU_CNT = "1" *) 
  (* LC_PROBE934_PID = "16'b0000001110100110" *) 
  (* LC_PROBE934_TYPE = "1" *) 
  (* LC_PROBE934_WIDTH = "1" *) 
  (* LC_PROBE935_IS_DATA = "1'b0" *) 
  (* LC_PROBE935_IS_TRIG = "1'b0" *) 
  (* LC_PROBE935_MU_CNT = "1" *) 
  (* LC_PROBE935_PID = "16'b0000001110100111" *) 
  (* LC_PROBE935_TYPE = "1" *) 
  (* LC_PROBE935_WIDTH = "1" *) 
  (* LC_PROBE936_IS_DATA = "1'b0" *) 
  (* LC_PROBE936_IS_TRIG = "1'b0" *) 
  (* LC_PROBE936_MU_CNT = "1" *) 
  (* LC_PROBE936_PID = "16'b0000001110101000" *) 
  (* LC_PROBE936_TYPE = "1" *) 
  (* LC_PROBE936_WIDTH = "1" *) 
  (* LC_PROBE937_IS_DATA = "1'b0" *) 
  (* LC_PROBE937_IS_TRIG = "1'b0" *) 
  (* LC_PROBE937_MU_CNT = "1" *) 
  (* LC_PROBE937_PID = "16'b0000001110101001" *) 
  (* LC_PROBE937_TYPE = "1" *) 
  (* LC_PROBE937_WIDTH = "1" *) 
  (* LC_PROBE938_IS_DATA = "1'b0" *) 
  (* LC_PROBE938_IS_TRIG = "1'b0" *) 
  (* LC_PROBE938_MU_CNT = "1" *) 
  (* LC_PROBE938_PID = "16'b0000001110101010" *) 
  (* LC_PROBE938_TYPE = "1" *) 
  (* LC_PROBE938_WIDTH = "1" *) 
  (* LC_PROBE939_IS_DATA = "1'b0" *) 
  (* LC_PROBE939_IS_TRIG = "1'b0" *) 
  (* LC_PROBE939_MU_CNT = "1" *) 
  (* LC_PROBE939_PID = "16'b0000001110101011" *) 
  (* LC_PROBE939_TYPE = "1" *) 
  (* LC_PROBE939_WIDTH = "1" *) 
  (* LC_PROBE93_IS_DATA = "1'b0" *) 
  (* LC_PROBE93_IS_TRIG = "1'b0" *) 
  (* LC_PROBE93_MU_CNT = "1" *) 
  (* LC_PROBE93_PID = "16'b0000000001011101" *) 
  (* LC_PROBE93_TYPE = "1" *) 
  (* LC_PROBE93_WIDTH = "1" *) 
  (* LC_PROBE940_IS_DATA = "1'b0" *) 
  (* LC_PROBE940_IS_TRIG = "1'b0" *) 
  (* LC_PROBE940_MU_CNT = "1" *) 
  (* LC_PROBE940_PID = "16'b0000001110101100" *) 
  (* LC_PROBE940_TYPE = "1" *) 
  (* LC_PROBE940_WIDTH = "1" *) 
  (* LC_PROBE941_IS_DATA = "1'b0" *) 
  (* LC_PROBE941_IS_TRIG = "1'b0" *) 
  (* LC_PROBE941_MU_CNT = "1" *) 
  (* LC_PROBE941_PID = "16'b0000001110101101" *) 
  (* LC_PROBE941_TYPE = "1" *) 
  (* LC_PROBE941_WIDTH = "1" *) 
  (* LC_PROBE942_IS_DATA = "1'b0" *) 
  (* LC_PROBE942_IS_TRIG = "1'b0" *) 
  (* LC_PROBE942_MU_CNT = "1" *) 
  (* LC_PROBE942_PID = "16'b0000001110101110" *) 
  (* LC_PROBE942_TYPE = "1" *) 
  (* LC_PROBE942_WIDTH = "1" *) 
  (* LC_PROBE943_IS_DATA = "1'b0" *) 
  (* LC_PROBE943_IS_TRIG = "1'b0" *) 
  (* LC_PROBE943_MU_CNT = "1" *) 
  (* LC_PROBE943_PID = "16'b0000001110101111" *) 
  (* LC_PROBE943_TYPE = "1" *) 
  (* LC_PROBE943_WIDTH = "1" *) 
  (* LC_PROBE944_IS_DATA = "1'b0" *) 
  (* LC_PROBE944_IS_TRIG = "1'b0" *) 
  (* LC_PROBE944_MU_CNT = "1" *) 
  (* LC_PROBE944_PID = "16'b0000001110110000" *) 
  (* LC_PROBE944_TYPE = "1" *) 
  (* LC_PROBE944_WIDTH = "1" *) 
  (* LC_PROBE945_IS_DATA = "1'b0" *) 
  (* LC_PROBE945_IS_TRIG = "1'b0" *) 
  (* LC_PROBE945_MU_CNT = "1" *) 
  (* LC_PROBE945_PID = "16'b0000001110110001" *) 
  (* LC_PROBE945_TYPE = "1" *) 
  (* LC_PROBE945_WIDTH = "1" *) 
  (* LC_PROBE946_IS_DATA = "1'b0" *) 
  (* LC_PROBE946_IS_TRIG = "1'b0" *) 
  (* LC_PROBE946_MU_CNT = "1" *) 
  (* LC_PROBE946_PID = "16'b0000001110110010" *) 
  (* LC_PROBE946_TYPE = "1" *) 
  (* LC_PROBE946_WIDTH = "1" *) 
  (* LC_PROBE947_IS_DATA = "1'b0" *) 
  (* LC_PROBE947_IS_TRIG = "1'b0" *) 
  (* LC_PROBE947_MU_CNT = "1" *) 
  (* LC_PROBE947_PID = "16'b0000001110110011" *) 
  (* LC_PROBE947_TYPE = "1" *) 
  (* LC_PROBE947_WIDTH = "1" *) 
  (* LC_PROBE948_IS_DATA = "1'b0" *) 
  (* LC_PROBE948_IS_TRIG = "1'b0" *) 
  (* LC_PROBE948_MU_CNT = "1" *) 
  (* LC_PROBE948_PID = "16'b0000001110110100" *) 
  (* LC_PROBE948_TYPE = "1" *) 
  (* LC_PROBE948_WIDTH = "1" *) 
  (* LC_PROBE949_IS_DATA = "1'b0" *) 
  (* LC_PROBE949_IS_TRIG = "1'b0" *) 
  (* LC_PROBE949_MU_CNT = "1" *) 
  (* LC_PROBE949_PID = "16'b0000001110110101" *) 
  (* LC_PROBE949_TYPE = "1" *) 
  (* LC_PROBE949_WIDTH = "1" *) 
  (* LC_PROBE94_IS_DATA = "1'b0" *) 
  (* LC_PROBE94_IS_TRIG = "1'b0" *) 
  (* LC_PROBE94_MU_CNT = "1" *) 
  (* LC_PROBE94_PID = "16'b0000000001011110" *) 
  (* LC_PROBE94_TYPE = "1" *) 
  (* LC_PROBE94_WIDTH = "1" *) 
  (* LC_PROBE950_IS_DATA = "1'b0" *) 
  (* LC_PROBE950_IS_TRIG = "1'b0" *) 
  (* LC_PROBE950_MU_CNT = "1" *) 
  (* LC_PROBE950_PID = "16'b0000001110110110" *) 
  (* LC_PROBE950_TYPE = "1" *) 
  (* LC_PROBE950_WIDTH = "1" *) 
  (* LC_PROBE951_IS_DATA = "1'b0" *) 
  (* LC_PROBE951_IS_TRIG = "1'b0" *) 
  (* LC_PROBE951_MU_CNT = "1" *) 
  (* LC_PROBE951_PID = "16'b0000001110110111" *) 
  (* LC_PROBE951_TYPE = "1" *) 
  (* LC_PROBE951_WIDTH = "1" *) 
  (* LC_PROBE952_IS_DATA = "1'b0" *) 
  (* LC_PROBE952_IS_TRIG = "1'b0" *) 
  (* LC_PROBE952_MU_CNT = "1" *) 
  (* LC_PROBE952_PID = "16'b0000001110111000" *) 
  (* LC_PROBE952_TYPE = "1" *) 
  (* LC_PROBE952_WIDTH = "1" *) 
  (* LC_PROBE953_IS_DATA = "1'b0" *) 
  (* LC_PROBE953_IS_TRIG = "1'b0" *) 
  (* LC_PROBE953_MU_CNT = "1" *) 
  (* LC_PROBE953_PID = "16'b0000001110111001" *) 
  (* LC_PROBE953_TYPE = "1" *) 
  (* LC_PROBE953_WIDTH = "1" *) 
  (* LC_PROBE954_IS_DATA = "1'b0" *) 
  (* LC_PROBE954_IS_TRIG = "1'b0" *) 
  (* LC_PROBE954_MU_CNT = "1" *) 
  (* LC_PROBE954_PID = "16'b0000001110111010" *) 
  (* LC_PROBE954_TYPE = "1" *) 
  (* LC_PROBE954_WIDTH = "1" *) 
  (* LC_PROBE955_IS_DATA = "1'b0" *) 
  (* LC_PROBE955_IS_TRIG = "1'b0" *) 
  (* LC_PROBE955_MU_CNT = "1" *) 
  (* LC_PROBE955_PID = "16'b0000001110111011" *) 
  (* LC_PROBE955_TYPE = "1" *) 
  (* LC_PROBE955_WIDTH = "1" *) 
  (* LC_PROBE956_IS_DATA = "1'b0" *) 
  (* LC_PROBE956_IS_TRIG = "1'b0" *) 
  (* LC_PROBE956_MU_CNT = "1" *) 
  (* LC_PROBE956_PID = "16'b0000001110111100" *) 
  (* LC_PROBE956_TYPE = "1" *) 
  (* LC_PROBE956_WIDTH = "1" *) 
  (* LC_PROBE957_IS_DATA = "1'b0" *) 
  (* LC_PROBE957_IS_TRIG = "1'b0" *) 
  (* LC_PROBE957_MU_CNT = "1" *) 
  (* LC_PROBE957_PID = "16'b0000001110111101" *) 
  (* LC_PROBE957_TYPE = "1" *) 
  (* LC_PROBE957_WIDTH = "1" *) 
  (* LC_PROBE958_IS_DATA = "1'b0" *) 
  (* LC_PROBE958_IS_TRIG = "1'b0" *) 
  (* LC_PROBE958_MU_CNT = "1" *) 
  (* LC_PROBE958_PID = "16'b0000001110111110" *) 
  (* LC_PROBE958_TYPE = "1" *) 
  (* LC_PROBE958_WIDTH = "1" *) 
  (* LC_PROBE959_IS_DATA = "1'b0" *) 
  (* LC_PROBE959_IS_TRIG = "1'b0" *) 
  (* LC_PROBE959_MU_CNT = "1" *) 
  (* LC_PROBE959_PID = "16'b0000001110111111" *) 
  (* LC_PROBE959_TYPE = "1" *) 
  (* LC_PROBE959_WIDTH = "1" *) 
  (* LC_PROBE95_IS_DATA = "1'b0" *) 
  (* LC_PROBE95_IS_TRIG = "1'b0" *) 
  (* LC_PROBE95_MU_CNT = "1" *) 
  (* LC_PROBE95_PID = "16'b0000000001011111" *) 
  (* LC_PROBE95_TYPE = "1" *) 
  (* LC_PROBE95_WIDTH = "1" *) 
  (* LC_PROBE960_IS_DATA = "1'b0" *) 
  (* LC_PROBE960_IS_TRIG = "1'b0" *) 
  (* LC_PROBE960_MU_CNT = "1" *) 
  (* LC_PROBE960_PID = "16'b0000001111000000" *) 
  (* LC_PROBE960_TYPE = "1" *) 
  (* LC_PROBE960_WIDTH = "1" *) 
  (* LC_PROBE961_IS_DATA = "1'b0" *) 
  (* LC_PROBE961_IS_TRIG = "1'b0" *) 
  (* LC_PROBE961_MU_CNT = "1" *) 
  (* LC_PROBE961_PID = "16'b0000001111000001" *) 
  (* LC_PROBE961_TYPE = "1" *) 
  (* LC_PROBE961_WIDTH = "1" *) 
  (* LC_PROBE962_IS_DATA = "1'b0" *) 
  (* LC_PROBE962_IS_TRIG = "1'b0" *) 
  (* LC_PROBE962_MU_CNT = "1" *) 
  (* LC_PROBE962_PID = "16'b0000001111000010" *) 
  (* LC_PROBE962_TYPE = "1" *) 
  (* LC_PROBE962_WIDTH = "1" *) 
  (* LC_PROBE963_IS_DATA = "1'b0" *) 
  (* LC_PROBE963_IS_TRIG = "1'b0" *) 
  (* LC_PROBE963_MU_CNT = "1" *) 
  (* LC_PROBE963_PID = "16'b0000001111000011" *) 
  (* LC_PROBE963_TYPE = "1" *) 
  (* LC_PROBE963_WIDTH = "1" *) 
  (* LC_PROBE964_IS_DATA = "1'b0" *) 
  (* LC_PROBE964_IS_TRIG = "1'b0" *) 
  (* LC_PROBE964_MU_CNT = "1" *) 
  (* LC_PROBE964_PID = "16'b0000001111000100" *) 
  (* LC_PROBE964_TYPE = "1" *) 
  (* LC_PROBE964_WIDTH = "1" *) 
  (* LC_PROBE965_IS_DATA = "1'b0" *) 
  (* LC_PROBE965_IS_TRIG = "1'b0" *) 
  (* LC_PROBE965_MU_CNT = "1" *) 
  (* LC_PROBE965_PID = "16'b0000001111000101" *) 
  (* LC_PROBE965_TYPE = "1" *) 
  (* LC_PROBE965_WIDTH = "1" *) 
  (* LC_PROBE966_IS_DATA = "1'b0" *) 
  (* LC_PROBE966_IS_TRIG = "1'b0" *) 
  (* LC_PROBE966_MU_CNT = "1" *) 
  (* LC_PROBE966_PID = "16'b0000001111000110" *) 
  (* LC_PROBE966_TYPE = "1" *) 
  (* LC_PROBE966_WIDTH = "1" *) 
  (* LC_PROBE967_IS_DATA = "1'b0" *) 
  (* LC_PROBE967_IS_TRIG = "1'b0" *) 
  (* LC_PROBE967_MU_CNT = "1" *) 
  (* LC_PROBE967_PID = "16'b0000001111000111" *) 
  (* LC_PROBE967_TYPE = "1" *) 
  (* LC_PROBE967_WIDTH = "1" *) 
  (* LC_PROBE968_IS_DATA = "1'b0" *) 
  (* LC_PROBE968_IS_TRIG = "1'b0" *) 
  (* LC_PROBE968_MU_CNT = "1" *) 
  (* LC_PROBE968_PID = "16'b0000001111001000" *) 
  (* LC_PROBE968_TYPE = "1" *) 
  (* LC_PROBE968_WIDTH = "1" *) 
  (* LC_PROBE969_IS_DATA = "1'b0" *) 
  (* LC_PROBE969_IS_TRIG = "1'b0" *) 
  (* LC_PROBE969_MU_CNT = "1" *) 
  (* LC_PROBE969_PID = "16'b0000001111001001" *) 
  (* LC_PROBE969_TYPE = "1" *) 
  (* LC_PROBE969_WIDTH = "1" *) 
  (* LC_PROBE96_IS_DATA = "1'b0" *) 
  (* LC_PROBE96_IS_TRIG = "1'b0" *) 
  (* LC_PROBE96_MU_CNT = "1" *) 
  (* LC_PROBE96_PID = "16'b0000000001100000" *) 
  (* LC_PROBE96_TYPE = "1" *) 
  (* LC_PROBE96_WIDTH = "1" *) 
  (* LC_PROBE970_IS_DATA = "1'b0" *) 
  (* LC_PROBE970_IS_TRIG = "1'b0" *) 
  (* LC_PROBE970_MU_CNT = "1" *) 
  (* LC_PROBE970_PID = "16'b0000001111001010" *) 
  (* LC_PROBE970_TYPE = "1" *) 
  (* LC_PROBE970_WIDTH = "1" *) 
  (* LC_PROBE971_IS_DATA = "1'b0" *) 
  (* LC_PROBE971_IS_TRIG = "1'b0" *) 
  (* LC_PROBE971_MU_CNT = "1" *) 
  (* LC_PROBE971_PID = "16'b0000001111001011" *) 
  (* LC_PROBE971_TYPE = "1" *) 
  (* LC_PROBE971_WIDTH = "1" *) 
  (* LC_PROBE972_IS_DATA = "1'b0" *) 
  (* LC_PROBE972_IS_TRIG = "1'b0" *) 
  (* LC_PROBE972_MU_CNT = "1" *) 
  (* LC_PROBE972_PID = "16'b0000001111001100" *) 
  (* LC_PROBE972_TYPE = "1" *) 
  (* LC_PROBE972_WIDTH = "1" *) 
  (* LC_PROBE973_IS_DATA = "1'b0" *) 
  (* LC_PROBE973_IS_TRIG = "1'b0" *) 
  (* LC_PROBE973_MU_CNT = "1" *) 
  (* LC_PROBE973_PID = "16'b0000001111001101" *) 
  (* LC_PROBE973_TYPE = "1" *) 
  (* LC_PROBE973_WIDTH = "1" *) 
  (* LC_PROBE974_IS_DATA = "1'b0" *) 
  (* LC_PROBE974_IS_TRIG = "1'b0" *) 
  (* LC_PROBE974_MU_CNT = "1" *) 
  (* LC_PROBE974_PID = "16'b0000001111001110" *) 
  (* LC_PROBE974_TYPE = "1" *) 
  (* LC_PROBE974_WIDTH = "1" *) 
  (* LC_PROBE975_IS_DATA = "1'b0" *) 
  (* LC_PROBE975_IS_TRIG = "1'b0" *) 
  (* LC_PROBE975_MU_CNT = "1" *) 
  (* LC_PROBE975_PID = "16'b0000001111001111" *) 
  (* LC_PROBE975_TYPE = "1" *) 
  (* LC_PROBE975_WIDTH = "1" *) 
  (* LC_PROBE976_IS_DATA = "1'b0" *) 
  (* LC_PROBE976_IS_TRIG = "1'b0" *) 
  (* LC_PROBE976_MU_CNT = "1" *) 
  (* LC_PROBE976_PID = "16'b0000001111010000" *) 
  (* LC_PROBE976_TYPE = "1" *) 
  (* LC_PROBE976_WIDTH = "1" *) 
  (* LC_PROBE977_IS_DATA = "1'b0" *) 
  (* LC_PROBE977_IS_TRIG = "1'b0" *) 
  (* LC_PROBE977_MU_CNT = "1" *) 
  (* LC_PROBE977_PID = "16'b0000001111010001" *) 
  (* LC_PROBE977_TYPE = "1" *) 
  (* LC_PROBE977_WIDTH = "1" *) 
  (* LC_PROBE978_IS_DATA = "1'b0" *) 
  (* LC_PROBE978_IS_TRIG = "1'b0" *) 
  (* LC_PROBE978_MU_CNT = "1" *) 
  (* LC_PROBE978_PID = "16'b0000001111010010" *) 
  (* LC_PROBE978_TYPE = "1" *) 
  (* LC_PROBE978_WIDTH = "1" *) 
  (* LC_PROBE979_IS_DATA = "1'b0" *) 
  (* LC_PROBE979_IS_TRIG = "1'b0" *) 
  (* LC_PROBE979_MU_CNT = "1" *) 
  (* LC_PROBE979_PID = "16'b0000001111010011" *) 
  (* LC_PROBE979_TYPE = "1" *) 
  (* LC_PROBE979_WIDTH = "1" *) 
  (* LC_PROBE97_IS_DATA = "1'b0" *) 
  (* LC_PROBE97_IS_TRIG = "1'b0" *) 
  (* LC_PROBE97_MU_CNT = "1" *) 
  (* LC_PROBE97_PID = "16'b0000000001100001" *) 
  (* LC_PROBE97_TYPE = "1" *) 
  (* LC_PROBE97_WIDTH = "1" *) 
  (* LC_PROBE980_IS_DATA = "1'b0" *) 
  (* LC_PROBE980_IS_TRIG = "1'b0" *) 
  (* LC_PROBE980_MU_CNT = "1" *) 
  (* LC_PROBE980_PID = "16'b0000001111010100" *) 
  (* LC_PROBE980_TYPE = "1" *) 
  (* LC_PROBE980_WIDTH = "1" *) 
  (* LC_PROBE981_IS_DATA = "1'b0" *) 
  (* LC_PROBE981_IS_TRIG = "1'b0" *) 
  (* LC_PROBE981_MU_CNT = "1" *) 
  (* LC_PROBE981_PID = "16'b0000001111010101" *) 
  (* LC_PROBE981_TYPE = "1" *) 
  (* LC_PROBE981_WIDTH = "1" *) 
  (* LC_PROBE982_IS_DATA = "1'b0" *) 
  (* LC_PROBE982_IS_TRIG = "1'b0" *) 
  (* LC_PROBE982_MU_CNT = "1" *) 
  (* LC_PROBE982_PID = "16'b0000001111010110" *) 
  (* LC_PROBE982_TYPE = "1" *) 
  (* LC_PROBE982_WIDTH = "1" *) 
  (* LC_PROBE983_IS_DATA = "1'b0" *) 
  (* LC_PROBE983_IS_TRIG = "1'b0" *) 
  (* LC_PROBE983_MU_CNT = "1" *) 
  (* LC_PROBE983_PID = "16'b0000001111010111" *) 
  (* LC_PROBE983_TYPE = "1" *) 
  (* LC_PROBE983_WIDTH = "1" *) 
  (* LC_PROBE984_IS_DATA = "1'b0" *) 
  (* LC_PROBE984_IS_TRIG = "1'b0" *) 
  (* LC_PROBE984_MU_CNT = "1" *) 
  (* LC_PROBE984_PID = "16'b0000001111011000" *) 
  (* LC_PROBE984_TYPE = "1" *) 
  (* LC_PROBE984_WIDTH = "1" *) 
  (* LC_PROBE985_IS_DATA = "1'b0" *) 
  (* LC_PROBE985_IS_TRIG = "1'b0" *) 
  (* LC_PROBE985_MU_CNT = "1" *) 
  (* LC_PROBE985_PID = "16'b0000001111011001" *) 
  (* LC_PROBE985_TYPE = "1" *) 
  (* LC_PROBE985_WIDTH = "1" *) 
  (* LC_PROBE986_IS_DATA = "1'b0" *) 
  (* LC_PROBE986_IS_TRIG = "1'b0" *) 
  (* LC_PROBE986_MU_CNT = "1" *) 
  (* LC_PROBE986_PID = "16'b0000001111011010" *) 
  (* LC_PROBE986_TYPE = "1" *) 
  (* LC_PROBE986_WIDTH = "1" *) 
  (* LC_PROBE987_IS_DATA = "1'b0" *) 
  (* LC_PROBE987_IS_TRIG = "1'b0" *) 
  (* LC_PROBE987_MU_CNT = "1" *) 
  (* LC_PROBE987_PID = "16'b0000001111011011" *) 
  (* LC_PROBE987_TYPE = "1" *) 
  (* LC_PROBE987_WIDTH = "1" *) 
  (* LC_PROBE988_IS_DATA = "1'b0" *) 
  (* LC_PROBE988_IS_TRIG = "1'b0" *) 
  (* LC_PROBE988_MU_CNT = "1" *) 
  (* LC_PROBE988_PID = "16'b0000001111011100" *) 
  (* LC_PROBE988_TYPE = "1" *) 
  (* LC_PROBE988_WIDTH = "1" *) 
  (* LC_PROBE989_IS_DATA = "1'b0" *) 
  (* LC_PROBE989_IS_TRIG = "1'b0" *) 
  (* LC_PROBE989_MU_CNT = "1" *) 
  (* LC_PROBE989_PID = "16'b0000001111011101" *) 
  (* LC_PROBE989_TYPE = "1" *) 
  (* LC_PROBE989_WIDTH = "1" *) 
  (* LC_PROBE98_IS_DATA = "1'b0" *) 
  (* LC_PROBE98_IS_TRIG = "1'b0" *) 
  (* LC_PROBE98_MU_CNT = "1" *) 
  (* LC_PROBE98_PID = "16'b0000000001100010" *) 
  (* LC_PROBE98_TYPE = "1" *) 
  (* LC_PROBE98_WIDTH = "1" *) 
  (* LC_PROBE990_IS_DATA = "1'b0" *) 
  (* LC_PROBE990_IS_TRIG = "1'b0" *) 
  (* LC_PROBE990_MU_CNT = "1" *) 
  (* LC_PROBE990_PID = "16'b0000001111011110" *) 
  (* LC_PROBE990_TYPE = "1" *) 
  (* LC_PROBE990_WIDTH = "1" *) 
  (* LC_PROBE991_IS_DATA = "1'b0" *) 
  (* LC_PROBE991_IS_TRIG = "1'b0" *) 
  (* LC_PROBE991_MU_CNT = "1" *) 
  (* LC_PROBE991_PID = "16'b0000001111011111" *) 
  (* LC_PROBE991_TYPE = "1" *) 
  (* LC_PROBE991_WIDTH = "1" *) 
  (* LC_PROBE992_IS_DATA = "1'b0" *) 
  (* LC_PROBE992_IS_TRIG = "1'b0" *) 
  (* LC_PROBE992_MU_CNT = "1" *) 
  (* LC_PROBE992_PID = "16'b0000001111100000" *) 
  (* LC_PROBE992_TYPE = "1" *) 
  (* LC_PROBE992_WIDTH = "1" *) 
  (* LC_PROBE993_IS_DATA = "1'b0" *) 
  (* LC_PROBE993_IS_TRIG = "1'b0" *) 
  (* LC_PROBE993_MU_CNT = "1" *) 
  (* LC_PROBE993_PID = "16'b0000001111100001" *) 
  (* LC_PROBE993_TYPE = "1" *) 
  (* LC_PROBE993_WIDTH = "1" *) 
  (* LC_PROBE994_IS_DATA = "1'b0" *) 
  (* LC_PROBE994_IS_TRIG = "1'b0" *) 
  (* LC_PROBE994_MU_CNT = "1" *) 
  (* LC_PROBE994_PID = "16'b0000001111100010" *) 
  (* LC_PROBE994_TYPE = "1" *) 
  (* LC_PROBE994_WIDTH = "1" *) 
  (* LC_PROBE995_IS_DATA = "1'b0" *) 
  (* LC_PROBE995_IS_TRIG = "1'b0" *) 
  (* LC_PROBE995_MU_CNT = "1" *) 
  (* LC_PROBE995_PID = "16'b0000001111100011" *) 
  (* LC_PROBE995_TYPE = "1" *) 
  (* LC_PROBE995_WIDTH = "1" *) 
  (* LC_PROBE996_IS_DATA = "1'b0" *) 
  (* LC_PROBE996_IS_TRIG = "1'b0" *) 
  (* LC_PROBE996_MU_CNT = "1" *) 
  (* LC_PROBE996_PID = "16'b0000001111100100" *) 
  (* LC_PROBE996_TYPE = "1" *) 
  (* LC_PROBE996_WIDTH = "1" *) 
  (* LC_PROBE997_IS_DATA = "1'b0" *) 
  (* LC_PROBE997_IS_TRIG = "1'b0" *) 
  (* LC_PROBE997_MU_CNT = "1" *) 
  (* LC_PROBE997_PID = "16'b0000001111100101" *) 
  (* LC_PROBE997_TYPE = "1" *) 
  (* LC_PROBE997_WIDTH = "1" *) 
  (* LC_PROBE998_IS_DATA = "1'b0" *) 
  (* LC_PROBE998_IS_TRIG = "1'b0" *) 
  (* LC_PROBE998_MU_CNT = "1" *) 
  (* LC_PROBE998_PID = "16'b0000001111100110" *) 
  (* LC_PROBE998_TYPE = "1" *) 
  (* LC_PROBE998_WIDTH = "1" *) 
  (* LC_PROBE999_IS_DATA = "1'b0" *) 
  (* LC_PROBE999_IS_TRIG = "1'b0" *) 
  (* LC_PROBE999_MU_CNT = "1" *) 
  (* LC_PROBE999_PID = "16'b0000001111100111" *) 
  (* LC_PROBE999_TYPE = "1" *) 
  (* LC_PROBE999_WIDTH = "1" *) 
  (* LC_PROBE99_IS_DATA = "1'b0" *) 
  (* LC_PROBE99_IS_TRIG = "1'b0" *) 
  (* LC_PROBE99_MU_CNT = "1" *) 
  (* LC_PROBE99_PID = "16'b0000000001100011" *) 
  (* LC_PROBE99_TYPE = "1" *) 
  (* LC_PROBE99_WIDTH = "1" *) 
  (* LC_PROBE9_IS_DATA = "1'b0" *) 
  (* LC_PROBE9_IS_TRIG = "1'b0" *) 
  (* LC_PROBE9_MU_CNT = "1" *) 
  (* LC_PROBE9_PID = "16'b0000000000001001" *) 
  (* LC_PROBE9_TYPE = "1" *) 
  (* LC_PROBE9_WIDTH = "1" *) 
  (* LC_PROBES_WIDTH = "65" *) 
  (* LC_PROBE_IS_DATA_STRING = "1024'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111" *) 
  (* LC_PROBE_IS_TRIG_STRING = "4096' " *) 
  (* LC_PROBE_WIDTH_STRING = "16384' " *) 
  (* LC_TIME_TAG_MU_CNT = "2" *) 
  (* LC_TIME_TAG_TYPE = "0" *) 
  (* LC_TIME_TAG_WIDTH = "1" *) 
  (* LC_TRIG_WIDTH = "65" *) 
  (* syn_noprune = "1" *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila inst
       (.clk(clk),
        .clk_nobuf(1'b0),
        .clkdiv_out(NLW_inst_clkdiv_out_UNCONNECTED),
        .probe0(probe0),
        .probe1(probe1),
        .probe10(1'b0),
        .probe100(1'b0),
        .probe1000(1'b0),
        .probe1001(1'b0),
        .probe1002(1'b0),
        .probe1003(1'b0),
        .probe1004(1'b0),
        .probe1005(1'b0),
        .probe1006(1'b0),
        .probe1007(1'b0),
        .probe1008(1'b0),
        .probe1009(1'b0),
        .probe101(1'b0),
        .probe1010(1'b0),
        .probe1011(1'b0),
        .probe1012(1'b0),
        .probe1013(1'b0),
        .probe1014(1'b0),
        .probe1015(1'b0),
        .probe1016(1'b0),
        .probe1017(1'b0),
        .probe1018(1'b0),
        .probe1019(1'b0),
        .probe102(1'b0),
        .probe1020(1'b0),
        .probe1021(1'b0),
        .probe1022(1'b0),
        .probe1023(1'b0),
        .probe103(1'b0),
        .probe104(1'b0),
        .probe105(1'b0),
        .probe106(1'b0),
        .probe107(1'b0),
        .probe108(1'b0),
        .probe109(1'b0),
        .probe11(1'b0),
        .probe110(1'b0),
        .probe111(1'b0),
        .probe112(1'b0),
        .probe113(1'b0),
        .probe114(1'b0),
        .probe115(1'b0),
        .probe116(1'b0),
        .probe117(1'b0),
        .probe118(1'b0),
        .probe119(1'b0),
        .probe12(1'b0),
        .probe120(1'b0),
        .probe121(1'b0),
        .probe122(1'b0),
        .probe123(1'b0),
        .probe124(1'b0),
        .probe125(1'b0),
        .probe126(1'b0),
        .probe127(1'b0),
        .probe128(1'b0),
        .probe129(1'b0),
        .probe13(1'b0),
        .probe130(1'b0),
        .probe131(1'b0),
        .probe132(1'b0),
        .probe133(1'b0),
        .probe134(1'b0),
        .probe135(1'b0),
        .probe136(1'b0),
        .probe137(1'b0),
        .probe138(1'b0),
        .probe139(1'b0),
        .probe14(1'b0),
        .probe140(1'b0),
        .probe141(1'b0),
        .probe142(1'b0),
        .probe143(1'b0),
        .probe144(1'b0),
        .probe145(1'b0),
        .probe146(1'b0),
        .probe147(1'b0),
        .probe148(1'b0),
        .probe149(1'b0),
        .probe15(1'b0),
        .probe150(1'b0),
        .probe151(1'b0),
        .probe152(1'b0),
        .probe153(1'b0),
        .probe154(1'b0),
        .probe155(1'b0),
        .probe156(1'b0),
        .probe157(1'b0),
        .probe158(1'b0),
        .probe159(1'b0),
        .probe16(1'b0),
        .probe160(1'b0),
        .probe161(1'b0),
        .probe162(1'b0),
        .probe163(1'b0),
        .probe164(1'b0),
        .probe165(1'b0),
        .probe166(1'b0),
        .probe167(1'b0),
        .probe168(1'b0),
        .probe169(1'b0),
        .probe17(1'b0),
        .probe170(1'b0),
        .probe171(1'b0),
        .probe172(1'b0),
        .probe173(1'b0),
        .probe174(1'b0),
        .probe175(1'b0),
        .probe176(1'b0),
        .probe177(1'b0),
        .probe178(1'b0),
        .probe179(1'b0),
        .probe18(1'b0),
        .probe180(1'b0),
        .probe181(1'b0),
        .probe182(1'b0),
        .probe183(1'b0),
        .probe184(1'b0),
        .probe185(1'b0),
        .probe186(1'b0),
        .probe187(1'b0),
        .probe188(1'b0),
        .probe189(1'b0),
        .probe19(1'b0),
        .probe190(1'b0),
        .probe191(1'b0),
        .probe192(1'b0),
        .probe193(1'b0),
        .probe194(1'b0),
        .probe195(1'b0),
        .probe196(1'b0),
        .probe197(1'b0),
        .probe198(1'b0),
        .probe199(1'b0),
        .probe2(probe2),
        .probe20(1'b0),
        .probe200(1'b0),
        .probe201(1'b0),
        .probe202(1'b0),
        .probe203(1'b0),
        .probe204(1'b0),
        .probe205(1'b0),
        .probe206(1'b0),
        .probe207(1'b0),
        .probe208(1'b0),
        .probe209(1'b0),
        .probe21(1'b0),
        .probe210(1'b0),
        .probe211(1'b0),
        .probe212(1'b0),
        .probe213(1'b0),
        .probe214(1'b0),
        .probe215(1'b0),
        .probe216(1'b0),
        .probe217(1'b0),
        .probe218(1'b0),
        .probe219(1'b0),
        .probe22(1'b0),
        .probe220(1'b0),
        .probe221(1'b0),
        .probe222(1'b0),
        .probe223(1'b0),
        .probe224(1'b0),
        .probe225(1'b0),
        .probe226(1'b0),
        .probe227(1'b0),
        .probe228(1'b0),
        .probe229(1'b0),
        .probe23(1'b0),
        .probe230(1'b0),
        .probe231(1'b0),
        .probe232(1'b0),
        .probe233(1'b0),
        .probe234(1'b0),
        .probe235(1'b0),
        .probe236(1'b0),
        .probe237(1'b0),
        .probe238(1'b0),
        .probe239(1'b0),
        .probe24(1'b0),
        .probe240(1'b0),
        .probe241(1'b0),
        .probe242(1'b0),
        .probe243(1'b0),
        .probe244(1'b0),
        .probe245(1'b0),
        .probe246(1'b0),
        .probe247(1'b0),
        .probe248(1'b0),
        .probe249(1'b0),
        .probe25(1'b0),
        .probe250(1'b0),
        .probe251(1'b0),
        .probe252(1'b0),
        .probe253(1'b0),
        .probe254(1'b0),
        .probe255(1'b0),
        .probe256(1'b0),
        .probe257(1'b0),
        .probe258(1'b0),
        .probe259(1'b0),
        .probe26(1'b0),
        .probe260(1'b0),
        .probe261(1'b0),
        .probe262(1'b0),
        .probe263(1'b0),
        .probe264(1'b0),
        .probe265(1'b0),
        .probe266(1'b0),
        .probe267(1'b0),
        .probe268(1'b0),
        .probe269(1'b0),
        .probe27(1'b0),
        .probe270(1'b0),
        .probe271(1'b0),
        .probe272(1'b0),
        .probe273(1'b0),
        .probe274(1'b0),
        .probe275(1'b0),
        .probe276(1'b0),
        .probe277(1'b0),
        .probe278(1'b0),
        .probe279(1'b0),
        .probe28(1'b0),
        .probe280(1'b0),
        .probe281(1'b0),
        .probe282(1'b0),
        .probe283(1'b0),
        .probe284(1'b0),
        .probe285(1'b0),
        .probe286(1'b0),
        .probe287(1'b0),
        .probe288(1'b0),
        .probe289(1'b0),
        .probe29(1'b0),
        .probe290(1'b0),
        .probe291(1'b0),
        .probe292(1'b0),
        .probe293(1'b0),
        .probe294(1'b0),
        .probe295(1'b0),
        .probe296(1'b0),
        .probe297(1'b0),
        .probe298(1'b0),
        .probe299(1'b0),
        .probe3(1'b0),
        .probe30(1'b0),
        .probe300(1'b0),
        .probe301(1'b0),
        .probe302(1'b0),
        .probe303(1'b0),
        .probe304(1'b0),
        .probe305(1'b0),
        .probe306(1'b0),
        .probe307(1'b0),
        .probe308(1'b0),
        .probe309(1'b0),
        .probe31(1'b0),
        .probe310(1'b0),
        .probe311(1'b0),
        .probe312(1'b0),
        .probe313(1'b0),
        .probe314(1'b0),
        .probe315(1'b0),
        .probe316(1'b0),
        .probe317(1'b0),
        .probe318(1'b0),
        .probe319(1'b0),
        .probe32(1'b0),
        .probe320(1'b0),
        .probe321(1'b0),
        .probe322(1'b0),
        .probe323(1'b0),
        .probe324(1'b0),
        .probe325(1'b0),
        .probe326(1'b0),
        .probe327(1'b0),
        .probe328(1'b0),
        .probe329(1'b0),
        .probe33(1'b0),
        .probe330(1'b0),
        .probe331(1'b0),
        .probe332(1'b0),
        .probe333(1'b0),
        .probe334(1'b0),
        .probe335(1'b0),
        .probe336(1'b0),
        .probe337(1'b0),
        .probe338(1'b0),
        .probe339(1'b0),
        .probe34(1'b0),
        .probe340(1'b0),
        .probe341(1'b0),
        .probe342(1'b0),
        .probe343(1'b0),
        .probe344(1'b0),
        .probe345(1'b0),
        .probe346(1'b0),
        .probe347(1'b0),
        .probe348(1'b0),
        .probe349(1'b0),
        .probe35(1'b0),
        .probe350(1'b0),
        .probe351(1'b0),
        .probe352(1'b0),
        .probe353(1'b0),
        .probe354(1'b0),
        .probe355(1'b0),
        .probe356(1'b0),
        .probe357(1'b0),
        .probe358(1'b0),
        .probe359(1'b0),
        .probe36(1'b0),
        .probe360(1'b0),
        .probe361(1'b0),
        .probe362(1'b0),
        .probe363(1'b0),
        .probe364(1'b0),
        .probe365(1'b0),
        .probe366(1'b0),
        .probe367(1'b0),
        .probe368(1'b0),
        .probe369(1'b0),
        .probe37(1'b0),
        .probe370(1'b0),
        .probe371(1'b0),
        .probe372(1'b0),
        .probe373(1'b0),
        .probe374(1'b0),
        .probe375(1'b0),
        .probe376(1'b0),
        .probe377(1'b0),
        .probe378(1'b0),
        .probe379(1'b0),
        .probe38(1'b0),
        .probe380(1'b0),
        .probe381(1'b0),
        .probe382(1'b0),
        .probe383(1'b0),
        .probe384(1'b0),
        .probe385(1'b0),
        .probe386(1'b0),
        .probe387(1'b0),
        .probe388(1'b0),
        .probe389(1'b0),
        .probe39(1'b0),
        .probe390(1'b0),
        .probe391(1'b0),
        .probe392(1'b0),
        .probe393(1'b0),
        .probe394(1'b0),
        .probe395(1'b0),
        .probe396(1'b0),
        .probe397(1'b0),
        .probe398(1'b0),
        .probe399(1'b0),
        .probe4(1'b0),
        .probe40(1'b0),
        .probe400(1'b0),
        .probe401(1'b0),
        .probe402(1'b0),
        .probe403(1'b0),
        .probe404(1'b0),
        .probe405(1'b0),
        .probe406(1'b0),
        .probe407(1'b0),
        .probe408(1'b0),
        .probe409(1'b0),
        .probe41(1'b0),
        .probe410(1'b0),
        .probe411(1'b0),
        .probe412(1'b0),
        .probe413(1'b0),
        .probe414(1'b0),
        .probe415(1'b0),
        .probe416(1'b0),
        .probe417(1'b0),
        .probe418(1'b0),
        .probe419(1'b0),
        .probe42(1'b0),
        .probe420(1'b0),
        .probe421(1'b0),
        .probe422(1'b0),
        .probe423(1'b0),
        .probe424(1'b0),
        .probe425(1'b0),
        .probe426(1'b0),
        .probe427(1'b0),
        .probe428(1'b0),
        .probe429(1'b0),
        .probe43(1'b0),
        .probe430(1'b0),
        .probe431(1'b0),
        .probe432(1'b0),
        .probe433(1'b0),
        .probe434(1'b0),
        .probe435(1'b0),
        .probe436(1'b0),
        .probe437(1'b0),
        .probe438(1'b0),
        .probe439(1'b0),
        .probe44(1'b0),
        .probe440(1'b0),
        .probe441(1'b0),
        .probe442(1'b0),
        .probe443(1'b0),
        .probe444(1'b0),
        .probe445(1'b0),
        .probe446(1'b0),
        .probe447(1'b0),
        .probe448(1'b0),
        .probe449(1'b0),
        .probe45(1'b0),
        .probe450(1'b0),
        .probe451(1'b0),
        .probe452(1'b0),
        .probe453(1'b0),
        .probe454(1'b0),
        .probe455(1'b0),
        .probe456(1'b0),
        .probe457(1'b0),
        .probe458(1'b0),
        .probe459(1'b0),
        .probe46(1'b0),
        .probe460(1'b0),
        .probe461(1'b0),
        .probe462(1'b0),
        .probe463(1'b0),
        .probe464(1'b0),
        .probe465(1'b0),
        .probe466(1'b0),
        .probe467(1'b0),
        .probe468(1'b0),
        .probe469(1'b0),
        .probe47(1'b0),
        .probe470(1'b0),
        .probe471(1'b0),
        .probe472(1'b0),
        .probe473(1'b0),
        .probe474(1'b0),
        .probe475(1'b0),
        .probe476(1'b0),
        .probe477(1'b0),
        .probe478(1'b0),
        .probe479(1'b0),
        .probe48(1'b0),
        .probe480(1'b0),
        .probe481(1'b0),
        .probe482(1'b0),
        .probe483(1'b0),
        .probe484(1'b0),
        .probe485(1'b0),
        .probe486(1'b0),
        .probe487(1'b0),
        .probe488(1'b0),
        .probe489(1'b0),
        .probe49(1'b0),
        .probe490(1'b0),
        .probe491(1'b0),
        .probe492(1'b0),
        .probe493(1'b0),
        .probe494(1'b0),
        .probe495(1'b0),
        .probe496(1'b0),
        .probe497(1'b0),
        .probe498(1'b0),
        .probe499(1'b0),
        .probe5(1'b0),
        .probe50(1'b0),
        .probe500(1'b0),
        .probe501(1'b0),
        .probe502(1'b0),
        .probe503(1'b0),
        .probe504(1'b0),
        .probe505(1'b0),
        .probe506(1'b0),
        .probe507(1'b0),
        .probe508(1'b0),
        .probe509(1'b0),
        .probe51(1'b0),
        .probe510(1'b0),
        .probe511(1'b0),
        .probe512(1'b0),
        .probe513(1'b0),
        .probe514(1'b0),
        .probe515(1'b0),
        .probe516(1'b0),
        .probe517(1'b0),
        .probe518(1'b0),
        .probe519(1'b0),
        .probe52(1'b0),
        .probe520(1'b0),
        .probe521(1'b0),
        .probe522(1'b0),
        .probe523(1'b0),
        .probe524(1'b0),
        .probe525(1'b0),
        .probe526(1'b0),
        .probe527(1'b0),
        .probe528(1'b0),
        .probe529(1'b0),
        .probe53(1'b0),
        .probe530(1'b0),
        .probe531(1'b0),
        .probe532(1'b0),
        .probe533(1'b0),
        .probe534(1'b0),
        .probe535(1'b0),
        .probe536(1'b0),
        .probe537(1'b0),
        .probe538(1'b0),
        .probe539(1'b0),
        .probe54(1'b0),
        .probe540(1'b0),
        .probe541(1'b0),
        .probe542(1'b0),
        .probe543(1'b0),
        .probe544(1'b0),
        .probe545(1'b0),
        .probe546(1'b0),
        .probe547(1'b0),
        .probe548(1'b0),
        .probe549(1'b0),
        .probe55(1'b0),
        .probe550(1'b0),
        .probe551(1'b0),
        .probe552(1'b0),
        .probe553(1'b0),
        .probe554(1'b0),
        .probe555(1'b0),
        .probe556(1'b0),
        .probe557(1'b0),
        .probe558(1'b0),
        .probe559(1'b0),
        .probe56(1'b0),
        .probe560(1'b0),
        .probe561(1'b0),
        .probe562(1'b0),
        .probe563(1'b0),
        .probe564(1'b0),
        .probe565(1'b0),
        .probe566(1'b0),
        .probe567(1'b0),
        .probe568(1'b0),
        .probe569(1'b0),
        .probe57(1'b0),
        .probe570(1'b0),
        .probe571(1'b0),
        .probe572(1'b0),
        .probe573(1'b0),
        .probe574(1'b0),
        .probe575(1'b0),
        .probe576(1'b0),
        .probe577(1'b0),
        .probe578(1'b0),
        .probe579(1'b0),
        .probe58(1'b0),
        .probe580(1'b0),
        .probe581(1'b0),
        .probe582(1'b0),
        .probe583(1'b0),
        .probe584(1'b0),
        .probe585(1'b0),
        .probe586(1'b0),
        .probe587(1'b0),
        .probe588(1'b0),
        .probe589(1'b0),
        .probe59(1'b0),
        .probe590(1'b0),
        .probe591(1'b0),
        .probe592(1'b0),
        .probe593(1'b0),
        .probe594(1'b0),
        .probe595(1'b0),
        .probe596(1'b0),
        .probe597(1'b0),
        .probe598(1'b0),
        .probe599(1'b0),
        .probe6(1'b0),
        .probe60(1'b0),
        .probe600(1'b0),
        .probe601(1'b0),
        .probe602(1'b0),
        .probe603(1'b0),
        .probe604(1'b0),
        .probe605(1'b0),
        .probe606(1'b0),
        .probe607(1'b0),
        .probe608(1'b0),
        .probe609(1'b0),
        .probe61(1'b0),
        .probe610(1'b0),
        .probe611(1'b0),
        .probe612(1'b0),
        .probe613(1'b0),
        .probe614(1'b0),
        .probe615(1'b0),
        .probe616(1'b0),
        .probe617(1'b0),
        .probe618(1'b0),
        .probe619(1'b0),
        .probe62(1'b0),
        .probe620(1'b0),
        .probe621(1'b0),
        .probe622(1'b0),
        .probe623(1'b0),
        .probe624(1'b0),
        .probe625(1'b0),
        .probe626(1'b0),
        .probe627(1'b0),
        .probe628(1'b0),
        .probe629(1'b0),
        .probe63(1'b0),
        .probe630(1'b0),
        .probe631(1'b0),
        .probe632(1'b0),
        .probe633(1'b0),
        .probe634(1'b0),
        .probe635(1'b0),
        .probe636(1'b0),
        .probe637(1'b0),
        .probe638(1'b0),
        .probe639(1'b0),
        .probe64(1'b0),
        .probe640(1'b0),
        .probe641(1'b0),
        .probe642(1'b0),
        .probe643(1'b0),
        .probe644(1'b0),
        .probe645(1'b0),
        .probe646(1'b0),
        .probe647(1'b0),
        .probe648(1'b0),
        .probe649(1'b0),
        .probe65(1'b0),
        .probe650(1'b0),
        .probe651(1'b0),
        .probe652(1'b0),
        .probe653(1'b0),
        .probe654(1'b0),
        .probe655(1'b0),
        .probe656(1'b0),
        .probe657(1'b0),
        .probe658(1'b0),
        .probe659(1'b0),
        .probe66(1'b0),
        .probe660(1'b0),
        .probe661(1'b0),
        .probe662(1'b0),
        .probe663(1'b0),
        .probe664(1'b0),
        .probe665(1'b0),
        .probe666(1'b0),
        .probe667(1'b0),
        .probe668(1'b0),
        .probe669(1'b0),
        .probe67(1'b0),
        .probe670(1'b0),
        .probe671(1'b0),
        .probe672(1'b0),
        .probe673(1'b0),
        .probe674(1'b0),
        .probe675(1'b0),
        .probe676(1'b0),
        .probe677(1'b0),
        .probe678(1'b0),
        .probe679(1'b0),
        .probe68(1'b0),
        .probe680(1'b0),
        .probe681(1'b0),
        .probe682(1'b0),
        .probe683(1'b0),
        .probe684(1'b0),
        .probe685(1'b0),
        .probe686(1'b0),
        .probe687(1'b0),
        .probe688(1'b0),
        .probe689(1'b0),
        .probe69(1'b0),
        .probe690(1'b0),
        .probe691(1'b0),
        .probe692(1'b0),
        .probe693(1'b0),
        .probe694(1'b0),
        .probe695(1'b0),
        .probe696(1'b0),
        .probe697(1'b0),
        .probe698(1'b0),
        .probe699(1'b0),
        .probe7(1'b0),
        .probe70(1'b0),
        .probe700(1'b0),
        .probe701(1'b0),
        .probe702(1'b0),
        .probe703(1'b0),
        .probe704(1'b0),
        .probe705(1'b0),
        .probe706(1'b0),
        .probe707(1'b0),
        .probe708(1'b0),
        .probe709(1'b0),
        .probe71(1'b0),
        .probe710(1'b0),
        .probe711(1'b0),
        .probe712(1'b0),
        .probe713(1'b0),
        .probe714(1'b0),
        .probe715(1'b0),
        .probe716(1'b0),
        .probe717(1'b0),
        .probe718(1'b0),
        .probe719(1'b0),
        .probe72(1'b0),
        .probe720(1'b0),
        .probe721(1'b0),
        .probe722(1'b0),
        .probe723(1'b0),
        .probe724(1'b0),
        .probe725(1'b0),
        .probe726(1'b0),
        .probe727(1'b0),
        .probe728(1'b0),
        .probe729(1'b0),
        .probe73(1'b0),
        .probe730(1'b0),
        .probe731(1'b0),
        .probe732(1'b0),
        .probe733(1'b0),
        .probe734(1'b0),
        .probe735(1'b0),
        .probe736(1'b0),
        .probe737(1'b0),
        .probe738(1'b0),
        .probe739(1'b0),
        .probe74(1'b0),
        .probe740(1'b0),
        .probe741(1'b0),
        .probe742(1'b0),
        .probe743(1'b0),
        .probe744(1'b0),
        .probe745(1'b0),
        .probe746(1'b0),
        .probe747(1'b0),
        .probe748(1'b0),
        .probe749(1'b0),
        .probe75(1'b0),
        .probe750(1'b0),
        .probe751(1'b0),
        .probe752(1'b0),
        .probe753(1'b0),
        .probe754(1'b0),
        .probe755(1'b0),
        .probe756(1'b0),
        .probe757(1'b0),
        .probe758(1'b0),
        .probe759(1'b0),
        .probe76(1'b0),
        .probe760(1'b0),
        .probe761(1'b0),
        .probe762(1'b0),
        .probe763(1'b0),
        .probe764(1'b0),
        .probe765(1'b0),
        .probe766(1'b0),
        .probe767(1'b0),
        .probe768(1'b0),
        .probe769(1'b0),
        .probe77(1'b0),
        .probe770(1'b0),
        .probe771(1'b0),
        .probe772(1'b0),
        .probe773(1'b0),
        .probe774(1'b0),
        .probe775(1'b0),
        .probe776(1'b0),
        .probe777(1'b0),
        .probe778(1'b0),
        .probe779(1'b0),
        .probe78(1'b0),
        .probe780(1'b0),
        .probe781(1'b0),
        .probe782(1'b0),
        .probe783(1'b0),
        .probe784(1'b0),
        .probe785(1'b0),
        .probe786(1'b0),
        .probe787(1'b0),
        .probe788(1'b0),
        .probe789(1'b0),
        .probe79(1'b0),
        .probe790(1'b0),
        .probe791(1'b0),
        .probe792(1'b0),
        .probe793(1'b0),
        .probe794(1'b0),
        .probe795(1'b0),
        .probe796(1'b0),
        .probe797(1'b0),
        .probe798(1'b0),
        .probe799(1'b0),
        .probe8(1'b0),
        .probe80(1'b0),
        .probe800(1'b0),
        .probe801(1'b0),
        .probe802(1'b0),
        .probe803(1'b0),
        .probe804(1'b0),
        .probe805(1'b0),
        .probe806(1'b0),
        .probe807(1'b0),
        .probe808(1'b0),
        .probe809(1'b0),
        .probe81(1'b0),
        .probe810(1'b0),
        .probe811(1'b0),
        .probe812(1'b0),
        .probe813(1'b0),
        .probe814(1'b0),
        .probe815(1'b0),
        .probe816(1'b0),
        .probe817(1'b0),
        .probe818(1'b0),
        .probe819(1'b0),
        .probe82(1'b0),
        .probe820(1'b0),
        .probe821(1'b0),
        .probe822(1'b0),
        .probe823(1'b0),
        .probe824(1'b0),
        .probe825(1'b0),
        .probe826(1'b0),
        .probe827(1'b0),
        .probe828(1'b0),
        .probe829(1'b0),
        .probe83(1'b0),
        .probe830(1'b0),
        .probe831(1'b0),
        .probe832(1'b0),
        .probe833(1'b0),
        .probe834(1'b0),
        .probe835(1'b0),
        .probe836(1'b0),
        .probe837(1'b0),
        .probe838(1'b0),
        .probe839(1'b0),
        .probe84(1'b0),
        .probe840(1'b0),
        .probe841(1'b0),
        .probe842(1'b0),
        .probe843(1'b0),
        .probe844(1'b0),
        .probe845(1'b0),
        .probe846(1'b0),
        .probe847(1'b0),
        .probe848(1'b0),
        .probe849(1'b0),
        .probe85(1'b0),
        .probe850(1'b0),
        .probe851(1'b0),
        .probe852(1'b0),
        .probe853(1'b0),
        .probe854(1'b0),
        .probe855(1'b0),
        .probe856(1'b0),
        .probe857(1'b0),
        .probe858(1'b0),
        .probe859(1'b0),
        .probe86(1'b0),
        .probe860(1'b0),
        .probe861(1'b0),
        .probe862(1'b0),
        .probe863(1'b0),
        .probe864(1'b0),
        .probe865(1'b0),
        .probe866(1'b0),
        .probe867(1'b0),
        .probe868(1'b0),
        .probe869(1'b0),
        .probe87(1'b0),
        .probe870(1'b0),
        .probe871(1'b0),
        .probe872(1'b0),
        .probe873(1'b0),
        .probe874(1'b0),
        .probe875(1'b0),
        .probe876(1'b0),
        .probe877(1'b0),
        .probe878(1'b0),
        .probe879(1'b0),
        .probe88(1'b0),
        .probe880(1'b0),
        .probe881(1'b0),
        .probe882(1'b0),
        .probe883(1'b0),
        .probe884(1'b0),
        .probe885(1'b0),
        .probe886(1'b0),
        .probe887(1'b0),
        .probe888(1'b0),
        .probe889(1'b0),
        .probe89(1'b0),
        .probe890(1'b0),
        .probe891(1'b0),
        .probe892(1'b0),
        .probe893(1'b0),
        .probe894(1'b0),
        .probe895(1'b0),
        .probe896(1'b0),
        .probe897(1'b0),
        .probe898(1'b0),
        .probe899(1'b0),
        .probe9(1'b0),
        .probe90(1'b0),
        .probe900(1'b0),
        .probe901(1'b0),
        .probe902(1'b0),
        .probe903(1'b0),
        .probe904(1'b0),
        .probe905(1'b0),
        .probe906(1'b0),
        .probe907(1'b0),
        .probe908(1'b0),
        .probe909(1'b0),
        .probe91(1'b0),
        .probe910(1'b0),
        .probe911(1'b0),
        .probe912(1'b0),
        .probe913(1'b0),
        .probe914(1'b0),
        .probe915(1'b0),
        .probe916(1'b0),
        .probe917(1'b0),
        .probe918(1'b0),
        .probe919(1'b0),
        .probe92(1'b0),
        .probe920(1'b0),
        .probe921(1'b0),
        .probe922(1'b0),
        .probe923(1'b0),
        .probe924(1'b0),
        .probe925(1'b0),
        .probe926(1'b0),
        .probe927(1'b0),
        .probe928(1'b0),
        .probe929(1'b0),
        .probe93(1'b0),
        .probe930(1'b0),
        .probe931(1'b0),
        .probe932(1'b0),
        .probe933(1'b0),
        .probe934(1'b0),
        .probe935(1'b0),
        .probe936(1'b0),
        .probe937(1'b0),
        .probe938(1'b0),
        .probe939(1'b0),
        .probe94(1'b0),
        .probe940(1'b0),
        .probe941(1'b0),
        .probe942(1'b0),
        .probe943(1'b0),
        .probe944(1'b0),
        .probe945(1'b0),
        .probe946(1'b0),
        .probe947(1'b0),
        .probe948(1'b0),
        .probe949(1'b0),
        .probe95(1'b0),
        .probe950(1'b0),
        .probe951(1'b0),
        .probe952(1'b0),
        .probe953(1'b0),
        .probe954(1'b0),
        .probe955(1'b0),
        .probe956(1'b0),
        .probe957(1'b0),
        .probe958(1'b0),
        .probe959(1'b0),
        .probe96(1'b0),
        .probe960(1'b0),
        .probe961(1'b0),
        .probe962(1'b0),
        .probe963(1'b0),
        .probe964(1'b0),
        .probe965(1'b0),
        .probe966(1'b0),
        .probe967(1'b0),
        .probe968(1'b0),
        .probe969(1'b0),
        .probe97(1'b0),
        .probe970(1'b0),
        .probe971(1'b0),
        .probe972(1'b0),
        .probe973(1'b0),
        .probe974(1'b0),
        .probe975(1'b0),
        .probe976(1'b0),
        .probe977(1'b0),
        .probe978(1'b0),
        .probe979(1'b0),
        .probe98(1'b0),
        .probe980(1'b0),
        .probe981(1'b0),
        .probe982(1'b0),
        .probe983(1'b0),
        .probe984(1'b0),
        .probe985(1'b0),
        .probe986(1'b0),
        .probe987(1'b0),
        .probe988(1'b0),
        .probe989(1'b0),
        .probe99(1'b0),
        .probe990(1'b0),
        .probe991(1'b0),
        .probe992(1'b0),
        .probe993(1'b0),
        .probe994(1'b0),
        .probe995(1'b0),
        .probe996(1'b0),
        .probe997(1'b0),
        .probe998(1'b0),
        .probe999(1'b0),
        .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]),
        .trig_in(1'b0),
        .trig_in_ack(NLW_inst_trig_in_ack_UNCONNECTED),
        .trig_out(NLW_inst_trig_out_UNCONNECTED),
        .trig_out_ack(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    DIADI,
    DIPADIP,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 );
  output [65:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;

  wire [65:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r 
       (.D(D[35:0]),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .DIADI(DIADI),
        .DIPADIP(DIPADIP),
        .Q(Q),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r 
       (.D(D[65:36]),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
        .Q(Q),
        .out(out));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    DIADI,
    DIPADIP);
  output [35:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;

  wire [35:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram 
       (.D(D),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .DIADI(DIADI),
        .DIPADIP(DIPADIP),
        .Q(Q),
        .out(out));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 );
  output [29:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;

  wire [29:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram 
       (.D(D),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
        .Q(Q),
        .out(out));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ,
    Q,
    DIADI,
    DIPADIP);
  output [35:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;

  wire [35:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
  wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
  wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(36),
    .RSTREG_PRIORITY_A("REGCE"),
    .RSTREG_PRIORITY_B("REGCE"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(36),
    .WRITE_WIDTH_B(36)) 
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
       (.ADDRARDADDR({1'b1,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .CLKBWRCLK(out),
        .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
        .DIADI(DIADI),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP(DIPADIP),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
        .DOBDO({D[34:27],D[25:18],D[16:9],D[7:0]}),
        .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
        .DOPBDOP({D[35],D[26],D[17],D[8]}),
        .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ,
    Q,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 );
  output [29:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  input [9:0]Q;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ;

  wire [29:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_36 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_52 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_72 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_73 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_74 ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_75 ;
  wire [9:0]Q;
  wire [0:0]out;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
  wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
  wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;

  (* box_type = "PRIMITIVE" *) 
  RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(36),
    .RSTREG_PRIORITY_A("REGCE"),
    .RSTREG_PRIORITY_B("REGCE"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(36),
    .WRITE_WIDTH_B(36)) 
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
       (.ADDRARDADDR({1'b1,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .CLKBWRCLK(out),
        .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
        .DIADI({1'b0,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [29:15],1'b0,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4 [14:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,1'b0,1'b0}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
        .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_36 ,D[29:15],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_52 ,D[14:0]}),
        .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
        .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_72 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_73 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_74 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_75 }),
        .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    DIADI,
    DIPADIP,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 );
  output [65:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;

  wire [65:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr 
       (.D(D),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
        .DIADI(DIADI),
        .DIPADIP(DIPADIP),
        .Q(Q),
        .out(out));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    DIADI,
    DIPADIP,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 );
  output [65:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;

  wire [65:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
       (.D(D),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
        .DIADI(DIADI),
        .DIPADIP(DIPADIP),
        .Q(Q),
        .out(out));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    DIADI,
    DIPADIP,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 );
  output [65:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;

  wire [65:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen 
       (.D(D),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
        .DIADI(DIADI),
        .DIPADIP(DIPADIP),
        .Q(Q),
        .out(out));
endmodule

(* CNT_MAX = "17'b10000000000000000" *) (* C_COUNTER_WIDTH = "17" *) (* dont_touch = "true" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [15:0]counter;
  wire [16:1]counter0;
  wire \counter[16]_i_1_n_0 ;
  wire \counter[16]_i_3_n_0 ;
  wire \counter_load_i_reg[17]_srl15_n_0 ;
  wire \counter_reg[12]_i_2_n_0 ;
  wire \counter_reg[12]_i_2_n_1 ;
  wire \counter_reg[12]_i_2_n_2 ;
  wire \counter_reg[12]_i_2_n_3 ;
  wire \counter_reg[16]_i_4_n_1 ;
  wire \counter_reg[16]_i_4_n_2 ;
  wire \counter_reg[16]_i_4_n_3 ;
  wire \counter_reg[4]_i_2_n_0 ;
  wire \counter_reg[4]_i_2_n_1 ;
  wire \counter_reg[4]_i_2_n_2 ;
  wire \counter_reg[4]_i_2_n_3 ;
  wire \counter_reg[8]_i_2_n_0 ;
  wire \counter_reg[8]_i_2_n_1 ;
  wire \counter_reg[8]_i_2_n_2 ;
  wire \counter_reg[8]_i_2_n_3 ;
  wire [15:0]p_0_in;
  wire [16:0]p_1_in;
  wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;

  LUT5 #(
    .INIT(32'hCDC8CDCD)) 
    \counter[0]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(CNT_LOAD_DOUT),
        .I2(CNT_CTRL[0]),
        .I3(COUNTER_MATCH),
        .I4(counter[0]),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[10]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[9]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[10]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[11]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[10]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[11]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[12]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[11]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[12]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[12]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[13]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[12]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[13]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[14]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[13]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[14]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[14]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[15]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[14]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[15]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hFFFFFFAE)) 
    \counter[16]_i_1 
       (.I0(SCNT_RESET),
        .I1(RESET[1]),
        .I2(RESET[0]),
        .I3(CNT_CTRL[1]),
        .I4(CNT_CTRL[0]),
        .O(\counter[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[16]_i_2 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[15]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[16]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[16]));
  LUT3 #(
    .INIT(8'hF4)) 
    \counter[16]_i_3 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(SCNT_RESET),
        .O(\counter[16]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[1]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[0]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[1]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[1]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[2]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[1]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[2]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[3]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[2]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[3]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[4]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[3]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[4]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[5]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[4]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[5]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[6]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[5]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[6]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[7]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[6]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[7]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[7]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[8]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[7]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[8]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[9]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[8]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[9]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[9]));
  FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
  FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[10]),
        .Q(p_0_in[9]),
        .R(1'b0));
  FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[11]),
        .Q(p_0_in[10]),
        .R(1'b0));
  FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[12]),
        .Q(p_0_in[11]),
        .R(1'b0));
  FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[13]),
        .Q(p_0_in[12]),
        .R(1'b0));
  FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[14]),
        .Q(p_0_in[13]),
        .R(1'b0));
  FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[15]),
        .Q(p_0_in[14]),
        .R(1'b0));
  FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\counter_load_i_reg[17]_srl15_n_0 ),
        .Q(p_0_in[15]),
        .R(1'b0));
  (* srl_bus_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg " *) 
  (* srl_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg[17]_srl15 " *) 
  SRL16E \counter_load_i_reg[17]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\counter_load_i_reg[17]_srl15_n_0 ));
  FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[1]),
        .Q(p_0_in[0]),
        .R(1'b0));
  FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[2]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[3]),
        .Q(p_0_in[2]),
        .R(1'b0));
  FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[4]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[5]),
        .Q(p_0_in[4]),
        .R(1'b0));
  FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[6]),
        .Q(p_0_in[5]),
        .R(1'b0));
  FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[7]),
        .Q(p_0_in[6]),
        .R(1'b0));
  FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[8]),
        .Q(p_0_in[7]),
        .R(1'b0));
  FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[9]),
        .Q(p_0_in[8]),
        .R(1'b0));
  FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(counter[0]),
        .R(1'b0));
  FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(counter[10]),
        .R(1'b0));
  FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(counter[11]),
        .R(1'b0));
  FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(counter[12]),
        .R(1'b0));
  CARRY4 \counter_reg[12]_i_2 
       (.CI(\counter_reg[8]_i_2_n_0 ),
        .CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[12:9]),
        .S(counter[12:9]));
  FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(counter[13]),
        .R(1'b0));
  FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(counter[14]),
        .R(1'b0));
  FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(counter[15]),
        .R(1'b0));
  FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[16]),
        .Q(COUNTER_MATCH),
        .R(1'b0));
  CARRY4 \counter_reg[16]_i_4 
       (.CI(\counter_reg[12]_i_2_n_0 ),
        .CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[16:13]),
        .S({COUNTER_MATCH,counter[15:13]}));
  FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(counter[1]),
        .R(1'b0));
  FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(counter[2]),
        .R(1'b0));
  FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(counter[3]),
        .R(1'b0));
  FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(counter[4]),
        .R(1'b0));
  CARRY4 \counter_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
        .CYINIT(counter[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[4:1]),
        .S(counter[4:1]));
  FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(counter[5]),
        .R(1'b0));
  FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(counter[6]),
        .R(1'b0));
  FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(counter[7]),
        .R(1'b0));
  FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(counter[8]),
        .R(1'b0));
  CARRY4 \counter_reg[8]_i_2 
       (.CI(\counter_reg[4]_i_2_n_0 ),
        .CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[8:5]),
        .S(counter[8:5]));
  FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* CNT_MAX = "17'b10000000000000000" *) (* C_COUNTER_WIDTH = "17" *) (* ORIG_REF_NAME = "ila_v6_2_8_generic_counter" *) 
(* dont_touch = "true" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter__1
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [15:0]counter;
  wire [16:1]counter0;
  wire \counter[16]_i_1_n_0 ;
  wire \counter[16]_i_3_n_0 ;
  wire \counter_load_i_reg[17]_srl15_n_0 ;
  wire \counter_reg[12]_i_2_n_0 ;
  wire \counter_reg[12]_i_2_n_1 ;
  wire \counter_reg[12]_i_2_n_2 ;
  wire \counter_reg[12]_i_2_n_3 ;
  wire \counter_reg[16]_i_4_n_1 ;
  wire \counter_reg[16]_i_4_n_2 ;
  wire \counter_reg[16]_i_4_n_3 ;
  wire \counter_reg[4]_i_2_n_0 ;
  wire \counter_reg[4]_i_2_n_1 ;
  wire \counter_reg[4]_i_2_n_2 ;
  wire \counter_reg[4]_i_2_n_3 ;
  wire \counter_reg[8]_i_2_n_0 ;
  wire \counter_reg[8]_i_2_n_1 ;
  wire \counter_reg[8]_i_2_n_2 ;
  wire \counter_reg[8]_i_2_n_3 ;
  wire [15:0]p_0_in;
  wire [16:0]p_1_in;
  wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;

  LUT5 #(
    .INIT(32'hCDC8CDCD)) 
    \counter[0]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(CNT_LOAD_DOUT),
        .I2(CNT_CTRL[0]),
        .I3(COUNTER_MATCH),
        .I4(counter[0]),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[10]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[9]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[10]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[11]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[10]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[11]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[12]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[11]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[12]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[12]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[13]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[12]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[13]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[14]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[13]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[14]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[14]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[15]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[14]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[15]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hFFFFFFAE)) 
    \counter[16]_i_1 
       (.I0(SCNT_RESET),
        .I1(RESET[1]),
        .I2(RESET[0]),
        .I3(CNT_CTRL[1]),
        .I4(CNT_CTRL[0]),
        .O(\counter[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[16]_i_2 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[15]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[16]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[16]));
  LUT3 #(
    .INIT(8'hF4)) 
    \counter[16]_i_3 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(SCNT_RESET),
        .O(\counter[16]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[1]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[0]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[1]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[1]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[2]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[1]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[2]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[3]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[2]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[3]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[4]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[3]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[4]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[5]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[4]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[5]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[6]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[5]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[6]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[7]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[6]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[7]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[7]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[8]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[7]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[8]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[9]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[8]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[9]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[9]));
  FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
  FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[10]),
        .Q(p_0_in[9]),
        .R(1'b0));
  FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[11]),
        .Q(p_0_in[10]),
        .R(1'b0));
  FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[12]),
        .Q(p_0_in[11]),
        .R(1'b0));
  FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[13]),
        .Q(p_0_in[12]),
        .R(1'b0));
  FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[14]),
        .Q(p_0_in[13]),
        .R(1'b0));
  FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[15]),
        .Q(p_0_in[14]),
        .R(1'b0));
  FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\counter_load_i_reg[17]_srl15_n_0 ),
        .Q(p_0_in[15]),
        .R(1'b0));
  (* srl_bus_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg " *) 
  (* srl_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg[17]_srl15 " *) 
  SRL16E \counter_load_i_reg[17]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\counter_load_i_reg[17]_srl15_n_0 ));
  FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[1]),
        .Q(p_0_in[0]),
        .R(1'b0));
  FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[2]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[3]),
        .Q(p_0_in[2]),
        .R(1'b0));
  FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[4]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[5]),
        .Q(p_0_in[4]),
        .R(1'b0));
  FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[6]),
        .Q(p_0_in[5]),
        .R(1'b0));
  FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[7]),
        .Q(p_0_in[6]),
        .R(1'b0));
  FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[8]),
        .Q(p_0_in[7]),
        .R(1'b0));
  FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[9]),
        .Q(p_0_in[8]),
        .R(1'b0));
  FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(counter[0]),
        .R(1'b0));
  FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(counter[10]),
        .R(1'b0));
  FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(counter[11]),
        .R(1'b0));
  FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(counter[12]),
        .R(1'b0));
  CARRY4 \counter_reg[12]_i_2 
       (.CI(\counter_reg[8]_i_2_n_0 ),
        .CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[12:9]),
        .S(counter[12:9]));
  FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(counter[13]),
        .R(1'b0));
  FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(counter[14]),
        .R(1'b0));
  FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(counter[15]),
        .R(1'b0));
  FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[16]),
        .Q(COUNTER_MATCH),
        .R(1'b0));
  CARRY4 \counter_reg[16]_i_4 
       (.CI(\counter_reg[12]_i_2_n_0 ),
        .CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[16:13]),
        .S({COUNTER_MATCH,counter[15:13]}));
  FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(counter[1]),
        .R(1'b0));
  FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(counter[2]),
        .R(1'b0));
  FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(counter[3]),
        .R(1'b0));
  FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(counter[4]),
        .R(1'b0));
  CARRY4 \counter_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
        .CYINIT(counter[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[4:1]),
        .S(counter[4:1]));
  FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(counter[5]),
        .R(1'b0));
  FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(counter[6]),
        .R(1'b0));
  FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(counter[7]),
        .R(1'b0));
  FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(counter[8]),
        .R(1'b0));
  CARRY4 \counter_reg[8]_i_2 
       (.CI(\counter_reg[4]_i_2_n_0 ),
        .CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[8:5]),
        .S(counter[8:5]));
  FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* CNT_MAX = "17'b10000000000000000" *) (* C_COUNTER_WIDTH = "17" *) (* ORIG_REF_NAME = "ila_v6_2_8_generic_counter" *) 
(* dont_touch = "true" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter__2
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [15:0]counter;
  wire [16:1]counter0;
  wire \counter[16]_i_1_n_0 ;
  wire \counter[16]_i_3_n_0 ;
  wire \counter_load_i_reg[17]_srl15_n_0 ;
  wire \counter_reg[12]_i_2_n_0 ;
  wire \counter_reg[12]_i_2_n_1 ;
  wire \counter_reg[12]_i_2_n_2 ;
  wire \counter_reg[12]_i_2_n_3 ;
  wire \counter_reg[16]_i_4_n_1 ;
  wire \counter_reg[16]_i_4_n_2 ;
  wire \counter_reg[16]_i_4_n_3 ;
  wire \counter_reg[4]_i_2_n_0 ;
  wire \counter_reg[4]_i_2_n_1 ;
  wire \counter_reg[4]_i_2_n_2 ;
  wire \counter_reg[4]_i_2_n_3 ;
  wire \counter_reg[8]_i_2_n_0 ;
  wire \counter_reg[8]_i_2_n_1 ;
  wire \counter_reg[8]_i_2_n_2 ;
  wire \counter_reg[8]_i_2_n_3 ;
  wire [15:0]p_0_in;
  wire [16:0]p_1_in;
  wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;

  LUT5 #(
    .INIT(32'hCDC8CDCD)) 
    \counter[0]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(CNT_LOAD_DOUT),
        .I2(CNT_CTRL[0]),
        .I3(COUNTER_MATCH),
        .I4(counter[0]),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[10]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[9]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[10]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[11]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[10]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[11]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[12]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[11]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[12]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[12]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[13]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[12]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[13]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[14]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[13]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[14]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[14]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[15]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[14]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[15]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hFFFFFFAE)) 
    \counter[16]_i_1 
       (.I0(SCNT_RESET),
        .I1(RESET[1]),
        .I2(RESET[0]),
        .I3(CNT_CTRL[1]),
        .I4(CNT_CTRL[0]),
        .O(\counter[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[16]_i_2 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[15]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[16]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[16]));
  LUT3 #(
    .INIT(8'hF4)) 
    \counter[16]_i_3 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(SCNT_RESET),
        .O(\counter[16]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[1]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[0]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[1]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[1]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[2]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[1]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[2]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[3]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[2]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[3]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[4]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[3]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[4]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[5]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[4]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[5]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[6]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[5]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[6]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[7]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[6]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[7]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[7]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[8]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[7]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[8]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[9]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[8]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[9]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[9]));
  FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
  FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[10]),
        .Q(p_0_in[9]),
        .R(1'b0));
  FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[11]),
        .Q(p_0_in[10]),
        .R(1'b0));
  FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[12]),
        .Q(p_0_in[11]),
        .R(1'b0));
  FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[13]),
        .Q(p_0_in[12]),
        .R(1'b0));
  FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[14]),
        .Q(p_0_in[13]),
        .R(1'b0));
  FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[15]),
        .Q(p_0_in[14]),
        .R(1'b0));
  FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\counter_load_i_reg[17]_srl15_n_0 ),
        .Q(p_0_in[15]),
        .R(1'b0));
  (* srl_bus_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg " *) 
  (* srl_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg[17]_srl15 " *) 
  SRL16E \counter_load_i_reg[17]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\counter_load_i_reg[17]_srl15_n_0 ));
  FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[1]),
        .Q(p_0_in[0]),
        .R(1'b0));
  FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[2]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[3]),
        .Q(p_0_in[2]),
        .R(1'b0));
  FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[4]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[5]),
        .Q(p_0_in[4]),
        .R(1'b0));
  FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[6]),
        .Q(p_0_in[5]),
        .R(1'b0));
  FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[7]),
        .Q(p_0_in[6]),
        .R(1'b0));
  FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[8]),
        .Q(p_0_in[7]),
        .R(1'b0));
  FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[9]),
        .Q(p_0_in[8]),
        .R(1'b0));
  FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(counter[0]),
        .R(1'b0));
  FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(counter[10]),
        .R(1'b0));
  FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(counter[11]),
        .R(1'b0));
  FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(counter[12]),
        .R(1'b0));
  CARRY4 \counter_reg[12]_i_2 
       (.CI(\counter_reg[8]_i_2_n_0 ),
        .CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[12:9]),
        .S(counter[12:9]));
  FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(counter[13]),
        .R(1'b0));
  FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(counter[14]),
        .R(1'b0));
  FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(counter[15]),
        .R(1'b0));
  FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[16]),
        .Q(COUNTER_MATCH),
        .R(1'b0));
  CARRY4 \counter_reg[16]_i_4 
       (.CI(\counter_reg[12]_i_2_n_0 ),
        .CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[16:13]),
        .S({COUNTER_MATCH,counter[15:13]}));
  FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(counter[1]),
        .R(1'b0));
  FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(counter[2]),
        .R(1'b0));
  FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(counter[3]),
        .R(1'b0));
  FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(counter[4]),
        .R(1'b0));
  CARRY4 \counter_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
        .CYINIT(counter[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[4:1]),
        .S(counter[4:1]));
  FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(counter[5]),
        .R(1'b0));
  FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(counter[6]),
        .R(1'b0));
  FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(counter[7]),
        .R(1'b0));
  FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(counter[8]),
        .R(1'b0));
  CARRY4 \counter_reg[8]_i_2 
       (.CI(\counter_reg[4]_i_2_n_0 ),
        .CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[8:5]),
        .S(counter[8:5]));
  FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* CNT_MAX = "17'b10000000000000000" *) (* C_COUNTER_WIDTH = "17" *) (* ORIG_REF_NAME = "ila_v6_2_8_generic_counter" *) 
(* dont_touch = "true" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter__3
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [15:0]counter;
  wire [16:1]counter0;
  wire \counter[16]_i_1_n_0 ;
  wire \counter[16]_i_3_n_0 ;
  wire \counter_load_i_reg[17]_srl15_n_0 ;
  wire \counter_reg[12]_i_2_n_0 ;
  wire \counter_reg[12]_i_2_n_1 ;
  wire \counter_reg[12]_i_2_n_2 ;
  wire \counter_reg[12]_i_2_n_3 ;
  wire \counter_reg[16]_i_4_n_1 ;
  wire \counter_reg[16]_i_4_n_2 ;
  wire \counter_reg[16]_i_4_n_3 ;
  wire \counter_reg[4]_i_2_n_0 ;
  wire \counter_reg[4]_i_2_n_1 ;
  wire \counter_reg[4]_i_2_n_2 ;
  wire \counter_reg[4]_i_2_n_3 ;
  wire \counter_reg[8]_i_2_n_0 ;
  wire \counter_reg[8]_i_2_n_1 ;
  wire \counter_reg[8]_i_2_n_2 ;
  wire \counter_reg[8]_i_2_n_3 ;
  wire [15:0]p_0_in;
  wire [16:0]p_1_in;
  wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;

  LUT5 #(
    .INIT(32'hCDC8CDCD)) 
    \counter[0]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(CNT_LOAD_DOUT),
        .I2(CNT_CTRL[0]),
        .I3(COUNTER_MATCH),
        .I4(counter[0]),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[10]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[9]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[10]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[11]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[10]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[11]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[12]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[11]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[12]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[12]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[13]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[12]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[13]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[14]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[13]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[14]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[14]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[15]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[14]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[15]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hFFFFFFAE)) 
    \counter[16]_i_1 
       (.I0(SCNT_RESET),
        .I1(RESET[1]),
        .I2(RESET[0]),
        .I3(CNT_CTRL[1]),
        .I4(CNT_CTRL[0]),
        .O(\counter[16]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[16]_i_2 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[15]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[16]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[16]));
  LUT3 #(
    .INIT(8'hF4)) 
    \counter[16]_i_3 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(SCNT_RESET),
        .O(\counter[16]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[1]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[0]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[1]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[1]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[2]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[1]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[2]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[3]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[2]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[3]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[4]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[3]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[4]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[5]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[4]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[5]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[6]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[5]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[6]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[7]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[6]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[7]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[7]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[8]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[7]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[8]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hC8C8CDC8)) 
    \counter[9]_i_1 
       (.I0(\counter[16]_i_3_n_0 ),
        .I1(p_0_in[8]),
        .I2(CNT_CTRL[0]),
        .I3(counter0[9]),
        .I4(COUNTER_MATCH),
        .O(p_1_in[9]));
  FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
  FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[10]),
        .Q(p_0_in[9]),
        .R(1'b0));
  FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[11]),
        .Q(p_0_in[10]),
        .R(1'b0));
  FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[12]),
        .Q(p_0_in[11]),
        .R(1'b0));
  FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[13]),
        .Q(p_0_in[12]),
        .R(1'b0));
  FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[14]),
        .Q(p_0_in[13]),
        .R(1'b0));
  FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[15]),
        .Q(p_0_in[14]),
        .R(1'b0));
  FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\counter_load_i_reg[17]_srl15_n_0 ),
        .Q(p_0_in[15]),
        .R(1'b0));
  (* srl_bus_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg " *) 
  (* srl_name = "inst/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg[17]_srl15 " *) 
  SRL16E \counter_load_i_reg[17]_srl15 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\counter_load_i_reg[17]_srl15_n_0 ));
  FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[1]),
        .Q(p_0_in[0]),
        .R(1'b0));
  FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[2]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[3]),
        .Q(p_0_in[2]),
        .R(1'b0));
  FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[4]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[5]),
        .Q(p_0_in[4]),
        .R(1'b0));
  FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[6]),
        .Q(p_0_in[5]),
        .R(1'b0));
  FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[7]),
        .Q(p_0_in[6]),
        .R(1'b0));
  FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[8]),
        .Q(p_0_in[7]),
        .R(1'b0));
  FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_0_in[9]),
        .Q(p_0_in[8]),
        .R(1'b0));
  FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(counter[0]),
        .R(1'b0));
  FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(counter[10]),
        .R(1'b0));
  FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(counter[11]),
        .R(1'b0));
  FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(counter[12]),
        .R(1'b0));
  CARRY4 \counter_reg[12]_i_2 
       (.CI(\counter_reg[8]_i_2_n_0 ),
        .CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[12:9]),
        .S(counter[12:9]));
  FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(counter[13]),
        .R(1'b0));
  FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(counter[14]),
        .R(1'b0));
  FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(counter[15]),
        .R(1'b0));
  FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[16]),
        .Q(COUNTER_MATCH),
        .R(1'b0));
  CARRY4 \counter_reg[16]_i_4 
       (.CI(\counter_reg[12]_i_2_n_0 ),
        .CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[16:13]),
        .S({COUNTER_MATCH,counter[15:13]}));
  FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(counter[1]),
        .R(1'b0));
  FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(counter[2]),
        .R(1'b0));
  FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(counter[3]),
        .R(1'b0));
  FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(counter[4]),
        .R(1'b0));
  CARRY4 \counter_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
        .CYINIT(counter[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[4:1]),
        .S(counter[4:1]));
  FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(counter[5]),
        .R(1'b0));
  FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(counter[6]),
        .R(1'b0));
  FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(counter[7]),
        .R(1'b0));
  FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(counter[8]),
        .R(1'b0));
  CARRY4 \counter_reg[8]_i_2 
       (.CI(\counter_reg[4]_i_2_n_0 ),
        .CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[8:5]),
        .S(counter[8:5]));
  FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\counter[16]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* C_ADV_TRIGGER = "1" *) (* C_BUILD_REVISION = "0" *) (* C_CAPTURE_TYPE = "0" *) 
(* C_CLKFBOUT_MULT_F = "10" *) (* C_CLKOUT0_DIVIDE_F = "10" *) (* C_CLK_FREQ = "200" *) 
(* C_CLK_PERIOD = "5.000000" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_CORE_MAJOR_VER = "6" *) (* C_CORE_MINOR_VER = "2" *) (* C_CORE_TYPE = "1" *) 
(* C_CSE_DRV_VER = "2" *) (* C_DATA_DEPTH = "1024" *) (* C_DDR_CLK_GEN = "0" *) 
(* C_DIVCLK_DIVIDE = "3" *) (* C_ENABLE_ILA_AXI_MON = "0" *) (* C_EN_DDR_ILA = "0" *) 
(* C_EN_STRG_QUAL = "1" *) (* C_EN_TIME_TAG = "0" *) (* C_ILA_CLK_FREQ = "2000000" *) 
(* C_INPUT_PIPE_STAGES = "0" *) (* C_MAJOR_VERSION = "2018" *) (* C_MINOR_VERSION = "3" *) 
(* C_MU_TYPE = "0" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_MONITOR_SLOTS = "1" *) 
(* C_NUM_OF_PROBES = "3" *) (* C_PIPE_IFACE = "1" *) (* C_PROBE0_MU_CNT = "4" *) 
(* C_PROBE0_TYPE = "0" *) (* C_PROBE0_WIDTH = "21" *) (* C_PROBE1000_MU_CNT = "1" *) 
(* C_PROBE1000_TYPE = "1" *) (* C_PROBE1000_WIDTH = "1" *) (* C_PROBE1001_MU_CNT = "1" *) 
(* C_PROBE1001_TYPE = "1" *) (* C_PROBE1001_WIDTH = "1" *) (* C_PROBE1002_MU_CNT = "1" *) 
(* C_PROBE1002_TYPE = "1" *) (* C_PROBE1002_WIDTH = "1" *) (* C_PROBE1003_MU_CNT = "1" *) 
(* C_PROBE1003_TYPE = "1" *) (* C_PROBE1003_WIDTH = "1" *) (* C_PROBE1004_MU_CNT = "1" *) 
(* C_PROBE1004_TYPE = "1" *) (* C_PROBE1004_WIDTH = "1" *) (* C_PROBE1005_MU_CNT = "1" *) 
(* C_PROBE1005_TYPE = "1" *) (* C_PROBE1005_WIDTH = "1" *) (* C_PROBE1006_MU_CNT = "1" *) 
(* C_PROBE1006_TYPE = "1" *) (* C_PROBE1006_WIDTH = "1" *) (* C_PROBE1007_MU_CNT = "1" *) 
(* C_PROBE1007_TYPE = "1" *) (* C_PROBE1007_WIDTH = "1" *) (* C_PROBE1008_MU_CNT = "1" *) 
(* C_PROBE1008_TYPE = "1" *) (* C_PROBE1008_WIDTH = "1" *) (* C_PROBE1009_MU_CNT = "1" *) 
(* C_PROBE1009_TYPE = "1" *) (* C_PROBE1009_WIDTH = "1" *) (* C_PROBE100_MU_CNT = "1" *) 
(* C_PROBE100_TYPE = "1" *) (* C_PROBE100_WIDTH = "1" *) (* C_PROBE1010_MU_CNT = "1" *) 
(* C_PROBE1010_TYPE = "1" *) (* C_PROBE1010_WIDTH = "1" *) (* C_PROBE1011_MU_CNT = "1" *) 
(* C_PROBE1011_TYPE = "1" *) (* C_PROBE1011_WIDTH = "1" *) (* C_PROBE1012_MU_CNT = "1" *) 
(* C_PROBE1012_TYPE = "1" *) (* C_PROBE1012_WIDTH = "1" *) (* C_PROBE1013_MU_CNT = "1" *) 
(* C_PROBE1013_TYPE = "1" *) (* C_PROBE1013_WIDTH = "1" *) (* C_PROBE1014_MU_CNT = "1" *) 
(* C_PROBE1014_TYPE = "1" *) (* C_PROBE1014_WIDTH = "1" *) (* C_PROBE1015_MU_CNT = "1" *) 
(* C_PROBE1015_TYPE = "1" *) (* C_PROBE1015_WIDTH = "1" *) (* C_PROBE1016_MU_CNT = "1" *) 
(* C_PROBE1016_TYPE = "1" *) (* C_PROBE1016_WIDTH = "1" *) (* C_PROBE1017_MU_CNT = "1" *) 
(* C_PROBE1017_TYPE = "1" *) (* C_PROBE1017_WIDTH = "1" *) (* C_PROBE1018_MU_CNT = "1" *) 
(* C_PROBE1018_TYPE = "1" *) (* C_PROBE1018_WIDTH = "1" *) (* C_PROBE1019_MU_CNT = "1" *) 
(* C_PROBE1019_TYPE = "1" *) (* C_PROBE1019_WIDTH = "1" *) (* C_PROBE101_MU_CNT = "1" *) 
(* C_PROBE101_TYPE = "1" *) (* C_PROBE101_WIDTH = "1" *) (* C_PROBE1020_MU_CNT = "1" *) 
(* C_PROBE1020_TYPE = "1" *) (* C_PROBE1020_WIDTH = "1" *) (* C_PROBE1021_MU_CNT = "1" *) 
(* C_PROBE1021_TYPE = "1" *) (* C_PROBE1021_WIDTH = "1" *) (* C_PROBE1022_MU_CNT = "1" *) 
(* C_PROBE1022_TYPE = "1" *) (* C_PROBE1022_WIDTH = "1" *) (* C_PROBE1023_MU_CNT = "1" *) 
(* C_PROBE1023_TYPE = "1" *) (* C_PROBE1023_WIDTH = "1" *) (* C_PROBE102_MU_CNT = "1" *) 
(* C_PROBE102_TYPE = "1" *) (* C_PROBE102_WIDTH = "1" *) (* C_PROBE103_MU_CNT = "1" *) 
(* C_PROBE103_TYPE = "1" *) (* C_PROBE103_WIDTH = "1" *) (* C_PROBE104_MU_CNT = "1" *) 
(* C_PROBE104_TYPE = "1" *) (* C_PROBE104_WIDTH = "1" *) (* C_PROBE105_MU_CNT = "1" *) 
(* C_PROBE105_TYPE = "1" *) (* C_PROBE105_WIDTH = "1" *) (* C_PROBE106_MU_CNT = "1" *) 
(* C_PROBE106_TYPE = "1" *) (* C_PROBE106_WIDTH = "1" *) (* C_PROBE107_MU_CNT = "1" *) 
(* C_PROBE107_TYPE = "1" *) (* C_PROBE107_WIDTH = "1" *) (* C_PROBE108_MU_CNT = "1" *) 
(* C_PROBE108_TYPE = "1" *) (* C_PROBE108_WIDTH = "1" *) (* C_PROBE109_MU_CNT = "1" *) 
(* C_PROBE109_TYPE = "1" *) (* C_PROBE109_WIDTH = "1" *) (* C_PROBE10_MU_CNT = "1" *) 
(* C_PROBE10_TYPE = "1" *) (* C_PROBE10_WIDTH = "1" *) (* C_PROBE110_MU_CNT = "1" *) 
(* C_PROBE110_TYPE = "1" *) (* C_PROBE110_WIDTH = "1" *) (* C_PROBE111_MU_CNT = "1" *) 
(* C_PROBE111_TYPE = "1" *) (* C_PROBE111_WIDTH = "1" *) (* C_PROBE112_MU_CNT = "1" *) 
(* C_PROBE112_TYPE = "1" *) (* C_PROBE112_WIDTH = "1" *) (* C_PROBE113_MU_CNT = "1" *) 
(* C_PROBE113_TYPE = "1" *) (* C_PROBE113_WIDTH = "1" *) (* C_PROBE114_MU_CNT = "1" *) 
(* C_PROBE114_TYPE = "1" *) (* C_PROBE114_WIDTH = "1" *) (* C_PROBE115_MU_CNT = "1" *) 
(* C_PROBE115_TYPE = "1" *) (* C_PROBE115_WIDTH = "1" *) (* C_PROBE116_MU_CNT = "1" *) 
(* C_PROBE116_TYPE = "1" *) (* C_PROBE116_WIDTH = "1" *) (* C_PROBE117_MU_CNT = "1" *) 
(* C_PROBE117_TYPE = "1" *) (* C_PROBE117_WIDTH = "1" *) (* C_PROBE118_MU_CNT = "1" *) 
(* C_PROBE118_TYPE = "1" *) (* C_PROBE118_WIDTH = "1" *) (* C_PROBE119_MU_CNT = "1" *) 
(* C_PROBE119_TYPE = "1" *) (* C_PROBE119_WIDTH = "1" *) (* C_PROBE11_MU_CNT = "1" *) 
(* C_PROBE11_TYPE = "1" *) (* C_PROBE11_WIDTH = "1" *) (* C_PROBE120_MU_CNT = "1" *) 
(* C_PROBE120_TYPE = "1" *) (* C_PROBE120_WIDTH = "1" *) (* C_PROBE121_MU_CNT = "1" *) 
(* C_PROBE121_TYPE = "1" *) (* C_PROBE121_WIDTH = "1" *) (* C_PROBE122_MU_CNT = "1" *) 
(* C_PROBE122_TYPE = "1" *) (* C_PROBE122_WIDTH = "1" *) (* C_PROBE123_MU_CNT = "1" *) 
(* C_PROBE123_TYPE = "1" *) (* C_PROBE123_WIDTH = "1" *) (* C_PROBE124_MU_CNT = "1" *) 
(* C_PROBE124_TYPE = "1" *) (* C_PROBE124_WIDTH = "1" *) (* C_PROBE125_MU_CNT = "1" *) 
(* C_PROBE125_TYPE = "1" *) (* C_PROBE125_WIDTH = "1" *) (* C_PROBE126_MU_CNT = "1" *) 
(* C_PROBE126_TYPE = "1" *) (* C_PROBE126_WIDTH = "1" *) (* C_PROBE127_MU_CNT = "1" *) 
(* C_PROBE127_TYPE = "1" *) (* C_PROBE127_WIDTH = "1" *) (* C_PROBE128_MU_CNT = "1" *) 
(* C_PROBE128_TYPE = "1" *) (* C_PROBE128_WIDTH = "1" *) (* C_PROBE129_MU_CNT = "1" *) 
(* C_PROBE129_TYPE = "1" *) (* C_PROBE129_WIDTH = "1" *) (* C_PROBE12_MU_CNT = "1" *) 
(* C_PROBE12_TYPE = "1" *) (* C_PROBE12_WIDTH = "1" *) (* C_PROBE130_MU_CNT = "1" *) 
(* C_PROBE130_TYPE = "1" *) (* C_PROBE130_WIDTH = "1" *) (* C_PROBE131_MU_CNT = "1" *) 
(* C_PROBE131_TYPE = "1" *) (* C_PROBE131_WIDTH = "1" *) (* C_PROBE132_MU_CNT = "1" *) 
(* C_PROBE132_TYPE = "1" *) (* C_PROBE132_WIDTH = "1" *) (* C_PROBE133_MU_CNT = "1" *) 
(* C_PROBE133_TYPE = "1" *) (* C_PROBE133_WIDTH = "1" *) (* C_PROBE134_MU_CNT = "1" *) 
(* C_PROBE134_TYPE = "1" *) (* C_PROBE134_WIDTH = "1" *) (* C_PROBE135_MU_CNT = "1" *) 
(* C_PROBE135_TYPE = "1" *) (* C_PROBE135_WIDTH = "1" *) (* C_PROBE136_MU_CNT = "1" *) 
(* C_PROBE136_TYPE = "1" *) (* C_PROBE136_WIDTH = "1" *) (* C_PROBE137_MU_CNT = "1" *) 
(* C_PROBE137_TYPE = "1" *) (* C_PROBE137_WIDTH = "1" *) (* C_PROBE138_MU_CNT = "1" *) 
(* C_PROBE138_TYPE = "1" *) (* C_PROBE138_WIDTH = "1" *) (* C_PROBE139_MU_CNT = "1" *) 
(* C_PROBE139_TYPE = "1" *) (* C_PROBE139_WIDTH = "1" *) (* C_PROBE13_MU_CNT = "1" *) 
(* C_PROBE13_TYPE = "1" *) (* C_PROBE13_WIDTH = "1" *) (* C_PROBE140_MU_CNT = "1" *) 
(* C_PROBE140_TYPE = "1" *) (* C_PROBE140_WIDTH = "1" *) (* C_PROBE141_MU_CNT = "1" *) 
(* C_PROBE141_TYPE = "1" *) (* C_PROBE141_WIDTH = "1" *) (* C_PROBE142_MU_CNT = "1" *) 
(* C_PROBE142_TYPE = "1" *) (* C_PROBE142_WIDTH = "1" *) (* C_PROBE143_MU_CNT = "1" *) 
(* C_PROBE143_TYPE = "1" *) (* C_PROBE143_WIDTH = "1" *) (* C_PROBE144_MU_CNT = "1" *) 
(* C_PROBE144_TYPE = "1" *) (* C_PROBE144_WIDTH = "1" *) (* C_PROBE145_MU_CNT = "1" *) 
(* C_PROBE145_TYPE = "1" *) (* C_PROBE145_WIDTH = "1" *) (* C_PROBE146_MU_CNT = "1" *) 
(* C_PROBE146_TYPE = "1" *) (* C_PROBE146_WIDTH = "1" *) (* C_PROBE147_MU_CNT = "1" *) 
(* C_PROBE147_TYPE = "1" *) (* C_PROBE147_WIDTH = "1" *) (* C_PROBE148_MU_CNT = "1" *) 
(* C_PROBE148_TYPE = "1" *) (* C_PROBE148_WIDTH = "1" *) (* C_PROBE149_MU_CNT = "1" *) 
(* C_PROBE149_TYPE = "1" *) (* C_PROBE149_WIDTH = "1" *) (* C_PROBE14_MU_CNT = "1" *) 
(* C_PROBE14_TYPE = "1" *) (* C_PROBE14_WIDTH = "1" *) (* C_PROBE150_MU_CNT = "1" *) 
(* C_PROBE150_TYPE = "1" *) (* C_PROBE150_WIDTH = "1" *) (* C_PROBE151_MU_CNT = "1" *) 
(* C_PROBE151_TYPE = "1" *) (* C_PROBE151_WIDTH = "1" *) (* C_PROBE152_MU_CNT = "1" *) 
(* C_PROBE152_TYPE = "1" *) (* C_PROBE152_WIDTH = "1" *) (* C_PROBE153_MU_CNT = "1" *) 
(* C_PROBE153_TYPE = "1" *) (* C_PROBE153_WIDTH = "1" *) (* C_PROBE154_MU_CNT = "1" *) 
(* C_PROBE154_TYPE = "1" *) (* C_PROBE154_WIDTH = "1" *) (* C_PROBE155_MU_CNT = "1" *) 
(* C_PROBE155_TYPE = "1" *) (* C_PROBE155_WIDTH = "1" *) (* C_PROBE156_MU_CNT = "1" *) 
(* C_PROBE156_TYPE = "1" *) (* C_PROBE156_WIDTH = "1" *) (* C_PROBE157_MU_CNT = "1" *) 
(* C_PROBE157_TYPE = "1" *) (* C_PROBE157_WIDTH = "1" *) (* C_PROBE158_MU_CNT = "1" *) 
(* C_PROBE158_TYPE = "1" *) (* C_PROBE158_WIDTH = "1" *) (* C_PROBE159_MU_CNT = "1" *) 
(* C_PROBE159_TYPE = "1" *) (* C_PROBE159_WIDTH = "1" *) (* C_PROBE15_MU_CNT = "1" *) 
(* C_PROBE15_TYPE = "1" *) (* C_PROBE15_WIDTH = "1" *) (* C_PROBE160_MU_CNT = "1" *) 
(* C_PROBE160_TYPE = "1" *) (* C_PROBE160_WIDTH = "1" *) (* C_PROBE161_MU_CNT = "1" *) 
(* C_PROBE161_TYPE = "1" *) (* C_PROBE161_WIDTH = "1" *) (* C_PROBE162_MU_CNT = "1" *) 
(* C_PROBE162_TYPE = "1" *) (* C_PROBE162_WIDTH = "1" *) (* C_PROBE163_MU_CNT = "1" *) 
(* C_PROBE163_TYPE = "1" *) (* C_PROBE163_WIDTH = "1" *) (* C_PROBE164_MU_CNT = "1" *) 
(* C_PROBE164_TYPE = "1" *) (* C_PROBE164_WIDTH = "1" *) (* C_PROBE165_MU_CNT = "1" *) 
(* C_PROBE165_TYPE = "1" *) (* C_PROBE165_WIDTH = "1" *) (* C_PROBE166_MU_CNT = "1" *) 
(* C_PROBE166_TYPE = "1" *) (* C_PROBE166_WIDTH = "1" *) (* C_PROBE167_MU_CNT = "1" *) 
(* C_PROBE167_TYPE = "1" *) (* C_PROBE167_WIDTH = "1" *) (* C_PROBE168_MU_CNT = "1" *) 
(* C_PROBE168_TYPE = "1" *) (* C_PROBE168_WIDTH = "1" *) (* C_PROBE169_MU_CNT = "1" *) 
(* C_PROBE169_TYPE = "1" *) (* C_PROBE169_WIDTH = "1" *) (* C_PROBE16_MU_CNT = "1" *) 
(* C_PROBE16_TYPE = "1" *) (* C_PROBE16_WIDTH = "1" *) (* C_PROBE170_MU_CNT = "1" *) 
(* C_PROBE170_TYPE = "1" *) (* C_PROBE170_WIDTH = "1" *) (* C_PROBE171_MU_CNT = "1" *) 
(* C_PROBE171_TYPE = "1" *) (* C_PROBE171_WIDTH = "1" *) (* C_PROBE172_MU_CNT = "1" *) 
(* C_PROBE172_TYPE = "1" *) (* C_PROBE172_WIDTH = "1" *) (* C_PROBE173_MU_CNT = "1" *) 
(* C_PROBE173_TYPE = "1" *) (* C_PROBE173_WIDTH = "1" *) (* C_PROBE174_MU_CNT = "1" *) 
(* C_PROBE174_TYPE = "1" *) (* C_PROBE174_WIDTH = "1" *) (* C_PROBE175_MU_CNT = "1" *) 
(* C_PROBE175_TYPE = "1" *) (* C_PROBE175_WIDTH = "1" *) (* C_PROBE176_MU_CNT = "1" *) 
(* C_PROBE176_TYPE = "1" *) (* C_PROBE176_WIDTH = "1" *) (* C_PROBE177_MU_CNT = "1" *) 
(* C_PROBE177_TYPE = "1" *) (* C_PROBE177_WIDTH = "1" *) (* C_PROBE178_MU_CNT = "1" *) 
(* C_PROBE178_TYPE = "1" *) (* C_PROBE178_WIDTH = "1" *) (* C_PROBE179_MU_CNT = "1" *) 
(* C_PROBE179_TYPE = "1" *) (* C_PROBE179_WIDTH = "1" *) (* C_PROBE17_MU_CNT = "1" *) 
(* C_PROBE17_TYPE = "1" *) (* C_PROBE17_WIDTH = "1" *) (* C_PROBE180_MU_CNT = "1" *) 
(* C_PROBE180_TYPE = "1" *) (* C_PROBE180_WIDTH = "1" *) (* C_PROBE181_MU_CNT = "1" *) 
(* C_PROBE181_TYPE = "1" *) (* C_PROBE181_WIDTH = "1" *) (* C_PROBE182_MU_CNT = "1" *) 
(* C_PROBE182_TYPE = "1" *) (* C_PROBE182_WIDTH = "1" *) (* C_PROBE183_MU_CNT = "1" *) 
(* C_PROBE183_TYPE = "1" *) (* C_PROBE183_WIDTH = "1" *) (* C_PROBE184_MU_CNT = "1" *) 
(* C_PROBE184_TYPE = "1" *) (* C_PROBE184_WIDTH = "1" *) (* C_PROBE185_MU_CNT = "1" *) 
(* C_PROBE185_TYPE = "1" *) (* C_PROBE185_WIDTH = "1" *) (* C_PROBE186_MU_CNT = "1" *) 
(* C_PROBE186_TYPE = "1" *) (* C_PROBE186_WIDTH = "1" *) (* C_PROBE187_MU_CNT = "1" *) 
(* C_PROBE187_TYPE = "1" *) (* C_PROBE187_WIDTH = "1" *) (* C_PROBE188_MU_CNT = "1" *) 
(* C_PROBE188_TYPE = "1" *) (* C_PROBE188_WIDTH = "1" *) (* C_PROBE189_MU_CNT = "1" *) 
(* C_PROBE189_TYPE = "1" *) (* C_PROBE189_WIDTH = "1" *) (* C_PROBE18_MU_CNT = "1" *) 
(* C_PROBE18_TYPE = "1" *) (* C_PROBE18_WIDTH = "1" *) (* C_PROBE190_MU_CNT = "1" *) 
(* C_PROBE190_TYPE = "1" *) (* C_PROBE190_WIDTH = "1" *) (* C_PROBE191_MU_CNT = "1" *) 
(* C_PROBE191_TYPE = "1" *) (* C_PROBE191_WIDTH = "1" *) (* C_PROBE192_MU_CNT = "1" *) 
(* C_PROBE192_TYPE = "1" *) (* C_PROBE192_WIDTH = "1" *) (* C_PROBE193_MU_CNT = "1" *) 
(* C_PROBE193_TYPE = "1" *) (* C_PROBE193_WIDTH = "1" *) (* C_PROBE194_MU_CNT = "1" *) 
(* C_PROBE194_TYPE = "1" *) (* C_PROBE194_WIDTH = "1" *) (* C_PROBE195_MU_CNT = "1" *) 
(* C_PROBE195_TYPE = "1" *) (* C_PROBE195_WIDTH = "1" *) (* C_PROBE196_MU_CNT = "1" *) 
(* C_PROBE196_TYPE = "1" *) (* C_PROBE196_WIDTH = "1" *) (* C_PROBE197_MU_CNT = "1" *) 
(* C_PROBE197_TYPE = "1" *) (* C_PROBE197_WIDTH = "1" *) (* C_PROBE198_MU_CNT = "1" *) 
(* C_PROBE198_TYPE = "1" *) (* C_PROBE198_WIDTH = "1" *) (* C_PROBE199_MU_CNT = "1" *) 
(* C_PROBE199_TYPE = "1" *) (* C_PROBE199_WIDTH = "1" *) (* C_PROBE19_MU_CNT = "1" *) 
(* C_PROBE19_TYPE = "1" *) (* C_PROBE19_WIDTH = "1" *) (* C_PROBE1_MU_CNT = "4" *) 
(* C_PROBE1_TYPE = "0" *) (* C_PROBE1_WIDTH = "22" *) (* C_PROBE200_MU_CNT = "1" *) 
(* C_PROBE200_TYPE = "1" *) (* C_PROBE200_WIDTH = "1" *) (* C_PROBE201_MU_CNT = "1" *) 
(* C_PROBE201_TYPE = "1" *) (* C_PROBE201_WIDTH = "1" *) (* C_PROBE202_MU_CNT = "1" *) 
(* C_PROBE202_TYPE = "1" *) (* C_PROBE202_WIDTH = "1" *) (* C_PROBE203_MU_CNT = "1" *) 
(* C_PROBE203_TYPE = "1" *) (* C_PROBE203_WIDTH = "1" *) (* C_PROBE204_MU_CNT = "1" *) 
(* C_PROBE204_TYPE = "1" *) (* C_PROBE204_WIDTH = "1" *) (* C_PROBE205_MU_CNT = "1" *) 
(* C_PROBE205_TYPE = "1" *) (* C_PROBE205_WIDTH = "1" *) (* C_PROBE206_MU_CNT = "1" *) 
(* C_PROBE206_TYPE = "1" *) (* C_PROBE206_WIDTH = "1" *) (* C_PROBE207_MU_CNT = "1" *) 
(* C_PROBE207_TYPE = "1" *) (* C_PROBE207_WIDTH = "1" *) (* C_PROBE208_MU_CNT = "1" *) 
(* C_PROBE208_TYPE = "1" *) (* C_PROBE208_WIDTH = "1" *) (* C_PROBE209_MU_CNT = "1" *) 
(* C_PROBE209_TYPE = "1" *) (* C_PROBE209_WIDTH = "1" *) (* C_PROBE20_MU_CNT = "1" *) 
(* C_PROBE20_TYPE = "1" *) (* C_PROBE20_WIDTH = "1" *) (* C_PROBE210_MU_CNT = "1" *) 
(* C_PROBE210_TYPE = "1" *) (* C_PROBE210_WIDTH = "1" *) (* C_PROBE211_MU_CNT = "1" *) 
(* C_PROBE211_TYPE = "1" *) (* C_PROBE211_WIDTH = "1" *) (* C_PROBE212_MU_CNT = "1" *) 
(* C_PROBE212_TYPE = "1" *) (* C_PROBE212_WIDTH = "1" *) (* C_PROBE213_MU_CNT = "1" *) 
(* C_PROBE213_TYPE = "1" *) (* C_PROBE213_WIDTH = "1" *) (* C_PROBE214_MU_CNT = "1" *) 
(* C_PROBE214_TYPE = "1" *) (* C_PROBE214_WIDTH = "1" *) (* C_PROBE215_MU_CNT = "1" *) 
(* C_PROBE215_TYPE = "1" *) (* C_PROBE215_WIDTH = "1" *) (* C_PROBE216_MU_CNT = "1" *) 
(* C_PROBE216_TYPE = "1" *) (* C_PROBE216_WIDTH = "1" *) (* C_PROBE217_MU_CNT = "1" *) 
(* C_PROBE217_TYPE = "1" *) (* C_PROBE217_WIDTH = "1" *) (* C_PROBE218_MU_CNT = "1" *) 
(* C_PROBE218_TYPE = "1" *) (* C_PROBE218_WIDTH = "1" *) (* C_PROBE219_MU_CNT = "1" *) 
(* C_PROBE219_TYPE = "1" *) (* C_PROBE219_WIDTH = "1" *) (* C_PROBE21_MU_CNT = "1" *) 
(* C_PROBE21_TYPE = "1" *) (* C_PROBE21_WIDTH = "1" *) (* C_PROBE220_MU_CNT = "1" *) 
(* C_PROBE220_TYPE = "1" *) (* C_PROBE220_WIDTH = "1" *) (* C_PROBE221_MU_CNT = "1" *) 
(* C_PROBE221_TYPE = "1" *) (* C_PROBE221_WIDTH = "1" *) (* C_PROBE222_MU_CNT = "1" *) 
(* C_PROBE222_TYPE = "1" *) (* C_PROBE222_WIDTH = "1" *) (* C_PROBE223_MU_CNT = "1" *) 
(* C_PROBE223_TYPE = "1" *) (* C_PROBE223_WIDTH = "1" *) (* C_PROBE224_MU_CNT = "1" *) 
(* C_PROBE224_TYPE = "1" *) (* C_PROBE224_WIDTH = "1" *) (* C_PROBE225_MU_CNT = "1" *) 
(* C_PROBE225_TYPE = "1" *) (* C_PROBE225_WIDTH = "1" *) (* C_PROBE226_MU_CNT = "1" *) 
(* C_PROBE226_TYPE = "1" *) (* C_PROBE226_WIDTH = "1" *) (* C_PROBE227_MU_CNT = "1" *) 
(* C_PROBE227_TYPE = "1" *) (* C_PROBE227_WIDTH = "1" *) (* C_PROBE228_MU_CNT = "1" *) 
(* C_PROBE228_TYPE = "1" *) (* C_PROBE228_WIDTH = "1" *) (* C_PROBE229_MU_CNT = "1" *) 
(* C_PROBE229_TYPE = "1" *) (* C_PROBE229_WIDTH = "1" *) (* C_PROBE22_MU_CNT = "1" *) 
(* C_PROBE22_TYPE = "1" *) (* C_PROBE22_WIDTH = "1" *) (* C_PROBE230_MU_CNT = "1" *) 
(* C_PROBE230_TYPE = "1" *) (* C_PROBE230_WIDTH = "1" *) (* C_PROBE231_MU_CNT = "1" *) 
(* C_PROBE231_TYPE = "1" *) (* C_PROBE231_WIDTH = "1" *) (* C_PROBE232_MU_CNT = "1" *) 
(* C_PROBE232_TYPE = "1" *) (* C_PROBE232_WIDTH = "1" *) (* C_PROBE233_MU_CNT = "1" *) 
(* C_PROBE233_TYPE = "1" *) (* C_PROBE233_WIDTH = "1" *) (* C_PROBE234_MU_CNT = "1" *) 
(* C_PROBE234_TYPE = "1" *) (* C_PROBE234_WIDTH = "1" *) (* C_PROBE235_MU_CNT = "1" *) 
(* C_PROBE235_TYPE = "1" *) (* C_PROBE235_WIDTH = "1" *) (* C_PROBE236_MU_CNT = "1" *) 
(* C_PROBE236_TYPE = "1" *) (* C_PROBE236_WIDTH = "1" *) (* C_PROBE237_MU_CNT = "1" *) 
(* C_PROBE237_TYPE = "1" *) (* C_PROBE237_WIDTH = "1" *) (* C_PROBE238_MU_CNT = "1" *) 
(* C_PROBE238_TYPE = "1" *) (* C_PROBE238_WIDTH = "1" *) (* C_PROBE239_MU_CNT = "1" *) 
(* C_PROBE239_TYPE = "1" *) (* C_PROBE239_WIDTH = "1" *) (* C_PROBE23_MU_CNT = "1" *) 
(* C_PROBE23_TYPE = "1" *) (* C_PROBE23_WIDTH = "1" *) (* C_PROBE240_MU_CNT = "1" *) 
(* C_PROBE240_TYPE = "1" *) (* C_PROBE240_WIDTH = "1" *) (* C_PROBE241_MU_CNT = "1" *) 
(* C_PROBE241_TYPE = "1" *) (* C_PROBE241_WIDTH = "1" *) (* C_PROBE242_MU_CNT = "1" *) 
(* C_PROBE242_TYPE = "1" *) (* C_PROBE242_WIDTH = "1" *) (* C_PROBE243_MU_CNT = "1" *) 
(* C_PROBE243_TYPE = "1" *) (* C_PROBE243_WIDTH = "1" *) (* C_PROBE244_MU_CNT = "1" *) 
(* C_PROBE244_TYPE = "1" *) (* C_PROBE244_WIDTH = "1" *) (* C_PROBE245_MU_CNT = "1" *) 
(* C_PROBE245_TYPE = "1" *) (* C_PROBE245_WIDTH = "1" *) (* C_PROBE246_MU_CNT = "1" *) 
(* C_PROBE246_TYPE = "1" *) (* C_PROBE246_WIDTH = "1" *) (* C_PROBE247_MU_CNT = "1" *) 
(* C_PROBE247_TYPE = "1" *) (* C_PROBE247_WIDTH = "1" *) (* C_PROBE248_MU_CNT = "1" *) 
(* C_PROBE248_TYPE = "1" *) (* C_PROBE248_WIDTH = "1" *) (* C_PROBE249_MU_CNT = "1" *) 
(* C_PROBE249_TYPE = "1" *) (* C_PROBE249_WIDTH = "1" *) (* C_PROBE24_MU_CNT = "1" *) 
(* C_PROBE24_TYPE = "1" *) (* C_PROBE24_WIDTH = "1" *) (* C_PROBE250_MU_CNT = "1" *) 
(* C_PROBE250_TYPE = "1" *) (* C_PROBE250_WIDTH = "1" *) (* C_PROBE251_MU_CNT = "1" *) 
(* C_PROBE251_TYPE = "1" *) (* C_PROBE251_WIDTH = "1" *) (* C_PROBE252_MU_CNT = "1" *) 
(* C_PROBE252_TYPE = "1" *) (* C_PROBE252_WIDTH = "1" *) (* C_PROBE253_MU_CNT = "1" *) 
(* C_PROBE253_TYPE = "1" *) (* C_PROBE253_WIDTH = "1" *) (* C_PROBE254_MU_CNT = "1" *) 
(* C_PROBE254_TYPE = "1" *) (* C_PROBE254_WIDTH = "1" *) (* C_PROBE255_MU_CNT = "1" *) 
(* C_PROBE255_TYPE = "1" *) (* C_PROBE255_WIDTH = "1" *) (* C_PROBE256_MU_CNT = "1" *) 
(* C_PROBE256_TYPE = "1" *) (* C_PROBE256_WIDTH = "1" *) (* C_PROBE257_MU_CNT = "1" *) 
(* C_PROBE257_TYPE = "1" *) (* C_PROBE257_WIDTH = "1" *) (* C_PROBE258_MU_CNT = "1" *) 
(* C_PROBE258_TYPE = "1" *) (* C_PROBE258_WIDTH = "1" *) (* C_PROBE259_MU_CNT = "1" *) 
(* C_PROBE259_TYPE = "1" *) (* C_PROBE259_WIDTH = "1" *) (* C_PROBE25_MU_CNT = "1" *) 
(* C_PROBE25_TYPE = "1" *) (* C_PROBE25_WIDTH = "1" *) (* C_PROBE260_MU_CNT = "1" *) 
(* C_PROBE260_TYPE = "1" *) (* C_PROBE260_WIDTH = "1" *) (* C_PROBE261_MU_CNT = "1" *) 
(* C_PROBE261_TYPE = "1" *) (* C_PROBE261_WIDTH = "1" *) (* C_PROBE262_MU_CNT = "1" *) 
(* C_PROBE262_TYPE = "1" *) (* C_PROBE262_WIDTH = "1" *) (* C_PROBE263_MU_CNT = "1" *) 
(* C_PROBE263_TYPE = "1" *) (* C_PROBE263_WIDTH = "1" *) (* C_PROBE264_MU_CNT = "1" *) 
(* C_PROBE264_TYPE = "1" *) (* C_PROBE264_WIDTH = "1" *) (* C_PROBE265_MU_CNT = "1" *) 
(* C_PROBE265_TYPE = "1" *) (* C_PROBE265_WIDTH = "1" *) (* C_PROBE266_MU_CNT = "1" *) 
(* C_PROBE266_TYPE = "1" *) (* C_PROBE266_WIDTH = "1" *) (* C_PROBE267_MU_CNT = "1" *) 
(* C_PROBE267_TYPE = "1" *) (* C_PROBE267_WIDTH = "1" *) (* C_PROBE268_MU_CNT = "1" *) 
(* C_PROBE268_TYPE = "1" *) (* C_PROBE268_WIDTH = "1" *) (* C_PROBE269_MU_CNT = "1" *) 
(* C_PROBE269_TYPE = "1" *) (* C_PROBE269_WIDTH = "1" *) (* C_PROBE26_MU_CNT = "1" *) 
(* C_PROBE26_TYPE = "1" *) (* C_PROBE26_WIDTH = "1" *) (* C_PROBE270_MU_CNT = "1" *) 
(* C_PROBE270_TYPE = "1" *) (* C_PROBE270_WIDTH = "1" *) (* C_PROBE271_MU_CNT = "1" *) 
(* C_PROBE271_TYPE = "1" *) (* C_PROBE271_WIDTH = "1" *) (* C_PROBE272_MU_CNT = "1" *) 
(* C_PROBE272_TYPE = "1" *) (* C_PROBE272_WIDTH = "1" *) (* C_PROBE273_MU_CNT = "1" *) 
(* C_PROBE273_TYPE = "1" *) (* C_PROBE273_WIDTH = "1" *) (* C_PROBE274_MU_CNT = "1" *) 
(* C_PROBE274_TYPE = "1" *) (* C_PROBE274_WIDTH = "1" *) (* C_PROBE275_MU_CNT = "1" *) 
(* C_PROBE275_TYPE = "1" *) (* C_PROBE275_WIDTH = "1" *) (* C_PROBE276_MU_CNT = "1" *) 
(* C_PROBE276_TYPE = "1" *) (* C_PROBE276_WIDTH = "1" *) (* C_PROBE277_MU_CNT = "1" *) 
(* C_PROBE277_TYPE = "1" *) (* C_PROBE277_WIDTH = "1" *) (* C_PROBE278_MU_CNT = "1" *) 
(* C_PROBE278_TYPE = "1" *) (* C_PROBE278_WIDTH = "1" *) (* C_PROBE279_MU_CNT = "1" *) 
(* C_PROBE279_TYPE = "1" *) (* C_PROBE279_WIDTH = "1" *) (* C_PROBE27_MU_CNT = "1" *) 
(* C_PROBE27_TYPE = "1" *) (* C_PROBE27_WIDTH = "1" *) (* C_PROBE280_MU_CNT = "1" *) 
(* C_PROBE280_TYPE = "1" *) (* C_PROBE280_WIDTH = "1" *) (* C_PROBE281_MU_CNT = "1" *) 
(* C_PROBE281_TYPE = "1" *) (* C_PROBE281_WIDTH = "1" *) (* C_PROBE282_MU_CNT = "1" *) 
(* C_PROBE282_TYPE = "1" *) (* C_PROBE282_WIDTH = "1" *) (* C_PROBE283_MU_CNT = "1" *) 
(* C_PROBE283_TYPE = "1" *) (* C_PROBE283_WIDTH = "1" *) (* C_PROBE284_MU_CNT = "1" *) 
(* C_PROBE284_TYPE = "1" *) (* C_PROBE284_WIDTH = "1" *) (* C_PROBE285_MU_CNT = "1" *) 
(* C_PROBE285_TYPE = "1" *) (* C_PROBE285_WIDTH = "1" *) (* C_PROBE286_MU_CNT = "1" *) 
(* C_PROBE286_TYPE = "1" *) (* C_PROBE286_WIDTH = "1" *) (* C_PROBE287_MU_CNT = "1" *) 
(* C_PROBE287_TYPE = "1" *) (* C_PROBE287_WIDTH = "1" *) (* C_PROBE288_MU_CNT = "1" *) 
(* C_PROBE288_TYPE = "1" *) (* C_PROBE288_WIDTH = "1" *) (* C_PROBE289_MU_CNT = "1" *) 
(* C_PROBE289_TYPE = "1" *) (* C_PROBE289_WIDTH = "1" *) (* C_PROBE28_MU_CNT = "1" *) 
(* C_PROBE28_TYPE = "1" *) (* C_PROBE28_WIDTH = "1" *) (* C_PROBE290_MU_CNT = "1" *) 
(* C_PROBE290_TYPE = "1" *) (* C_PROBE290_WIDTH = "1" *) (* C_PROBE291_MU_CNT = "1" *) 
(* C_PROBE291_TYPE = "1" *) (* C_PROBE291_WIDTH = "1" *) (* C_PROBE292_MU_CNT = "1" *) 
(* C_PROBE292_TYPE = "1" *) (* C_PROBE292_WIDTH = "1" *) (* C_PROBE293_MU_CNT = "1" *) 
(* C_PROBE293_TYPE = "1" *) (* C_PROBE293_WIDTH = "1" *) (* C_PROBE294_MU_CNT = "1" *) 
(* C_PROBE294_TYPE = "1" *) (* C_PROBE294_WIDTH = "1" *) (* C_PROBE295_MU_CNT = "1" *) 
(* C_PROBE295_TYPE = "1" *) (* C_PROBE295_WIDTH = "1" *) (* C_PROBE296_MU_CNT = "1" *) 
(* C_PROBE296_TYPE = "1" *) (* C_PROBE296_WIDTH = "1" *) (* C_PROBE297_MU_CNT = "1" *) 
(* C_PROBE297_TYPE = "1" *) (* C_PROBE297_WIDTH = "1" *) (* C_PROBE298_MU_CNT = "1" *) 
(* C_PROBE298_TYPE = "1" *) (* C_PROBE298_WIDTH = "1" *) (* C_PROBE299_MU_CNT = "1" *) 
(* C_PROBE299_TYPE = "1" *) (* C_PROBE299_WIDTH = "1" *) (* C_PROBE29_MU_CNT = "1" *) 
(* C_PROBE29_TYPE = "1" *) (* C_PROBE29_WIDTH = "1" *) (* C_PROBE2_MU_CNT = "4" *) 
(* C_PROBE2_TYPE = "0" *) (* C_PROBE2_WIDTH = "22" *) (* C_PROBE300_MU_CNT = "1" *) 
(* C_PROBE300_TYPE = "1" *) (* C_PROBE300_WIDTH = "1" *) (* C_PROBE301_MU_CNT = "1" *) 
(* C_PROBE301_TYPE = "1" *) (* C_PROBE301_WIDTH = "1" *) (* C_PROBE302_MU_CNT = "1" *) 
(* C_PROBE302_TYPE = "1" *) (* C_PROBE302_WIDTH = "1" *) (* C_PROBE303_MU_CNT = "1" *) 
(* C_PROBE303_TYPE = "1" *) (* C_PROBE303_WIDTH = "1" *) (* C_PROBE304_MU_CNT = "1" *) 
(* C_PROBE304_TYPE = "1" *) (* C_PROBE304_WIDTH = "1" *) (* C_PROBE305_MU_CNT = "1" *) 
(* C_PROBE305_TYPE = "1" *) (* C_PROBE305_WIDTH = "1" *) (* C_PROBE306_MU_CNT = "1" *) 
(* C_PROBE306_TYPE = "1" *) (* C_PROBE306_WIDTH = "1" *) (* C_PROBE307_MU_CNT = "1" *) 
(* C_PROBE307_TYPE = "1" *) (* C_PROBE307_WIDTH = "1" *) (* C_PROBE308_MU_CNT = "1" *) 
(* C_PROBE308_TYPE = "1" *) (* C_PROBE308_WIDTH = "1" *) (* C_PROBE309_MU_CNT = "1" *) 
(* C_PROBE309_TYPE = "1" *) (* C_PROBE309_WIDTH = "1" *) (* C_PROBE30_MU_CNT = "1" *) 
(* C_PROBE30_TYPE = "1" *) (* C_PROBE30_WIDTH = "1" *) (* C_PROBE310_MU_CNT = "1" *) 
(* C_PROBE310_TYPE = "1" *) (* C_PROBE310_WIDTH = "1" *) (* C_PROBE311_MU_CNT = "1" *) 
(* C_PROBE311_TYPE = "1" *) (* C_PROBE311_WIDTH = "1" *) (* C_PROBE312_MU_CNT = "1" *) 
(* C_PROBE312_TYPE = "1" *) (* C_PROBE312_WIDTH = "1" *) (* C_PROBE313_MU_CNT = "1" *) 
(* C_PROBE313_TYPE = "1" *) (* C_PROBE313_WIDTH = "1" *) (* C_PROBE314_MU_CNT = "1" *) 
(* C_PROBE314_TYPE = "1" *) (* C_PROBE314_WIDTH = "1" *) (* C_PROBE315_MU_CNT = "1" *) 
(* C_PROBE315_TYPE = "1" *) (* C_PROBE315_WIDTH = "1" *) (* C_PROBE316_MU_CNT = "1" *) 
(* C_PROBE316_TYPE = "1" *) (* C_PROBE316_WIDTH = "1" *) (* C_PROBE317_MU_CNT = "1" *) 
(* C_PROBE317_TYPE = "1" *) (* C_PROBE317_WIDTH = "1" *) (* C_PROBE318_MU_CNT = "1" *) 
(* C_PROBE318_TYPE = "1" *) (* C_PROBE318_WIDTH = "1" *) (* C_PROBE319_MU_CNT = "1" *) 
(* C_PROBE319_TYPE = "1" *) (* C_PROBE319_WIDTH = "1" *) (* C_PROBE31_MU_CNT = "1" *) 
(* C_PROBE31_TYPE = "1" *) (* C_PROBE31_WIDTH = "1" *) (* C_PROBE320_MU_CNT = "1" *) 
(* C_PROBE320_TYPE = "1" *) (* C_PROBE320_WIDTH = "1" *) (* C_PROBE321_MU_CNT = "1" *) 
(* C_PROBE321_TYPE = "1" *) (* C_PROBE321_WIDTH = "1" *) (* C_PROBE322_MU_CNT = "1" *) 
(* C_PROBE322_TYPE = "1" *) (* C_PROBE322_WIDTH = "1" *) (* C_PROBE323_MU_CNT = "1" *) 
(* C_PROBE323_TYPE = "1" *) (* C_PROBE323_WIDTH = "1" *) (* C_PROBE324_MU_CNT = "1" *) 
(* C_PROBE324_TYPE = "1" *) (* C_PROBE324_WIDTH = "1" *) (* C_PROBE325_MU_CNT = "1" *) 
(* C_PROBE325_TYPE = "1" *) (* C_PROBE325_WIDTH = "1" *) (* C_PROBE326_MU_CNT = "1" *) 
(* C_PROBE326_TYPE = "1" *) (* C_PROBE326_WIDTH = "1" *) (* C_PROBE327_MU_CNT = "1" *) 
(* C_PROBE327_TYPE = "1" *) (* C_PROBE327_WIDTH = "1" *) (* C_PROBE328_MU_CNT = "1" *) 
(* C_PROBE328_TYPE = "1" *) (* C_PROBE328_WIDTH = "1" *) (* C_PROBE329_MU_CNT = "1" *) 
(* C_PROBE329_TYPE = "1" *) (* C_PROBE329_WIDTH = "1" *) (* C_PROBE32_MU_CNT = "1" *) 
(* C_PROBE32_TYPE = "1" *) (* C_PROBE32_WIDTH = "1" *) (* C_PROBE330_MU_CNT = "1" *) 
(* C_PROBE330_TYPE = "1" *) (* C_PROBE330_WIDTH = "1" *) (* C_PROBE331_MU_CNT = "1" *) 
(* C_PROBE331_TYPE = "1" *) (* C_PROBE331_WIDTH = "1" *) (* C_PROBE332_MU_CNT = "1" *) 
(* C_PROBE332_TYPE = "1" *) (* C_PROBE332_WIDTH = "1" *) (* C_PROBE333_MU_CNT = "1" *) 
(* C_PROBE333_TYPE = "1" *) (* C_PROBE333_WIDTH = "1" *) (* C_PROBE334_MU_CNT = "1" *) 
(* C_PROBE334_TYPE = "1" *) (* C_PROBE334_WIDTH = "1" *) (* C_PROBE335_MU_CNT = "1" *) 
(* C_PROBE335_TYPE = "1" *) (* C_PROBE335_WIDTH = "1" *) (* C_PROBE336_MU_CNT = "1" *) 
(* C_PROBE336_TYPE = "1" *) (* C_PROBE336_WIDTH = "1" *) (* C_PROBE337_MU_CNT = "1" *) 
(* C_PROBE337_TYPE = "1" *) (* C_PROBE337_WIDTH = "1" *) (* C_PROBE338_MU_CNT = "1" *) 
(* C_PROBE338_TYPE = "1" *) (* C_PROBE338_WIDTH = "1" *) (* C_PROBE339_MU_CNT = "1" *) 
(* C_PROBE339_TYPE = "1" *) (* C_PROBE339_WIDTH = "1" *) (* C_PROBE33_MU_CNT = "1" *) 
(* C_PROBE33_TYPE = "1" *) (* C_PROBE33_WIDTH = "1" *) (* C_PROBE340_MU_CNT = "1" *) 
(* C_PROBE340_TYPE = "1" *) (* C_PROBE340_WIDTH = "1" *) (* C_PROBE341_MU_CNT = "1" *) 
(* C_PROBE341_TYPE = "1" *) (* C_PROBE341_WIDTH = "1" *) (* C_PROBE342_MU_CNT = "1" *) 
(* C_PROBE342_TYPE = "1" *) (* C_PROBE342_WIDTH = "1" *) (* C_PROBE343_MU_CNT = "1" *) 
(* C_PROBE343_TYPE = "1" *) (* C_PROBE343_WIDTH = "1" *) (* C_PROBE344_MU_CNT = "1" *) 
(* C_PROBE344_TYPE = "1" *) (* C_PROBE344_WIDTH = "1" *) (* C_PROBE345_MU_CNT = "1" *) 
(* C_PROBE345_TYPE = "1" *) (* C_PROBE345_WIDTH = "1" *) (* C_PROBE346_MU_CNT = "1" *) 
(* C_PROBE346_TYPE = "1" *) (* C_PROBE346_WIDTH = "1" *) (* C_PROBE347_MU_CNT = "1" *) 
(* C_PROBE347_TYPE = "1" *) (* C_PROBE347_WIDTH = "1" *) (* C_PROBE348_MU_CNT = "1" *) 
(* C_PROBE348_TYPE = "1" *) (* C_PROBE348_WIDTH = "1" *) (* C_PROBE349_MU_CNT = "1" *) 
(* C_PROBE349_TYPE = "1" *) (* C_PROBE349_WIDTH = "1" *) (* C_PROBE34_MU_CNT = "1" *) 
(* C_PROBE34_TYPE = "1" *) (* C_PROBE34_WIDTH = "1" *) (* C_PROBE350_MU_CNT = "1" *) 
(* C_PROBE350_TYPE = "1" *) (* C_PROBE350_WIDTH = "1" *) (* C_PROBE351_MU_CNT = "1" *) 
(* C_PROBE351_TYPE = "1" *) (* C_PROBE351_WIDTH = "1" *) (* C_PROBE352_MU_CNT = "1" *) 
(* C_PROBE352_TYPE = "1" *) (* C_PROBE352_WIDTH = "1" *) (* C_PROBE353_MU_CNT = "1" *) 
(* C_PROBE353_TYPE = "1" *) (* C_PROBE353_WIDTH = "1" *) (* C_PROBE354_MU_CNT = "1" *) 
(* C_PROBE354_TYPE = "1" *) (* C_PROBE354_WIDTH = "1" *) (* C_PROBE355_MU_CNT = "1" *) 
(* C_PROBE355_TYPE = "1" *) (* C_PROBE355_WIDTH = "1" *) (* C_PROBE356_MU_CNT = "1" *) 
(* C_PROBE356_TYPE = "1" *) (* C_PROBE356_WIDTH = "1" *) (* C_PROBE357_MU_CNT = "1" *) 
(* C_PROBE357_TYPE = "1" *) (* C_PROBE357_WIDTH = "1" *) (* C_PROBE358_MU_CNT = "1" *) 
(* C_PROBE358_TYPE = "1" *) (* C_PROBE358_WIDTH = "1" *) (* C_PROBE359_MU_CNT = "1" *) 
(* C_PROBE359_TYPE = "1" *) (* C_PROBE359_WIDTH = "1" *) (* C_PROBE35_MU_CNT = "1" *) 
(* C_PROBE35_TYPE = "1" *) (* C_PROBE35_WIDTH = "1" *) (* C_PROBE360_MU_CNT = "1" *) 
(* C_PROBE360_TYPE = "1" *) (* C_PROBE360_WIDTH = "1" *) (* C_PROBE361_MU_CNT = "1" *) 
(* C_PROBE361_TYPE = "1" *) (* C_PROBE361_WIDTH = "1" *) (* C_PROBE362_MU_CNT = "1" *) 
(* C_PROBE362_TYPE = "1" *) (* C_PROBE362_WIDTH = "1" *) (* C_PROBE363_MU_CNT = "1" *) 
(* C_PROBE363_TYPE = "1" *) (* C_PROBE363_WIDTH = "1" *) (* C_PROBE364_MU_CNT = "1" *) 
(* C_PROBE364_TYPE = "1" *) (* C_PROBE364_WIDTH = "1" *) (* C_PROBE365_MU_CNT = "1" *) 
(* C_PROBE365_TYPE = "1" *) (* C_PROBE365_WIDTH = "1" *) (* C_PROBE366_MU_CNT = "1" *) 
(* C_PROBE366_TYPE = "1" *) (* C_PROBE366_WIDTH = "1" *) (* C_PROBE367_MU_CNT = "1" *) 
(* C_PROBE367_TYPE = "1" *) (* C_PROBE367_WIDTH = "1" *) (* C_PROBE368_MU_CNT = "1" *) 
(* C_PROBE368_TYPE = "1" *) (* C_PROBE368_WIDTH = "1" *) (* C_PROBE369_MU_CNT = "1" *) 
(* C_PROBE369_TYPE = "1" *) (* C_PROBE369_WIDTH = "1" *) (* C_PROBE36_MU_CNT = "1" *) 
(* C_PROBE36_TYPE = "1" *) (* C_PROBE36_WIDTH = "1" *) (* C_PROBE370_MU_CNT = "1" *) 
(* C_PROBE370_TYPE = "1" *) (* C_PROBE370_WIDTH = "1" *) (* C_PROBE371_MU_CNT = "1" *) 
(* C_PROBE371_TYPE = "1" *) (* C_PROBE371_WIDTH = "1" *) (* C_PROBE372_MU_CNT = "1" *) 
(* C_PROBE372_TYPE = "1" *) (* C_PROBE372_WIDTH = "1" *) (* C_PROBE373_MU_CNT = "1" *) 
(* C_PROBE373_TYPE = "1" *) (* C_PROBE373_WIDTH = "1" *) (* C_PROBE374_MU_CNT = "1" *) 
(* C_PROBE374_TYPE = "1" *) (* C_PROBE374_WIDTH = "1" *) (* C_PROBE375_MU_CNT = "1" *) 
(* C_PROBE375_TYPE = "1" *) (* C_PROBE375_WIDTH = "1" *) (* C_PROBE376_MU_CNT = "1" *) 
(* C_PROBE376_TYPE = "1" *) (* C_PROBE376_WIDTH = "1" *) (* C_PROBE377_MU_CNT = "1" *) 
(* C_PROBE377_TYPE = "1" *) (* C_PROBE377_WIDTH = "1" *) (* C_PROBE378_MU_CNT = "1" *) 
(* C_PROBE378_TYPE = "1" *) (* C_PROBE378_WIDTH = "1" *) (* C_PROBE379_MU_CNT = "1" *) 
(* C_PROBE379_TYPE = "1" *) (* C_PROBE379_WIDTH = "1" *) (* C_PROBE37_MU_CNT = "1" *) 
(* C_PROBE37_TYPE = "1" *) (* C_PROBE37_WIDTH = "1" *) (* C_PROBE380_MU_CNT = "1" *) 
(* C_PROBE380_TYPE = "1" *) (* C_PROBE380_WIDTH = "1" *) (* C_PROBE381_MU_CNT = "1" *) 
(* C_PROBE381_TYPE = "1" *) (* C_PROBE381_WIDTH = "1" *) (* C_PROBE382_MU_CNT = "1" *) 
(* C_PROBE382_TYPE = "1" *) (* C_PROBE382_WIDTH = "1" *) (* C_PROBE383_MU_CNT = "1" *) 
(* C_PROBE383_TYPE = "1" *) (* C_PROBE383_WIDTH = "1" *) (* C_PROBE384_MU_CNT = "1" *) 
(* C_PROBE384_TYPE = "1" *) (* C_PROBE384_WIDTH = "1" *) (* C_PROBE385_MU_CNT = "1" *) 
(* C_PROBE385_TYPE = "1" *) (* C_PROBE385_WIDTH = "1" *) (* C_PROBE386_MU_CNT = "1" *) 
(* C_PROBE386_TYPE = "1" *) (* C_PROBE386_WIDTH = "1" *) (* C_PROBE387_MU_CNT = "1" *) 
(* C_PROBE387_TYPE = "1" *) (* C_PROBE387_WIDTH = "1" *) (* C_PROBE388_MU_CNT = "1" *) 
(* C_PROBE388_TYPE = "1" *) (* C_PROBE388_WIDTH = "1" *) (* C_PROBE389_MU_CNT = "1" *) 
(* C_PROBE389_TYPE = "1" *) (* C_PROBE389_WIDTH = "1" *) (* C_PROBE38_MU_CNT = "1" *) 
(* C_PROBE38_TYPE = "1" *) (* C_PROBE38_WIDTH = "1" *) (* C_PROBE390_MU_CNT = "1" *) 
(* C_PROBE390_TYPE = "1" *) (* C_PROBE390_WIDTH = "1" *) (* C_PROBE391_MU_CNT = "1" *) 
(* C_PROBE391_TYPE = "1" *) (* C_PROBE391_WIDTH = "1" *) (* C_PROBE392_MU_CNT = "1" *) 
(* C_PROBE392_TYPE = "1" *) (* C_PROBE392_WIDTH = "1" *) (* C_PROBE393_MU_CNT = "1" *) 
(* C_PROBE393_TYPE = "1" *) (* C_PROBE393_WIDTH = "1" *) (* C_PROBE394_MU_CNT = "1" *) 
(* C_PROBE394_TYPE = "1" *) (* C_PROBE394_WIDTH = "1" *) (* C_PROBE395_MU_CNT = "1" *) 
(* C_PROBE395_TYPE = "1" *) (* C_PROBE395_WIDTH = "1" *) (* C_PROBE396_MU_CNT = "1" *) 
(* C_PROBE396_TYPE = "1" *) (* C_PROBE396_WIDTH = "1" *) (* C_PROBE397_MU_CNT = "1" *) 
(* C_PROBE397_TYPE = "1" *) (* C_PROBE397_WIDTH = "1" *) (* C_PROBE398_MU_CNT = "1" *) 
(* C_PROBE398_TYPE = "1" *) (* C_PROBE398_WIDTH = "1" *) (* C_PROBE399_MU_CNT = "1" *) 
(* C_PROBE399_TYPE = "1" *) (* C_PROBE399_WIDTH = "1" *) (* C_PROBE39_MU_CNT = "1" *) 
(* C_PROBE39_TYPE = "1" *) (* C_PROBE39_WIDTH = "1" *) (* C_PROBE3_MU_CNT = "1" *) 
(* C_PROBE3_TYPE = "1" *) (* C_PROBE3_WIDTH = "1" *) (* C_PROBE400_MU_CNT = "1" *) 
(* C_PROBE400_TYPE = "1" *) (* C_PROBE400_WIDTH = "1" *) (* C_PROBE401_MU_CNT = "1" *) 
(* C_PROBE401_TYPE = "1" *) (* C_PROBE401_WIDTH = "1" *) (* C_PROBE402_MU_CNT = "1" *) 
(* C_PROBE402_TYPE = "1" *) (* C_PROBE402_WIDTH = "1" *) (* C_PROBE403_MU_CNT = "1" *) 
(* C_PROBE403_TYPE = "1" *) (* C_PROBE403_WIDTH = "1" *) (* C_PROBE404_MU_CNT = "1" *) 
(* C_PROBE404_TYPE = "1" *) (* C_PROBE404_WIDTH = "1" *) (* C_PROBE405_MU_CNT = "1" *) 
(* C_PROBE405_TYPE = "1" *) (* C_PROBE405_WIDTH = "1" *) (* C_PROBE406_MU_CNT = "1" *) 
(* C_PROBE406_TYPE = "1" *) (* C_PROBE406_WIDTH = "1" *) (* C_PROBE407_MU_CNT = "1" *) 
(* C_PROBE407_TYPE = "1" *) (* C_PROBE407_WIDTH = "1" *) (* C_PROBE408_MU_CNT = "1" *) 
(* C_PROBE408_TYPE = "1" *) (* C_PROBE408_WIDTH = "1" *) (* C_PROBE409_MU_CNT = "1" *) 
(* C_PROBE409_TYPE = "1" *) (* C_PROBE409_WIDTH = "1" *) (* C_PROBE40_MU_CNT = "1" *) 
(* C_PROBE40_TYPE = "1" *) (* C_PROBE40_WIDTH = "1" *) (* C_PROBE410_MU_CNT = "1" *) 
(* C_PROBE410_TYPE = "1" *) (* C_PROBE410_WIDTH = "1" *) (* C_PROBE411_MU_CNT = "1" *) 
(* C_PROBE411_TYPE = "1" *) (* C_PROBE411_WIDTH = "1" *) (* C_PROBE412_MU_CNT = "1" *) 
(* C_PROBE412_TYPE = "1" *) (* C_PROBE412_WIDTH = "1" *) (* C_PROBE413_MU_CNT = "1" *) 
(* C_PROBE413_TYPE = "1" *) (* C_PROBE413_WIDTH = "1" *) (* C_PROBE414_MU_CNT = "1" *) 
(* C_PROBE414_TYPE = "1" *) (* C_PROBE414_WIDTH = "1" *) (* C_PROBE415_MU_CNT = "1" *) 
(* C_PROBE415_TYPE = "1" *) (* C_PROBE415_WIDTH = "1" *) (* C_PROBE416_MU_CNT = "1" *) 
(* C_PROBE416_TYPE = "1" *) (* C_PROBE416_WIDTH = "1" *) (* C_PROBE417_MU_CNT = "1" *) 
(* C_PROBE417_TYPE = "1" *) (* C_PROBE417_WIDTH = "1" *) (* C_PROBE418_MU_CNT = "1" *) 
(* C_PROBE418_TYPE = "1" *) (* C_PROBE418_WIDTH = "1" *) (* C_PROBE419_MU_CNT = "1" *) 
(* C_PROBE419_TYPE = "1" *) (* C_PROBE419_WIDTH = "1" *) (* C_PROBE41_MU_CNT = "1" *) 
(* C_PROBE41_TYPE = "1" *) (* C_PROBE41_WIDTH = "1" *) (* C_PROBE420_MU_CNT = "1" *) 
(* C_PROBE420_TYPE = "1" *) (* C_PROBE420_WIDTH = "1" *) (* C_PROBE421_MU_CNT = "1" *) 
(* C_PROBE421_TYPE = "1" *) (* C_PROBE421_WIDTH = "1" *) (* C_PROBE422_MU_CNT = "1" *) 
(* C_PROBE422_TYPE = "1" *) (* C_PROBE422_WIDTH = "1" *) (* C_PROBE423_MU_CNT = "1" *) 
(* C_PROBE423_TYPE = "1" *) (* C_PROBE423_WIDTH = "1" *) (* C_PROBE424_MU_CNT = "1" *) 
(* C_PROBE424_TYPE = "1" *) (* C_PROBE424_WIDTH = "1" *) (* C_PROBE425_MU_CNT = "1" *) 
(* C_PROBE425_TYPE = "1" *) (* C_PROBE425_WIDTH = "1" *) (* C_PROBE426_MU_CNT = "1" *) 
(* C_PROBE426_TYPE = "1" *) (* C_PROBE426_WIDTH = "1" *) (* C_PROBE427_MU_CNT = "1" *) 
(* C_PROBE427_TYPE = "1" *) (* C_PROBE427_WIDTH = "1" *) (* C_PROBE428_MU_CNT = "1" *) 
(* C_PROBE428_TYPE = "1" *) (* C_PROBE428_WIDTH = "1" *) (* C_PROBE429_MU_CNT = "1" *) 
(* C_PROBE429_TYPE = "1" *) (* C_PROBE429_WIDTH = "1" *) (* C_PROBE42_MU_CNT = "1" *) 
(* C_PROBE42_TYPE = "1" *) (* C_PROBE42_WIDTH = "1" *) (* C_PROBE430_MU_CNT = "1" *) 
(* C_PROBE430_TYPE = "1" *) (* C_PROBE430_WIDTH = "1" *) (* C_PROBE431_MU_CNT = "1" *) 
(* C_PROBE431_TYPE = "1" *) (* C_PROBE431_WIDTH = "1" *) (* C_PROBE432_MU_CNT = "1" *) 
(* C_PROBE432_TYPE = "1" *) (* C_PROBE432_WIDTH = "1" *) (* C_PROBE433_MU_CNT = "1" *) 
(* C_PROBE433_TYPE = "1" *) (* C_PROBE433_WIDTH = "1" *) (* C_PROBE434_MU_CNT = "1" *) 
(* C_PROBE434_TYPE = "1" *) (* C_PROBE434_WIDTH = "1" *) (* C_PROBE435_MU_CNT = "1" *) 
(* C_PROBE435_TYPE = "1" *) (* C_PROBE435_WIDTH = "1" *) (* C_PROBE436_MU_CNT = "1" *) 
(* C_PROBE436_TYPE = "1" *) (* C_PROBE436_WIDTH = "1" *) (* C_PROBE437_MU_CNT = "1" *) 
(* C_PROBE437_TYPE = "1" *) (* C_PROBE437_WIDTH = "1" *) (* C_PROBE438_MU_CNT = "1" *) 
(* C_PROBE438_TYPE = "1" *) (* C_PROBE438_WIDTH = "1" *) (* C_PROBE439_MU_CNT = "1" *) 
(* C_PROBE439_TYPE = "1" *) (* C_PROBE439_WIDTH = "1" *) (* C_PROBE43_MU_CNT = "1" *) 
(* C_PROBE43_TYPE = "1" *) (* C_PROBE43_WIDTH = "1" *) (* C_PROBE440_MU_CNT = "1" *) 
(* C_PROBE440_TYPE = "1" *) (* C_PROBE440_WIDTH = "1" *) (* C_PROBE441_MU_CNT = "1" *) 
(* C_PROBE441_TYPE = "1" *) (* C_PROBE441_WIDTH = "1" *) (* C_PROBE442_MU_CNT = "1" *) 
(* C_PROBE442_TYPE = "1" *) (* C_PROBE442_WIDTH = "1" *) (* C_PROBE443_MU_CNT = "1" *) 
(* C_PROBE443_TYPE = "1" *) (* C_PROBE443_WIDTH = "1" *) (* C_PROBE444_MU_CNT = "1" *) 
(* C_PROBE444_TYPE = "1" *) (* C_PROBE444_WIDTH = "1" *) (* C_PROBE445_MU_CNT = "1" *) 
(* C_PROBE445_TYPE = "1" *) (* C_PROBE445_WIDTH = "1" *) (* C_PROBE446_MU_CNT = "1" *) 
(* C_PROBE446_TYPE = "1" *) (* C_PROBE446_WIDTH = "1" *) (* C_PROBE447_MU_CNT = "1" *) 
(* C_PROBE447_TYPE = "1" *) (* C_PROBE447_WIDTH = "1" *) (* C_PROBE448_MU_CNT = "1" *) 
(* C_PROBE448_TYPE = "1" *) (* C_PROBE448_WIDTH = "1" *) (* C_PROBE449_MU_CNT = "1" *) 
(* C_PROBE449_TYPE = "1" *) (* C_PROBE449_WIDTH = "1" *) (* C_PROBE44_MU_CNT = "1" *) 
(* C_PROBE44_TYPE = "1" *) (* C_PROBE44_WIDTH = "1" *) (* C_PROBE450_MU_CNT = "1" *) 
(* C_PROBE450_TYPE = "1" *) (* C_PROBE450_WIDTH = "1" *) (* C_PROBE451_MU_CNT = "1" *) 
(* C_PROBE451_TYPE = "1" *) (* C_PROBE451_WIDTH = "1" *) (* C_PROBE452_MU_CNT = "1" *) 
(* C_PROBE452_TYPE = "1" *) (* C_PROBE452_WIDTH = "1" *) (* C_PROBE453_MU_CNT = "1" *) 
(* C_PROBE453_TYPE = "1" *) (* C_PROBE453_WIDTH = "1" *) (* C_PROBE454_MU_CNT = "1" *) 
(* C_PROBE454_TYPE = "1" *) (* C_PROBE454_WIDTH = "1" *) (* C_PROBE455_MU_CNT = "1" *) 
(* C_PROBE455_TYPE = "1" *) (* C_PROBE455_WIDTH = "1" *) (* C_PROBE456_MU_CNT = "1" *) 
(* C_PROBE456_TYPE = "1" *) (* C_PROBE456_WIDTH = "1" *) (* C_PROBE457_MU_CNT = "1" *) 
(* C_PROBE457_TYPE = "1" *) (* C_PROBE457_WIDTH = "1" *) (* C_PROBE458_MU_CNT = "1" *) 
(* C_PROBE458_TYPE = "1" *) (* C_PROBE458_WIDTH = "1" *) (* C_PROBE459_MU_CNT = "1" *) 
(* C_PROBE459_TYPE = "1" *) (* C_PROBE459_WIDTH = "1" *) (* C_PROBE45_MU_CNT = "1" *) 
(* C_PROBE45_TYPE = "1" *) (* C_PROBE45_WIDTH = "1" *) (* C_PROBE460_MU_CNT = "1" *) 
(* C_PROBE460_TYPE = "1" *) (* C_PROBE460_WIDTH = "1" *) (* C_PROBE461_MU_CNT = "1" *) 
(* C_PROBE461_TYPE = "1" *) (* C_PROBE461_WIDTH = "1" *) (* C_PROBE462_MU_CNT = "1" *) 
(* C_PROBE462_TYPE = "1" *) (* C_PROBE462_WIDTH = "1" *) (* C_PROBE463_MU_CNT = "1" *) 
(* C_PROBE463_TYPE = "1" *) (* C_PROBE463_WIDTH = "1" *) (* C_PROBE464_MU_CNT = "1" *) 
(* C_PROBE464_TYPE = "1" *) (* C_PROBE464_WIDTH = "1" *) (* C_PROBE465_MU_CNT = "1" *) 
(* C_PROBE465_TYPE = "1" *) (* C_PROBE465_WIDTH = "1" *) (* C_PROBE466_MU_CNT = "1" *) 
(* C_PROBE466_TYPE = "1" *) (* C_PROBE466_WIDTH = "1" *) (* C_PROBE467_MU_CNT = "1" *) 
(* C_PROBE467_TYPE = "1" *) (* C_PROBE467_WIDTH = "1" *) (* C_PROBE468_MU_CNT = "1" *) 
(* C_PROBE468_TYPE = "1" *) (* C_PROBE468_WIDTH = "1" *) (* C_PROBE469_MU_CNT = "1" *) 
(* C_PROBE469_TYPE = "1" *) (* C_PROBE469_WIDTH = "1" *) (* C_PROBE46_MU_CNT = "1" *) 
(* C_PROBE46_TYPE = "1" *) (* C_PROBE46_WIDTH = "1" *) (* C_PROBE470_MU_CNT = "1" *) 
(* C_PROBE470_TYPE = "1" *) (* C_PROBE470_WIDTH = "1" *) (* C_PROBE471_MU_CNT = "1" *) 
(* C_PROBE471_TYPE = "1" *) (* C_PROBE471_WIDTH = "1" *) (* C_PROBE472_MU_CNT = "1" *) 
(* C_PROBE472_TYPE = "1" *) (* C_PROBE472_WIDTH = "1" *) (* C_PROBE473_MU_CNT = "1" *) 
(* C_PROBE473_TYPE = "1" *) (* C_PROBE473_WIDTH = "1" *) (* C_PROBE474_MU_CNT = "1" *) 
(* C_PROBE474_TYPE = "1" *) (* C_PROBE474_WIDTH = "1" *) (* C_PROBE475_MU_CNT = "1" *) 
(* C_PROBE475_TYPE = "1" *) (* C_PROBE475_WIDTH = "1" *) (* C_PROBE476_MU_CNT = "1" *) 
(* C_PROBE476_TYPE = "1" *) (* C_PROBE476_WIDTH = "1" *) (* C_PROBE477_MU_CNT = "1" *) 
(* C_PROBE477_TYPE = "1" *) (* C_PROBE477_WIDTH = "1" *) (* C_PROBE478_MU_CNT = "1" *) 
(* C_PROBE478_TYPE = "1" *) (* C_PROBE478_WIDTH = "1" *) (* C_PROBE479_MU_CNT = "1" *) 
(* C_PROBE479_TYPE = "1" *) (* C_PROBE479_WIDTH = "1" *) (* C_PROBE47_MU_CNT = "1" *) 
(* C_PROBE47_TYPE = "1" *) (* C_PROBE47_WIDTH = "1" *) (* C_PROBE480_MU_CNT = "1" *) 
(* C_PROBE480_TYPE = "1" *) (* C_PROBE480_WIDTH = "1" *) (* C_PROBE481_MU_CNT = "1" *) 
(* C_PROBE481_TYPE = "1" *) (* C_PROBE481_WIDTH = "1" *) (* C_PROBE482_MU_CNT = "1" *) 
(* C_PROBE482_TYPE = "1" *) (* C_PROBE482_WIDTH = "1" *) (* C_PROBE483_MU_CNT = "1" *) 
(* C_PROBE483_TYPE = "1" *) (* C_PROBE483_WIDTH = "1" *) (* C_PROBE484_MU_CNT = "1" *) 
(* C_PROBE484_TYPE = "1" *) (* C_PROBE484_WIDTH = "1" *) (* C_PROBE485_MU_CNT = "1" *) 
(* C_PROBE485_TYPE = "1" *) (* C_PROBE485_WIDTH = "1" *) (* C_PROBE486_MU_CNT = "1" *) 
(* C_PROBE486_TYPE = "1" *) (* C_PROBE486_WIDTH = "1" *) (* C_PROBE487_MU_CNT = "1" *) 
(* C_PROBE487_TYPE = "1" *) (* C_PROBE487_WIDTH = "1" *) (* C_PROBE488_MU_CNT = "1" *) 
(* C_PROBE488_TYPE = "1" *) (* C_PROBE488_WIDTH = "1" *) (* C_PROBE489_MU_CNT = "1" *) 
(* C_PROBE489_TYPE = "1" *) (* C_PROBE489_WIDTH = "1" *) (* C_PROBE48_MU_CNT = "1" *) 
(* C_PROBE48_TYPE = "1" *) (* C_PROBE48_WIDTH = "1" *) (* C_PROBE490_MU_CNT = "1" *) 
(* C_PROBE490_TYPE = "1" *) (* C_PROBE490_WIDTH = "1" *) (* C_PROBE491_MU_CNT = "1" *) 
(* C_PROBE491_TYPE = "1" *) (* C_PROBE491_WIDTH = "1" *) (* C_PROBE492_MU_CNT = "1" *) 
(* C_PROBE492_TYPE = "1" *) (* C_PROBE492_WIDTH = "1" *) (* C_PROBE493_MU_CNT = "1" *) 
(* C_PROBE493_TYPE = "1" *) (* C_PROBE493_WIDTH = "1" *) (* C_PROBE494_MU_CNT = "1" *) 
(* C_PROBE494_TYPE = "1" *) (* C_PROBE494_WIDTH = "1" *) (* C_PROBE495_MU_CNT = "1" *) 
(* C_PROBE495_TYPE = "1" *) (* C_PROBE495_WIDTH = "1" *) (* C_PROBE496_MU_CNT = "1" *) 
(* C_PROBE496_TYPE = "1" *) (* C_PROBE496_WIDTH = "1" *) (* C_PROBE497_MU_CNT = "1" *) 
(* C_PROBE497_TYPE = "1" *) (* C_PROBE497_WIDTH = "1" *) (* C_PROBE498_MU_CNT = "1" *) 
(* C_PROBE498_TYPE = "1" *) (* C_PROBE498_WIDTH = "1" *) (* C_PROBE499_MU_CNT = "1" *) 
(* C_PROBE499_TYPE = "1" *) (* C_PROBE499_WIDTH = "1" *) (* C_PROBE49_MU_CNT = "1" *) 
(* C_PROBE49_TYPE = "1" *) (* C_PROBE49_WIDTH = "1" *) (* C_PROBE4_MU_CNT = "1" *) 
(* C_PROBE4_TYPE = "1" *) (* C_PROBE4_WIDTH = "1" *) (* C_PROBE500_MU_CNT = "1" *) 
(* C_PROBE500_TYPE = "1" *) (* C_PROBE500_WIDTH = "1" *) (* C_PROBE501_MU_CNT = "1" *) 
(* C_PROBE501_TYPE = "1" *) (* C_PROBE501_WIDTH = "1" *) (* C_PROBE502_MU_CNT = "1" *) 
(* C_PROBE502_TYPE = "1" *) (* C_PROBE502_WIDTH = "1" *) (* C_PROBE503_MU_CNT = "1" *) 
(* C_PROBE503_TYPE = "1" *) (* C_PROBE503_WIDTH = "1" *) (* C_PROBE504_MU_CNT = "1" *) 
(* C_PROBE504_TYPE = "1" *) (* C_PROBE504_WIDTH = "1" *) (* C_PROBE505_MU_CNT = "1" *) 
(* C_PROBE505_TYPE = "1" *) (* C_PROBE505_WIDTH = "1" *) (* C_PROBE506_MU_CNT = "1" *) 
(* C_PROBE506_TYPE = "1" *) (* C_PROBE506_WIDTH = "1" *) (* C_PROBE507_MU_CNT = "1" *) 
(* C_PROBE507_TYPE = "1" *) (* C_PROBE507_WIDTH = "1" *) (* C_PROBE508_MU_CNT = "1" *) 
(* C_PROBE508_TYPE = "1" *) (* C_PROBE508_WIDTH = "1" *) (* C_PROBE509_MU_CNT = "1" *) 
(* C_PROBE509_TYPE = "1" *) (* C_PROBE509_WIDTH = "1" *) (* C_PROBE50_MU_CNT = "1" *) 
(* C_PROBE50_TYPE = "1" *) (* C_PROBE50_WIDTH = "1" *) (* C_PROBE510_MU_CNT = "1" *) 
(* C_PROBE510_TYPE = "1" *) (* C_PROBE510_WIDTH = "1" *) (* C_PROBE511_MU_CNT = "1" *) 
(* C_PROBE511_TYPE = "1" *) (* C_PROBE511_WIDTH = "1" *) (* C_PROBE512_MU_CNT = "1" *) 
(* C_PROBE512_TYPE = "1" *) (* C_PROBE512_WIDTH = "1" *) (* C_PROBE513_MU_CNT = "1" *) 
(* C_PROBE513_TYPE = "1" *) (* C_PROBE513_WIDTH = "1" *) (* C_PROBE514_MU_CNT = "1" *) 
(* C_PROBE514_TYPE = "1" *) (* C_PROBE514_WIDTH = "1" *) (* C_PROBE515_MU_CNT = "1" *) 
(* C_PROBE515_TYPE = "1" *) (* C_PROBE515_WIDTH = "1" *) (* C_PROBE516_MU_CNT = "1" *) 
(* C_PROBE516_TYPE = "1" *) (* C_PROBE516_WIDTH = "1" *) (* C_PROBE517_MU_CNT = "1" *) 
(* C_PROBE517_TYPE = "1" *) (* C_PROBE517_WIDTH = "1" *) (* C_PROBE518_MU_CNT = "1" *) 
(* C_PROBE518_TYPE = "1" *) (* C_PROBE518_WIDTH = "1" *) (* C_PROBE519_MU_CNT = "1" *) 
(* C_PROBE519_TYPE = "1" *) (* C_PROBE519_WIDTH = "1" *) (* C_PROBE51_MU_CNT = "1" *) 
(* C_PROBE51_TYPE = "1" *) (* C_PROBE51_WIDTH = "1" *) (* C_PROBE520_MU_CNT = "1" *) 
(* C_PROBE520_TYPE = "1" *) (* C_PROBE520_WIDTH = "1" *) (* C_PROBE521_MU_CNT = "1" *) 
(* C_PROBE521_TYPE = "1" *) (* C_PROBE521_WIDTH = "1" *) (* C_PROBE522_MU_CNT = "1" *) 
(* C_PROBE522_TYPE = "1" *) (* C_PROBE522_WIDTH = "1" *) (* C_PROBE523_MU_CNT = "1" *) 
(* C_PROBE523_TYPE = "1" *) (* C_PROBE523_WIDTH = "1" *) (* C_PROBE524_MU_CNT = "1" *) 
(* C_PROBE524_TYPE = "1" *) (* C_PROBE524_WIDTH = "1" *) (* C_PROBE525_MU_CNT = "1" *) 
(* C_PROBE525_TYPE = "1" *) (* C_PROBE525_WIDTH = "1" *) (* C_PROBE526_MU_CNT = "1" *) 
(* C_PROBE526_TYPE = "1" *) (* C_PROBE526_WIDTH = "1" *) (* C_PROBE527_MU_CNT = "1" *) 
(* C_PROBE527_TYPE = "1" *) (* C_PROBE527_WIDTH = "1" *) (* C_PROBE528_MU_CNT = "1" *) 
(* C_PROBE528_TYPE = "1" *) (* C_PROBE528_WIDTH = "1" *) (* C_PROBE529_MU_CNT = "1" *) 
(* C_PROBE529_TYPE = "1" *) (* C_PROBE529_WIDTH = "1" *) (* C_PROBE52_MU_CNT = "1" *) 
(* C_PROBE52_TYPE = "1" *) (* C_PROBE52_WIDTH = "1" *) (* C_PROBE530_MU_CNT = "1" *) 
(* C_PROBE530_TYPE = "1" *) (* C_PROBE530_WIDTH = "1" *) (* C_PROBE531_MU_CNT = "1" *) 
(* C_PROBE531_TYPE = "1" *) (* C_PROBE531_WIDTH = "1" *) (* C_PROBE532_MU_CNT = "1" *) 
(* C_PROBE532_TYPE = "1" *) (* C_PROBE532_WIDTH = "1" *) (* C_PROBE533_MU_CNT = "1" *) 
(* C_PROBE533_TYPE = "1" *) (* C_PROBE533_WIDTH = "1" *) (* C_PROBE534_MU_CNT = "1" *) 
(* C_PROBE534_TYPE = "1" *) (* C_PROBE534_WIDTH = "1" *) (* C_PROBE535_MU_CNT = "1" *) 
(* C_PROBE535_TYPE = "1" *) (* C_PROBE535_WIDTH = "1" *) (* C_PROBE536_MU_CNT = "1" *) 
(* C_PROBE536_TYPE = "1" *) (* C_PROBE536_WIDTH = "1" *) (* C_PROBE537_MU_CNT = "1" *) 
(* C_PROBE537_TYPE = "1" *) (* C_PROBE537_WIDTH = "1" *) (* C_PROBE538_MU_CNT = "1" *) 
(* C_PROBE538_TYPE = "1" *) (* C_PROBE538_WIDTH = "1" *) (* C_PROBE539_MU_CNT = "1" *) 
(* C_PROBE539_TYPE = "1" *) (* C_PROBE539_WIDTH = "1" *) (* C_PROBE53_MU_CNT = "1" *) 
(* C_PROBE53_TYPE = "1" *) (* C_PROBE53_WIDTH = "1" *) (* C_PROBE540_MU_CNT = "1" *) 
(* C_PROBE540_TYPE = "1" *) (* C_PROBE540_WIDTH = "1" *) (* C_PROBE541_MU_CNT = "1" *) 
(* C_PROBE541_TYPE = "1" *) (* C_PROBE541_WIDTH = "1" *) (* C_PROBE542_MU_CNT = "1" *) 
(* C_PROBE542_TYPE = "1" *) (* C_PROBE542_WIDTH = "1" *) (* C_PROBE543_MU_CNT = "1" *) 
(* C_PROBE543_TYPE = "1" *) (* C_PROBE543_WIDTH = "1" *) (* C_PROBE544_MU_CNT = "1" *) 
(* C_PROBE544_TYPE = "1" *) (* C_PROBE544_WIDTH = "1" *) (* C_PROBE545_MU_CNT = "1" *) 
(* C_PROBE545_TYPE = "1" *) (* C_PROBE545_WIDTH = "1" *) (* C_PROBE546_MU_CNT = "1" *) 
(* C_PROBE546_TYPE = "1" *) (* C_PROBE546_WIDTH = "1" *) (* C_PROBE547_MU_CNT = "1" *) 
(* C_PROBE547_TYPE = "1" *) (* C_PROBE547_WIDTH = "1" *) (* C_PROBE548_MU_CNT = "1" *) 
(* C_PROBE548_TYPE = "1" *) (* C_PROBE548_WIDTH = "1" *) (* C_PROBE549_MU_CNT = "1" *) 
(* C_PROBE549_TYPE = "1" *) (* C_PROBE549_WIDTH = "1" *) (* C_PROBE54_MU_CNT = "1" *) 
(* C_PROBE54_TYPE = "1" *) (* C_PROBE54_WIDTH = "1" *) (* C_PROBE550_MU_CNT = "1" *) 
(* C_PROBE550_TYPE = "1" *) (* C_PROBE550_WIDTH = "1" *) (* C_PROBE551_MU_CNT = "1" *) 
(* C_PROBE551_TYPE = "1" *) (* C_PROBE551_WIDTH = "1" *) (* C_PROBE552_MU_CNT = "1" *) 
(* C_PROBE552_TYPE = "1" *) (* C_PROBE552_WIDTH = "1" *) (* C_PROBE553_MU_CNT = "1" *) 
(* C_PROBE553_TYPE = "1" *) (* C_PROBE553_WIDTH = "1" *) (* C_PROBE554_MU_CNT = "1" *) 
(* C_PROBE554_TYPE = "1" *) (* C_PROBE554_WIDTH = "1" *) (* C_PROBE555_MU_CNT = "1" *) 
(* C_PROBE555_TYPE = "1" *) (* C_PROBE555_WIDTH = "1" *) (* C_PROBE556_MU_CNT = "1" *) 
(* C_PROBE556_TYPE = "1" *) (* C_PROBE556_WIDTH = "1" *) (* C_PROBE557_MU_CNT = "1" *) 
(* C_PROBE557_TYPE = "1" *) (* C_PROBE557_WIDTH = "1" *) (* C_PROBE558_MU_CNT = "1" *) 
(* C_PROBE558_TYPE = "1" *) (* C_PROBE558_WIDTH = "1" *) (* C_PROBE559_MU_CNT = "1" *) 
(* C_PROBE559_TYPE = "1" *) (* C_PROBE559_WIDTH = "1" *) (* C_PROBE55_MU_CNT = "1" *) 
(* C_PROBE55_TYPE = "1" *) (* C_PROBE55_WIDTH = "1" *) (* C_PROBE560_MU_CNT = "1" *) 
(* C_PROBE560_TYPE = "1" *) (* C_PROBE560_WIDTH = "1" *) (* C_PROBE561_MU_CNT = "1" *) 
(* C_PROBE561_TYPE = "1" *) (* C_PROBE561_WIDTH = "1" *) (* C_PROBE562_MU_CNT = "1" *) 
(* C_PROBE562_TYPE = "1" *) (* C_PROBE562_WIDTH = "1" *) (* C_PROBE563_MU_CNT = "1" *) 
(* C_PROBE563_TYPE = "1" *) (* C_PROBE563_WIDTH = "1" *) (* C_PROBE564_MU_CNT = "1" *) 
(* C_PROBE564_TYPE = "1" *) (* C_PROBE564_WIDTH = "1" *) (* C_PROBE565_MU_CNT = "1" *) 
(* C_PROBE565_TYPE = "1" *) (* C_PROBE565_WIDTH = "1" *) (* C_PROBE566_MU_CNT = "1" *) 
(* C_PROBE566_TYPE = "1" *) (* C_PROBE566_WIDTH = "1" *) (* C_PROBE567_MU_CNT = "1" *) 
(* C_PROBE567_TYPE = "1" *) (* C_PROBE567_WIDTH = "1" *) (* C_PROBE568_MU_CNT = "1" *) 
(* C_PROBE568_TYPE = "1" *) (* C_PROBE568_WIDTH = "1" *) (* C_PROBE569_MU_CNT = "1" *) 
(* C_PROBE569_TYPE = "1" *) (* C_PROBE569_WIDTH = "1" *) (* C_PROBE56_MU_CNT = "1" *) 
(* C_PROBE56_TYPE = "1" *) (* C_PROBE56_WIDTH = "1" *) (* C_PROBE570_MU_CNT = "1" *) 
(* C_PROBE570_TYPE = "1" *) (* C_PROBE570_WIDTH = "1" *) (* C_PROBE571_MU_CNT = "1" *) 
(* C_PROBE571_TYPE = "1" *) (* C_PROBE571_WIDTH = "1" *) (* C_PROBE572_MU_CNT = "1" *) 
(* C_PROBE572_TYPE = "1" *) (* C_PROBE572_WIDTH = "1" *) (* C_PROBE573_MU_CNT = "1" *) 
(* C_PROBE573_TYPE = "1" *) (* C_PROBE573_WIDTH = "1" *) (* C_PROBE574_MU_CNT = "1" *) 
(* C_PROBE574_TYPE = "1" *) (* C_PROBE574_WIDTH = "1" *) (* C_PROBE575_MU_CNT = "1" *) 
(* C_PROBE575_TYPE = "1" *) (* C_PROBE575_WIDTH = "1" *) (* C_PROBE576_MU_CNT = "1" *) 
(* C_PROBE576_TYPE = "1" *) (* C_PROBE576_WIDTH = "1" *) (* C_PROBE577_MU_CNT = "1" *) 
(* C_PROBE577_TYPE = "1" *) (* C_PROBE577_WIDTH = "1" *) (* C_PROBE578_MU_CNT = "1" *) 
(* C_PROBE578_TYPE = "1" *) (* C_PROBE578_WIDTH = "1" *) (* C_PROBE579_MU_CNT = "1" *) 
(* C_PROBE579_TYPE = "1" *) (* C_PROBE579_WIDTH = "1" *) (* C_PROBE57_MU_CNT = "1" *) 
(* C_PROBE57_TYPE = "1" *) (* C_PROBE57_WIDTH = "1" *) (* C_PROBE580_MU_CNT = "1" *) 
(* C_PROBE580_TYPE = "1" *) (* C_PROBE580_WIDTH = "1" *) (* C_PROBE581_MU_CNT = "1" *) 
(* C_PROBE581_TYPE = "1" *) (* C_PROBE581_WIDTH = "1" *) (* C_PROBE582_MU_CNT = "1" *) 
(* C_PROBE582_TYPE = "1" *) (* C_PROBE582_WIDTH = "1" *) (* C_PROBE583_MU_CNT = "1" *) 
(* C_PROBE583_TYPE = "1" *) (* C_PROBE583_WIDTH = "1" *) (* C_PROBE584_MU_CNT = "1" *) 
(* C_PROBE584_TYPE = "1" *) (* C_PROBE584_WIDTH = "1" *) (* C_PROBE585_MU_CNT = "1" *) 
(* C_PROBE585_TYPE = "1" *) (* C_PROBE585_WIDTH = "1" *) (* C_PROBE586_MU_CNT = "1" *) 
(* C_PROBE586_TYPE = "1" *) (* C_PROBE586_WIDTH = "1" *) (* C_PROBE587_MU_CNT = "1" *) 
(* C_PROBE587_TYPE = "1" *) (* C_PROBE587_WIDTH = "1" *) (* C_PROBE588_MU_CNT = "1" *) 
(* C_PROBE588_TYPE = "1" *) (* C_PROBE588_WIDTH = "1" *) (* C_PROBE589_MU_CNT = "1" *) 
(* C_PROBE589_TYPE = "1" *) (* C_PROBE589_WIDTH = "1" *) (* C_PROBE58_MU_CNT = "1" *) 
(* C_PROBE58_TYPE = "1" *) (* C_PROBE58_WIDTH = "1" *) (* C_PROBE590_MU_CNT = "1" *) 
(* C_PROBE590_TYPE = "1" *) (* C_PROBE590_WIDTH = "1" *) (* C_PROBE591_MU_CNT = "1" *) 
(* C_PROBE591_TYPE = "1" *) (* C_PROBE591_WIDTH = "1" *) (* C_PROBE592_MU_CNT = "1" *) 
(* C_PROBE592_TYPE = "1" *) (* C_PROBE592_WIDTH = "1" *) (* C_PROBE593_MU_CNT = "1" *) 
(* C_PROBE593_TYPE = "1" *) (* C_PROBE593_WIDTH = "1" *) (* C_PROBE594_MU_CNT = "1" *) 
(* C_PROBE594_TYPE = "1" *) (* C_PROBE594_WIDTH = "1" *) (* C_PROBE595_MU_CNT = "1" *) 
(* C_PROBE595_TYPE = "1" *) (* C_PROBE595_WIDTH = "1" *) (* C_PROBE596_MU_CNT = "1" *) 
(* C_PROBE596_TYPE = "1" *) (* C_PROBE596_WIDTH = "1" *) (* C_PROBE597_MU_CNT = "1" *) 
(* C_PROBE597_TYPE = "1" *) (* C_PROBE597_WIDTH = "1" *) (* C_PROBE598_MU_CNT = "1" *) 
(* C_PROBE598_TYPE = "1" *) (* C_PROBE598_WIDTH = "1" *) (* C_PROBE599_MU_CNT = "1" *) 
(* C_PROBE599_TYPE = "1" *) (* C_PROBE599_WIDTH = "1" *) (* C_PROBE59_MU_CNT = "1" *) 
(* C_PROBE59_TYPE = "1" *) (* C_PROBE59_WIDTH = "1" *) (* C_PROBE5_MU_CNT = "1" *) 
(* C_PROBE5_TYPE = "1" *) (* C_PROBE5_WIDTH = "1" *) (* C_PROBE600_MU_CNT = "1" *) 
(* C_PROBE600_TYPE = "1" *) (* C_PROBE600_WIDTH = "1" *) (* C_PROBE601_MU_CNT = "1" *) 
(* C_PROBE601_TYPE = "1" *) (* C_PROBE601_WIDTH = "1" *) (* C_PROBE602_MU_CNT = "1" *) 
(* C_PROBE602_TYPE = "1" *) (* C_PROBE602_WIDTH = "1" *) (* C_PROBE603_MU_CNT = "1" *) 
(* C_PROBE603_TYPE = "1" *) (* C_PROBE603_WIDTH = "1" *) (* C_PROBE604_MU_CNT = "1" *) 
(* C_PROBE604_TYPE = "1" *) (* C_PROBE604_WIDTH = "1" *) (* C_PROBE605_MU_CNT = "1" *) 
(* C_PROBE605_TYPE = "1" *) (* C_PROBE605_WIDTH = "1" *) (* C_PROBE606_MU_CNT = "1" *) 
(* C_PROBE606_TYPE = "1" *) (* C_PROBE606_WIDTH = "1" *) (* C_PROBE607_MU_CNT = "1" *) 
(* C_PROBE607_TYPE = "1" *) (* C_PROBE607_WIDTH = "1" *) (* C_PROBE608_MU_CNT = "1" *) 
(* C_PROBE608_TYPE = "1" *) (* C_PROBE608_WIDTH = "1" *) (* C_PROBE609_MU_CNT = "1" *) 
(* C_PROBE609_TYPE = "1" *) (* C_PROBE609_WIDTH = "1" *) (* C_PROBE60_MU_CNT = "1" *) 
(* C_PROBE60_TYPE = "1" *) (* C_PROBE60_WIDTH = "1" *) (* C_PROBE610_MU_CNT = "1" *) 
(* C_PROBE610_TYPE = "1" *) (* C_PROBE610_WIDTH = "1" *) (* C_PROBE611_MU_CNT = "1" *) 
(* C_PROBE611_TYPE = "1" *) (* C_PROBE611_WIDTH = "1" *) (* C_PROBE612_MU_CNT = "1" *) 
(* C_PROBE612_TYPE = "1" *) (* C_PROBE612_WIDTH = "1" *) (* C_PROBE613_MU_CNT = "1" *) 
(* C_PROBE613_TYPE = "1" *) (* C_PROBE613_WIDTH = "1" *) (* C_PROBE614_MU_CNT = "1" *) 
(* C_PROBE614_TYPE = "1" *) (* C_PROBE614_WIDTH = "1" *) (* C_PROBE615_MU_CNT = "1" *) 
(* C_PROBE615_TYPE = "1" *) (* C_PROBE615_WIDTH = "1" *) (* C_PROBE616_MU_CNT = "1" *) 
(* C_PROBE616_TYPE = "1" *) (* C_PROBE616_WIDTH = "1" *) (* C_PROBE617_MU_CNT = "1" *) 
(* C_PROBE617_TYPE = "1" *) (* C_PROBE617_WIDTH = "1" *) (* C_PROBE618_MU_CNT = "1" *) 
(* C_PROBE618_TYPE = "1" *) (* C_PROBE618_WIDTH = "1" *) (* C_PROBE619_MU_CNT = "1" *) 
(* C_PROBE619_TYPE = "1" *) (* C_PROBE619_WIDTH = "1" *) (* C_PROBE61_MU_CNT = "1" *) 
(* C_PROBE61_TYPE = "1" *) (* C_PROBE61_WIDTH = "1" *) (* C_PROBE620_MU_CNT = "1" *) 
(* C_PROBE620_TYPE = "1" *) (* C_PROBE620_WIDTH = "1" *) (* C_PROBE621_MU_CNT = "1" *) 
(* C_PROBE621_TYPE = "1" *) (* C_PROBE621_WIDTH = "1" *) (* C_PROBE622_MU_CNT = "1" *) 
(* C_PROBE622_TYPE = "1" *) (* C_PROBE622_WIDTH = "1" *) (* C_PROBE623_MU_CNT = "1" *) 
(* C_PROBE623_TYPE = "1" *) (* C_PROBE623_WIDTH = "1" *) (* C_PROBE624_MU_CNT = "1" *) 
(* C_PROBE624_TYPE = "1" *) (* C_PROBE624_WIDTH = "1" *) (* C_PROBE625_MU_CNT = "1" *) 
(* C_PROBE625_TYPE = "1" *) (* C_PROBE625_WIDTH = "1" *) (* C_PROBE626_MU_CNT = "1" *) 
(* C_PROBE626_TYPE = "1" *) (* C_PROBE626_WIDTH = "1" *) (* C_PROBE627_MU_CNT = "1" *) 
(* C_PROBE627_TYPE = "1" *) (* C_PROBE627_WIDTH = "1" *) (* C_PROBE628_MU_CNT = "1" *) 
(* C_PROBE628_TYPE = "1" *) (* C_PROBE628_WIDTH = "1" *) (* C_PROBE629_MU_CNT = "1" *) 
(* C_PROBE629_TYPE = "1" *) (* C_PROBE629_WIDTH = "1" *) (* C_PROBE62_MU_CNT = "1" *) 
(* C_PROBE62_TYPE = "1" *) (* C_PROBE62_WIDTH = "1" *) (* C_PROBE630_MU_CNT = "1" *) 
(* C_PROBE630_TYPE = "1" *) (* C_PROBE630_WIDTH = "1" *) (* C_PROBE631_MU_CNT = "1" *) 
(* C_PROBE631_TYPE = "1" *) (* C_PROBE631_WIDTH = "1" *) (* C_PROBE632_MU_CNT = "1" *) 
(* C_PROBE632_TYPE = "1" *) (* C_PROBE632_WIDTH = "1" *) (* C_PROBE633_MU_CNT = "1" *) 
(* C_PROBE633_TYPE = "1" *) (* C_PROBE633_WIDTH = "1" *) (* C_PROBE634_MU_CNT = "1" *) 
(* C_PROBE634_TYPE = "1" *) (* C_PROBE634_WIDTH = "1" *) (* C_PROBE635_MU_CNT = "1" *) 
(* C_PROBE635_TYPE = "1" *) (* C_PROBE635_WIDTH = "1" *) (* C_PROBE636_MU_CNT = "1" *) 
(* C_PROBE636_TYPE = "1" *) (* C_PROBE636_WIDTH = "1" *) (* C_PROBE637_MU_CNT = "1" *) 
(* C_PROBE637_TYPE = "1" *) (* C_PROBE637_WIDTH = "1" *) (* C_PROBE638_MU_CNT = "1" *) 
(* C_PROBE638_TYPE = "1" *) (* C_PROBE638_WIDTH = "1" *) (* C_PROBE639_MU_CNT = "1" *) 
(* C_PROBE639_TYPE = "1" *) (* C_PROBE639_WIDTH = "1" *) (* C_PROBE63_MU_CNT = "1" *) 
(* C_PROBE63_TYPE = "1" *) (* C_PROBE63_WIDTH = "1" *) (* C_PROBE640_MU_CNT = "1" *) 
(* C_PROBE640_TYPE = "1" *) (* C_PROBE640_WIDTH = "1" *) (* C_PROBE641_MU_CNT = "1" *) 
(* C_PROBE641_TYPE = "1" *) (* C_PROBE641_WIDTH = "1" *) (* C_PROBE642_MU_CNT = "1" *) 
(* C_PROBE642_TYPE = "1" *) (* C_PROBE642_WIDTH = "1" *) (* C_PROBE643_MU_CNT = "1" *) 
(* C_PROBE643_TYPE = "1" *) (* C_PROBE643_WIDTH = "1" *) (* C_PROBE644_MU_CNT = "1" *) 
(* C_PROBE644_TYPE = "1" *) (* C_PROBE644_WIDTH = "1" *) (* C_PROBE645_MU_CNT = "1" *) 
(* C_PROBE645_TYPE = "1" *) (* C_PROBE645_WIDTH = "1" *) (* C_PROBE646_MU_CNT = "1" *) 
(* C_PROBE646_TYPE = "1" *) (* C_PROBE646_WIDTH = "1" *) (* C_PROBE647_MU_CNT = "1" *) 
(* C_PROBE647_TYPE = "1" *) (* C_PROBE647_WIDTH = "1" *) (* C_PROBE648_MU_CNT = "1" *) 
(* C_PROBE648_TYPE = "1" *) (* C_PROBE648_WIDTH = "1" *) (* C_PROBE649_MU_CNT = "1" *) 
(* C_PROBE649_TYPE = "1" *) (* C_PROBE649_WIDTH = "1" *) (* C_PROBE64_MU_CNT = "1" *) 
(* C_PROBE64_TYPE = "1" *) (* C_PROBE64_WIDTH = "1" *) (* C_PROBE650_MU_CNT = "1" *) 
(* C_PROBE650_TYPE = "1" *) (* C_PROBE650_WIDTH = "1" *) (* C_PROBE651_MU_CNT = "1" *) 
(* C_PROBE651_TYPE = "1" *) (* C_PROBE651_WIDTH = "1" *) (* C_PROBE652_MU_CNT = "1" *) 
(* C_PROBE652_TYPE = "1" *) (* C_PROBE652_WIDTH = "1" *) (* C_PROBE653_MU_CNT = "1" *) 
(* C_PROBE653_TYPE = "1" *) (* C_PROBE653_WIDTH = "1" *) (* C_PROBE654_MU_CNT = "1" *) 
(* C_PROBE654_TYPE = "1" *) (* C_PROBE654_WIDTH = "1" *) (* C_PROBE655_MU_CNT = "1" *) 
(* C_PROBE655_TYPE = "1" *) (* C_PROBE655_WIDTH = "1" *) (* C_PROBE656_MU_CNT = "1" *) 
(* C_PROBE656_TYPE = "1" *) (* C_PROBE656_WIDTH = "1" *) (* C_PROBE657_MU_CNT = "1" *) 
(* C_PROBE657_TYPE = "1" *) (* C_PROBE657_WIDTH = "1" *) (* C_PROBE658_MU_CNT = "1" *) 
(* C_PROBE658_TYPE = "1" *) (* C_PROBE658_WIDTH = "1" *) (* C_PROBE659_MU_CNT = "1" *) 
(* C_PROBE659_TYPE = "1" *) (* C_PROBE659_WIDTH = "1" *) (* C_PROBE65_MU_CNT = "1" *) 
(* C_PROBE65_TYPE = "1" *) (* C_PROBE65_WIDTH = "1" *) (* C_PROBE660_MU_CNT = "1" *) 
(* C_PROBE660_TYPE = "1" *) (* C_PROBE660_WIDTH = "1" *) (* C_PROBE661_MU_CNT = "1" *) 
(* C_PROBE661_TYPE = "1" *) (* C_PROBE661_WIDTH = "1" *) (* C_PROBE662_MU_CNT = "1" *) 
(* C_PROBE662_TYPE = "1" *) (* C_PROBE662_WIDTH = "1" *) (* C_PROBE663_MU_CNT = "1" *) 
(* C_PROBE663_TYPE = "1" *) (* C_PROBE663_WIDTH = "1" *) (* C_PROBE664_MU_CNT = "1" *) 
(* C_PROBE664_TYPE = "1" *) (* C_PROBE664_WIDTH = "1" *) (* C_PROBE665_MU_CNT = "1" *) 
(* C_PROBE665_TYPE = "1" *) (* C_PROBE665_WIDTH = "1" *) (* C_PROBE666_MU_CNT = "1" *) 
(* C_PROBE666_TYPE = "1" *) (* C_PROBE666_WIDTH = "1" *) (* C_PROBE667_MU_CNT = "1" *) 
(* C_PROBE667_TYPE = "1" *) (* C_PROBE667_WIDTH = "1" *) (* C_PROBE668_MU_CNT = "1" *) 
(* C_PROBE668_TYPE = "1" *) (* C_PROBE668_WIDTH = "1" *) (* C_PROBE669_MU_CNT = "1" *) 
(* C_PROBE669_TYPE = "1" *) (* C_PROBE669_WIDTH = "1" *) (* C_PROBE66_MU_CNT = "1" *) 
(* C_PROBE66_TYPE = "1" *) (* C_PROBE66_WIDTH = "1" *) (* C_PROBE670_MU_CNT = "1" *) 
(* C_PROBE670_TYPE = "1" *) (* C_PROBE670_WIDTH = "1" *) (* C_PROBE671_MU_CNT = "1" *) 
(* C_PROBE671_TYPE = "1" *) (* C_PROBE671_WIDTH = "1" *) (* C_PROBE672_MU_CNT = "1" *) 
(* C_PROBE672_TYPE = "1" *) (* C_PROBE672_WIDTH = "1" *) (* C_PROBE673_MU_CNT = "1" *) 
(* C_PROBE673_TYPE = "1" *) (* C_PROBE673_WIDTH = "1" *) (* C_PROBE674_MU_CNT = "1" *) 
(* C_PROBE674_TYPE = "1" *) (* C_PROBE674_WIDTH = "1" *) (* C_PROBE675_MU_CNT = "1" *) 
(* C_PROBE675_TYPE = "1" *) (* C_PROBE675_WIDTH = "1" *) (* C_PROBE676_MU_CNT = "1" *) 
(* C_PROBE676_TYPE = "1" *) (* C_PROBE676_WIDTH = "1" *) (* C_PROBE677_MU_CNT = "1" *) 
(* C_PROBE677_TYPE = "1" *) (* C_PROBE677_WIDTH = "1" *) (* C_PROBE678_MU_CNT = "1" *) 
(* C_PROBE678_TYPE = "1" *) (* C_PROBE678_WIDTH = "1" *) (* C_PROBE679_MU_CNT = "1" *) 
(* C_PROBE679_TYPE = "1" *) (* C_PROBE679_WIDTH = "1" *) (* C_PROBE67_MU_CNT = "1" *) 
(* C_PROBE67_TYPE = "1" *) (* C_PROBE67_WIDTH = "1" *) (* C_PROBE680_MU_CNT = "1" *) 
(* C_PROBE680_TYPE = "1" *) (* C_PROBE680_WIDTH = "1" *) (* C_PROBE681_MU_CNT = "1" *) 
(* C_PROBE681_TYPE = "1" *) (* C_PROBE681_WIDTH = "1" *) (* C_PROBE682_MU_CNT = "1" *) 
(* C_PROBE682_TYPE = "1" *) (* C_PROBE682_WIDTH = "1" *) (* C_PROBE683_MU_CNT = "1" *) 
(* C_PROBE683_TYPE = "1" *) (* C_PROBE683_WIDTH = "1" *) (* C_PROBE684_MU_CNT = "1" *) 
(* C_PROBE684_TYPE = "1" *) (* C_PROBE684_WIDTH = "1" *) (* C_PROBE685_MU_CNT = "1" *) 
(* C_PROBE685_TYPE = "1" *) (* C_PROBE685_WIDTH = "1" *) (* C_PROBE686_MU_CNT = "1" *) 
(* C_PROBE686_TYPE = "1" *) (* C_PROBE686_WIDTH = "1" *) (* C_PROBE687_MU_CNT = "1" *) 
(* C_PROBE687_TYPE = "1" *) (* C_PROBE687_WIDTH = "1" *) (* C_PROBE688_MU_CNT = "1" *) 
(* C_PROBE688_TYPE = "1" *) (* C_PROBE688_WIDTH = "1" *) (* C_PROBE689_MU_CNT = "1" *) 
(* C_PROBE689_TYPE = "1" *) (* C_PROBE689_WIDTH = "1" *) (* C_PROBE68_MU_CNT = "1" *) 
(* C_PROBE68_TYPE = "1" *) (* C_PROBE68_WIDTH = "1" *) (* C_PROBE690_MU_CNT = "1" *) 
(* C_PROBE690_TYPE = "1" *) (* C_PROBE690_WIDTH = "1" *) (* C_PROBE691_MU_CNT = "1" *) 
(* C_PROBE691_TYPE = "1" *) (* C_PROBE691_WIDTH = "1" *) (* C_PROBE692_MU_CNT = "1" *) 
(* C_PROBE692_TYPE = "1" *) (* C_PROBE692_WIDTH = "1" *) (* C_PROBE693_MU_CNT = "1" *) 
(* C_PROBE693_TYPE = "1" *) (* C_PROBE693_WIDTH = "1" *) (* C_PROBE694_MU_CNT = "1" *) 
(* C_PROBE694_TYPE = "1" *) (* C_PROBE694_WIDTH = "1" *) (* C_PROBE695_MU_CNT = "1" *) 
(* C_PROBE695_TYPE = "1" *) (* C_PROBE695_WIDTH = "1" *) (* C_PROBE696_MU_CNT = "1" *) 
(* C_PROBE696_TYPE = "1" *) (* C_PROBE696_WIDTH = "1" *) (* C_PROBE697_MU_CNT = "1" *) 
(* C_PROBE697_TYPE = "1" *) (* C_PROBE697_WIDTH = "1" *) (* C_PROBE698_MU_CNT = "1" *) 
(* C_PROBE698_TYPE = "1" *) (* C_PROBE698_WIDTH = "1" *) (* C_PROBE699_MU_CNT = "1" *) 
(* C_PROBE699_TYPE = "1" *) (* C_PROBE699_WIDTH = "1" *) (* C_PROBE69_MU_CNT = "1" *) 
(* C_PROBE69_TYPE = "1" *) (* C_PROBE69_WIDTH = "1" *) (* C_PROBE6_MU_CNT = "1" *) 
(* C_PROBE6_TYPE = "1" *) (* C_PROBE6_WIDTH = "1" *) (* C_PROBE700_MU_CNT = "1" *) 
(* C_PROBE700_TYPE = "1" *) (* C_PROBE700_WIDTH = "1" *) (* C_PROBE701_MU_CNT = "1" *) 
(* C_PROBE701_TYPE = "1" *) (* C_PROBE701_WIDTH = "1" *) (* C_PROBE702_MU_CNT = "1" *) 
(* C_PROBE702_TYPE = "1" *) (* C_PROBE702_WIDTH = "1" *) (* C_PROBE703_MU_CNT = "1" *) 
(* C_PROBE703_TYPE = "1" *) (* C_PROBE703_WIDTH = "1" *) (* C_PROBE704_MU_CNT = "1" *) 
(* C_PROBE704_TYPE = "1" *) (* C_PROBE704_WIDTH = "1" *) (* C_PROBE705_MU_CNT = "1" *) 
(* C_PROBE705_TYPE = "1" *) (* C_PROBE705_WIDTH = "1" *) (* C_PROBE706_MU_CNT = "1" *) 
(* C_PROBE706_TYPE = "1" *) (* C_PROBE706_WIDTH = "1" *) (* C_PROBE707_MU_CNT = "1" *) 
(* C_PROBE707_TYPE = "1" *) (* C_PROBE707_WIDTH = "1" *) (* C_PROBE708_MU_CNT = "1" *) 
(* C_PROBE708_TYPE = "1" *) (* C_PROBE708_WIDTH = "1" *) (* C_PROBE709_MU_CNT = "1" *) 
(* C_PROBE709_TYPE = "1" *) (* C_PROBE709_WIDTH = "1" *) (* C_PROBE70_MU_CNT = "1" *) 
(* C_PROBE70_TYPE = "1" *) (* C_PROBE70_WIDTH = "1" *) (* C_PROBE710_MU_CNT = "1" *) 
(* C_PROBE710_TYPE = "1" *) (* C_PROBE710_WIDTH = "1" *) (* C_PROBE711_MU_CNT = "1" *) 
(* C_PROBE711_TYPE = "1" *) (* C_PROBE711_WIDTH = "1" *) (* C_PROBE712_MU_CNT = "1" *) 
(* C_PROBE712_TYPE = "1" *) (* C_PROBE712_WIDTH = "1" *) (* C_PROBE713_MU_CNT = "1" *) 
(* C_PROBE713_TYPE = "1" *) (* C_PROBE713_WIDTH = "1" *) (* C_PROBE714_MU_CNT = "1" *) 
(* C_PROBE714_TYPE = "1" *) (* C_PROBE714_WIDTH = "1" *) (* C_PROBE715_MU_CNT = "1" *) 
(* C_PROBE715_TYPE = "1" *) (* C_PROBE715_WIDTH = "1" *) (* C_PROBE716_MU_CNT = "1" *) 
(* C_PROBE716_TYPE = "1" *) (* C_PROBE716_WIDTH = "1" *) (* C_PROBE717_MU_CNT = "1" *) 
(* C_PROBE717_TYPE = "1" *) (* C_PROBE717_WIDTH = "1" *) (* C_PROBE718_MU_CNT = "1" *) 
(* C_PROBE718_TYPE = "1" *) (* C_PROBE718_WIDTH = "1" *) (* C_PROBE719_MU_CNT = "1" *) 
(* C_PROBE719_TYPE = "1" *) (* C_PROBE719_WIDTH = "1" *) (* C_PROBE71_MU_CNT = "1" *) 
(* C_PROBE71_TYPE = "1" *) (* C_PROBE71_WIDTH = "1" *) (* C_PROBE720_MU_CNT = "1" *) 
(* C_PROBE720_TYPE = "1" *) (* C_PROBE720_WIDTH = "1" *) (* C_PROBE721_MU_CNT = "1" *) 
(* C_PROBE721_TYPE = "1" *) (* C_PROBE721_WIDTH = "1" *) (* C_PROBE722_MU_CNT = "1" *) 
(* C_PROBE722_TYPE = "1" *) (* C_PROBE722_WIDTH = "1" *) (* C_PROBE723_MU_CNT = "1" *) 
(* C_PROBE723_TYPE = "1" *) (* C_PROBE723_WIDTH = "1" *) (* C_PROBE724_MU_CNT = "1" *) 
(* C_PROBE724_TYPE = "1" *) (* C_PROBE724_WIDTH = "1" *) (* C_PROBE725_MU_CNT = "1" *) 
(* C_PROBE725_TYPE = "1" *) (* C_PROBE725_WIDTH = "1" *) (* C_PROBE726_MU_CNT = "1" *) 
(* C_PROBE726_TYPE = "1" *) (* C_PROBE726_WIDTH = "1" *) (* C_PROBE727_MU_CNT = "1" *) 
(* C_PROBE727_TYPE = "1" *) (* C_PROBE727_WIDTH = "1" *) (* C_PROBE728_MU_CNT = "1" *) 
(* C_PROBE728_TYPE = "1" *) (* C_PROBE728_WIDTH = "1" *) (* C_PROBE729_MU_CNT = "1" *) 
(* C_PROBE729_TYPE = "1" *) (* C_PROBE729_WIDTH = "1" *) (* C_PROBE72_MU_CNT = "1" *) 
(* C_PROBE72_TYPE = "1" *) (* C_PROBE72_WIDTH = "1" *) (* C_PROBE730_MU_CNT = "1" *) 
(* C_PROBE730_TYPE = "1" *) (* C_PROBE730_WIDTH = "1" *) (* C_PROBE731_MU_CNT = "1" *) 
(* C_PROBE731_TYPE = "1" *) (* C_PROBE731_WIDTH = "1" *) (* C_PROBE732_MU_CNT = "1" *) 
(* C_PROBE732_TYPE = "1" *) (* C_PROBE732_WIDTH = "1" *) (* C_PROBE733_MU_CNT = "1" *) 
(* C_PROBE733_TYPE = "1" *) (* C_PROBE733_WIDTH = "1" *) (* C_PROBE734_MU_CNT = "1" *) 
(* C_PROBE734_TYPE = "1" *) (* C_PROBE734_WIDTH = "1" *) (* C_PROBE735_MU_CNT = "1" *) 
(* C_PROBE735_TYPE = "1" *) (* C_PROBE735_WIDTH = "1" *) (* C_PROBE736_MU_CNT = "1" *) 
(* C_PROBE736_TYPE = "1" *) (* C_PROBE736_WIDTH = "1" *) (* C_PROBE737_MU_CNT = "1" *) 
(* C_PROBE737_TYPE = "1" *) (* C_PROBE737_WIDTH = "1" *) (* C_PROBE738_MU_CNT = "1" *) 
(* C_PROBE738_TYPE = "1" *) (* C_PROBE738_WIDTH = "1" *) (* C_PROBE739_MU_CNT = "1" *) 
(* C_PROBE739_TYPE = "1" *) (* C_PROBE739_WIDTH = "1" *) (* C_PROBE73_MU_CNT = "1" *) 
(* C_PROBE73_TYPE = "1" *) (* C_PROBE73_WIDTH = "1" *) (* C_PROBE740_MU_CNT = "1" *) 
(* C_PROBE740_TYPE = "1" *) (* C_PROBE740_WIDTH = "1" *) (* C_PROBE741_MU_CNT = "1" *) 
(* C_PROBE741_TYPE = "1" *) (* C_PROBE741_WIDTH = "1" *) (* C_PROBE742_MU_CNT = "1" *) 
(* C_PROBE742_TYPE = "1" *) (* C_PROBE742_WIDTH = "1" *) (* C_PROBE743_MU_CNT = "1" *) 
(* C_PROBE743_TYPE = "1" *) (* C_PROBE743_WIDTH = "1" *) (* C_PROBE744_MU_CNT = "1" *) 
(* C_PROBE744_TYPE = "1" *) (* C_PROBE744_WIDTH = "1" *) (* C_PROBE745_MU_CNT = "1" *) 
(* C_PROBE745_TYPE = "1" *) (* C_PROBE745_WIDTH = "1" *) (* C_PROBE746_MU_CNT = "1" *) 
(* C_PROBE746_TYPE = "1" *) (* C_PROBE746_WIDTH = "1" *) (* C_PROBE747_MU_CNT = "1" *) 
(* C_PROBE747_TYPE = "1" *) (* C_PROBE747_WIDTH = "1" *) (* C_PROBE748_MU_CNT = "1" *) 
(* C_PROBE748_TYPE = "1" *) (* C_PROBE748_WIDTH = "1" *) (* C_PROBE749_MU_CNT = "1" *) 
(* C_PROBE749_TYPE = "1" *) (* C_PROBE749_WIDTH = "1" *) (* C_PROBE74_MU_CNT = "1" *) 
(* C_PROBE74_TYPE = "1" *) (* C_PROBE74_WIDTH = "1" *) (* C_PROBE750_MU_CNT = "1" *) 
(* C_PROBE750_TYPE = "1" *) (* C_PROBE750_WIDTH = "1" *) (* C_PROBE751_MU_CNT = "1" *) 
(* C_PROBE751_TYPE = "1" *) (* C_PROBE751_WIDTH = "1" *) (* C_PROBE752_MU_CNT = "1" *) 
(* C_PROBE752_TYPE = "1" *) (* C_PROBE752_WIDTH = "1" *) (* C_PROBE753_MU_CNT = "1" *) 
(* C_PROBE753_TYPE = "1" *) (* C_PROBE753_WIDTH = "1" *) (* C_PROBE754_MU_CNT = "1" *) 
(* C_PROBE754_TYPE = "1" *) (* C_PROBE754_WIDTH = "1" *) (* C_PROBE755_MU_CNT = "1" *) 
(* C_PROBE755_TYPE = "1" *) (* C_PROBE755_WIDTH = "1" *) (* C_PROBE756_MU_CNT = "1" *) 
(* C_PROBE756_TYPE = "1" *) (* C_PROBE756_WIDTH = "1" *) (* C_PROBE757_MU_CNT = "1" *) 
(* C_PROBE757_TYPE = "1" *) (* C_PROBE757_WIDTH = "1" *) (* C_PROBE758_MU_CNT = "1" *) 
(* C_PROBE758_TYPE = "1" *) (* C_PROBE758_WIDTH = "1" *) (* C_PROBE759_MU_CNT = "1" *) 
(* C_PROBE759_TYPE = "1" *) (* C_PROBE759_WIDTH = "1" *) (* C_PROBE75_MU_CNT = "1" *) 
(* C_PROBE75_TYPE = "1" *) (* C_PROBE75_WIDTH = "1" *) (* C_PROBE760_MU_CNT = "1" *) 
(* C_PROBE760_TYPE = "1" *) (* C_PROBE760_WIDTH = "1" *) (* C_PROBE761_MU_CNT = "1" *) 
(* C_PROBE761_TYPE = "1" *) (* C_PROBE761_WIDTH = "1" *) (* C_PROBE762_MU_CNT = "1" *) 
(* C_PROBE762_TYPE = "1" *) (* C_PROBE762_WIDTH = "1" *) (* C_PROBE763_MU_CNT = "1" *) 
(* C_PROBE763_TYPE = "1" *) (* C_PROBE763_WIDTH = "1" *) (* C_PROBE764_MU_CNT = "1" *) 
(* C_PROBE764_TYPE = "1" *) (* C_PROBE764_WIDTH = "1" *) (* C_PROBE765_MU_CNT = "1" *) 
(* C_PROBE765_TYPE = "1" *) (* C_PROBE765_WIDTH = "1" *) (* C_PROBE766_MU_CNT = "1" *) 
(* C_PROBE766_TYPE = "1" *) (* C_PROBE766_WIDTH = "1" *) (* C_PROBE767_MU_CNT = "1" *) 
(* C_PROBE767_TYPE = "1" *) (* C_PROBE767_WIDTH = "1" *) (* C_PROBE768_MU_CNT = "1" *) 
(* C_PROBE768_TYPE = "1" *) (* C_PROBE768_WIDTH = "1" *) (* C_PROBE769_MU_CNT = "1" *) 
(* C_PROBE769_TYPE = "1" *) (* C_PROBE769_WIDTH = "1" *) (* C_PROBE76_MU_CNT = "1" *) 
(* C_PROBE76_TYPE = "1" *) (* C_PROBE76_WIDTH = "1" *) (* C_PROBE770_MU_CNT = "1" *) 
(* C_PROBE770_TYPE = "1" *) (* C_PROBE770_WIDTH = "1" *) (* C_PROBE771_MU_CNT = "1" *) 
(* C_PROBE771_TYPE = "1" *) (* C_PROBE771_WIDTH = "1" *) (* C_PROBE772_MU_CNT = "1" *) 
(* C_PROBE772_TYPE = "1" *) (* C_PROBE772_WIDTH = "1" *) (* C_PROBE773_MU_CNT = "1" *) 
(* C_PROBE773_TYPE = "1" *) (* C_PROBE773_WIDTH = "1" *) (* C_PROBE774_MU_CNT = "1" *) 
(* C_PROBE774_TYPE = "1" *) (* C_PROBE774_WIDTH = "1" *) (* C_PROBE775_MU_CNT = "1" *) 
(* C_PROBE775_TYPE = "1" *) (* C_PROBE775_WIDTH = "1" *) (* C_PROBE776_MU_CNT = "1" *) 
(* C_PROBE776_TYPE = "1" *) (* C_PROBE776_WIDTH = "1" *) (* C_PROBE777_MU_CNT = "1" *) 
(* C_PROBE777_TYPE = "1" *) (* C_PROBE777_WIDTH = "1" *) (* C_PROBE778_MU_CNT = "1" *) 
(* C_PROBE778_TYPE = "1" *) (* C_PROBE778_WIDTH = "1" *) (* C_PROBE779_MU_CNT = "1" *) 
(* C_PROBE779_TYPE = "1" *) (* C_PROBE779_WIDTH = "1" *) (* C_PROBE77_MU_CNT = "1" *) 
(* C_PROBE77_TYPE = "1" *) (* C_PROBE77_WIDTH = "1" *) (* C_PROBE780_MU_CNT = "1" *) 
(* C_PROBE780_TYPE = "1" *) (* C_PROBE780_WIDTH = "1" *) (* C_PROBE781_MU_CNT = "1" *) 
(* C_PROBE781_TYPE = "1" *) (* C_PROBE781_WIDTH = "1" *) (* C_PROBE782_MU_CNT = "1" *) 
(* C_PROBE782_TYPE = "1" *) (* C_PROBE782_WIDTH = "1" *) (* C_PROBE783_MU_CNT = "1" *) 
(* C_PROBE783_TYPE = "1" *) (* C_PROBE783_WIDTH = "1" *) (* C_PROBE784_MU_CNT = "1" *) 
(* C_PROBE784_TYPE = "1" *) (* C_PROBE784_WIDTH = "1" *) (* C_PROBE785_MU_CNT = "1" *) 
(* C_PROBE785_TYPE = "1" *) (* C_PROBE785_WIDTH = "1" *) (* C_PROBE786_MU_CNT = "1" *) 
(* C_PROBE786_TYPE = "1" *) (* C_PROBE786_WIDTH = "1" *) (* C_PROBE787_MU_CNT = "1" *) 
(* C_PROBE787_TYPE = "1" *) (* C_PROBE787_WIDTH = "1" *) (* C_PROBE788_MU_CNT = "1" *) 
(* C_PROBE788_TYPE = "1" *) (* C_PROBE788_WIDTH = "1" *) (* C_PROBE789_MU_CNT = "1" *) 
(* C_PROBE789_TYPE = "1" *) (* C_PROBE789_WIDTH = "1" *) (* C_PROBE78_MU_CNT = "1" *) 
(* C_PROBE78_TYPE = "1" *) (* C_PROBE78_WIDTH = "1" *) (* C_PROBE790_MU_CNT = "1" *) 
(* C_PROBE790_TYPE = "1" *) (* C_PROBE790_WIDTH = "1" *) (* C_PROBE791_MU_CNT = "1" *) 
(* C_PROBE791_TYPE = "1" *) (* C_PROBE791_WIDTH = "1" *) (* C_PROBE792_MU_CNT = "1" *) 
(* C_PROBE792_TYPE = "1" *) (* C_PROBE792_WIDTH = "1" *) (* C_PROBE793_MU_CNT = "1" *) 
(* C_PROBE793_TYPE = "1" *) (* C_PROBE793_WIDTH = "1" *) (* C_PROBE794_MU_CNT = "1" *) 
(* C_PROBE794_TYPE = "1" *) (* C_PROBE794_WIDTH = "1" *) (* C_PROBE795_MU_CNT = "1" *) 
(* C_PROBE795_TYPE = "1" *) (* C_PROBE795_WIDTH = "1" *) (* C_PROBE796_MU_CNT = "1" *) 
(* C_PROBE796_TYPE = "1" *) (* C_PROBE796_WIDTH = "1" *) (* C_PROBE797_MU_CNT = "1" *) 
(* C_PROBE797_TYPE = "1" *) (* C_PROBE797_WIDTH = "1" *) (* C_PROBE798_MU_CNT = "1" *) 
(* C_PROBE798_TYPE = "1" *) (* C_PROBE798_WIDTH = "1" *) (* C_PROBE799_MU_CNT = "1" *) 
(* C_PROBE799_TYPE = "1" *) (* C_PROBE799_WIDTH = "1" *) (* C_PROBE79_MU_CNT = "1" *) 
(* C_PROBE79_TYPE = "1" *) (* C_PROBE79_WIDTH = "1" *) (* C_PROBE7_MU_CNT = "1" *) 
(* C_PROBE7_TYPE = "1" *) (* C_PROBE7_WIDTH = "1" *) (* C_PROBE800_MU_CNT = "1" *) 
(* C_PROBE800_TYPE = "1" *) (* C_PROBE800_WIDTH = "1" *) (* C_PROBE801_MU_CNT = "1" *) 
(* C_PROBE801_TYPE = "1" *) (* C_PROBE801_WIDTH = "1" *) (* C_PROBE802_MU_CNT = "1" *) 
(* C_PROBE802_TYPE = "1" *) (* C_PROBE802_WIDTH = "1" *) (* C_PROBE803_MU_CNT = "1" *) 
(* C_PROBE803_TYPE = "1" *) (* C_PROBE803_WIDTH = "1" *) (* C_PROBE804_MU_CNT = "1" *) 
(* C_PROBE804_TYPE = "1" *) (* C_PROBE804_WIDTH = "1" *) (* C_PROBE805_MU_CNT = "1" *) 
(* C_PROBE805_TYPE = "1" *) (* C_PROBE805_WIDTH = "1" *) (* C_PROBE806_MU_CNT = "1" *) 
(* C_PROBE806_TYPE = "1" *) (* C_PROBE806_WIDTH = "1" *) (* C_PROBE807_MU_CNT = "1" *) 
(* C_PROBE807_TYPE = "1" *) (* C_PROBE807_WIDTH = "1" *) (* C_PROBE808_MU_CNT = "1" *) 
(* C_PROBE808_TYPE = "1" *) (* C_PROBE808_WIDTH = "1" *) (* C_PROBE809_MU_CNT = "1" *) 
(* C_PROBE809_TYPE = "1" *) (* C_PROBE809_WIDTH = "1" *) (* C_PROBE80_MU_CNT = "1" *) 
(* C_PROBE80_TYPE = "1" *) (* C_PROBE80_WIDTH = "1" *) (* C_PROBE810_MU_CNT = "1" *) 
(* C_PROBE810_TYPE = "1" *) (* C_PROBE810_WIDTH = "1" *) (* C_PROBE811_MU_CNT = "1" *) 
(* C_PROBE811_TYPE = "1" *) (* C_PROBE811_WIDTH = "1" *) (* C_PROBE812_MU_CNT = "1" *) 
(* C_PROBE812_TYPE = "1" *) (* C_PROBE812_WIDTH = "1" *) (* C_PROBE813_MU_CNT = "1" *) 
(* C_PROBE813_TYPE = "1" *) (* C_PROBE813_WIDTH = "1" *) (* C_PROBE814_MU_CNT = "1" *) 
(* C_PROBE814_TYPE = "1" *) (* C_PROBE814_WIDTH = "1" *) (* C_PROBE815_MU_CNT = "1" *) 
(* C_PROBE815_TYPE = "1" *) (* C_PROBE815_WIDTH = "1" *) (* C_PROBE816_MU_CNT = "1" *) 
(* C_PROBE816_TYPE = "1" *) (* C_PROBE816_WIDTH = "1" *) (* C_PROBE817_MU_CNT = "1" *) 
(* C_PROBE817_TYPE = "1" *) (* C_PROBE817_WIDTH = "1" *) (* C_PROBE818_MU_CNT = "1" *) 
(* C_PROBE818_TYPE = "1" *) (* C_PROBE818_WIDTH = "1" *) (* C_PROBE819_MU_CNT = "1" *) 
(* C_PROBE819_TYPE = "1" *) (* C_PROBE819_WIDTH = "1" *) (* C_PROBE81_MU_CNT = "1" *) 
(* C_PROBE81_TYPE = "1" *) (* C_PROBE81_WIDTH = "1" *) (* C_PROBE820_MU_CNT = "1" *) 
(* C_PROBE820_TYPE = "1" *) (* C_PROBE820_WIDTH = "1" *) (* C_PROBE821_MU_CNT = "1" *) 
(* C_PROBE821_TYPE = "1" *) (* C_PROBE821_WIDTH = "1" *) (* C_PROBE822_MU_CNT = "1" *) 
(* C_PROBE822_TYPE = "1" *) (* C_PROBE822_WIDTH = "1" *) (* C_PROBE823_MU_CNT = "1" *) 
(* C_PROBE823_TYPE = "1" *) (* C_PROBE823_WIDTH = "1" *) (* C_PROBE824_MU_CNT = "1" *) 
(* C_PROBE824_TYPE = "1" *) (* C_PROBE824_WIDTH = "1" *) (* C_PROBE825_MU_CNT = "1" *) 
(* C_PROBE825_TYPE = "1" *) (* C_PROBE825_WIDTH = "1" *) (* C_PROBE826_MU_CNT = "1" *) 
(* C_PROBE826_TYPE = "1" *) (* C_PROBE826_WIDTH = "1" *) (* C_PROBE827_MU_CNT = "1" *) 
(* C_PROBE827_TYPE = "1" *) (* C_PROBE827_WIDTH = "1" *) (* C_PROBE828_MU_CNT = "1" *) 
(* C_PROBE828_TYPE = "1" *) (* C_PROBE828_WIDTH = "1" *) (* C_PROBE829_MU_CNT = "1" *) 
(* C_PROBE829_TYPE = "1" *) (* C_PROBE829_WIDTH = "1" *) (* C_PROBE82_MU_CNT = "1" *) 
(* C_PROBE82_TYPE = "1" *) (* C_PROBE82_WIDTH = "1" *) (* C_PROBE830_MU_CNT = "1" *) 
(* C_PROBE830_TYPE = "1" *) (* C_PROBE830_WIDTH = "1" *) (* C_PROBE831_MU_CNT = "1" *) 
(* C_PROBE831_TYPE = "1" *) (* C_PROBE831_WIDTH = "1" *) (* C_PROBE832_MU_CNT = "1" *) 
(* C_PROBE832_TYPE = "1" *) (* C_PROBE832_WIDTH = "1" *) (* C_PROBE833_MU_CNT = "1" *) 
(* C_PROBE833_TYPE = "1" *) (* C_PROBE833_WIDTH = "1" *) (* C_PROBE834_MU_CNT = "1" *) 
(* C_PROBE834_TYPE = "1" *) (* C_PROBE834_WIDTH = "1" *) (* C_PROBE835_MU_CNT = "1" *) 
(* C_PROBE835_TYPE = "1" *) (* C_PROBE835_WIDTH = "1" *) (* C_PROBE836_MU_CNT = "1" *) 
(* C_PROBE836_TYPE = "1" *) (* C_PROBE836_WIDTH = "1" *) (* C_PROBE837_MU_CNT = "1" *) 
(* C_PROBE837_TYPE = "1" *) (* C_PROBE837_WIDTH = "1" *) (* C_PROBE838_MU_CNT = "1" *) 
(* C_PROBE838_TYPE = "1" *) (* C_PROBE838_WIDTH = "1" *) (* C_PROBE839_MU_CNT = "1" *) 
(* C_PROBE839_TYPE = "1" *) (* C_PROBE839_WIDTH = "1" *) (* C_PROBE83_MU_CNT = "1" *) 
(* C_PROBE83_TYPE = "1" *) (* C_PROBE83_WIDTH = "1" *) (* C_PROBE840_MU_CNT = "1" *) 
(* C_PROBE840_TYPE = "1" *) (* C_PROBE840_WIDTH = "1" *) (* C_PROBE841_MU_CNT = "1" *) 
(* C_PROBE841_TYPE = "1" *) (* C_PROBE841_WIDTH = "1" *) (* C_PROBE842_MU_CNT = "1" *) 
(* C_PROBE842_TYPE = "1" *) (* C_PROBE842_WIDTH = "1" *) (* C_PROBE843_MU_CNT = "1" *) 
(* C_PROBE843_TYPE = "1" *) (* C_PROBE843_WIDTH = "1" *) (* C_PROBE844_MU_CNT = "1" *) 
(* C_PROBE844_TYPE = "1" *) (* C_PROBE844_WIDTH = "1" *) (* C_PROBE845_MU_CNT = "1" *) 
(* C_PROBE845_TYPE = "1" *) (* C_PROBE845_WIDTH = "1" *) (* C_PROBE846_MU_CNT = "1" *) 
(* C_PROBE846_TYPE = "1" *) (* C_PROBE846_WIDTH = "1" *) (* C_PROBE847_MU_CNT = "1" *) 
(* C_PROBE847_TYPE = "1" *) (* C_PROBE847_WIDTH = "1" *) (* C_PROBE848_MU_CNT = "1" *) 
(* C_PROBE848_TYPE = "1" *) (* C_PROBE848_WIDTH = "1" *) (* C_PROBE849_MU_CNT = "1" *) 
(* C_PROBE849_TYPE = "1" *) (* C_PROBE849_WIDTH = "1" *) (* C_PROBE84_MU_CNT = "1" *) 
(* C_PROBE84_TYPE = "1" *) (* C_PROBE84_WIDTH = "1" *) (* C_PROBE850_MU_CNT = "1" *) 
(* C_PROBE850_TYPE = "1" *) (* C_PROBE850_WIDTH = "1" *) (* C_PROBE851_MU_CNT = "1" *) 
(* C_PROBE851_TYPE = "1" *) (* C_PROBE851_WIDTH = "1" *) (* C_PROBE852_MU_CNT = "1" *) 
(* C_PROBE852_TYPE = "1" *) (* C_PROBE852_WIDTH = "1" *) (* C_PROBE853_MU_CNT = "1" *) 
(* C_PROBE853_TYPE = "1" *) (* C_PROBE853_WIDTH = "1" *) (* C_PROBE854_MU_CNT = "1" *) 
(* C_PROBE854_TYPE = "1" *) (* C_PROBE854_WIDTH = "1" *) (* C_PROBE855_MU_CNT = "1" *) 
(* C_PROBE855_TYPE = "1" *) (* C_PROBE855_WIDTH = "1" *) (* C_PROBE856_MU_CNT = "1" *) 
(* C_PROBE856_TYPE = "1" *) (* C_PROBE856_WIDTH = "1" *) (* C_PROBE857_MU_CNT = "1" *) 
(* C_PROBE857_TYPE = "1" *) (* C_PROBE857_WIDTH = "1" *) (* C_PROBE858_MU_CNT = "1" *) 
(* C_PROBE858_TYPE = "1" *) (* C_PROBE858_WIDTH = "1" *) (* C_PROBE859_MU_CNT = "1" *) 
(* C_PROBE859_TYPE = "1" *) (* C_PROBE859_WIDTH = "1" *) (* C_PROBE85_MU_CNT = "1" *) 
(* C_PROBE85_TYPE = "1" *) (* C_PROBE85_WIDTH = "1" *) (* C_PROBE860_MU_CNT = "1" *) 
(* C_PROBE860_TYPE = "1" *) (* C_PROBE860_WIDTH = "1" *) (* C_PROBE861_MU_CNT = "1" *) 
(* C_PROBE861_TYPE = "1" *) (* C_PROBE861_WIDTH = "1" *) (* C_PROBE862_MU_CNT = "1" *) 
(* C_PROBE862_TYPE = "1" *) (* C_PROBE862_WIDTH = "1" *) (* C_PROBE863_MU_CNT = "1" *) 
(* C_PROBE863_TYPE = "1" *) (* C_PROBE863_WIDTH = "1" *) (* C_PROBE864_MU_CNT = "1" *) 
(* C_PROBE864_TYPE = "1" *) (* C_PROBE864_WIDTH = "1" *) (* C_PROBE865_MU_CNT = "1" *) 
(* C_PROBE865_TYPE = "1" *) (* C_PROBE865_WIDTH = "1" *) (* C_PROBE866_MU_CNT = "1" *) 
(* C_PROBE866_TYPE = "1" *) (* C_PROBE866_WIDTH = "1" *) (* C_PROBE867_MU_CNT = "1" *) 
(* C_PROBE867_TYPE = "1" *) (* C_PROBE867_WIDTH = "1" *) (* C_PROBE868_MU_CNT = "1" *) 
(* C_PROBE868_TYPE = "1" *) (* C_PROBE868_WIDTH = "1" *) (* C_PROBE869_MU_CNT = "1" *) 
(* C_PROBE869_TYPE = "1" *) (* C_PROBE869_WIDTH = "1" *) (* C_PROBE86_MU_CNT = "1" *) 
(* C_PROBE86_TYPE = "1" *) (* C_PROBE86_WIDTH = "1" *) (* C_PROBE870_MU_CNT = "1" *) 
(* C_PROBE870_TYPE = "1" *) (* C_PROBE870_WIDTH = "1" *) (* C_PROBE871_MU_CNT = "1" *) 
(* C_PROBE871_TYPE = "1" *) (* C_PROBE871_WIDTH = "1" *) (* C_PROBE872_MU_CNT = "1" *) 
(* C_PROBE872_TYPE = "1" *) (* C_PROBE872_WIDTH = "1" *) (* C_PROBE873_MU_CNT = "1" *) 
(* C_PROBE873_TYPE = "1" *) (* C_PROBE873_WIDTH = "1" *) (* C_PROBE874_MU_CNT = "1" *) 
(* C_PROBE874_TYPE = "1" *) (* C_PROBE874_WIDTH = "1" *) (* C_PROBE875_MU_CNT = "1" *) 
(* C_PROBE875_TYPE = "1" *) (* C_PROBE875_WIDTH = "1" *) (* C_PROBE876_MU_CNT = "1" *) 
(* C_PROBE876_TYPE = "1" *) (* C_PROBE876_WIDTH = "1" *) (* C_PROBE877_MU_CNT = "1" *) 
(* C_PROBE877_TYPE = "1" *) (* C_PROBE877_WIDTH = "1" *) (* C_PROBE878_MU_CNT = "1" *) 
(* C_PROBE878_TYPE = "1" *) (* C_PROBE878_WIDTH = "1" *) (* C_PROBE879_MU_CNT = "1" *) 
(* C_PROBE879_TYPE = "1" *) (* C_PROBE879_WIDTH = "1" *) (* C_PROBE87_MU_CNT = "1" *) 
(* C_PROBE87_TYPE = "1" *) (* C_PROBE87_WIDTH = "1" *) (* C_PROBE880_MU_CNT = "1" *) 
(* C_PROBE880_TYPE = "1" *) (* C_PROBE880_WIDTH = "1" *) (* C_PROBE881_MU_CNT = "1" *) 
(* C_PROBE881_TYPE = "1" *) (* C_PROBE881_WIDTH = "1" *) (* C_PROBE882_MU_CNT = "1" *) 
(* C_PROBE882_TYPE = "1" *) (* C_PROBE882_WIDTH = "1" *) (* C_PROBE883_MU_CNT = "1" *) 
(* C_PROBE883_TYPE = "1" *) (* C_PROBE883_WIDTH = "1" *) (* C_PROBE884_MU_CNT = "1" *) 
(* C_PROBE884_TYPE = "1" *) (* C_PROBE884_WIDTH = "1" *) (* C_PROBE885_MU_CNT = "1" *) 
(* C_PROBE885_TYPE = "1" *) (* C_PROBE885_WIDTH = "1" *) (* C_PROBE886_MU_CNT = "1" *) 
(* C_PROBE886_TYPE = "1" *) (* C_PROBE886_WIDTH = "1" *) (* C_PROBE887_MU_CNT = "1" *) 
(* C_PROBE887_TYPE = "1" *) (* C_PROBE887_WIDTH = "1" *) (* C_PROBE888_MU_CNT = "1" *) 
(* C_PROBE888_TYPE = "1" *) (* C_PROBE888_WIDTH = "1" *) (* C_PROBE889_MU_CNT = "1" *) 
(* C_PROBE889_TYPE = "1" *) (* C_PROBE889_WIDTH = "1" *) (* C_PROBE88_MU_CNT = "1" *) 
(* C_PROBE88_TYPE = "1" *) (* C_PROBE88_WIDTH = "1" *) (* C_PROBE890_MU_CNT = "1" *) 
(* C_PROBE890_TYPE = "1" *) (* C_PROBE890_WIDTH = "1" *) (* C_PROBE891_MU_CNT = "1" *) 
(* C_PROBE891_TYPE = "1" *) (* C_PROBE891_WIDTH = "1" *) (* C_PROBE892_MU_CNT = "1" *) 
(* C_PROBE892_TYPE = "1" *) (* C_PROBE892_WIDTH = "1" *) (* C_PROBE893_MU_CNT = "1" *) 
(* C_PROBE893_TYPE = "1" *) (* C_PROBE893_WIDTH = "1" *) (* C_PROBE894_MU_CNT = "1" *) 
(* C_PROBE894_TYPE = "1" *) (* C_PROBE894_WIDTH = "1" *) (* C_PROBE895_MU_CNT = "1" *) 
(* C_PROBE895_TYPE = "1" *) (* C_PROBE895_WIDTH = "1" *) (* C_PROBE896_MU_CNT = "1" *) 
(* C_PROBE896_TYPE = "1" *) (* C_PROBE896_WIDTH = "1" *) (* C_PROBE897_MU_CNT = "1" *) 
(* C_PROBE897_TYPE = "1" *) (* C_PROBE897_WIDTH = "1" *) (* C_PROBE898_MU_CNT = "1" *) 
(* C_PROBE898_TYPE = "1" *) (* C_PROBE898_WIDTH = "1" *) (* C_PROBE899_MU_CNT = "1" *) 
(* C_PROBE899_TYPE = "1" *) (* C_PROBE899_WIDTH = "1" *) (* C_PROBE89_MU_CNT = "1" *) 
(* C_PROBE89_TYPE = "1" *) (* C_PROBE89_WIDTH = "1" *) (* C_PROBE8_MU_CNT = "1" *) 
(* C_PROBE8_TYPE = "1" *) (* C_PROBE8_WIDTH = "1" *) (* C_PROBE900_MU_CNT = "1" *) 
(* C_PROBE900_TYPE = "1" *) (* C_PROBE900_WIDTH = "1" *) (* C_PROBE901_MU_CNT = "1" *) 
(* C_PROBE901_TYPE = "1" *) (* C_PROBE901_WIDTH = "1" *) (* C_PROBE902_MU_CNT = "1" *) 
(* C_PROBE902_TYPE = "1" *) (* C_PROBE902_WIDTH = "1" *) (* C_PROBE903_MU_CNT = "1" *) 
(* C_PROBE903_TYPE = "1" *) (* C_PROBE903_WIDTH = "1" *) (* C_PROBE904_MU_CNT = "1" *) 
(* C_PROBE904_TYPE = "1" *) (* C_PROBE904_WIDTH = "1" *) (* C_PROBE905_MU_CNT = "1" *) 
(* C_PROBE905_TYPE = "1" *) (* C_PROBE905_WIDTH = "1" *) (* C_PROBE906_MU_CNT = "1" *) 
(* C_PROBE906_TYPE = "1" *) (* C_PROBE906_WIDTH = "1" *) (* C_PROBE907_MU_CNT = "1" *) 
(* C_PROBE907_TYPE = "1" *) (* C_PROBE907_WIDTH = "1" *) (* C_PROBE908_MU_CNT = "1" *) 
(* C_PROBE908_TYPE = "1" *) (* C_PROBE908_WIDTH = "1" *) (* C_PROBE909_MU_CNT = "1" *) 
(* C_PROBE909_TYPE = "1" *) (* C_PROBE909_WIDTH = "1" *) (* C_PROBE90_MU_CNT = "1" *) 
(* C_PROBE90_TYPE = "1" *) (* C_PROBE90_WIDTH = "1" *) (* C_PROBE910_MU_CNT = "1" *) 
(* C_PROBE910_TYPE = "1" *) (* C_PROBE910_WIDTH = "1" *) (* C_PROBE911_MU_CNT = "1" *) 
(* C_PROBE911_TYPE = "1" *) (* C_PROBE911_WIDTH = "1" *) (* C_PROBE912_MU_CNT = "1" *) 
(* C_PROBE912_TYPE = "1" *) (* C_PROBE912_WIDTH = "1" *) (* C_PROBE913_MU_CNT = "1" *) 
(* C_PROBE913_TYPE = "1" *) (* C_PROBE913_WIDTH = "1" *) (* C_PROBE914_MU_CNT = "1" *) 
(* C_PROBE914_TYPE = "1" *) (* C_PROBE914_WIDTH = "1" *) (* C_PROBE915_MU_CNT = "1" *) 
(* C_PROBE915_TYPE = "1" *) (* C_PROBE915_WIDTH = "1" *) (* C_PROBE916_MU_CNT = "1" *) 
(* C_PROBE916_TYPE = "1" *) (* C_PROBE916_WIDTH = "1" *) (* C_PROBE917_MU_CNT = "1" *) 
(* C_PROBE917_TYPE = "1" *) (* C_PROBE917_WIDTH = "1" *) (* C_PROBE918_MU_CNT = "1" *) 
(* C_PROBE918_TYPE = "1" *) (* C_PROBE918_WIDTH = "1" *) (* C_PROBE919_MU_CNT = "1" *) 
(* C_PROBE919_TYPE = "1" *) (* C_PROBE919_WIDTH = "1" *) (* C_PROBE91_MU_CNT = "1" *) 
(* C_PROBE91_TYPE = "1" *) (* C_PROBE91_WIDTH = "1" *) (* C_PROBE920_MU_CNT = "1" *) 
(* C_PROBE920_TYPE = "1" *) (* C_PROBE920_WIDTH = "1" *) (* C_PROBE921_MU_CNT = "1" *) 
(* C_PROBE921_TYPE = "1" *) (* C_PROBE921_WIDTH = "1" *) (* C_PROBE922_MU_CNT = "1" *) 
(* C_PROBE922_TYPE = "1" *) (* C_PROBE922_WIDTH = "1" *) (* C_PROBE923_MU_CNT = "1" *) 
(* C_PROBE923_TYPE = "1" *) (* C_PROBE923_WIDTH = "1" *) (* C_PROBE924_MU_CNT = "1" *) 
(* C_PROBE924_TYPE = "1" *) (* C_PROBE924_WIDTH = "1" *) (* C_PROBE925_MU_CNT = "1" *) 
(* C_PROBE925_TYPE = "1" *) (* C_PROBE925_WIDTH = "1" *) (* C_PROBE926_MU_CNT = "1" *) 
(* C_PROBE926_TYPE = "1" *) (* C_PROBE926_WIDTH = "1" *) (* C_PROBE927_MU_CNT = "1" *) 
(* C_PROBE927_TYPE = "1" *) (* C_PROBE927_WIDTH = "1" *) (* C_PROBE928_MU_CNT = "1" *) 
(* C_PROBE928_TYPE = "1" *) (* C_PROBE928_WIDTH = "1" *) (* C_PROBE929_MU_CNT = "1" *) 
(* C_PROBE929_TYPE = "1" *) (* C_PROBE929_WIDTH = "1" *) (* C_PROBE92_MU_CNT = "1" *) 
(* C_PROBE92_TYPE = "1" *) (* C_PROBE92_WIDTH = "1" *) (* C_PROBE930_MU_CNT = "1" *) 
(* C_PROBE930_TYPE = "1" *) (* C_PROBE930_WIDTH = "1" *) (* C_PROBE931_MU_CNT = "1" *) 
(* C_PROBE931_TYPE = "1" *) (* C_PROBE931_WIDTH = "1" *) (* C_PROBE932_MU_CNT = "1" *) 
(* C_PROBE932_TYPE = "1" *) (* C_PROBE932_WIDTH = "1" *) (* C_PROBE933_MU_CNT = "1" *) 
(* C_PROBE933_TYPE = "1" *) (* C_PROBE933_WIDTH = "1" *) (* C_PROBE934_MU_CNT = "1" *) 
(* C_PROBE934_TYPE = "1" *) (* C_PROBE934_WIDTH = "1" *) (* C_PROBE935_MU_CNT = "1" *) 
(* C_PROBE935_TYPE = "1" *) (* C_PROBE935_WIDTH = "1" *) (* C_PROBE936_MU_CNT = "1" *) 
(* C_PROBE936_TYPE = "1" *) (* C_PROBE936_WIDTH = "1" *) (* C_PROBE937_MU_CNT = "1" *) 
(* C_PROBE937_TYPE = "1" *) (* C_PROBE937_WIDTH = "1" *) (* C_PROBE938_MU_CNT = "1" *) 
(* C_PROBE938_TYPE = "1" *) (* C_PROBE938_WIDTH = "1" *) (* C_PROBE939_MU_CNT = "1" *) 
(* C_PROBE939_TYPE = "1" *) (* C_PROBE939_WIDTH = "1" *) (* C_PROBE93_MU_CNT = "1" *) 
(* C_PROBE93_TYPE = "1" *) (* C_PROBE93_WIDTH = "1" *) (* C_PROBE940_MU_CNT = "1" *) 
(* C_PROBE940_TYPE = "1" *) (* C_PROBE940_WIDTH = "1" *) (* C_PROBE941_MU_CNT = "1" *) 
(* C_PROBE941_TYPE = "1" *) (* C_PROBE941_WIDTH = "1" *) (* C_PROBE942_MU_CNT = "1" *) 
(* C_PROBE942_TYPE = "1" *) (* C_PROBE942_WIDTH = "1" *) (* C_PROBE943_MU_CNT = "1" *) 
(* C_PROBE943_TYPE = "1" *) (* C_PROBE943_WIDTH = "1" *) (* C_PROBE944_MU_CNT = "1" *) 
(* C_PROBE944_TYPE = "1" *) (* C_PROBE944_WIDTH = "1" *) (* C_PROBE945_MU_CNT = "1" *) 
(* C_PROBE945_TYPE = "1" *) (* C_PROBE945_WIDTH = "1" *) (* C_PROBE946_MU_CNT = "1" *) 
(* C_PROBE946_TYPE = "1" *) (* C_PROBE946_WIDTH = "1" *) (* C_PROBE947_MU_CNT = "1" *) 
(* C_PROBE947_TYPE = "1" *) (* C_PROBE947_WIDTH = "1" *) (* C_PROBE948_MU_CNT = "1" *) 
(* C_PROBE948_TYPE = "1" *) (* C_PROBE948_WIDTH = "1" *) (* C_PROBE949_MU_CNT = "1" *) 
(* C_PROBE949_TYPE = "1" *) (* C_PROBE949_WIDTH = "1" *) (* C_PROBE94_MU_CNT = "1" *) 
(* C_PROBE94_TYPE = "1" *) (* C_PROBE94_WIDTH = "1" *) (* C_PROBE950_MU_CNT = "1" *) 
(* C_PROBE950_TYPE = "1" *) (* C_PROBE950_WIDTH = "1" *) (* C_PROBE951_MU_CNT = "1" *) 
(* C_PROBE951_TYPE = "1" *) (* C_PROBE951_WIDTH = "1" *) (* C_PROBE952_MU_CNT = "1" *) 
(* C_PROBE952_TYPE = "1" *) (* C_PROBE952_WIDTH = "1" *) (* C_PROBE953_MU_CNT = "1" *) 
(* C_PROBE953_TYPE = "1" *) (* C_PROBE953_WIDTH = "1" *) (* C_PROBE954_MU_CNT = "1" *) 
(* C_PROBE954_TYPE = "1" *) (* C_PROBE954_WIDTH = "1" *) (* C_PROBE955_MU_CNT = "1" *) 
(* C_PROBE955_TYPE = "1" *) (* C_PROBE955_WIDTH = "1" *) (* C_PROBE956_MU_CNT = "1" *) 
(* C_PROBE956_TYPE = "1" *) (* C_PROBE956_WIDTH = "1" *) (* C_PROBE957_MU_CNT = "1" *) 
(* C_PROBE957_TYPE = "1" *) (* C_PROBE957_WIDTH = "1" *) (* C_PROBE958_MU_CNT = "1" *) 
(* C_PROBE958_TYPE = "1" *) (* C_PROBE958_WIDTH = "1" *) (* C_PROBE959_MU_CNT = "1" *) 
(* C_PROBE959_TYPE = "1" *) (* C_PROBE959_WIDTH = "1" *) (* C_PROBE95_MU_CNT = "1" *) 
(* C_PROBE95_TYPE = "1" *) (* C_PROBE95_WIDTH = "1" *) (* C_PROBE960_MU_CNT = "1" *) 
(* C_PROBE960_TYPE = "1" *) (* C_PROBE960_WIDTH = "1" *) (* C_PROBE961_MU_CNT = "1" *) 
(* C_PROBE961_TYPE = "1" *) (* C_PROBE961_WIDTH = "1" *) (* C_PROBE962_MU_CNT = "1" *) 
(* C_PROBE962_TYPE = "1" *) (* C_PROBE962_WIDTH = "1" *) (* C_PROBE963_MU_CNT = "1" *) 
(* C_PROBE963_TYPE = "1" *) (* C_PROBE963_WIDTH = "1" *) (* C_PROBE964_MU_CNT = "1" *) 
(* C_PROBE964_TYPE = "1" *) (* C_PROBE964_WIDTH = "1" *) (* C_PROBE965_MU_CNT = "1" *) 
(* C_PROBE965_TYPE = "1" *) (* C_PROBE965_WIDTH = "1" *) (* C_PROBE966_MU_CNT = "1" *) 
(* C_PROBE966_TYPE = "1" *) (* C_PROBE966_WIDTH = "1" *) (* C_PROBE967_MU_CNT = "1" *) 
(* C_PROBE967_TYPE = "1" *) (* C_PROBE967_WIDTH = "1" *) (* C_PROBE968_MU_CNT = "1" *) 
(* C_PROBE968_TYPE = "1" *) (* C_PROBE968_WIDTH = "1" *) (* C_PROBE969_MU_CNT = "1" *) 
(* C_PROBE969_TYPE = "1" *) (* C_PROBE969_WIDTH = "1" *) (* C_PROBE96_MU_CNT = "1" *) 
(* C_PROBE96_TYPE = "1" *) (* C_PROBE96_WIDTH = "1" *) (* C_PROBE970_MU_CNT = "1" *) 
(* C_PROBE970_TYPE = "1" *) (* C_PROBE970_WIDTH = "1" *) (* C_PROBE971_MU_CNT = "1" *) 
(* C_PROBE971_TYPE = "1" *) (* C_PROBE971_WIDTH = "1" *) (* C_PROBE972_MU_CNT = "1" *) 
(* C_PROBE972_TYPE = "1" *) (* C_PROBE972_WIDTH = "1" *) (* C_PROBE973_MU_CNT = "1" *) 
(* C_PROBE973_TYPE = "1" *) (* C_PROBE973_WIDTH = "1" *) (* C_PROBE974_MU_CNT = "1" *) 
(* C_PROBE974_TYPE = "1" *) (* C_PROBE974_WIDTH = "1" *) (* C_PROBE975_MU_CNT = "1" *) 
(* C_PROBE975_TYPE = "1" *) (* C_PROBE975_WIDTH = "1" *) (* C_PROBE976_MU_CNT = "1" *) 
(* C_PROBE976_TYPE = "1" *) (* C_PROBE976_WIDTH = "1" *) (* C_PROBE977_MU_CNT = "1" *) 
(* C_PROBE977_TYPE = "1" *) (* C_PROBE977_WIDTH = "1" *) (* C_PROBE978_MU_CNT = "1" *) 
(* C_PROBE978_TYPE = "1" *) (* C_PROBE978_WIDTH = "1" *) (* C_PROBE979_MU_CNT = "1" *) 
(* C_PROBE979_TYPE = "1" *) (* C_PROBE979_WIDTH = "1" *) (* C_PROBE97_MU_CNT = "1" *) 
(* C_PROBE97_TYPE = "1" *) (* C_PROBE97_WIDTH = "1" *) (* C_PROBE980_MU_CNT = "1" *) 
(* C_PROBE980_TYPE = "1" *) (* C_PROBE980_WIDTH = "1" *) (* C_PROBE981_MU_CNT = "1" *) 
(* C_PROBE981_TYPE = "1" *) (* C_PROBE981_WIDTH = "1" *) (* C_PROBE982_MU_CNT = "1" *) 
(* C_PROBE982_TYPE = "1" *) (* C_PROBE982_WIDTH = "1" *) (* C_PROBE983_MU_CNT = "1" *) 
(* C_PROBE983_TYPE = "1" *) (* C_PROBE983_WIDTH = "1" *) (* C_PROBE984_MU_CNT = "1" *) 
(* C_PROBE984_TYPE = "1" *) (* C_PROBE984_WIDTH = "1" *) (* C_PROBE985_MU_CNT = "1" *) 
(* C_PROBE985_TYPE = "1" *) (* C_PROBE985_WIDTH = "1" *) (* C_PROBE986_MU_CNT = "1" *) 
(* C_PROBE986_TYPE = "1" *) (* C_PROBE986_WIDTH = "1" *) (* C_PROBE987_MU_CNT = "1" *) 
(* C_PROBE987_TYPE = "1" *) (* C_PROBE987_WIDTH = "1" *) (* C_PROBE988_MU_CNT = "1" *) 
(* C_PROBE988_TYPE = "1" *) (* C_PROBE988_WIDTH = "1" *) (* C_PROBE989_MU_CNT = "1" *) 
(* C_PROBE989_TYPE = "1" *) (* C_PROBE989_WIDTH = "1" *) (* C_PROBE98_MU_CNT = "1" *) 
(* C_PROBE98_TYPE = "1" *) (* C_PROBE98_WIDTH = "1" *) (* C_PROBE990_MU_CNT = "1" *) 
(* C_PROBE990_TYPE = "1" *) (* C_PROBE990_WIDTH = "1" *) (* C_PROBE991_MU_CNT = "1" *) 
(* C_PROBE991_TYPE = "1" *) (* C_PROBE991_WIDTH = "1" *) (* C_PROBE992_MU_CNT = "1" *) 
(* C_PROBE992_TYPE = "1" *) (* C_PROBE992_WIDTH = "1" *) (* C_PROBE993_MU_CNT = "1" *) 
(* C_PROBE993_TYPE = "1" *) (* C_PROBE993_WIDTH = "1" *) (* C_PROBE994_MU_CNT = "1" *) 
(* C_PROBE994_TYPE = "1" *) (* C_PROBE994_WIDTH = "1" *) (* C_PROBE995_MU_CNT = "1" *) 
(* C_PROBE995_TYPE = "1" *) (* C_PROBE995_WIDTH = "1" *) (* C_PROBE996_MU_CNT = "1" *) 
(* C_PROBE996_TYPE = "1" *) (* C_PROBE996_WIDTH = "1" *) (* C_PROBE997_MU_CNT = "1" *) 
(* C_PROBE997_TYPE = "1" *) (* C_PROBE997_WIDTH = "1" *) (* C_PROBE998_MU_CNT = "1" *) 
(* C_PROBE998_TYPE = "1" *) (* C_PROBE998_WIDTH = "1" *) (* C_PROBE999_MU_CNT = "1" *) 
(* C_PROBE999_TYPE = "1" *) (* C_PROBE999_WIDTH = "1" *) (* C_PROBE99_MU_CNT = "1" *) 
(* C_PROBE99_TYPE = "1" *) (* C_PROBE99_WIDTH = "1" *) (* C_PROBE9_MU_CNT = "1" *) 
(* C_PROBE9_TYPE = "1" *) (* C_PROBE9_WIDTH = "1" *) (* C_RAM_STYLE = "SUBCORE" *) 
(* C_SLOT_0_AXIS_TDEST_WIDTH = "1" *) (* C_SLOT_0_AXIS_TID_WIDTH = "1" *) (* C_SLOT_0_AXIS_TUSER_WIDTH = "1" *) 
(* C_SLOT_0_AXI_ARUSER_WIDTH = "1" *) (* C_SLOT_0_AXI_AWUSER_WIDTH = "1" *) (* C_SLOT_0_AXI_BUSER_WIDTH = "1" *) 
(* C_SLOT_0_AXI_ID_WIDTH = "1" *) (* C_SLOT_0_AXI_PROTOCOL = "AXI4" *) (* C_SLOT_0_AXI_RUSER_WIDTH = "1" *) 
(* C_SLOT_0_AXI_WUSER_WIDTH = "1" *) (* C_TC_TYPE = "0" *) (* C_TIME_TAG_WIDTH = "32" *) 
(* C_TRIGIN_EN = "0" *) (* C_TRIGOUT_EN = "0" *) (* C_USE_TEST_REG = "1" *) 
(* C_XDEVICEFAMILY = "zynq" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XLNX_HW_PROBE_INFO_DUMMY1 = "DEFAULT" *) 
(* C_XLNX_HW_PROBE_INFO_DUMMY2 = "DEFAULT" *) (* C_XLNX_HW_PROBE_INFO_DUMMY3 = "DEFAULT" *) (* C_XLNX_HW_PROBE_INFO_DUMMY4 = "DEFAULT" *) 
(* C_XSDB_SLAVE_TYPE = "17" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IS_DEBUG_CORE = "TRUE" *) 
(* LC_COMPUTED_DATA_WIDTH = "65" *) (* LC_DATA_WIDTH = "65" *) (* LC_MATCH_TPID_VEC = "3072'b000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000100000000000000010000000000000001000000000000000010000000000000001000000000000000100000000000000010000000000000000000000000000000000000000000000000000000000000000" *) 
(* LC_MU_CNT_STRING = "4096' " *) (* LC_MU_COUNT = "12" *) (* LC_MU_COUNT_EN = "12" *) 
(* LC_NUM_OF_PROBES = "3" *) (* LC_NUM_PROBES = "3" *) (* LC_NUM_TRIG_EQS = "32" *) 
(* LC_PROBE0_IS_DATA = "1'b1" *) (* LC_PROBE0_IS_TRIG = "4'b1111" *) (* LC_PROBE0_MU_CNT = "4" *) 
(* LC_PROBE0_PID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE0_TYPE = "0" *) (* LC_PROBE0_WIDTH = "21" *) 
(* LC_PROBE1000_IS_DATA = "1'b0" *) (* LC_PROBE1000_IS_TRIG = "1'b0" *) (* LC_PROBE1000_MU_CNT = "1" *) 
(* LC_PROBE1000_PID = "16'b0000001111101000" *) (* LC_PROBE1000_TYPE = "1" *) (* LC_PROBE1000_WIDTH = "1" *) 
(* LC_PROBE1001_IS_DATA = "1'b0" *) (* LC_PROBE1001_IS_TRIG = "1'b0" *) (* LC_PROBE1001_MU_CNT = "1" *) 
(* LC_PROBE1001_PID = "16'b0000001111101001" *) (* LC_PROBE1001_TYPE = "1" *) (* LC_PROBE1001_WIDTH = "1" *) 
(* LC_PROBE1002_IS_DATA = "1'b0" *) (* LC_PROBE1002_IS_TRIG = "1'b0" *) (* LC_PROBE1002_MU_CNT = "1" *) 
(* LC_PROBE1002_PID = "16'b0000001111101010" *) (* LC_PROBE1002_TYPE = "1" *) (* LC_PROBE1002_WIDTH = "1" *) 
(* LC_PROBE1003_IS_DATA = "1'b0" *) (* LC_PROBE1003_IS_TRIG = "1'b0" *) (* LC_PROBE1003_MU_CNT = "1" *) 
(* LC_PROBE1003_PID = "16'b0000001111101011" *) (* LC_PROBE1003_TYPE = "1" *) (* LC_PROBE1003_WIDTH = "1" *) 
(* LC_PROBE1004_IS_DATA = "1'b0" *) (* LC_PROBE1004_IS_TRIG = "1'b0" *) (* LC_PROBE1004_MU_CNT = "1" *) 
(* LC_PROBE1004_PID = "16'b0000001111101100" *) (* LC_PROBE1004_TYPE = "1" *) (* LC_PROBE1004_WIDTH = "1" *) 
(* LC_PROBE1005_IS_DATA = "1'b0" *) (* LC_PROBE1005_IS_TRIG = "1'b0" *) (* LC_PROBE1005_MU_CNT = "1" *) 
(* LC_PROBE1005_PID = "16'b0000001111101101" *) (* LC_PROBE1005_TYPE = "1" *) (* LC_PROBE1005_WIDTH = "1" *) 
(* LC_PROBE1006_IS_DATA = "1'b0" *) (* LC_PROBE1006_IS_TRIG = "1'b0" *) (* LC_PROBE1006_MU_CNT = "1" *) 
(* LC_PROBE1006_PID = "16'b0000001111101110" *) (* LC_PROBE1006_TYPE = "1" *) (* LC_PROBE1006_WIDTH = "1" *) 
(* LC_PROBE1007_IS_DATA = "1'b0" *) (* LC_PROBE1007_IS_TRIG = "1'b0" *) (* LC_PROBE1007_MU_CNT = "1" *) 
(* LC_PROBE1007_PID = "16'b0000001111101111" *) (* LC_PROBE1007_TYPE = "1" *) (* LC_PROBE1007_WIDTH = "1" *) 
(* LC_PROBE1008_IS_DATA = "1'b0" *) (* LC_PROBE1008_IS_TRIG = "1'b0" *) (* LC_PROBE1008_MU_CNT = "1" *) 
(* LC_PROBE1008_PID = "16'b0000001111110000" *) (* LC_PROBE1008_TYPE = "1" *) (* LC_PROBE1008_WIDTH = "1" *) 
(* LC_PROBE1009_IS_DATA = "1'b0" *) (* LC_PROBE1009_IS_TRIG = "1'b0" *) (* LC_PROBE1009_MU_CNT = "1" *) 
(* LC_PROBE1009_PID = "16'b0000001111110001" *) (* LC_PROBE1009_TYPE = "1" *) (* LC_PROBE1009_WIDTH = "1" *) 
(* LC_PROBE100_IS_DATA = "1'b0" *) (* LC_PROBE100_IS_TRIG = "1'b0" *) (* LC_PROBE100_MU_CNT = "1" *) 
(* LC_PROBE100_PID = "16'b0000000001100100" *) (* LC_PROBE100_TYPE = "1" *) (* LC_PROBE100_WIDTH = "1" *) 
(* LC_PROBE1010_IS_DATA = "1'b0" *) (* LC_PROBE1010_IS_TRIG = "1'b0" *) (* LC_PROBE1010_MU_CNT = "1" *) 
(* LC_PROBE1010_PID = "16'b0000001111110010" *) (* LC_PROBE1010_TYPE = "1" *) (* LC_PROBE1010_WIDTH = "1" *) 
(* LC_PROBE1011_IS_DATA = "1'b0" *) (* LC_PROBE1011_IS_TRIG = "1'b0" *) (* LC_PROBE1011_MU_CNT = "1" *) 
(* LC_PROBE1011_PID = "16'b0000001111110011" *) (* LC_PROBE1011_TYPE = "1" *) (* LC_PROBE1011_WIDTH = "1" *) 
(* LC_PROBE1012_IS_DATA = "1'b0" *) (* LC_PROBE1012_IS_TRIG = "1'b0" *) (* LC_PROBE1012_MU_CNT = "1" *) 
(* LC_PROBE1012_PID = "16'b0000001111110100" *) (* LC_PROBE1012_TYPE = "1" *) (* LC_PROBE1012_WIDTH = "1" *) 
(* LC_PROBE1013_IS_DATA = "1'b0" *) (* LC_PROBE1013_IS_TRIG = "1'b0" *) (* LC_PROBE1013_MU_CNT = "1" *) 
(* LC_PROBE1013_PID = "16'b0000001111110101" *) (* LC_PROBE1013_TYPE = "1" *) (* LC_PROBE1013_WIDTH = "1" *) 
(* LC_PROBE1014_IS_DATA = "1'b0" *) (* LC_PROBE1014_IS_TRIG = "1'b0" *) (* LC_PROBE1014_MU_CNT = "1" *) 
(* LC_PROBE1014_PID = "16'b0000001111110110" *) (* LC_PROBE1014_TYPE = "1" *) (* LC_PROBE1014_WIDTH = "1" *) 
(* LC_PROBE1015_IS_DATA = "1'b0" *) (* LC_PROBE1015_IS_TRIG = "1'b0" *) (* LC_PROBE1015_MU_CNT = "1" *) 
(* LC_PROBE1015_PID = "16'b0000001111110111" *) (* LC_PROBE1015_TYPE = "1" *) (* LC_PROBE1015_WIDTH = "1" *) 
(* LC_PROBE1016_IS_DATA = "1'b0" *) (* LC_PROBE1016_IS_TRIG = "1'b0" *) (* LC_PROBE1016_MU_CNT = "1" *) 
(* LC_PROBE1016_PID = "16'b0000001111111000" *) (* LC_PROBE1016_TYPE = "1" *) (* LC_PROBE1016_WIDTH = "1" *) 
(* LC_PROBE1017_IS_DATA = "1'b0" *) (* LC_PROBE1017_IS_TRIG = "1'b0" *) (* LC_PROBE1017_MU_CNT = "1" *) 
(* LC_PROBE1017_PID = "16'b0000001111111001" *) (* LC_PROBE1017_TYPE = "1" *) (* LC_PROBE1017_WIDTH = "1" *) 
(* LC_PROBE1018_IS_DATA = "1'b0" *) (* LC_PROBE1018_IS_TRIG = "1'b0" *) (* LC_PROBE1018_MU_CNT = "1" *) 
(* LC_PROBE1018_PID = "16'b0000001111111010" *) (* LC_PROBE1018_TYPE = "1" *) (* LC_PROBE1018_WIDTH = "1" *) 
(* LC_PROBE1019_IS_DATA = "1'b0" *) (* LC_PROBE1019_IS_TRIG = "1'b0" *) (* LC_PROBE1019_MU_CNT = "1" *) 
(* LC_PROBE1019_PID = "16'b0000001111111011" *) (* LC_PROBE1019_TYPE = "1" *) (* LC_PROBE1019_WIDTH = "1" *) 
(* LC_PROBE101_IS_DATA = "1'b0" *) (* LC_PROBE101_IS_TRIG = "1'b0" *) (* LC_PROBE101_MU_CNT = "1" *) 
(* LC_PROBE101_PID = "16'b0000000001100101" *) (* LC_PROBE101_TYPE = "1" *) (* LC_PROBE101_WIDTH = "1" *) 
(* LC_PROBE1020_IS_DATA = "1'b0" *) (* LC_PROBE1020_IS_TRIG = "1'b0" *) (* LC_PROBE1020_MU_CNT = "1" *) 
(* LC_PROBE1020_PID = "16'b0000001111111100" *) (* LC_PROBE1020_TYPE = "1" *) (* LC_PROBE1020_WIDTH = "1" *) 
(* LC_PROBE1021_IS_DATA = "1'b0" *) (* LC_PROBE1021_IS_TRIG = "1'b0" *) (* LC_PROBE1021_MU_CNT = "1" *) 
(* LC_PROBE1021_PID = "16'b0000001111111101" *) (* LC_PROBE1021_TYPE = "1" *) (* LC_PROBE1021_WIDTH = "1" *) 
(* LC_PROBE1022_IS_DATA = "1'b0" *) (* LC_PROBE1022_IS_TRIG = "1'b0" *) (* LC_PROBE1022_MU_CNT = "1" *) 
(* LC_PROBE1022_PID = "16'b0000001111111110" *) (* LC_PROBE1022_TYPE = "1" *) (* LC_PROBE1022_WIDTH = "1" *) 
(* LC_PROBE1023_IS_DATA = "1'b0" *) (* LC_PROBE1023_IS_TRIG = "1'b0" *) (* LC_PROBE1023_MU_CNT = "1" *) 
(* LC_PROBE1023_PID = "16'b0000001111111111" *) (* LC_PROBE1023_TYPE = "1" *) (* LC_PROBE1023_WIDTH = "1" *) 
(* LC_PROBE102_IS_DATA = "1'b0" *) (* LC_PROBE102_IS_TRIG = "1'b0" *) (* LC_PROBE102_MU_CNT = "1" *) 
(* LC_PROBE102_PID = "16'b0000000001100110" *) (* LC_PROBE102_TYPE = "1" *) (* LC_PROBE102_WIDTH = "1" *) 
(* LC_PROBE103_IS_DATA = "1'b0" *) (* LC_PROBE103_IS_TRIG = "1'b0" *) (* LC_PROBE103_MU_CNT = "1" *) 
(* LC_PROBE103_PID = "16'b0000000001100111" *) (* LC_PROBE103_TYPE = "1" *) (* LC_PROBE103_WIDTH = "1" *) 
(* LC_PROBE104_IS_DATA = "1'b0" *) (* LC_PROBE104_IS_TRIG = "1'b0" *) (* LC_PROBE104_MU_CNT = "1" *) 
(* LC_PROBE104_PID = "16'b0000000001101000" *) (* LC_PROBE104_TYPE = "1" *) (* LC_PROBE104_WIDTH = "1" *) 
(* LC_PROBE105_IS_DATA = "1'b0" *) (* LC_PROBE105_IS_TRIG = "1'b0" *) (* LC_PROBE105_MU_CNT = "1" *) 
(* LC_PROBE105_PID = "16'b0000000001101001" *) (* LC_PROBE105_TYPE = "1" *) (* LC_PROBE105_WIDTH = "1" *) 
(* LC_PROBE106_IS_DATA = "1'b0" *) (* LC_PROBE106_IS_TRIG = "1'b0" *) (* LC_PROBE106_MU_CNT = "1" *) 
(* LC_PROBE106_PID = "16'b0000000001101010" *) (* LC_PROBE106_TYPE = "1" *) (* LC_PROBE106_WIDTH = "1" *) 
(* LC_PROBE107_IS_DATA = "1'b0" *) (* LC_PROBE107_IS_TRIG = "1'b0" *) (* LC_PROBE107_MU_CNT = "1" *) 
(* LC_PROBE107_PID = "16'b0000000001101011" *) (* LC_PROBE107_TYPE = "1" *) (* LC_PROBE107_WIDTH = "1" *) 
(* LC_PROBE108_IS_DATA = "1'b0" *) (* LC_PROBE108_IS_TRIG = "1'b0" *) (* LC_PROBE108_MU_CNT = "1" *) 
(* LC_PROBE108_PID = "16'b0000000001101100" *) (* LC_PROBE108_TYPE = "1" *) (* LC_PROBE108_WIDTH = "1" *) 
(* LC_PROBE109_IS_DATA = "1'b0" *) (* LC_PROBE109_IS_TRIG = "1'b0" *) (* LC_PROBE109_MU_CNT = "1" *) 
(* LC_PROBE109_PID = "16'b0000000001101101" *) (* LC_PROBE109_TYPE = "1" *) (* LC_PROBE109_WIDTH = "1" *) 
(* LC_PROBE10_IS_DATA = "1'b0" *) (* LC_PROBE10_IS_TRIG = "1'b0" *) (* LC_PROBE10_MU_CNT = "1" *) 
(* LC_PROBE10_PID = "16'b0000000000001010" *) (* LC_PROBE10_TYPE = "1" *) (* LC_PROBE10_WIDTH = "1" *) 
(* LC_PROBE110_IS_DATA = "1'b0" *) (* LC_PROBE110_IS_TRIG = "1'b0" *) (* LC_PROBE110_MU_CNT = "1" *) 
(* LC_PROBE110_PID = "16'b0000000001101110" *) (* LC_PROBE110_TYPE = "1" *) (* LC_PROBE110_WIDTH = "1" *) 
(* LC_PROBE111_IS_DATA = "1'b0" *) (* LC_PROBE111_IS_TRIG = "1'b0" *) (* LC_PROBE111_MU_CNT = "1" *) 
(* LC_PROBE111_PID = "16'b0000000001101111" *) (* LC_PROBE111_TYPE = "1" *) (* LC_PROBE111_WIDTH = "1" *) 
(* LC_PROBE112_IS_DATA = "1'b0" *) (* LC_PROBE112_IS_TRIG = "1'b0" *) (* LC_PROBE112_MU_CNT = "1" *) 
(* LC_PROBE112_PID = "16'b0000000001110000" *) (* LC_PROBE112_TYPE = "1" *) (* LC_PROBE112_WIDTH = "1" *) 
(* LC_PROBE113_IS_DATA = "1'b0" *) (* LC_PROBE113_IS_TRIG = "1'b0" *) (* LC_PROBE113_MU_CNT = "1" *) 
(* LC_PROBE113_PID = "16'b0000000001110001" *) (* LC_PROBE113_TYPE = "1" *) (* LC_PROBE113_WIDTH = "1" *) 
(* LC_PROBE114_IS_DATA = "1'b0" *) (* LC_PROBE114_IS_TRIG = "1'b0" *) (* LC_PROBE114_MU_CNT = "1" *) 
(* LC_PROBE114_PID = "16'b0000000001110010" *) (* LC_PROBE114_TYPE = "1" *) (* LC_PROBE114_WIDTH = "1" *) 
(* LC_PROBE115_IS_DATA = "1'b0" *) (* LC_PROBE115_IS_TRIG = "1'b0" *) (* LC_PROBE115_MU_CNT = "1" *) 
(* LC_PROBE115_PID = "16'b0000000001110011" *) (* LC_PROBE115_TYPE = "1" *) (* LC_PROBE115_WIDTH = "1" *) 
(* LC_PROBE116_IS_DATA = "1'b0" *) (* LC_PROBE116_IS_TRIG = "1'b0" *) (* LC_PROBE116_MU_CNT = "1" *) 
(* LC_PROBE116_PID = "16'b0000000001110100" *) (* LC_PROBE116_TYPE = "1" *) (* LC_PROBE116_WIDTH = "1" *) 
(* LC_PROBE117_IS_DATA = "1'b0" *) (* LC_PROBE117_IS_TRIG = "1'b0" *) (* LC_PROBE117_MU_CNT = "1" *) 
(* LC_PROBE117_PID = "16'b0000000001110101" *) (* LC_PROBE117_TYPE = "1" *) (* LC_PROBE117_WIDTH = "1" *) 
(* LC_PROBE118_IS_DATA = "1'b0" *) (* LC_PROBE118_IS_TRIG = "1'b0" *) (* LC_PROBE118_MU_CNT = "1" *) 
(* LC_PROBE118_PID = "16'b0000000001110110" *) (* LC_PROBE118_TYPE = "1" *) (* LC_PROBE118_WIDTH = "1" *) 
(* LC_PROBE119_IS_DATA = "1'b0" *) (* LC_PROBE119_IS_TRIG = "1'b0" *) (* LC_PROBE119_MU_CNT = "1" *) 
(* LC_PROBE119_PID = "16'b0000000001110111" *) (* LC_PROBE119_TYPE = "1" *) (* LC_PROBE119_WIDTH = "1" *) 
(* LC_PROBE11_IS_DATA = "1'b0" *) (* LC_PROBE11_IS_TRIG = "1'b0" *) (* LC_PROBE11_MU_CNT = "1" *) 
(* LC_PROBE11_PID = "16'b0000000000001011" *) (* LC_PROBE11_TYPE = "1" *) (* LC_PROBE11_WIDTH = "1" *) 
(* LC_PROBE120_IS_DATA = "1'b0" *) (* LC_PROBE120_IS_TRIG = "1'b0" *) (* LC_PROBE120_MU_CNT = "1" *) 
(* LC_PROBE120_PID = "16'b0000000001111000" *) (* LC_PROBE120_TYPE = "1" *) (* LC_PROBE120_WIDTH = "1" *) 
(* LC_PROBE121_IS_DATA = "1'b0" *) (* LC_PROBE121_IS_TRIG = "1'b0" *) (* LC_PROBE121_MU_CNT = "1" *) 
(* LC_PROBE121_PID = "16'b0000000001111001" *) (* LC_PROBE121_TYPE = "1" *) (* LC_PROBE121_WIDTH = "1" *) 
(* LC_PROBE122_IS_DATA = "1'b0" *) (* LC_PROBE122_IS_TRIG = "1'b0" *) (* LC_PROBE122_MU_CNT = "1" *) 
(* LC_PROBE122_PID = "16'b0000000001111010" *) (* LC_PROBE122_TYPE = "1" *) (* LC_PROBE122_WIDTH = "1" *) 
(* LC_PROBE123_IS_DATA = "1'b0" *) (* LC_PROBE123_IS_TRIG = "1'b0" *) (* LC_PROBE123_MU_CNT = "1" *) 
(* LC_PROBE123_PID = "16'b0000000001111011" *) (* LC_PROBE123_TYPE = "1" *) (* LC_PROBE123_WIDTH = "1" *) 
(* LC_PROBE124_IS_DATA = "1'b0" *) (* LC_PROBE124_IS_TRIG = "1'b0" *) (* LC_PROBE124_MU_CNT = "1" *) 
(* LC_PROBE124_PID = "16'b0000000001111100" *) (* LC_PROBE124_TYPE = "1" *) (* LC_PROBE124_WIDTH = "1" *) 
(* LC_PROBE125_IS_DATA = "1'b0" *) (* LC_PROBE125_IS_TRIG = "1'b0" *) (* LC_PROBE125_MU_CNT = "1" *) 
(* LC_PROBE125_PID = "16'b0000000001111101" *) (* LC_PROBE125_TYPE = "1" *) (* LC_PROBE125_WIDTH = "1" *) 
(* LC_PROBE126_IS_DATA = "1'b0" *) (* LC_PROBE126_IS_TRIG = "1'b0" *) (* LC_PROBE126_MU_CNT = "1" *) 
(* LC_PROBE126_PID = "16'b0000000001111110" *) (* LC_PROBE126_TYPE = "1" *) (* LC_PROBE126_WIDTH = "1" *) 
(* LC_PROBE127_IS_DATA = "1'b0" *) (* LC_PROBE127_IS_TRIG = "1'b0" *) (* LC_PROBE127_MU_CNT = "1" *) 
(* LC_PROBE127_PID = "16'b0000000001111111" *) (* LC_PROBE127_TYPE = "1" *) (* LC_PROBE127_WIDTH = "1" *) 
(* LC_PROBE128_IS_DATA = "1'b0" *) (* LC_PROBE128_IS_TRIG = "1'b0" *) (* LC_PROBE128_MU_CNT = "1" *) 
(* LC_PROBE128_PID = "16'b0000000010000000" *) (* LC_PROBE128_TYPE = "1" *) (* LC_PROBE128_WIDTH = "1" *) 
(* LC_PROBE129_IS_DATA = "1'b0" *) (* LC_PROBE129_IS_TRIG = "1'b0" *) (* LC_PROBE129_MU_CNT = "1" *) 
(* LC_PROBE129_PID = "16'b0000000010000001" *) (* LC_PROBE129_TYPE = "1" *) (* LC_PROBE129_WIDTH = "1" *) 
(* LC_PROBE12_IS_DATA = "1'b0" *) (* LC_PROBE12_IS_TRIG = "1'b0" *) (* LC_PROBE12_MU_CNT = "1" *) 
(* LC_PROBE12_PID = "16'b0000000000001100" *) (* LC_PROBE12_TYPE = "1" *) (* LC_PROBE12_WIDTH = "1" *) 
(* LC_PROBE130_IS_DATA = "1'b0" *) (* LC_PROBE130_IS_TRIG = "1'b0" *) (* LC_PROBE130_MU_CNT = "1" *) 
(* LC_PROBE130_PID = "16'b0000000010000010" *) (* LC_PROBE130_TYPE = "1" *) (* LC_PROBE130_WIDTH = "1" *) 
(* LC_PROBE131_IS_DATA = "1'b0" *) (* LC_PROBE131_IS_TRIG = "1'b0" *) (* LC_PROBE131_MU_CNT = "1" *) 
(* LC_PROBE131_PID = "16'b0000000010000011" *) (* LC_PROBE131_TYPE = "1" *) (* LC_PROBE131_WIDTH = "1" *) 
(* LC_PROBE132_IS_DATA = "1'b0" *) (* LC_PROBE132_IS_TRIG = "1'b0" *) (* LC_PROBE132_MU_CNT = "1" *) 
(* LC_PROBE132_PID = "16'b0000000010000100" *) (* LC_PROBE132_TYPE = "1" *) (* LC_PROBE132_WIDTH = "1" *) 
(* LC_PROBE133_IS_DATA = "1'b0" *) (* LC_PROBE133_IS_TRIG = "1'b0" *) (* LC_PROBE133_MU_CNT = "1" *) 
(* LC_PROBE133_PID = "16'b0000000010000101" *) (* LC_PROBE133_TYPE = "1" *) (* LC_PROBE133_WIDTH = "1" *) 
(* LC_PROBE134_IS_DATA = "1'b0" *) (* LC_PROBE134_IS_TRIG = "1'b0" *) (* LC_PROBE134_MU_CNT = "1" *) 
(* LC_PROBE134_PID = "16'b0000000010000110" *) (* LC_PROBE134_TYPE = "1" *) (* LC_PROBE134_WIDTH = "1" *) 
(* LC_PROBE135_IS_DATA = "1'b0" *) (* LC_PROBE135_IS_TRIG = "1'b0" *) (* LC_PROBE135_MU_CNT = "1" *) 
(* LC_PROBE135_PID = "16'b0000000010000111" *) (* LC_PROBE135_TYPE = "1" *) (* LC_PROBE135_WIDTH = "1" *) 
(* LC_PROBE136_IS_DATA = "1'b0" *) (* LC_PROBE136_IS_TRIG = "1'b0" *) (* LC_PROBE136_MU_CNT = "1" *) 
(* LC_PROBE136_PID = "16'b0000000010001000" *) (* LC_PROBE136_TYPE = "1" *) (* LC_PROBE136_WIDTH = "1" *) 
(* LC_PROBE137_IS_DATA = "1'b0" *) (* LC_PROBE137_IS_TRIG = "1'b0" *) (* LC_PROBE137_MU_CNT = "1" *) 
(* LC_PROBE137_PID = "16'b0000000010001001" *) (* LC_PROBE137_TYPE = "1" *) (* LC_PROBE137_WIDTH = "1" *) 
(* LC_PROBE138_IS_DATA = "1'b0" *) (* LC_PROBE138_IS_TRIG = "1'b0" *) (* LC_PROBE138_MU_CNT = "1" *) 
(* LC_PROBE138_PID = "16'b0000000010001010" *) (* LC_PROBE138_TYPE = "1" *) (* LC_PROBE138_WIDTH = "1" *) 
(* LC_PROBE139_IS_DATA = "1'b0" *) (* LC_PROBE139_IS_TRIG = "1'b0" *) (* LC_PROBE139_MU_CNT = "1" *) 
(* LC_PROBE139_PID = "16'b0000000010001011" *) (* LC_PROBE139_TYPE = "1" *) (* LC_PROBE139_WIDTH = "1" *) 
(* LC_PROBE13_IS_DATA = "1'b0" *) (* LC_PROBE13_IS_TRIG = "1'b0" *) (* LC_PROBE13_MU_CNT = "1" *) 
(* LC_PROBE13_PID = "16'b0000000000001101" *) (* LC_PROBE13_TYPE = "1" *) (* LC_PROBE13_WIDTH = "1" *) 
(* LC_PROBE140_IS_DATA = "1'b0" *) (* LC_PROBE140_IS_TRIG = "1'b0" *) (* LC_PROBE140_MU_CNT = "1" *) 
(* LC_PROBE140_PID = "16'b0000000010001100" *) (* LC_PROBE140_TYPE = "1" *) (* LC_PROBE140_WIDTH = "1" *) 
(* LC_PROBE141_IS_DATA = "1'b0" *) (* LC_PROBE141_IS_TRIG = "1'b0" *) (* LC_PROBE141_MU_CNT = "1" *) 
(* LC_PROBE141_PID = "16'b0000000010001101" *) (* LC_PROBE141_TYPE = "1" *) (* LC_PROBE141_WIDTH = "1" *) 
(* LC_PROBE142_IS_DATA = "1'b0" *) (* LC_PROBE142_IS_TRIG = "1'b0" *) (* LC_PROBE142_MU_CNT = "1" *) 
(* LC_PROBE142_PID = "16'b0000000010001110" *) (* LC_PROBE142_TYPE = "1" *) (* LC_PROBE142_WIDTH = "1" *) 
(* LC_PROBE143_IS_DATA = "1'b0" *) (* LC_PROBE143_IS_TRIG = "1'b0" *) (* LC_PROBE143_MU_CNT = "1" *) 
(* LC_PROBE143_PID = "16'b0000000010001111" *) (* LC_PROBE143_TYPE = "1" *) (* LC_PROBE143_WIDTH = "1" *) 
(* LC_PROBE144_IS_DATA = "1'b0" *) (* LC_PROBE144_IS_TRIG = "1'b0" *) (* LC_PROBE144_MU_CNT = "1" *) 
(* LC_PROBE144_PID = "16'b0000000010010000" *) (* LC_PROBE144_TYPE = "1" *) (* LC_PROBE144_WIDTH = "1" *) 
(* LC_PROBE145_IS_DATA = "1'b0" *) (* LC_PROBE145_IS_TRIG = "1'b0" *) (* LC_PROBE145_MU_CNT = "1" *) 
(* LC_PROBE145_PID = "16'b0000000010010001" *) (* LC_PROBE145_TYPE = "1" *) (* LC_PROBE145_WIDTH = "1" *) 
(* LC_PROBE146_IS_DATA = "1'b0" *) (* LC_PROBE146_IS_TRIG = "1'b0" *) (* LC_PROBE146_MU_CNT = "1" *) 
(* LC_PROBE146_PID = "16'b0000000010010010" *) (* LC_PROBE146_TYPE = "1" *) (* LC_PROBE146_WIDTH = "1" *) 
(* LC_PROBE147_IS_DATA = "1'b0" *) (* LC_PROBE147_IS_TRIG = "1'b0" *) (* LC_PROBE147_MU_CNT = "1" *) 
(* LC_PROBE147_PID = "16'b0000000010010011" *) (* LC_PROBE147_TYPE = "1" *) (* LC_PROBE147_WIDTH = "1" *) 
(* LC_PROBE148_IS_DATA = "1'b0" *) (* LC_PROBE148_IS_TRIG = "1'b0" *) (* LC_PROBE148_MU_CNT = "1" *) 
(* LC_PROBE148_PID = "16'b0000000010010100" *) (* LC_PROBE148_TYPE = "1" *) (* LC_PROBE148_WIDTH = "1" *) 
(* LC_PROBE149_IS_DATA = "1'b0" *) (* LC_PROBE149_IS_TRIG = "1'b0" *) (* LC_PROBE149_MU_CNT = "1" *) 
(* LC_PROBE149_PID = "16'b0000000010010101" *) (* LC_PROBE149_TYPE = "1" *) (* LC_PROBE149_WIDTH = "1" *) 
(* LC_PROBE14_IS_DATA = "1'b0" *) (* LC_PROBE14_IS_TRIG = "1'b0" *) (* LC_PROBE14_MU_CNT = "1" *) 
(* LC_PROBE14_PID = "16'b0000000000001110" *) (* LC_PROBE14_TYPE = "1" *) (* LC_PROBE14_WIDTH = "1" *) 
(* LC_PROBE150_IS_DATA = "1'b0" *) (* LC_PROBE150_IS_TRIG = "1'b0" *) (* LC_PROBE150_MU_CNT = "1" *) 
(* LC_PROBE150_PID = "16'b0000000010010110" *) (* LC_PROBE150_TYPE = "1" *) (* LC_PROBE150_WIDTH = "1" *) 
(* LC_PROBE151_IS_DATA = "1'b0" *) (* LC_PROBE151_IS_TRIG = "1'b0" *) (* LC_PROBE151_MU_CNT = "1" *) 
(* LC_PROBE151_PID = "16'b0000000010010111" *) (* LC_PROBE151_TYPE = "1" *) (* LC_PROBE151_WIDTH = "1" *) 
(* LC_PROBE152_IS_DATA = "1'b0" *) (* LC_PROBE152_IS_TRIG = "1'b0" *) (* LC_PROBE152_MU_CNT = "1" *) 
(* LC_PROBE152_PID = "16'b0000000010011000" *) (* LC_PROBE152_TYPE = "1" *) (* LC_PROBE152_WIDTH = "1" *) 
(* LC_PROBE153_IS_DATA = "1'b0" *) (* LC_PROBE153_IS_TRIG = "1'b0" *) (* LC_PROBE153_MU_CNT = "1" *) 
(* LC_PROBE153_PID = "16'b0000000010011001" *) (* LC_PROBE153_TYPE = "1" *) (* LC_PROBE153_WIDTH = "1" *) 
(* LC_PROBE154_IS_DATA = "1'b0" *) (* LC_PROBE154_IS_TRIG = "1'b0" *) (* LC_PROBE154_MU_CNT = "1" *) 
(* LC_PROBE154_PID = "16'b0000000010011010" *) (* LC_PROBE154_TYPE = "1" *) (* LC_PROBE154_WIDTH = "1" *) 
(* LC_PROBE155_IS_DATA = "1'b0" *) (* LC_PROBE155_IS_TRIG = "1'b0" *) (* LC_PROBE155_MU_CNT = "1" *) 
(* LC_PROBE155_PID = "16'b0000000010011011" *) (* LC_PROBE155_TYPE = "1" *) (* LC_PROBE155_WIDTH = "1" *) 
(* LC_PROBE156_IS_DATA = "1'b0" *) (* LC_PROBE156_IS_TRIG = "1'b0" *) (* LC_PROBE156_MU_CNT = "1" *) 
(* LC_PROBE156_PID = "16'b0000000010011100" *) (* LC_PROBE156_TYPE = "1" *) (* LC_PROBE156_WIDTH = "1" *) 
(* LC_PROBE157_IS_DATA = "1'b0" *) (* LC_PROBE157_IS_TRIG = "1'b0" *) (* LC_PROBE157_MU_CNT = "1" *) 
(* LC_PROBE157_PID = "16'b0000000010011101" *) (* LC_PROBE157_TYPE = "1" *) (* LC_PROBE157_WIDTH = "1" *) 
(* LC_PROBE158_IS_DATA = "1'b0" *) (* LC_PROBE158_IS_TRIG = "1'b0" *) (* LC_PROBE158_MU_CNT = "1" *) 
(* LC_PROBE158_PID = "16'b0000000010011110" *) (* LC_PROBE158_TYPE = "1" *) (* LC_PROBE158_WIDTH = "1" *) 
(* LC_PROBE159_IS_DATA = "1'b0" *) (* LC_PROBE159_IS_TRIG = "1'b0" *) (* LC_PROBE159_MU_CNT = "1" *) 
(* LC_PROBE159_PID = "16'b0000000010011111" *) (* LC_PROBE159_TYPE = "1" *) (* LC_PROBE159_WIDTH = "1" *) 
(* LC_PROBE15_IS_DATA = "1'b0" *) (* LC_PROBE15_IS_TRIG = "1'b0" *) (* LC_PROBE15_MU_CNT = "1" *) 
(* LC_PROBE15_PID = "16'b0000000000001111" *) (* LC_PROBE15_TYPE = "1" *) (* LC_PROBE15_WIDTH = "1" *) 
(* LC_PROBE160_IS_DATA = "1'b0" *) (* LC_PROBE160_IS_TRIG = "1'b0" *) (* LC_PROBE160_MU_CNT = "1" *) 
(* LC_PROBE160_PID = "16'b0000000010100000" *) (* LC_PROBE160_TYPE = "1" *) (* LC_PROBE160_WIDTH = "1" *) 
(* LC_PROBE161_IS_DATA = "1'b0" *) (* LC_PROBE161_IS_TRIG = "1'b0" *) (* LC_PROBE161_MU_CNT = "1" *) 
(* LC_PROBE161_PID = "16'b0000000010100001" *) (* LC_PROBE161_TYPE = "1" *) (* LC_PROBE161_WIDTH = "1" *) 
(* LC_PROBE162_IS_DATA = "1'b0" *) (* LC_PROBE162_IS_TRIG = "1'b0" *) (* LC_PROBE162_MU_CNT = "1" *) 
(* LC_PROBE162_PID = "16'b0000000010100010" *) (* LC_PROBE162_TYPE = "1" *) (* LC_PROBE162_WIDTH = "1" *) 
(* LC_PROBE163_IS_DATA = "1'b0" *) (* LC_PROBE163_IS_TRIG = "1'b0" *) (* LC_PROBE163_MU_CNT = "1" *) 
(* LC_PROBE163_PID = "16'b0000000010100011" *) (* LC_PROBE163_TYPE = "1" *) (* LC_PROBE163_WIDTH = "1" *) 
(* LC_PROBE164_IS_DATA = "1'b0" *) (* LC_PROBE164_IS_TRIG = "1'b0" *) (* LC_PROBE164_MU_CNT = "1" *) 
(* LC_PROBE164_PID = "16'b0000000010100100" *) (* LC_PROBE164_TYPE = "1" *) (* LC_PROBE164_WIDTH = "1" *) 
(* LC_PROBE165_IS_DATA = "1'b0" *) (* LC_PROBE165_IS_TRIG = "1'b0" *) (* LC_PROBE165_MU_CNT = "1" *) 
(* LC_PROBE165_PID = "16'b0000000010100101" *) (* LC_PROBE165_TYPE = "1" *) (* LC_PROBE165_WIDTH = "1" *) 
(* LC_PROBE166_IS_DATA = "1'b0" *) (* LC_PROBE166_IS_TRIG = "1'b0" *) (* LC_PROBE166_MU_CNT = "1" *) 
(* LC_PROBE166_PID = "16'b0000000010100110" *) (* LC_PROBE166_TYPE = "1" *) (* LC_PROBE166_WIDTH = "1" *) 
(* LC_PROBE167_IS_DATA = "1'b0" *) (* LC_PROBE167_IS_TRIG = "1'b0" *) (* LC_PROBE167_MU_CNT = "1" *) 
(* LC_PROBE167_PID = "16'b0000000010100111" *) (* LC_PROBE167_TYPE = "1" *) (* LC_PROBE167_WIDTH = "1" *) 
(* LC_PROBE168_IS_DATA = "1'b0" *) (* LC_PROBE168_IS_TRIG = "1'b0" *) (* LC_PROBE168_MU_CNT = "1" *) 
(* LC_PROBE168_PID = "16'b0000000010101000" *) (* LC_PROBE168_TYPE = "1" *) (* LC_PROBE168_WIDTH = "1" *) 
(* LC_PROBE169_IS_DATA = "1'b0" *) (* LC_PROBE169_IS_TRIG = "1'b0" *) (* LC_PROBE169_MU_CNT = "1" *) 
(* LC_PROBE169_PID = "16'b0000000010101001" *) (* LC_PROBE169_TYPE = "1" *) (* LC_PROBE169_WIDTH = "1" *) 
(* LC_PROBE16_IS_DATA = "1'b0" *) (* LC_PROBE16_IS_TRIG = "1'b0" *) (* LC_PROBE16_MU_CNT = "1" *) 
(* LC_PROBE16_PID = "16'b0000000000010000" *) (* LC_PROBE16_TYPE = "1" *) (* LC_PROBE16_WIDTH = "1" *) 
(* LC_PROBE170_IS_DATA = "1'b0" *) (* LC_PROBE170_IS_TRIG = "1'b0" *) (* LC_PROBE170_MU_CNT = "1" *) 
(* LC_PROBE170_PID = "16'b0000000010101010" *) (* LC_PROBE170_TYPE = "1" *) (* LC_PROBE170_WIDTH = "1" *) 
(* LC_PROBE171_IS_DATA = "1'b0" *) (* LC_PROBE171_IS_TRIG = "1'b0" *) (* LC_PROBE171_MU_CNT = "1" *) 
(* LC_PROBE171_PID = "16'b0000000010101011" *) (* LC_PROBE171_TYPE = "1" *) (* LC_PROBE171_WIDTH = "1" *) 
(* LC_PROBE172_IS_DATA = "1'b0" *) (* LC_PROBE172_IS_TRIG = "1'b0" *) (* LC_PROBE172_MU_CNT = "1" *) 
(* LC_PROBE172_PID = "16'b0000000010101100" *) (* LC_PROBE172_TYPE = "1" *) (* LC_PROBE172_WIDTH = "1" *) 
(* LC_PROBE173_IS_DATA = "1'b0" *) (* LC_PROBE173_IS_TRIG = "1'b0" *) (* LC_PROBE173_MU_CNT = "1" *) 
(* LC_PROBE173_PID = "16'b0000000010101101" *) (* LC_PROBE173_TYPE = "1" *) (* LC_PROBE173_WIDTH = "1" *) 
(* LC_PROBE174_IS_DATA = "1'b0" *) (* LC_PROBE174_IS_TRIG = "1'b0" *) (* LC_PROBE174_MU_CNT = "1" *) 
(* LC_PROBE174_PID = "16'b0000000010101110" *) (* LC_PROBE174_TYPE = "1" *) (* LC_PROBE174_WIDTH = "1" *) 
(* LC_PROBE175_IS_DATA = "1'b0" *) (* LC_PROBE175_IS_TRIG = "1'b0" *) (* LC_PROBE175_MU_CNT = "1" *) 
(* LC_PROBE175_PID = "16'b0000000010101111" *) (* LC_PROBE175_TYPE = "1" *) (* LC_PROBE175_WIDTH = "1" *) 
(* LC_PROBE176_IS_DATA = "1'b0" *) (* LC_PROBE176_IS_TRIG = "1'b0" *) (* LC_PROBE176_MU_CNT = "1" *) 
(* LC_PROBE176_PID = "16'b0000000010110000" *) (* LC_PROBE176_TYPE = "1" *) (* LC_PROBE176_WIDTH = "1" *) 
(* LC_PROBE177_IS_DATA = "1'b0" *) (* LC_PROBE177_IS_TRIG = "1'b0" *) (* LC_PROBE177_MU_CNT = "1" *) 
(* LC_PROBE177_PID = "16'b0000000010110001" *) (* LC_PROBE177_TYPE = "1" *) (* LC_PROBE177_WIDTH = "1" *) 
(* LC_PROBE178_IS_DATA = "1'b0" *) (* LC_PROBE178_IS_TRIG = "1'b0" *) (* LC_PROBE178_MU_CNT = "1" *) 
(* LC_PROBE178_PID = "16'b0000000010110010" *) (* LC_PROBE178_TYPE = "1" *) (* LC_PROBE178_WIDTH = "1" *) 
(* LC_PROBE179_IS_DATA = "1'b0" *) (* LC_PROBE179_IS_TRIG = "1'b0" *) (* LC_PROBE179_MU_CNT = "1" *) 
(* LC_PROBE179_PID = "16'b0000000010110011" *) (* LC_PROBE179_TYPE = "1" *) (* LC_PROBE179_WIDTH = "1" *) 
(* LC_PROBE17_IS_DATA = "1'b0" *) (* LC_PROBE17_IS_TRIG = "1'b0" *) (* LC_PROBE17_MU_CNT = "1" *) 
(* LC_PROBE17_PID = "16'b0000000000010001" *) (* LC_PROBE17_TYPE = "1" *) (* LC_PROBE17_WIDTH = "1" *) 
(* LC_PROBE180_IS_DATA = "1'b0" *) (* LC_PROBE180_IS_TRIG = "1'b0" *) (* LC_PROBE180_MU_CNT = "1" *) 
(* LC_PROBE180_PID = "16'b0000000010110100" *) (* LC_PROBE180_TYPE = "1" *) (* LC_PROBE180_WIDTH = "1" *) 
(* LC_PROBE181_IS_DATA = "1'b0" *) (* LC_PROBE181_IS_TRIG = "1'b0" *) (* LC_PROBE181_MU_CNT = "1" *) 
(* LC_PROBE181_PID = "16'b0000000010110101" *) (* LC_PROBE181_TYPE = "1" *) (* LC_PROBE181_WIDTH = "1" *) 
(* LC_PROBE182_IS_DATA = "1'b0" *) (* LC_PROBE182_IS_TRIG = "1'b0" *) (* LC_PROBE182_MU_CNT = "1" *) 
(* LC_PROBE182_PID = "16'b0000000010110110" *) (* LC_PROBE182_TYPE = "1" *) (* LC_PROBE182_WIDTH = "1" *) 
(* LC_PROBE183_IS_DATA = "1'b0" *) (* LC_PROBE183_IS_TRIG = "1'b0" *) (* LC_PROBE183_MU_CNT = "1" *) 
(* LC_PROBE183_PID = "16'b0000000010110111" *) (* LC_PROBE183_TYPE = "1" *) (* LC_PROBE183_WIDTH = "1" *) 
(* LC_PROBE184_IS_DATA = "1'b0" *) (* LC_PROBE184_IS_TRIG = "1'b0" *) (* LC_PROBE184_MU_CNT = "1" *) 
(* LC_PROBE184_PID = "16'b0000000010111000" *) (* LC_PROBE184_TYPE = "1" *) (* LC_PROBE184_WIDTH = "1" *) 
(* LC_PROBE185_IS_DATA = "1'b0" *) (* LC_PROBE185_IS_TRIG = "1'b0" *) (* LC_PROBE185_MU_CNT = "1" *) 
(* LC_PROBE185_PID = "16'b0000000010111001" *) (* LC_PROBE185_TYPE = "1" *) (* LC_PROBE185_WIDTH = "1" *) 
(* LC_PROBE186_IS_DATA = "1'b0" *) (* LC_PROBE186_IS_TRIG = "1'b0" *) (* LC_PROBE186_MU_CNT = "1" *) 
(* LC_PROBE186_PID = "16'b0000000010111010" *) (* LC_PROBE186_TYPE = "1" *) (* LC_PROBE186_WIDTH = "1" *) 
(* LC_PROBE187_IS_DATA = "1'b0" *) (* LC_PROBE187_IS_TRIG = "1'b0" *) (* LC_PROBE187_MU_CNT = "1" *) 
(* LC_PROBE187_PID = "16'b0000000010111011" *) (* LC_PROBE187_TYPE = "1" *) (* LC_PROBE187_WIDTH = "1" *) 
(* LC_PROBE188_IS_DATA = "1'b0" *) (* LC_PROBE188_IS_TRIG = "1'b0" *) (* LC_PROBE188_MU_CNT = "1" *) 
(* LC_PROBE188_PID = "16'b0000000010111100" *) (* LC_PROBE188_TYPE = "1" *) (* LC_PROBE188_WIDTH = "1" *) 
(* LC_PROBE189_IS_DATA = "1'b0" *) (* LC_PROBE189_IS_TRIG = "1'b0" *) (* LC_PROBE189_MU_CNT = "1" *) 
(* LC_PROBE189_PID = "16'b0000000010111101" *) (* LC_PROBE189_TYPE = "1" *) (* LC_PROBE189_WIDTH = "1" *) 
(* LC_PROBE18_IS_DATA = "1'b0" *) (* LC_PROBE18_IS_TRIG = "1'b0" *) (* LC_PROBE18_MU_CNT = "1" *) 
(* LC_PROBE18_PID = "16'b0000000000010010" *) (* LC_PROBE18_TYPE = "1" *) (* LC_PROBE18_WIDTH = "1" *) 
(* LC_PROBE190_IS_DATA = "1'b0" *) (* LC_PROBE190_IS_TRIG = "1'b0" *) (* LC_PROBE190_MU_CNT = "1" *) 
(* LC_PROBE190_PID = "16'b0000000010111110" *) (* LC_PROBE190_TYPE = "1" *) (* LC_PROBE190_WIDTH = "1" *) 
(* LC_PROBE191_IS_DATA = "1'b0" *) (* LC_PROBE191_IS_TRIG = "1'b0" *) (* LC_PROBE191_MU_CNT = "1" *) 
(* LC_PROBE191_PID = "16'b0000000010111111" *) (* LC_PROBE191_TYPE = "1" *) (* LC_PROBE191_WIDTH = "1" *) 
(* LC_PROBE192_IS_DATA = "1'b0" *) (* LC_PROBE192_IS_TRIG = "1'b0" *) (* LC_PROBE192_MU_CNT = "1" *) 
(* LC_PROBE192_PID = "16'b0000000011000000" *) (* LC_PROBE192_TYPE = "1" *) (* LC_PROBE192_WIDTH = "1" *) 
(* LC_PROBE193_IS_DATA = "1'b0" *) (* LC_PROBE193_IS_TRIG = "1'b0" *) (* LC_PROBE193_MU_CNT = "1" *) 
(* LC_PROBE193_PID = "16'b0000000011000001" *) (* LC_PROBE193_TYPE = "1" *) (* LC_PROBE193_WIDTH = "1" *) 
(* LC_PROBE194_IS_DATA = "1'b0" *) (* LC_PROBE194_IS_TRIG = "1'b0" *) (* LC_PROBE194_MU_CNT = "1" *) 
(* LC_PROBE194_PID = "16'b0000000011000010" *) (* LC_PROBE194_TYPE = "1" *) (* LC_PROBE194_WIDTH = "1" *) 
(* LC_PROBE195_IS_DATA = "1'b0" *) (* LC_PROBE195_IS_TRIG = "1'b0" *) (* LC_PROBE195_MU_CNT = "1" *) 
(* LC_PROBE195_PID = "16'b0000000011000011" *) (* LC_PROBE195_TYPE = "1" *) (* LC_PROBE195_WIDTH = "1" *) 
(* LC_PROBE196_IS_DATA = "1'b0" *) (* LC_PROBE196_IS_TRIG = "1'b0" *) (* LC_PROBE196_MU_CNT = "1" *) 
(* LC_PROBE196_PID = "16'b0000000011000100" *) (* LC_PROBE196_TYPE = "1" *) (* LC_PROBE196_WIDTH = "1" *) 
(* LC_PROBE197_IS_DATA = "1'b0" *) (* LC_PROBE197_IS_TRIG = "1'b0" *) (* LC_PROBE197_MU_CNT = "1" *) 
(* LC_PROBE197_PID = "16'b0000000011000101" *) (* LC_PROBE197_TYPE = "1" *) (* LC_PROBE197_WIDTH = "1" *) 
(* LC_PROBE198_IS_DATA = "1'b0" *) (* LC_PROBE198_IS_TRIG = "1'b0" *) (* LC_PROBE198_MU_CNT = "1" *) 
(* LC_PROBE198_PID = "16'b0000000011000110" *) (* LC_PROBE198_TYPE = "1" *) (* LC_PROBE198_WIDTH = "1" *) 
(* LC_PROBE199_IS_DATA = "1'b0" *) (* LC_PROBE199_IS_TRIG = "1'b0" *) (* LC_PROBE199_MU_CNT = "1" *) 
(* LC_PROBE199_PID = "16'b0000000011000111" *) (* LC_PROBE199_TYPE = "1" *) (* LC_PROBE199_WIDTH = "1" *) 
(* LC_PROBE19_IS_DATA = "1'b0" *) (* LC_PROBE19_IS_TRIG = "1'b0" *) (* LC_PROBE19_MU_CNT = "1" *) 
(* LC_PROBE19_PID = "16'b0000000000010011" *) (* LC_PROBE19_TYPE = "1" *) (* LC_PROBE19_WIDTH = "1" *) 
(* LC_PROBE1_IS_DATA = "1'b1" *) (* LC_PROBE1_IS_TRIG = "4'b1111" *) (* LC_PROBE1_MU_CNT = "4" *) 
(* LC_PROBE1_PID = "64'b0000000000000001000000000000000100000000000000010000000000000001" *) (* LC_PROBE1_TYPE = "0" *) (* LC_PROBE1_WIDTH = "22" *) 
(* LC_PROBE200_IS_DATA = "1'b0" *) (* LC_PROBE200_IS_TRIG = "1'b0" *) (* LC_PROBE200_MU_CNT = "1" *) 
(* LC_PROBE200_PID = "16'b0000000011001000" *) (* LC_PROBE200_TYPE = "1" *) (* LC_PROBE200_WIDTH = "1" *) 
(* LC_PROBE201_IS_DATA = "1'b0" *) (* LC_PROBE201_IS_TRIG = "1'b0" *) (* LC_PROBE201_MU_CNT = "1" *) 
(* LC_PROBE201_PID = "16'b0000000011001001" *) (* LC_PROBE201_TYPE = "1" *) (* LC_PROBE201_WIDTH = "1" *) 
(* LC_PROBE202_IS_DATA = "1'b0" *) (* LC_PROBE202_IS_TRIG = "1'b0" *) (* LC_PROBE202_MU_CNT = "1" *) 
(* LC_PROBE202_PID = "16'b0000000011001010" *) (* LC_PROBE202_TYPE = "1" *) (* LC_PROBE202_WIDTH = "1" *) 
(* LC_PROBE203_IS_DATA = "1'b0" *) (* LC_PROBE203_IS_TRIG = "1'b0" *) (* LC_PROBE203_MU_CNT = "1" *) 
(* LC_PROBE203_PID = "16'b0000000011001011" *) (* LC_PROBE203_TYPE = "1" *) (* LC_PROBE203_WIDTH = "1" *) 
(* LC_PROBE204_IS_DATA = "1'b0" *) (* LC_PROBE204_IS_TRIG = "1'b0" *) (* LC_PROBE204_MU_CNT = "1" *) 
(* LC_PROBE204_PID = "16'b0000000011001100" *) (* LC_PROBE204_TYPE = "1" *) (* LC_PROBE204_WIDTH = "1" *) 
(* LC_PROBE205_IS_DATA = "1'b0" *) (* LC_PROBE205_IS_TRIG = "1'b0" *) (* LC_PROBE205_MU_CNT = "1" *) 
(* LC_PROBE205_PID = "16'b0000000011001101" *) (* LC_PROBE205_TYPE = "1" *) (* LC_PROBE205_WIDTH = "1" *) 
(* LC_PROBE206_IS_DATA = "1'b0" *) (* LC_PROBE206_IS_TRIG = "1'b0" *) (* LC_PROBE206_MU_CNT = "1" *) 
(* LC_PROBE206_PID = "16'b0000000011001110" *) (* LC_PROBE206_TYPE = "1" *) (* LC_PROBE206_WIDTH = "1" *) 
(* LC_PROBE207_IS_DATA = "1'b0" *) (* LC_PROBE207_IS_TRIG = "1'b0" *) (* LC_PROBE207_MU_CNT = "1" *) 
(* LC_PROBE207_PID = "16'b0000000011001111" *) (* LC_PROBE207_TYPE = "1" *) (* LC_PROBE207_WIDTH = "1" *) 
(* LC_PROBE208_IS_DATA = "1'b0" *) (* LC_PROBE208_IS_TRIG = "1'b0" *) (* LC_PROBE208_MU_CNT = "1" *) 
(* LC_PROBE208_PID = "16'b0000000011010000" *) (* LC_PROBE208_TYPE = "1" *) (* LC_PROBE208_WIDTH = "1" *) 
(* LC_PROBE209_IS_DATA = "1'b0" *) (* LC_PROBE209_IS_TRIG = "1'b0" *) (* LC_PROBE209_MU_CNT = "1" *) 
(* LC_PROBE209_PID = "16'b0000000011010001" *) (* LC_PROBE209_TYPE = "1" *) (* LC_PROBE209_WIDTH = "1" *) 
(* LC_PROBE20_IS_DATA = "1'b0" *) (* LC_PROBE20_IS_TRIG = "1'b0" *) (* LC_PROBE20_MU_CNT = "1" *) 
(* LC_PROBE20_PID = "16'b0000000000010100" *) (* LC_PROBE20_TYPE = "1" *) (* LC_PROBE20_WIDTH = "1" *) 
(* LC_PROBE210_IS_DATA = "1'b0" *) (* LC_PROBE210_IS_TRIG = "1'b0" *) (* LC_PROBE210_MU_CNT = "1" *) 
(* LC_PROBE210_PID = "16'b0000000011010010" *) (* LC_PROBE210_TYPE = "1" *) (* LC_PROBE210_WIDTH = "1" *) 
(* LC_PROBE211_IS_DATA = "1'b0" *) (* LC_PROBE211_IS_TRIG = "1'b0" *) (* LC_PROBE211_MU_CNT = "1" *) 
(* LC_PROBE211_PID = "16'b0000000011010011" *) (* LC_PROBE211_TYPE = "1" *) (* LC_PROBE211_WIDTH = "1" *) 
(* LC_PROBE212_IS_DATA = "1'b0" *) (* LC_PROBE212_IS_TRIG = "1'b0" *) (* LC_PROBE212_MU_CNT = "1" *) 
(* LC_PROBE212_PID = "16'b0000000011010100" *) (* LC_PROBE212_TYPE = "1" *) (* LC_PROBE212_WIDTH = "1" *) 
(* LC_PROBE213_IS_DATA = "1'b0" *) (* LC_PROBE213_IS_TRIG = "1'b0" *) (* LC_PROBE213_MU_CNT = "1" *) 
(* LC_PROBE213_PID = "16'b0000000011010101" *) (* LC_PROBE213_TYPE = "1" *) (* LC_PROBE213_WIDTH = "1" *) 
(* LC_PROBE214_IS_DATA = "1'b0" *) (* LC_PROBE214_IS_TRIG = "1'b0" *) (* LC_PROBE214_MU_CNT = "1" *) 
(* LC_PROBE214_PID = "16'b0000000011010110" *) (* LC_PROBE214_TYPE = "1" *) (* LC_PROBE214_WIDTH = "1" *) 
(* LC_PROBE215_IS_DATA = "1'b0" *) (* LC_PROBE215_IS_TRIG = "1'b0" *) (* LC_PROBE215_MU_CNT = "1" *) 
(* LC_PROBE215_PID = "16'b0000000011010111" *) (* LC_PROBE215_TYPE = "1" *) (* LC_PROBE215_WIDTH = "1" *) 
(* LC_PROBE216_IS_DATA = "1'b0" *) (* LC_PROBE216_IS_TRIG = "1'b0" *) (* LC_PROBE216_MU_CNT = "1" *) 
(* LC_PROBE216_PID = "16'b0000000011011000" *) (* LC_PROBE216_TYPE = "1" *) (* LC_PROBE216_WIDTH = "1" *) 
(* LC_PROBE217_IS_DATA = "1'b0" *) (* LC_PROBE217_IS_TRIG = "1'b0" *) (* LC_PROBE217_MU_CNT = "1" *) 
(* LC_PROBE217_PID = "16'b0000000011011001" *) (* LC_PROBE217_TYPE = "1" *) (* LC_PROBE217_WIDTH = "1" *) 
(* LC_PROBE218_IS_DATA = "1'b0" *) (* LC_PROBE218_IS_TRIG = "1'b0" *) (* LC_PROBE218_MU_CNT = "1" *) 
(* LC_PROBE218_PID = "16'b0000000011011010" *) (* LC_PROBE218_TYPE = "1" *) (* LC_PROBE218_WIDTH = "1" *) 
(* LC_PROBE219_IS_DATA = "1'b0" *) (* LC_PROBE219_IS_TRIG = "1'b0" *) (* LC_PROBE219_MU_CNT = "1" *) 
(* LC_PROBE219_PID = "16'b0000000011011011" *) (* LC_PROBE219_TYPE = "1" *) (* LC_PROBE219_WIDTH = "1" *) 
(* LC_PROBE21_IS_DATA = "1'b0" *) (* LC_PROBE21_IS_TRIG = "1'b0" *) (* LC_PROBE21_MU_CNT = "1" *) 
(* LC_PROBE21_PID = "16'b0000000000010101" *) (* LC_PROBE21_TYPE = "1" *) (* LC_PROBE21_WIDTH = "1" *) 
(* LC_PROBE220_IS_DATA = "1'b0" *) (* LC_PROBE220_IS_TRIG = "1'b0" *) (* LC_PROBE220_MU_CNT = "1" *) 
(* LC_PROBE220_PID = "16'b0000000011011100" *) (* LC_PROBE220_TYPE = "1" *) (* LC_PROBE220_WIDTH = "1" *) 
(* LC_PROBE221_IS_DATA = "1'b0" *) (* LC_PROBE221_IS_TRIG = "1'b0" *) (* LC_PROBE221_MU_CNT = "1" *) 
(* LC_PROBE221_PID = "16'b0000000011011101" *) (* LC_PROBE221_TYPE = "1" *) (* LC_PROBE221_WIDTH = "1" *) 
(* LC_PROBE222_IS_DATA = "1'b0" *) (* LC_PROBE222_IS_TRIG = "1'b0" *) (* LC_PROBE222_MU_CNT = "1" *) 
(* LC_PROBE222_PID = "16'b0000000011011110" *) (* LC_PROBE222_TYPE = "1" *) (* LC_PROBE222_WIDTH = "1" *) 
(* LC_PROBE223_IS_DATA = "1'b0" *) (* LC_PROBE223_IS_TRIG = "1'b0" *) (* LC_PROBE223_MU_CNT = "1" *) 
(* LC_PROBE223_PID = "16'b0000000011011111" *) (* LC_PROBE223_TYPE = "1" *) (* LC_PROBE223_WIDTH = "1" *) 
(* LC_PROBE224_IS_DATA = "1'b0" *) (* LC_PROBE224_IS_TRIG = "1'b0" *) (* LC_PROBE224_MU_CNT = "1" *) 
(* LC_PROBE224_PID = "16'b0000000011100000" *) (* LC_PROBE224_TYPE = "1" *) (* LC_PROBE224_WIDTH = "1" *) 
(* LC_PROBE225_IS_DATA = "1'b0" *) (* LC_PROBE225_IS_TRIG = "1'b0" *) (* LC_PROBE225_MU_CNT = "1" *) 
(* LC_PROBE225_PID = "16'b0000000011100001" *) (* LC_PROBE225_TYPE = "1" *) (* LC_PROBE225_WIDTH = "1" *) 
(* LC_PROBE226_IS_DATA = "1'b0" *) (* LC_PROBE226_IS_TRIG = "1'b0" *) (* LC_PROBE226_MU_CNT = "1" *) 
(* LC_PROBE226_PID = "16'b0000000011100010" *) (* LC_PROBE226_TYPE = "1" *) (* LC_PROBE226_WIDTH = "1" *) 
(* LC_PROBE227_IS_DATA = "1'b0" *) (* LC_PROBE227_IS_TRIG = "1'b0" *) (* LC_PROBE227_MU_CNT = "1" *) 
(* LC_PROBE227_PID = "16'b0000000011100011" *) (* LC_PROBE227_TYPE = "1" *) (* LC_PROBE227_WIDTH = "1" *) 
(* LC_PROBE228_IS_DATA = "1'b0" *) (* LC_PROBE228_IS_TRIG = "1'b0" *) (* LC_PROBE228_MU_CNT = "1" *) 
(* LC_PROBE228_PID = "16'b0000000011100100" *) (* LC_PROBE228_TYPE = "1" *) (* LC_PROBE228_WIDTH = "1" *) 
(* LC_PROBE229_IS_DATA = "1'b0" *) (* LC_PROBE229_IS_TRIG = "1'b0" *) (* LC_PROBE229_MU_CNT = "1" *) 
(* LC_PROBE229_PID = "16'b0000000011100101" *) (* LC_PROBE229_TYPE = "1" *) (* LC_PROBE229_WIDTH = "1" *) 
(* LC_PROBE22_IS_DATA = "1'b0" *) (* LC_PROBE22_IS_TRIG = "1'b0" *) (* LC_PROBE22_MU_CNT = "1" *) 
(* LC_PROBE22_PID = "16'b0000000000010110" *) (* LC_PROBE22_TYPE = "1" *) (* LC_PROBE22_WIDTH = "1" *) 
(* LC_PROBE230_IS_DATA = "1'b0" *) (* LC_PROBE230_IS_TRIG = "1'b0" *) (* LC_PROBE230_MU_CNT = "1" *) 
(* LC_PROBE230_PID = "16'b0000000011100110" *) (* LC_PROBE230_TYPE = "1" *) (* LC_PROBE230_WIDTH = "1" *) 
(* LC_PROBE231_IS_DATA = "1'b0" *) (* LC_PROBE231_IS_TRIG = "1'b0" *) (* LC_PROBE231_MU_CNT = "1" *) 
(* LC_PROBE231_PID = "16'b0000000011100111" *) (* LC_PROBE231_TYPE = "1" *) (* LC_PROBE231_WIDTH = "1" *) 
(* LC_PROBE232_IS_DATA = "1'b0" *) (* LC_PROBE232_IS_TRIG = "1'b0" *) (* LC_PROBE232_MU_CNT = "1" *) 
(* LC_PROBE232_PID = "16'b0000000011101000" *) (* LC_PROBE232_TYPE = "1" *) (* LC_PROBE232_WIDTH = "1" *) 
(* LC_PROBE233_IS_DATA = "1'b0" *) (* LC_PROBE233_IS_TRIG = "1'b0" *) (* LC_PROBE233_MU_CNT = "1" *) 
(* LC_PROBE233_PID = "16'b0000000011101001" *) (* LC_PROBE233_TYPE = "1" *) (* LC_PROBE233_WIDTH = "1" *) 
(* LC_PROBE234_IS_DATA = "1'b0" *) (* LC_PROBE234_IS_TRIG = "1'b0" *) (* LC_PROBE234_MU_CNT = "1" *) 
(* LC_PROBE234_PID = "16'b0000000011101010" *) (* LC_PROBE234_TYPE = "1" *) (* LC_PROBE234_WIDTH = "1" *) 
(* LC_PROBE235_IS_DATA = "1'b0" *) (* LC_PROBE235_IS_TRIG = "1'b0" *) (* LC_PROBE235_MU_CNT = "1" *) 
(* LC_PROBE235_PID = "16'b0000000011101011" *) (* LC_PROBE235_TYPE = "1" *) (* LC_PROBE235_WIDTH = "1" *) 
(* LC_PROBE236_IS_DATA = "1'b0" *) (* LC_PROBE236_IS_TRIG = "1'b0" *) (* LC_PROBE236_MU_CNT = "1" *) 
(* LC_PROBE236_PID = "16'b0000000011101100" *) (* LC_PROBE236_TYPE = "1" *) (* LC_PROBE236_WIDTH = "1" *) 
(* LC_PROBE237_IS_DATA = "1'b0" *) (* LC_PROBE237_IS_TRIG = "1'b0" *) (* LC_PROBE237_MU_CNT = "1" *) 
(* LC_PROBE237_PID = "16'b0000000011101101" *) (* LC_PROBE237_TYPE = "1" *) (* LC_PROBE237_WIDTH = "1" *) 
(* LC_PROBE238_IS_DATA = "1'b0" *) (* LC_PROBE238_IS_TRIG = "1'b0" *) (* LC_PROBE238_MU_CNT = "1" *) 
(* LC_PROBE238_PID = "16'b0000000011101110" *) (* LC_PROBE238_TYPE = "1" *) (* LC_PROBE238_WIDTH = "1" *) 
(* LC_PROBE239_IS_DATA = "1'b0" *) (* LC_PROBE239_IS_TRIG = "1'b0" *) (* LC_PROBE239_MU_CNT = "1" *) 
(* LC_PROBE239_PID = "16'b0000000011101111" *) (* LC_PROBE239_TYPE = "1" *) (* LC_PROBE239_WIDTH = "1" *) 
(* LC_PROBE23_IS_DATA = "1'b0" *) (* LC_PROBE23_IS_TRIG = "1'b0" *) (* LC_PROBE23_MU_CNT = "1" *) 
(* LC_PROBE23_PID = "16'b0000000000010111" *) (* LC_PROBE23_TYPE = "1" *) (* LC_PROBE23_WIDTH = "1" *) 
(* LC_PROBE240_IS_DATA = "1'b0" *) (* LC_PROBE240_IS_TRIG = "1'b0" *) (* LC_PROBE240_MU_CNT = "1" *) 
(* LC_PROBE240_PID = "16'b0000000011110000" *) (* LC_PROBE240_TYPE = "1" *) (* LC_PROBE240_WIDTH = "1" *) 
(* LC_PROBE241_IS_DATA = "1'b0" *) (* LC_PROBE241_IS_TRIG = "1'b0" *) (* LC_PROBE241_MU_CNT = "1" *) 
(* LC_PROBE241_PID = "16'b0000000011110001" *) (* LC_PROBE241_TYPE = "1" *) (* LC_PROBE241_WIDTH = "1" *) 
(* LC_PROBE242_IS_DATA = "1'b0" *) (* LC_PROBE242_IS_TRIG = "1'b0" *) (* LC_PROBE242_MU_CNT = "1" *) 
(* LC_PROBE242_PID = "16'b0000000011110010" *) (* LC_PROBE242_TYPE = "1" *) (* LC_PROBE242_WIDTH = "1" *) 
(* LC_PROBE243_IS_DATA = "1'b0" *) (* LC_PROBE243_IS_TRIG = "1'b0" *) (* LC_PROBE243_MU_CNT = "1" *) 
(* LC_PROBE243_PID = "16'b0000000011110011" *) (* LC_PROBE243_TYPE = "1" *) (* LC_PROBE243_WIDTH = "1" *) 
(* LC_PROBE244_IS_DATA = "1'b0" *) (* LC_PROBE244_IS_TRIG = "1'b0" *) (* LC_PROBE244_MU_CNT = "1" *) 
(* LC_PROBE244_PID = "16'b0000000011110100" *) (* LC_PROBE244_TYPE = "1" *) (* LC_PROBE244_WIDTH = "1" *) 
(* LC_PROBE245_IS_DATA = "1'b0" *) (* LC_PROBE245_IS_TRIG = "1'b0" *) (* LC_PROBE245_MU_CNT = "1" *) 
(* LC_PROBE245_PID = "16'b0000000011110101" *) (* LC_PROBE245_TYPE = "1" *) (* LC_PROBE245_WIDTH = "1" *) 
(* LC_PROBE246_IS_DATA = "1'b0" *) (* LC_PROBE246_IS_TRIG = "1'b0" *) (* LC_PROBE246_MU_CNT = "1" *) 
(* LC_PROBE246_PID = "16'b0000000011110110" *) (* LC_PROBE246_TYPE = "1" *) (* LC_PROBE246_WIDTH = "1" *) 
(* LC_PROBE247_IS_DATA = "1'b0" *) (* LC_PROBE247_IS_TRIG = "1'b0" *) (* LC_PROBE247_MU_CNT = "1" *) 
(* LC_PROBE247_PID = "16'b0000000011110111" *) (* LC_PROBE247_TYPE = "1" *) (* LC_PROBE247_WIDTH = "1" *) 
(* LC_PROBE248_IS_DATA = "1'b0" *) (* LC_PROBE248_IS_TRIG = "1'b0" *) (* LC_PROBE248_MU_CNT = "1" *) 
(* LC_PROBE248_PID = "16'b0000000011111000" *) (* LC_PROBE248_TYPE = "1" *) (* LC_PROBE248_WIDTH = "1" *) 
(* LC_PROBE249_IS_DATA = "1'b0" *) (* LC_PROBE249_IS_TRIG = "1'b0" *) (* LC_PROBE249_MU_CNT = "1" *) 
(* LC_PROBE249_PID = "16'b0000000011111001" *) (* LC_PROBE249_TYPE = "1" *) (* LC_PROBE249_WIDTH = "1" *) 
(* LC_PROBE24_IS_DATA = "1'b0" *) (* LC_PROBE24_IS_TRIG = "1'b0" *) (* LC_PROBE24_MU_CNT = "1" *) 
(* LC_PROBE24_PID = "16'b0000000000011000" *) (* LC_PROBE24_TYPE = "1" *) (* LC_PROBE24_WIDTH = "1" *) 
(* LC_PROBE250_IS_DATA = "1'b0" *) (* LC_PROBE250_IS_TRIG = "1'b0" *) (* LC_PROBE250_MU_CNT = "1" *) 
(* LC_PROBE250_PID = "16'b0000000011111010" *) (* LC_PROBE250_TYPE = "1" *) (* LC_PROBE250_WIDTH = "1" *) 
(* LC_PROBE251_IS_DATA = "1'b0" *) (* LC_PROBE251_IS_TRIG = "1'b0" *) (* LC_PROBE251_MU_CNT = "1" *) 
(* LC_PROBE251_PID = "16'b0000000011111011" *) (* LC_PROBE251_TYPE = "1" *) (* LC_PROBE251_WIDTH = "1" *) 
(* LC_PROBE252_IS_DATA = "1'b0" *) (* LC_PROBE252_IS_TRIG = "1'b0" *) (* LC_PROBE252_MU_CNT = "1" *) 
(* LC_PROBE252_PID = "16'b0000000011111100" *) (* LC_PROBE252_TYPE = "1" *) (* LC_PROBE252_WIDTH = "1" *) 
(* LC_PROBE253_IS_DATA = "1'b0" *) (* LC_PROBE253_IS_TRIG = "1'b0" *) (* LC_PROBE253_MU_CNT = "1" *) 
(* LC_PROBE253_PID = "16'b0000000011111101" *) (* LC_PROBE253_TYPE = "1" *) (* LC_PROBE253_WIDTH = "1" *) 
(* LC_PROBE254_IS_DATA = "1'b0" *) (* LC_PROBE254_IS_TRIG = "1'b0" *) (* LC_PROBE254_MU_CNT = "1" *) 
(* LC_PROBE254_PID = "16'b0000000011111110" *) (* LC_PROBE254_TYPE = "1" *) (* LC_PROBE254_WIDTH = "1" *) 
(* LC_PROBE255_IS_DATA = "1'b0" *) (* LC_PROBE255_IS_TRIG = "1'b0" *) (* LC_PROBE255_MU_CNT = "1" *) 
(* LC_PROBE255_PID = "16'b0000000011111111" *) (* LC_PROBE255_TYPE = "1" *) (* LC_PROBE255_WIDTH = "1" *) 
(* LC_PROBE256_IS_DATA = "1'b0" *) (* LC_PROBE256_IS_TRIG = "1'b0" *) (* LC_PROBE256_MU_CNT = "1" *) 
(* LC_PROBE256_PID = "16'b0000000100000000" *) (* LC_PROBE256_TYPE = "1" *) (* LC_PROBE256_WIDTH = "1" *) 
(* LC_PROBE257_IS_DATA = "1'b0" *) (* LC_PROBE257_IS_TRIG = "1'b0" *) (* LC_PROBE257_MU_CNT = "1" *) 
(* LC_PROBE257_PID = "16'b0000000100000001" *) (* LC_PROBE257_TYPE = "1" *) (* LC_PROBE257_WIDTH = "1" *) 
(* LC_PROBE258_IS_DATA = "1'b0" *) (* LC_PROBE258_IS_TRIG = "1'b0" *) (* LC_PROBE258_MU_CNT = "1" *) 
(* LC_PROBE258_PID = "16'b0000000100000010" *) (* LC_PROBE258_TYPE = "1" *) (* LC_PROBE258_WIDTH = "1" *) 
(* LC_PROBE259_IS_DATA = "1'b0" *) (* LC_PROBE259_IS_TRIG = "1'b0" *) (* LC_PROBE259_MU_CNT = "1" *) 
(* LC_PROBE259_PID = "16'b0000000100000011" *) (* LC_PROBE259_TYPE = "1" *) (* LC_PROBE259_WIDTH = "1" *) 
(* LC_PROBE25_IS_DATA = "1'b0" *) (* LC_PROBE25_IS_TRIG = "1'b0" *) (* LC_PROBE25_MU_CNT = "1" *) 
(* LC_PROBE25_PID = "16'b0000000000011001" *) (* LC_PROBE25_TYPE = "1" *) (* LC_PROBE25_WIDTH = "1" *) 
(* LC_PROBE260_IS_DATA = "1'b0" *) (* LC_PROBE260_IS_TRIG = "1'b0" *) (* LC_PROBE260_MU_CNT = "1" *) 
(* LC_PROBE260_PID = "16'b0000000100000100" *) (* LC_PROBE260_TYPE = "1" *) (* LC_PROBE260_WIDTH = "1" *) 
(* LC_PROBE261_IS_DATA = "1'b0" *) (* LC_PROBE261_IS_TRIG = "1'b0" *) (* LC_PROBE261_MU_CNT = "1" *) 
(* LC_PROBE261_PID = "16'b0000000100000101" *) (* LC_PROBE261_TYPE = "1" *) (* LC_PROBE261_WIDTH = "1" *) 
(* LC_PROBE262_IS_DATA = "1'b0" *) (* LC_PROBE262_IS_TRIG = "1'b0" *) (* LC_PROBE262_MU_CNT = "1" *) 
(* LC_PROBE262_PID = "16'b0000000100000110" *) (* LC_PROBE262_TYPE = "1" *) (* LC_PROBE262_WIDTH = "1" *) 
(* LC_PROBE263_IS_DATA = "1'b0" *) (* LC_PROBE263_IS_TRIG = "1'b0" *) (* LC_PROBE263_MU_CNT = "1" *) 
(* LC_PROBE263_PID = "16'b0000000100000111" *) (* LC_PROBE263_TYPE = "1" *) (* LC_PROBE263_WIDTH = "1" *) 
(* LC_PROBE264_IS_DATA = "1'b0" *) (* LC_PROBE264_IS_TRIG = "1'b0" *) (* LC_PROBE264_MU_CNT = "1" *) 
(* LC_PROBE264_PID = "16'b0000000100001000" *) (* LC_PROBE264_TYPE = "1" *) (* LC_PROBE264_WIDTH = "1" *) 
(* LC_PROBE265_IS_DATA = "1'b0" *) (* LC_PROBE265_IS_TRIG = "1'b0" *) (* LC_PROBE265_MU_CNT = "1" *) 
(* LC_PROBE265_PID = "16'b0000000100001001" *) (* LC_PROBE265_TYPE = "1" *) (* LC_PROBE265_WIDTH = "1" *) 
(* LC_PROBE266_IS_DATA = "1'b0" *) (* LC_PROBE266_IS_TRIG = "1'b0" *) (* LC_PROBE266_MU_CNT = "1" *) 
(* LC_PROBE266_PID = "16'b0000000100001010" *) (* LC_PROBE266_TYPE = "1" *) (* LC_PROBE266_WIDTH = "1" *) 
(* LC_PROBE267_IS_DATA = "1'b0" *) (* LC_PROBE267_IS_TRIG = "1'b0" *) (* LC_PROBE267_MU_CNT = "1" *) 
(* LC_PROBE267_PID = "16'b0000000100001011" *) (* LC_PROBE267_TYPE = "1" *) (* LC_PROBE267_WIDTH = "1" *) 
(* LC_PROBE268_IS_DATA = "1'b0" *) (* LC_PROBE268_IS_TRIG = "1'b0" *) (* LC_PROBE268_MU_CNT = "1" *) 
(* LC_PROBE268_PID = "16'b0000000100001100" *) (* LC_PROBE268_TYPE = "1" *) (* LC_PROBE268_WIDTH = "1" *) 
(* LC_PROBE269_IS_DATA = "1'b0" *) (* LC_PROBE269_IS_TRIG = "1'b0" *) (* LC_PROBE269_MU_CNT = "1" *) 
(* LC_PROBE269_PID = "16'b0000000100001101" *) (* LC_PROBE269_TYPE = "1" *) (* LC_PROBE269_WIDTH = "1" *) 
(* LC_PROBE26_IS_DATA = "1'b0" *) (* LC_PROBE26_IS_TRIG = "1'b0" *) (* LC_PROBE26_MU_CNT = "1" *) 
(* LC_PROBE26_PID = "16'b0000000000011010" *) (* LC_PROBE26_TYPE = "1" *) (* LC_PROBE26_WIDTH = "1" *) 
(* LC_PROBE270_IS_DATA = "1'b0" *) (* LC_PROBE270_IS_TRIG = "1'b0" *) (* LC_PROBE270_MU_CNT = "1" *) 
(* LC_PROBE270_PID = "16'b0000000100001110" *) (* LC_PROBE270_TYPE = "1" *) (* LC_PROBE270_WIDTH = "1" *) 
(* LC_PROBE271_IS_DATA = "1'b0" *) (* LC_PROBE271_IS_TRIG = "1'b0" *) (* LC_PROBE271_MU_CNT = "1" *) 
(* LC_PROBE271_PID = "16'b0000000100001111" *) (* LC_PROBE271_TYPE = "1" *) (* LC_PROBE271_WIDTH = "1" *) 
(* LC_PROBE272_IS_DATA = "1'b0" *) (* LC_PROBE272_IS_TRIG = "1'b0" *) (* LC_PROBE272_MU_CNT = "1" *) 
(* LC_PROBE272_PID = "16'b0000000100010000" *) (* LC_PROBE272_TYPE = "1" *) (* LC_PROBE272_WIDTH = "1" *) 
(* LC_PROBE273_IS_DATA = "1'b0" *) (* LC_PROBE273_IS_TRIG = "1'b0" *) (* LC_PROBE273_MU_CNT = "1" *) 
(* LC_PROBE273_PID = "16'b0000000100010001" *) (* LC_PROBE273_TYPE = "1" *) (* LC_PROBE273_WIDTH = "1" *) 
(* LC_PROBE274_IS_DATA = "1'b0" *) (* LC_PROBE274_IS_TRIG = "1'b0" *) (* LC_PROBE274_MU_CNT = "1" *) 
(* LC_PROBE274_PID = "16'b0000000100010010" *) (* LC_PROBE274_TYPE = "1" *) (* LC_PROBE274_WIDTH = "1" *) 
(* LC_PROBE275_IS_DATA = "1'b0" *) (* LC_PROBE275_IS_TRIG = "1'b0" *) (* LC_PROBE275_MU_CNT = "1" *) 
(* LC_PROBE275_PID = "16'b0000000100010011" *) (* LC_PROBE275_TYPE = "1" *) (* LC_PROBE275_WIDTH = "1" *) 
(* LC_PROBE276_IS_DATA = "1'b0" *) (* LC_PROBE276_IS_TRIG = "1'b0" *) (* LC_PROBE276_MU_CNT = "1" *) 
(* LC_PROBE276_PID = "16'b0000000100010100" *) (* LC_PROBE276_TYPE = "1" *) (* LC_PROBE276_WIDTH = "1" *) 
(* LC_PROBE277_IS_DATA = "1'b0" *) (* LC_PROBE277_IS_TRIG = "1'b0" *) (* LC_PROBE277_MU_CNT = "1" *) 
(* LC_PROBE277_PID = "16'b0000000100010101" *) (* LC_PROBE277_TYPE = "1" *) (* LC_PROBE277_WIDTH = "1" *) 
(* LC_PROBE278_IS_DATA = "1'b0" *) (* LC_PROBE278_IS_TRIG = "1'b0" *) (* LC_PROBE278_MU_CNT = "1" *) 
(* LC_PROBE278_PID = "16'b0000000100010110" *) (* LC_PROBE278_TYPE = "1" *) (* LC_PROBE278_WIDTH = "1" *) 
(* LC_PROBE279_IS_DATA = "1'b0" *) (* LC_PROBE279_IS_TRIG = "1'b0" *) (* LC_PROBE279_MU_CNT = "1" *) 
(* LC_PROBE279_PID = "16'b0000000100010111" *) (* LC_PROBE279_TYPE = "1" *) (* LC_PROBE279_WIDTH = "1" *) 
(* LC_PROBE27_IS_DATA = "1'b0" *) (* LC_PROBE27_IS_TRIG = "1'b0" *) (* LC_PROBE27_MU_CNT = "1" *) 
(* LC_PROBE27_PID = "16'b0000000000011011" *) (* LC_PROBE27_TYPE = "1" *) (* LC_PROBE27_WIDTH = "1" *) 
(* LC_PROBE280_IS_DATA = "1'b0" *) (* LC_PROBE280_IS_TRIG = "1'b0" *) (* LC_PROBE280_MU_CNT = "1" *) 
(* LC_PROBE280_PID = "16'b0000000100011000" *) (* LC_PROBE280_TYPE = "1" *) (* LC_PROBE280_WIDTH = "1" *) 
(* LC_PROBE281_IS_DATA = "1'b0" *) (* LC_PROBE281_IS_TRIG = "1'b0" *) (* LC_PROBE281_MU_CNT = "1" *) 
(* LC_PROBE281_PID = "16'b0000000100011001" *) (* LC_PROBE281_TYPE = "1" *) (* LC_PROBE281_WIDTH = "1" *) 
(* LC_PROBE282_IS_DATA = "1'b0" *) (* LC_PROBE282_IS_TRIG = "1'b0" *) (* LC_PROBE282_MU_CNT = "1" *) 
(* LC_PROBE282_PID = "16'b0000000100011010" *) (* LC_PROBE282_TYPE = "1" *) (* LC_PROBE282_WIDTH = "1" *) 
(* LC_PROBE283_IS_DATA = "1'b0" *) (* LC_PROBE283_IS_TRIG = "1'b0" *) (* LC_PROBE283_MU_CNT = "1" *) 
(* LC_PROBE283_PID = "16'b0000000100011011" *) (* LC_PROBE283_TYPE = "1" *) (* LC_PROBE283_WIDTH = "1" *) 
(* LC_PROBE284_IS_DATA = "1'b0" *) (* LC_PROBE284_IS_TRIG = "1'b0" *) (* LC_PROBE284_MU_CNT = "1" *) 
(* LC_PROBE284_PID = "16'b0000000100011100" *) (* LC_PROBE284_TYPE = "1" *) (* LC_PROBE284_WIDTH = "1" *) 
(* LC_PROBE285_IS_DATA = "1'b0" *) (* LC_PROBE285_IS_TRIG = "1'b0" *) (* LC_PROBE285_MU_CNT = "1" *) 
(* LC_PROBE285_PID = "16'b0000000100011101" *) (* LC_PROBE285_TYPE = "1" *) (* LC_PROBE285_WIDTH = "1" *) 
(* LC_PROBE286_IS_DATA = "1'b0" *) (* LC_PROBE286_IS_TRIG = "1'b0" *) (* LC_PROBE286_MU_CNT = "1" *) 
(* LC_PROBE286_PID = "16'b0000000100011110" *) (* LC_PROBE286_TYPE = "1" *) (* LC_PROBE286_WIDTH = "1" *) 
(* LC_PROBE287_IS_DATA = "1'b0" *) (* LC_PROBE287_IS_TRIG = "1'b0" *) (* LC_PROBE287_MU_CNT = "1" *) 
(* LC_PROBE287_PID = "16'b0000000100011111" *) (* LC_PROBE287_TYPE = "1" *) (* LC_PROBE287_WIDTH = "1" *) 
(* LC_PROBE288_IS_DATA = "1'b0" *) (* LC_PROBE288_IS_TRIG = "1'b0" *) (* LC_PROBE288_MU_CNT = "1" *) 
(* LC_PROBE288_PID = "16'b0000000100100000" *) (* LC_PROBE288_TYPE = "1" *) (* LC_PROBE288_WIDTH = "1" *) 
(* LC_PROBE289_IS_DATA = "1'b0" *) (* LC_PROBE289_IS_TRIG = "1'b0" *) (* LC_PROBE289_MU_CNT = "1" *) 
(* LC_PROBE289_PID = "16'b0000000100100001" *) (* LC_PROBE289_TYPE = "1" *) (* LC_PROBE289_WIDTH = "1" *) 
(* LC_PROBE28_IS_DATA = "1'b0" *) (* LC_PROBE28_IS_TRIG = "1'b0" *) (* LC_PROBE28_MU_CNT = "1" *) 
(* LC_PROBE28_PID = "16'b0000000000011100" *) (* LC_PROBE28_TYPE = "1" *) (* LC_PROBE28_WIDTH = "1" *) 
(* LC_PROBE290_IS_DATA = "1'b0" *) (* LC_PROBE290_IS_TRIG = "1'b0" *) (* LC_PROBE290_MU_CNT = "1" *) 
(* LC_PROBE290_PID = "16'b0000000100100010" *) (* LC_PROBE290_TYPE = "1" *) (* LC_PROBE290_WIDTH = "1" *) 
(* LC_PROBE291_IS_DATA = "1'b0" *) (* LC_PROBE291_IS_TRIG = "1'b0" *) (* LC_PROBE291_MU_CNT = "1" *) 
(* LC_PROBE291_PID = "16'b0000000100100011" *) (* LC_PROBE291_TYPE = "1" *) (* LC_PROBE291_WIDTH = "1" *) 
(* LC_PROBE292_IS_DATA = "1'b0" *) (* LC_PROBE292_IS_TRIG = "1'b0" *) (* LC_PROBE292_MU_CNT = "1" *) 
(* LC_PROBE292_PID = "16'b0000000100100100" *) (* LC_PROBE292_TYPE = "1" *) (* LC_PROBE292_WIDTH = "1" *) 
(* LC_PROBE293_IS_DATA = "1'b0" *) (* LC_PROBE293_IS_TRIG = "1'b0" *) (* LC_PROBE293_MU_CNT = "1" *) 
(* LC_PROBE293_PID = "16'b0000000100100101" *) (* LC_PROBE293_TYPE = "1" *) (* LC_PROBE293_WIDTH = "1" *) 
(* LC_PROBE294_IS_DATA = "1'b0" *) (* LC_PROBE294_IS_TRIG = "1'b0" *) (* LC_PROBE294_MU_CNT = "1" *) 
(* LC_PROBE294_PID = "16'b0000000100100110" *) (* LC_PROBE294_TYPE = "1" *) (* LC_PROBE294_WIDTH = "1" *) 
(* LC_PROBE295_IS_DATA = "1'b0" *) (* LC_PROBE295_IS_TRIG = "1'b0" *) (* LC_PROBE295_MU_CNT = "1" *) 
(* LC_PROBE295_PID = "16'b0000000100100111" *) (* LC_PROBE295_TYPE = "1" *) (* LC_PROBE295_WIDTH = "1" *) 
(* LC_PROBE296_IS_DATA = "1'b0" *) (* LC_PROBE296_IS_TRIG = "1'b0" *) (* LC_PROBE296_MU_CNT = "1" *) 
(* LC_PROBE296_PID = "16'b0000000100101000" *) (* LC_PROBE296_TYPE = "1" *) (* LC_PROBE296_WIDTH = "1" *) 
(* LC_PROBE297_IS_DATA = "1'b0" *) (* LC_PROBE297_IS_TRIG = "1'b0" *) (* LC_PROBE297_MU_CNT = "1" *) 
(* LC_PROBE297_PID = "16'b0000000100101001" *) (* LC_PROBE297_TYPE = "1" *) (* LC_PROBE297_WIDTH = "1" *) 
(* LC_PROBE298_IS_DATA = "1'b0" *) (* LC_PROBE298_IS_TRIG = "1'b0" *) (* LC_PROBE298_MU_CNT = "1" *) 
(* LC_PROBE298_PID = "16'b0000000100101010" *) (* LC_PROBE298_TYPE = "1" *) (* LC_PROBE298_WIDTH = "1" *) 
(* LC_PROBE299_IS_DATA = "1'b0" *) (* LC_PROBE299_IS_TRIG = "1'b0" *) (* LC_PROBE299_MU_CNT = "1" *) 
(* LC_PROBE299_PID = "16'b0000000100101011" *) (* LC_PROBE299_TYPE = "1" *) (* LC_PROBE299_WIDTH = "1" *) 
(* LC_PROBE29_IS_DATA = "1'b0" *) (* LC_PROBE29_IS_TRIG = "1'b0" *) (* LC_PROBE29_MU_CNT = "1" *) 
(* LC_PROBE29_PID = "16'b0000000000011101" *) (* LC_PROBE29_TYPE = "1" *) (* LC_PROBE29_WIDTH = "1" *) 
(* LC_PROBE2_IS_DATA = "1'b1" *) (* LC_PROBE2_IS_TRIG = "4'b1111" *) (* LC_PROBE2_MU_CNT = "4" *) 
(* LC_PROBE2_PID = "64'b0000000000000010000000000000001000000000000000100000000000000010" *) (* LC_PROBE2_TYPE = "0" *) (* LC_PROBE2_WIDTH = "22" *) 
(* LC_PROBE300_IS_DATA = "1'b0" *) (* LC_PROBE300_IS_TRIG = "1'b0" *) (* LC_PROBE300_MU_CNT = "1" *) 
(* LC_PROBE300_PID = "16'b0000000100101100" *) (* LC_PROBE300_TYPE = "1" *) (* LC_PROBE300_WIDTH = "1" *) 
(* LC_PROBE301_IS_DATA = "1'b0" *) (* LC_PROBE301_IS_TRIG = "1'b0" *) (* LC_PROBE301_MU_CNT = "1" *) 
(* LC_PROBE301_PID = "16'b0000000100101101" *) (* LC_PROBE301_TYPE = "1" *) (* LC_PROBE301_WIDTH = "1" *) 
(* LC_PROBE302_IS_DATA = "1'b0" *) (* LC_PROBE302_IS_TRIG = "1'b0" *) (* LC_PROBE302_MU_CNT = "1" *) 
(* LC_PROBE302_PID = "16'b0000000100101110" *) (* LC_PROBE302_TYPE = "1" *) (* LC_PROBE302_WIDTH = "1" *) 
(* LC_PROBE303_IS_DATA = "1'b0" *) (* LC_PROBE303_IS_TRIG = "1'b0" *) (* LC_PROBE303_MU_CNT = "1" *) 
(* LC_PROBE303_PID = "16'b0000000100101111" *) (* LC_PROBE303_TYPE = "1" *) (* LC_PROBE303_WIDTH = "1" *) 
(* LC_PROBE304_IS_DATA = "1'b0" *) (* LC_PROBE304_IS_TRIG = "1'b0" *) (* LC_PROBE304_MU_CNT = "1" *) 
(* LC_PROBE304_PID = "16'b0000000100110000" *) (* LC_PROBE304_TYPE = "1" *) (* LC_PROBE304_WIDTH = "1" *) 
(* LC_PROBE305_IS_DATA = "1'b0" *) (* LC_PROBE305_IS_TRIG = "1'b0" *) (* LC_PROBE305_MU_CNT = "1" *) 
(* LC_PROBE305_PID = "16'b0000000100110001" *) (* LC_PROBE305_TYPE = "1" *) (* LC_PROBE305_WIDTH = "1" *) 
(* LC_PROBE306_IS_DATA = "1'b0" *) (* LC_PROBE306_IS_TRIG = "1'b0" *) (* LC_PROBE306_MU_CNT = "1" *) 
(* LC_PROBE306_PID = "16'b0000000100110010" *) (* LC_PROBE306_TYPE = "1" *) (* LC_PROBE306_WIDTH = "1" *) 
(* LC_PROBE307_IS_DATA = "1'b0" *) (* LC_PROBE307_IS_TRIG = "1'b0" *) (* LC_PROBE307_MU_CNT = "1" *) 
(* LC_PROBE307_PID = "16'b0000000100110011" *) (* LC_PROBE307_TYPE = "1" *) (* LC_PROBE307_WIDTH = "1" *) 
(* LC_PROBE308_IS_DATA = "1'b0" *) (* LC_PROBE308_IS_TRIG = "1'b0" *) (* LC_PROBE308_MU_CNT = "1" *) 
(* LC_PROBE308_PID = "16'b0000000100110100" *) (* LC_PROBE308_TYPE = "1" *) (* LC_PROBE308_WIDTH = "1" *) 
(* LC_PROBE309_IS_DATA = "1'b0" *) (* LC_PROBE309_IS_TRIG = "1'b0" *) (* LC_PROBE309_MU_CNT = "1" *) 
(* LC_PROBE309_PID = "16'b0000000100110101" *) (* LC_PROBE309_TYPE = "1" *) (* LC_PROBE309_WIDTH = "1" *) 
(* LC_PROBE30_IS_DATA = "1'b0" *) (* LC_PROBE30_IS_TRIG = "1'b0" *) (* LC_PROBE30_MU_CNT = "1" *) 
(* LC_PROBE30_PID = "16'b0000000000011110" *) (* LC_PROBE30_TYPE = "1" *) (* LC_PROBE30_WIDTH = "1" *) 
(* LC_PROBE310_IS_DATA = "1'b0" *) (* LC_PROBE310_IS_TRIG = "1'b0" *) (* LC_PROBE310_MU_CNT = "1" *) 
(* LC_PROBE310_PID = "16'b0000000100110110" *) (* LC_PROBE310_TYPE = "1" *) (* LC_PROBE310_WIDTH = "1" *) 
(* LC_PROBE311_IS_DATA = "1'b0" *) (* LC_PROBE311_IS_TRIG = "1'b0" *) (* LC_PROBE311_MU_CNT = "1" *) 
(* LC_PROBE311_PID = "16'b0000000100110111" *) (* LC_PROBE311_TYPE = "1" *) (* LC_PROBE311_WIDTH = "1" *) 
(* LC_PROBE312_IS_DATA = "1'b0" *) (* LC_PROBE312_IS_TRIG = "1'b0" *) (* LC_PROBE312_MU_CNT = "1" *) 
(* LC_PROBE312_PID = "16'b0000000100111000" *) (* LC_PROBE312_TYPE = "1" *) (* LC_PROBE312_WIDTH = "1" *) 
(* LC_PROBE313_IS_DATA = "1'b0" *) (* LC_PROBE313_IS_TRIG = "1'b0" *) (* LC_PROBE313_MU_CNT = "1" *) 
(* LC_PROBE313_PID = "16'b0000000100111001" *) (* LC_PROBE313_TYPE = "1" *) (* LC_PROBE313_WIDTH = "1" *) 
(* LC_PROBE314_IS_DATA = "1'b0" *) (* LC_PROBE314_IS_TRIG = "1'b0" *) (* LC_PROBE314_MU_CNT = "1" *) 
(* LC_PROBE314_PID = "16'b0000000100111010" *) (* LC_PROBE314_TYPE = "1" *) (* LC_PROBE314_WIDTH = "1" *) 
(* LC_PROBE315_IS_DATA = "1'b0" *) (* LC_PROBE315_IS_TRIG = "1'b0" *) (* LC_PROBE315_MU_CNT = "1" *) 
(* LC_PROBE315_PID = "16'b0000000100111011" *) (* LC_PROBE315_TYPE = "1" *) (* LC_PROBE315_WIDTH = "1" *) 
(* LC_PROBE316_IS_DATA = "1'b0" *) (* LC_PROBE316_IS_TRIG = "1'b0" *) (* LC_PROBE316_MU_CNT = "1" *) 
(* LC_PROBE316_PID = "16'b0000000100111100" *) (* LC_PROBE316_TYPE = "1" *) (* LC_PROBE316_WIDTH = "1" *) 
(* LC_PROBE317_IS_DATA = "1'b0" *) (* LC_PROBE317_IS_TRIG = "1'b0" *) (* LC_PROBE317_MU_CNT = "1" *) 
(* LC_PROBE317_PID = "16'b0000000100111101" *) (* LC_PROBE317_TYPE = "1" *) (* LC_PROBE317_WIDTH = "1" *) 
(* LC_PROBE318_IS_DATA = "1'b0" *) (* LC_PROBE318_IS_TRIG = "1'b0" *) (* LC_PROBE318_MU_CNT = "1" *) 
(* LC_PROBE318_PID = "16'b0000000100111110" *) (* LC_PROBE318_TYPE = "1" *) (* LC_PROBE318_WIDTH = "1" *) 
(* LC_PROBE319_IS_DATA = "1'b0" *) (* LC_PROBE319_IS_TRIG = "1'b0" *) (* LC_PROBE319_MU_CNT = "1" *) 
(* LC_PROBE319_PID = "16'b0000000100111111" *) (* LC_PROBE319_TYPE = "1" *) (* LC_PROBE319_WIDTH = "1" *) 
(* LC_PROBE31_IS_DATA = "1'b0" *) (* LC_PROBE31_IS_TRIG = "1'b0" *) (* LC_PROBE31_MU_CNT = "1" *) 
(* LC_PROBE31_PID = "16'b0000000000011111" *) (* LC_PROBE31_TYPE = "1" *) (* LC_PROBE31_WIDTH = "1" *) 
(* LC_PROBE320_IS_DATA = "1'b0" *) (* LC_PROBE320_IS_TRIG = "1'b0" *) (* LC_PROBE320_MU_CNT = "1" *) 
(* LC_PROBE320_PID = "16'b0000000101000000" *) (* LC_PROBE320_TYPE = "1" *) (* LC_PROBE320_WIDTH = "1" *) 
(* LC_PROBE321_IS_DATA = "1'b0" *) (* LC_PROBE321_IS_TRIG = "1'b0" *) (* LC_PROBE321_MU_CNT = "1" *) 
(* LC_PROBE321_PID = "16'b0000000101000001" *) (* LC_PROBE321_TYPE = "1" *) (* LC_PROBE321_WIDTH = "1" *) 
(* LC_PROBE322_IS_DATA = "1'b0" *) (* LC_PROBE322_IS_TRIG = "1'b0" *) (* LC_PROBE322_MU_CNT = "1" *) 
(* LC_PROBE322_PID = "16'b0000000101000010" *) (* LC_PROBE322_TYPE = "1" *) (* LC_PROBE322_WIDTH = "1" *) 
(* LC_PROBE323_IS_DATA = "1'b0" *) (* LC_PROBE323_IS_TRIG = "1'b0" *) (* LC_PROBE323_MU_CNT = "1" *) 
(* LC_PROBE323_PID = "16'b0000000101000011" *) (* LC_PROBE323_TYPE = "1" *) (* LC_PROBE323_WIDTH = "1" *) 
(* LC_PROBE324_IS_DATA = "1'b0" *) (* LC_PROBE324_IS_TRIG = "1'b0" *) (* LC_PROBE324_MU_CNT = "1" *) 
(* LC_PROBE324_PID = "16'b0000000101000100" *) (* LC_PROBE324_TYPE = "1" *) (* LC_PROBE324_WIDTH = "1" *) 
(* LC_PROBE325_IS_DATA = "1'b0" *) (* LC_PROBE325_IS_TRIG = "1'b0" *) (* LC_PROBE325_MU_CNT = "1" *) 
(* LC_PROBE325_PID = "16'b0000000101000101" *) (* LC_PROBE325_TYPE = "1" *) (* LC_PROBE325_WIDTH = "1" *) 
(* LC_PROBE326_IS_DATA = "1'b0" *) (* LC_PROBE326_IS_TRIG = "1'b0" *) (* LC_PROBE326_MU_CNT = "1" *) 
(* LC_PROBE326_PID = "16'b0000000101000110" *) (* LC_PROBE326_TYPE = "1" *) (* LC_PROBE326_WIDTH = "1" *) 
(* LC_PROBE327_IS_DATA = "1'b0" *) (* LC_PROBE327_IS_TRIG = "1'b0" *) (* LC_PROBE327_MU_CNT = "1" *) 
(* LC_PROBE327_PID = "16'b0000000101000111" *) (* LC_PROBE327_TYPE = "1" *) (* LC_PROBE327_WIDTH = "1" *) 
(* LC_PROBE328_IS_DATA = "1'b0" *) (* LC_PROBE328_IS_TRIG = "1'b0" *) (* LC_PROBE328_MU_CNT = "1" *) 
(* LC_PROBE328_PID = "16'b0000000101001000" *) (* LC_PROBE328_TYPE = "1" *) (* LC_PROBE328_WIDTH = "1" *) 
(* LC_PROBE329_IS_DATA = "1'b0" *) (* LC_PROBE329_IS_TRIG = "1'b0" *) (* LC_PROBE329_MU_CNT = "1" *) 
(* LC_PROBE329_PID = "16'b0000000101001001" *) (* LC_PROBE329_TYPE = "1" *) (* LC_PROBE329_WIDTH = "1" *) 
(* LC_PROBE32_IS_DATA = "1'b0" *) (* LC_PROBE32_IS_TRIG = "1'b0" *) (* LC_PROBE32_MU_CNT = "1" *) 
(* LC_PROBE32_PID = "16'b0000000000100000" *) (* LC_PROBE32_TYPE = "1" *) (* LC_PROBE32_WIDTH = "1" *) 
(* LC_PROBE330_IS_DATA = "1'b0" *) (* LC_PROBE330_IS_TRIG = "1'b0" *) (* LC_PROBE330_MU_CNT = "1" *) 
(* LC_PROBE330_PID = "16'b0000000101001010" *) (* LC_PROBE330_TYPE = "1" *) (* LC_PROBE330_WIDTH = "1" *) 
(* LC_PROBE331_IS_DATA = "1'b0" *) (* LC_PROBE331_IS_TRIG = "1'b0" *) (* LC_PROBE331_MU_CNT = "1" *) 
(* LC_PROBE331_PID = "16'b0000000101001011" *) (* LC_PROBE331_TYPE = "1" *) (* LC_PROBE331_WIDTH = "1" *) 
(* LC_PROBE332_IS_DATA = "1'b0" *) (* LC_PROBE332_IS_TRIG = "1'b0" *) (* LC_PROBE332_MU_CNT = "1" *) 
(* LC_PROBE332_PID = "16'b0000000101001100" *) (* LC_PROBE332_TYPE = "1" *) (* LC_PROBE332_WIDTH = "1" *) 
(* LC_PROBE333_IS_DATA = "1'b0" *) (* LC_PROBE333_IS_TRIG = "1'b0" *) (* LC_PROBE333_MU_CNT = "1" *) 
(* LC_PROBE333_PID = "16'b0000000101001101" *) (* LC_PROBE333_TYPE = "1" *) (* LC_PROBE333_WIDTH = "1" *) 
(* LC_PROBE334_IS_DATA = "1'b0" *) (* LC_PROBE334_IS_TRIG = "1'b0" *) (* LC_PROBE334_MU_CNT = "1" *) 
(* LC_PROBE334_PID = "16'b0000000101001110" *) (* LC_PROBE334_TYPE = "1" *) (* LC_PROBE334_WIDTH = "1" *) 
(* LC_PROBE335_IS_DATA = "1'b0" *) (* LC_PROBE335_IS_TRIG = "1'b0" *) (* LC_PROBE335_MU_CNT = "1" *) 
(* LC_PROBE335_PID = "16'b0000000101001111" *) (* LC_PROBE335_TYPE = "1" *) (* LC_PROBE335_WIDTH = "1" *) 
(* LC_PROBE336_IS_DATA = "1'b0" *) (* LC_PROBE336_IS_TRIG = "1'b0" *) (* LC_PROBE336_MU_CNT = "1" *) 
(* LC_PROBE336_PID = "16'b0000000101010000" *) (* LC_PROBE336_TYPE = "1" *) (* LC_PROBE336_WIDTH = "1" *) 
(* LC_PROBE337_IS_DATA = "1'b0" *) (* LC_PROBE337_IS_TRIG = "1'b0" *) (* LC_PROBE337_MU_CNT = "1" *) 
(* LC_PROBE337_PID = "16'b0000000101010001" *) (* LC_PROBE337_TYPE = "1" *) (* LC_PROBE337_WIDTH = "1" *) 
(* LC_PROBE338_IS_DATA = "1'b0" *) (* LC_PROBE338_IS_TRIG = "1'b0" *) (* LC_PROBE338_MU_CNT = "1" *) 
(* LC_PROBE338_PID = "16'b0000000101010010" *) (* LC_PROBE338_TYPE = "1" *) (* LC_PROBE338_WIDTH = "1" *) 
(* LC_PROBE339_IS_DATA = "1'b0" *) (* LC_PROBE339_IS_TRIG = "1'b0" *) (* LC_PROBE339_MU_CNT = "1" *) 
(* LC_PROBE339_PID = "16'b0000000101010011" *) (* LC_PROBE339_TYPE = "1" *) (* LC_PROBE339_WIDTH = "1" *) 
(* LC_PROBE33_IS_DATA = "1'b0" *) (* LC_PROBE33_IS_TRIG = "1'b0" *) (* LC_PROBE33_MU_CNT = "1" *) 
(* LC_PROBE33_PID = "16'b0000000000100001" *) (* LC_PROBE33_TYPE = "1" *) (* LC_PROBE33_WIDTH = "1" *) 
(* LC_PROBE340_IS_DATA = "1'b0" *) (* LC_PROBE340_IS_TRIG = "1'b0" *) (* LC_PROBE340_MU_CNT = "1" *) 
(* LC_PROBE340_PID = "16'b0000000101010100" *) (* LC_PROBE340_TYPE = "1" *) (* LC_PROBE340_WIDTH = "1" *) 
(* LC_PROBE341_IS_DATA = "1'b0" *) (* LC_PROBE341_IS_TRIG = "1'b0" *) (* LC_PROBE341_MU_CNT = "1" *) 
(* LC_PROBE341_PID = "16'b0000000101010101" *) (* LC_PROBE341_TYPE = "1" *) (* LC_PROBE341_WIDTH = "1" *) 
(* LC_PROBE342_IS_DATA = "1'b0" *) (* LC_PROBE342_IS_TRIG = "1'b0" *) (* LC_PROBE342_MU_CNT = "1" *) 
(* LC_PROBE342_PID = "16'b0000000101010110" *) (* LC_PROBE342_TYPE = "1" *) (* LC_PROBE342_WIDTH = "1" *) 
(* LC_PROBE343_IS_DATA = "1'b0" *) (* LC_PROBE343_IS_TRIG = "1'b0" *) (* LC_PROBE343_MU_CNT = "1" *) 
(* LC_PROBE343_PID = "16'b0000000101010111" *) (* LC_PROBE343_TYPE = "1" *) (* LC_PROBE343_WIDTH = "1" *) 
(* LC_PROBE344_IS_DATA = "1'b0" *) (* LC_PROBE344_IS_TRIG = "1'b0" *) (* LC_PROBE344_MU_CNT = "1" *) 
(* LC_PROBE344_PID = "16'b0000000101011000" *) (* LC_PROBE344_TYPE = "1" *) (* LC_PROBE344_WIDTH = "1" *) 
(* LC_PROBE345_IS_DATA = "1'b0" *) (* LC_PROBE345_IS_TRIG = "1'b0" *) (* LC_PROBE345_MU_CNT = "1" *) 
(* LC_PROBE345_PID = "16'b0000000101011001" *) (* LC_PROBE345_TYPE = "1" *) (* LC_PROBE345_WIDTH = "1" *) 
(* LC_PROBE346_IS_DATA = "1'b0" *) (* LC_PROBE346_IS_TRIG = "1'b0" *) (* LC_PROBE346_MU_CNT = "1" *) 
(* LC_PROBE346_PID = "16'b0000000101011010" *) (* LC_PROBE346_TYPE = "1" *) (* LC_PROBE346_WIDTH = "1" *) 
(* LC_PROBE347_IS_DATA = "1'b0" *) (* LC_PROBE347_IS_TRIG = "1'b0" *) (* LC_PROBE347_MU_CNT = "1" *) 
(* LC_PROBE347_PID = "16'b0000000101011011" *) (* LC_PROBE347_TYPE = "1" *) (* LC_PROBE347_WIDTH = "1" *) 
(* LC_PROBE348_IS_DATA = "1'b0" *) (* LC_PROBE348_IS_TRIG = "1'b0" *) (* LC_PROBE348_MU_CNT = "1" *) 
(* LC_PROBE348_PID = "16'b0000000101011100" *) (* LC_PROBE348_TYPE = "1" *) (* LC_PROBE348_WIDTH = "1" *) 
(* LC_PROBE349_IS_DATA = "1'b0" *) (* LC_PROBE349_IS_TRIG = "1'b0" *) (* LC_PROBE349_MU_CNT = "1" *) 
(* LC_PROBE349_PID = "16'b0000000101011101" *) (* LC_PROBE349_TYPE = "1" *) (* LC_PROBE349_WIDTH = "1" *) 
(* LC_PROBE34_IS_DATA = "1'b0" *) (* LC_PROBE34_IS_TRIG = "1'b0" *) (* LC_PROBE34_MU_CNT = "1" *) 
(* LC_PROBE34_PID = "16'b0000000000100010" *) (* LC_PROBE34_TYPE = "1" *) (* LC_PROBE34_WIDTH = "1" *) 
(* LC_PROBE350_IS_DATA = "1'b0" *) (* LC_PROBE350_IS_TRIG = "1'b0" *) (* LC_PROBE350_MU_CNT = "1" *) 
(* LC_PROBE350_PID = "16'b0000000101011110" *) (* LC_PROBE350_TYPE = "1" *) (* LC_PROBE350_WIDTH = "1" *) 
(* LC_PROBE351_IS_DATA = "1'b0" *) (* LC_PROBE351_IS_TRIG = "1'b0" *) (* LC_PROBE351_MU_CNT = "1" *) 
(* LC_PROBE351_PID = "16'b0000000101011111" *) (* LC_PROBE351_TYPE = "1" *) (* LC_PROBE351_WIDTH = "1" *) 
(* LC_PROBE352_IS_DATA = "1'b0" *) (* LC_PROBE352_IS_TRIG = "1'b0" *) (* LC_PROBE352_MU_CNT = "1" *) 
(* LC_PROBE352_PID = "16'b0000000101100000" *) (* LC_PROBE352_TYPE = "1" *) (* LC_PROBE352_WIDTH = "1" *) 
(* LC_PROBE353_IS_DATA = "1'b0" *) (* LC_PROBE353_IS_TRIG = "1'b0" *) (* LC_PROBE353_MU_CNT = "1" *) 
(* LC_PROBE353_PID = "16'b0000000101100001" *) (* LC_PROBE353_TYPE = "1" *) (* LC_PROBE353_WIDTH = "1" *) 
(* LC_PROBE354_IS_DATA = "1'b0" *) (* LC_PROBE354_IS_TRIG = "1'b0" *) (* LC_PROBE354_MU_CNT = "1" *) 
(* LC_PROBE354_PID = "16'b0000000101100010" *) (* LC_PROBE354_TYPE = "1" *) (* LC_PROBE354_WIDTH = "1" *) 
(* LC_PROBE355_IS_DATA = "1'b0" *) (* LC_PROBE355_IS_TRIG = "1'b0" *) (* LC_PROBE355_MU_CNT = "1" *) 
(* LC_PROBE355_PID = "16'b0000000101100011" *) (* LC_PROBE355_TYPE = "1" *) (* LC_PROBE355_WIDTH = "1" *) 
(* LC_PROBE356_IS_DATA = "1'b0" *) (* LC_PROBE356_IS_TRIG = "1'b0" *) (* LC_PROBE356_MU_CNT = "1" *) 
(* LC_PROBE356_PID = "16'b0000000101100100" *) (* LC_PROBE356_TYPE = "1" *) (* LC_PROBE356_WIDTH = "1" *) 
(* LC_PROBE357_IS_DATA = "1'b0" *) (* LC_PROBE357_IS_TRIG = "1'b0" *) (* LC_PROBE357_MU_CNT = "1" *) 
(* LC_PROBE357_PID = "16'b0000000101100101" *) (* LC_PROBE357_TYPE = "1" *) (* LC_PROBE357_WIDTH = "1" *) 
(* LC_PROBE358_IS_DATA = "1'b0" *) (* LC_PROBE358_IS_TRIG = "1'b0" *) (* LC_PROBE358_MU_CNT = "1" *) 
(* LC_PROBE358_PID = "16'b0000000101100110" *) (* LC_PROBE358_TYPE = "1" *) (* LC_PROBE358_WIDTH = "1" *) 
(* LC_PROBE359_IS_DATA = "1'b0" *) (* LC_PROBE359_IS_TRIG = "1'b0" *) (* LC_PROBE359_MU_CNT = "1" *) 
(* LC_PROBE359_PID = "16'b0000000101100111" *) (* LC_PROBE359_TYPE = "1" *) (* LC_PROBE359_WIDTH = "1" *) 
(* LC_PROBE35_IS_DATA = "1'b0" *) (* LC_PROBE35_IS_TRIG = "1'b0" *) (* LC_PROBE35_MU_CNT = "1" *) 
(* LC_PROBE35_PID = "16'b0000000000100011" *) (* LC_PROBE35_TYPE = "1" *) (* LC_PROBE35_WIDTH = "1" *) 
(* LC_PROBE360_IS_DATA = "1'b0" *) (* LC_PROBE360_IS_TRIG = "1'b0" *) (* LC_PROBE360_MU_CNT = "1" *) 
(* LC_PROBE360_PID = "16'b0000000101101000" *) (* LC_PROBE360_TYPE = "1" *) (* LC_PROBE360_WIDTH = "1" *) 
(* LC_PROBE361_IS_DATA = "1'b0" *) (* LC_PROBE361_IS_TRIG = "1'b0" *) (* LC_PROBE361_MU_CNT = "1" *) 
(* LC_PROBE361_PID = "16'b0000000101101001" *) (* LC_PROBE361_TYPE = "1" *) (* LC_PROBE361_WIDTH = "1" *) 
(* LC_PROBE362_IS_DATA = "1'b0" *) (* LC_PROBE362_IS_TRIG = "1'b0" *) (* LC_PROBE362_MU_CNT = "1" *) 
(* LC_PROBE362_PID = "16'b0000000101101010" *) (* LC_PROBE362_TYPE = "1" *) (* LC_PROBE362_WIDTH = "1" *) 
(* LC_PROBE363_IS_DATA = "1'b0" *) (* LC_PROBE363_IS_TRIG = "1'b0" *) (* LC_PROBE363_MU_CNT = "1" *) 
(* LC_PROBE363_PID = "16'b0000000101101011" *) (* LC_PROBE363_TYPE = "1" *) (* LC_PROBE363_WIDTH = "1" *) 
(* LC_PROBE364_IS_DATA = "1'b0" *) (* LC_PROBE364_IS_TRIG = "1'b0" *) (* LC_PROBE364_MU_CNT = "1" *) 
(* LC_PROBE364_PID = "16'b0000000101101100" *) (* LC_PROBE364_TYPE = "1" *) (* LC_PROBE364_WIDTH = "1" *) 
(* LC_PROBE365_IS_DATA = "1'b0" *) (* LC_PROBE365_IS_TRIG = "1'b0" *) (* LC_PROBE365_MU_CNT = "1" *) 
(* LC_PROBE365_PID = "16'b0000000101101101" *) (* LC_PROBE365_TYPE = "1" *) (* LC_PROBE365_WIDTH = "1" *) 
(* LC_PROBE366_IS_DATA = "1'b0" *) (* LC_PROBE366_IS_TRIG = "1'b0" *) (* LC_PROBE366_MU_CNT = "1" *) 
(* LC_PROBE366_PID = "16'b0000000101101110" *) (* LC_PROBE366_TYPE = "1" *) (* LC_PROBE366_WIDTH = "1" *) 
(* LC_PROBE367_IS_DATA = "1'b0" *) (* LC_PROBE367_IS_TRIG = "1'b0" *) (* LC_PROBE367_MU_CNT = "1" *) 
(* LC_PROBE367_PID = "16'b0000000101101111" *) (* LC_PROBE367_TYPE = "1" *) (* LC_PROBE367_WIDTH = "1" *) 
(* LC_PROBE368_IS_DATA = "1'b0" *) (* LC_PROBE368_IS_TRIG = "1'b0" *) (* LC_PROBE368_MU_CNT = "1" *) 
(* LC_PROBE368_PID = "16'b0000000101110000" *) (* LC_PROBE368_TYPE = "1" *) (* LC_PROBE368_WIDTH = "1" *) 
(* LC_PROBE369_IS_DATA = "1'b0" *) (* LC_PROBE369_IS_TRIG = "1'b0" *) (* LC_PROBE369_MU_CNT = "1" *) 
(* LC_PROBE369_PID = "16'b0000000101110001" *) (* LC_PROBE369_TYPE = "1" *) (* LC_PROBE369_WIDTH = "1" *) 
(* LC_PROBE36_IS_DATA = "1'b0" *) (* LC_PROBE36_IS_TRIG = "1'b0" *) (* LC_PROBE36_MU_CNT = "1" *) 
(* LC_PROBE36_PID = "16'b0000000000100100" *) (* LC_PROBE36_TYPE = "1" *) (* LC_PROBE36_WIDTH = "1" *) 
(* LC_PROBE370_IS_DATA = "1'b0" *) (* LC_PROBE370_IS_TRIG = "1'b0" *) (* LC_PROBE370_MU_CNT = "1" *) 
(* LC_PROBE370_PID = "16'b0000000101110010" *) (* LC_PROBE370_TYPE = "1" *) (* LC_PROBE370_WIDTH = "1" *) 
(* LC_PROBE371_IS_DATA = "1'b0" *) (* LC_PROBE371_IS_TRIG = "1'b0" *) (* LC_PROBE371_MU_CNT = "1" *) 
(* LC_PROBE371_PID = "16'b0000000101110011" *) (* LC_PROBE371_TYPE = "1" *) (* LC_PROBE371_WIDTH = "1" *) 
(* LC_PROBE372_IS_DATA = "1'b0" *) (* LC_PROBE372_IS_TRIG = "1'b0" *) (* LC_PROBE372_MU_CNT = "1" *) 
(* LC_PROBE372_PID = "16'b0000000101110100" *) (* LC_PROBE372_TYPE = "1" *) (* LC_PROBE372_WIDTH = "1" *) 
(* LC_PROBE373_IS_DATA = "1'b0" *) (* LC_PROBE373_IS_TRIG = "1'b0" *) (* LC_PROBE373_MU_CNT = "1" *) 
(* LC_PROBE373_PID = "16'b0000000101110101" *) (* LC_PROBE373_TYPE = "1" *) (* LC_PROBE373_WIDTH = "1" *) 
(* LC_PROBE374_IS_DATA = "1'b0" *) (* LC_PROBE374_IS_TRIG = "1'b0" *) (* LC_PROBE374_MU_CNT = "1" *) 
(* LC_PROBE374_PID = "16'b0000000101110110" *) (* LC_PROBE374_TYPE = "1" *) (* LC_PROBE374_WIDTH = "1" *) 
(* LC_PROBE375_IS_DATA = "1'b0" *) (* LC_PROBE375_IS_TRIG = "1'b0" *) (* LC_PROBE375_MU_CNT = "1" *) 
(* LC_PROBE375_PID = "16'b0000000101110111" *) (* LC_PROBE375_TYPE = "1" *) (* LC_PROBE375_WIDTH = "1" *) 
(* LC_PROBE376_IS_DATA = "1'b0" *) (* LC_PROBE376_IS_TRIG = "1'b0" *) (* LC_PROBE376_MU_CNT = "1" *) 
(* LC_PROBE376_PID = "16'b0000000101111000" *) (* LC_PROBE376_TYPE = "1" *) (* LC_PROBE376_WIDTH = "1" *) 
(* LC_PROBE377_IS_DATA = "1'b0" *) (* LC_PROBE377_IS_TRIG = "1'b0" *) (* LC_PROBE377_MU_CNT = "1" *) 
(* LC_PROBE377_PID = "16'b0000000101111001" *) (* LC_PROBE377_TYPE = "1" *) (* LC_PROBE377_WIDTH = "1" *) 
(* LC_PROBE378_IS_DATA = "1'b0" *) (* LC_PROBE378_IS_TRIG = "1'b0" *) (* LC_PROBE378_MU_CNT = "1" *) 
(* LC_PROBE378_PID = "16'b0000000101111010" *) (* LC_PROBE378_TYPE = "1" *) (* LC_PROBE378_WIDTH = "1" *) 
(* LC_PROBE379_IS_DATA = "1'b0" *) (* LC_PROBE379_IS_TRIG = "1'b0" *) (* LC_PROBE379_MU_CNT = "1" *) 
(* LC_PROBE379_PID = "16'b0000000101111011" *) (* LC_PROBE379_TYPE = "1" *) (* LC_PROBE379_WIDTH = "1" *) 
(* LC_PROBE37_IS_DATA = "1'b0" *) (* LC_PROBE37_IS_TRIG = "1'b0" *) (* LC_PROBE37_MU_CNT = "1" *) 
(* LC_PROBE37_PID = "16'b0000000000100101" *) (* LC_PROBE37_TYPE = "1" *) (* LC_PROBE37_WIDTH = "1" *) 
(* LC_PROBE380_IS_DATA = "1'b0" *) (* LC_PROBE380_IS_TRIG = "1'b0" *) (* LC_PROBE380_MU_CNT = "1" *) 
(* LC_PROBE380_PID = "16'b0000000101111100" *) (* LC_PROBE380_TYPE = "1" *) (* LC_PROBE380_WIDTH = "1" *) 
(* LC_PROBE381_IS_DATA = "1'b0" *) (* LC_PROBE381_IS_TRIG = "1'b0" *) (* LC_PROBE381_MU_CNT = "1" *) 
(* LC_PROBE381_PID = "16'b0000000101111101" *) (* LC_PROBE381_TYPE = "1" *) (* LC_PROBE381_WIDTH = "1" *) 
(* LC_PROBE382_IS_DATA = "1'b0" *) (* LC_PROBE382_IS_TRIG = "1'b0" *) (* LC_PROBE382_MU_CNT = "1" *) 
(* LC_PROBE382_PID = "16'b0000000101111110" *) (* LC_PROBE382_TYPE = "1" *) (* LC_PROBE382_WIDTH = "1" *) 
(* LC_PROBE383_IS_DATA = "1'b0" *) (* LC_PROBE383_IS_TRIG = "1'b0" *) (* LC_PROBE383_MU_CNT = "1" *) 
(* LC_PROBE383_PID = "16'b0000000101111111" *) (* LC_PROBE383_TYPE = "1" *) (* LC_PROBE383_WIDTH = "1" *) 
(* LC_PROBE384_IS_DATA = "1'b0" *) (* LC_PROBE384_IS_TRIG = "1'b0" *) (* LC_PROBE384_MU_CNT = "1" *) 
(* LC_PROBE384_PID = "16'b0000000110000000" *) (* LC_PROBE384_TYPE = "1" *) (* LC_PROBE384_WIDTH = "1" *) 
(* LC_PROBE385_IS_DATA = "1'b0" *) (* LC_PROBE385_IS_TRIG = "1'b0" *) (* LC_PROBE385_MU_CNT = "1" *) 
(* LC_PROBE385_PID = "16'b0000000110000001" *) (* LC_PROBE385_TYPE = "1" *) (* LC_PROBE385_WIDTH = "1" *) 
(* LC_PROBE386_IS_DATA = "1'b0" *) (* LC_PROBE386_IS_TRIG = "1'b0" *) (* LC_PROBE386_MU_CNT = "1" *) 
(* LC_PROBE386_PID = "16'b0000000110000010" *) (* LC_PROBE386_TYPE = "1" *) (* LC_PROBE386_WIDTH = "1" *) 
(* LC_PROBE387_IS_DATA = "1'b0" *) (* LC_PROBE387_IS_TRIG = "1'b0" *) (* LC_PROBE387_MU_CNT = "1" *) 
(* LC_PROBE387_PID = "16'b0000000110000011" *) (* LC_PROBE387_TYPE = "1" *) (* LC_PROBE387_WIDTH = "1" *) 
(* LC_PROBE388_IS_DATA = "1'b0" *) (* LC_PROBE388_IS_TRIG = "1'b0" *) (* LC_PROBE388_MU_CNT = "1" *) 
(* LC_PROBE388_PID = "16'b0000000110000100" *) (* LC_PROBE388_TYPE = "1" *) (* LC_PROBE388_WIDTH = "1" *) 
(* LC_PROBE389_IS_DATA = "1'b0" *) (* LC_PROBE389_IS_TRIG = "1'b0" *) (* LC_PROBE389_MU_CNT = "1" *) 
(* LC_PROBE389_PID = "16'b0000000110000101" *) (* LC_PROBE389_TYPE = "1" *) (* LC_PROBE389_WIDTH = "1" *) 
(* LC_PROBE38_IS_DATA = "1'b0" *) (* LC_PROBE38_IS_TRIG = "1'b0" *) (* LC_PROBE38_MU_CNT = "1" *) 
(* LC_PROBE38_PID = "16'b0000000000100110" *) (* LC_PROBE38_TYPE = "1" *) (* LC_PROBE38_WIDTH = "1" *) 
(* LC_PROBE390_IS_DATA = "1'b0" *) (* LC_PROBE390_IS_TRIG = "1'b0" *) (* LC_PROBE390_MU_CNT = "1" *) 
(* LC_PROBE390_PID = "16'b0000000110000110" *) (* LC_PROBE390_TYPE = "1" *) (* LC_PROBE390_WIDTH = "1" *) 
(* LC_PROBE391_IS_DATA = "1'b0" *) (* LC_PROBE391_IS_TRIG = "1'b0" *) (* LC_PROBE391_MU_CNT = "1" *) 
(* LC_PROBE391_PID = "16'b0000000110000111" *) (* LC_PROBE391_TYPE = "1" *) (* LC_PROBE391_WIDTH = "1" *) 
(* LC_PROBE392_IS_DATA = "1'b0" *) (* LC_PROBE392_IS_TRIG = "1'b0" *) (* LC_PROBE392_MU_CNT = "1" *) 
(* LC_PROBE392_PID = "16'b0000000110001000" *) (* LC_PROBE392_TYPE = "1" *) (* LC_PROBE392_WIDTH = "1" *) 
(* LC_PROBE393_IS_DATA = "1'b0" *) (* LC_PROBE393_IS_TRIG = "1'b0" *) (* LC_PROBE393_MU_CNT = "1" *) 
(* LC_PROBE393_PID = "16'b0000000110001001" *) (* LC_PROBE393_TYPE = "1" *) (* LC_PROBE393_WIDTH = "1" *) 
(* LC_PROBE394_IS_DATA = "1'b0" *) (* LC_PROBE394_IS_TRIG = "1'b0" *) (* LC_PROBE394_MU_CNT = "1" *) 
(* LC_PROBE394_PID = "16'b0000000110001010" *) (* LC_PROBE394_TYPE = "1" *) (* LC_PROBE394_WIDTH = "1" *) 
(* LC_PROBE395_IS_DATA = "1'b0" *) (* LC_PROBE395_IS_TRIG = "1'b0" *) (* LC_PROBE395_MU_CNT = "1" *) 
(* LC_PROBE395_PID = "16'b0000000110001011" *) (* LC_PROBE395_TYPE = "1" *) (* LC_PROBE395_WIDTH = "1" *) 
(* LC_PROBE396_IS_DATA = "1'b0" *) (* LC_PROBE396_IS_TRIG = "1'b0" *) (* LC_PROBE396_MU_CNT = "1" *) 
(* LC_PROBE396_PID = "16'b0000000110001100" *) (* LC_PROBE396_TYPE = "1" *) (* LC_PROBE396_WIDTH = "1" *) 
(* LC_PROBE397_IS_DATA = "1'b0" *) (* LC_PROBE397_IS_TRIG = "1'b0" *) (* LC_PROBE397_MU_CNT = "1" *) 
(* LC_PROBE397_PID = "16'b0000000110001101" *) (* LC_PROBE397_TYPE = "1" *) (* LC_PROBE397_WIDTH = "1" *) 
(* LC_PROBE398_IS_DATA = "1'b0" *) (* LC_PROBE398_IS_TRIG = "1'b0" *) (* LC_PROBE398_MU_CNT = "1" *) 
(* LC_PROBE398_PID = "16'b0000000110001110" *) (* LC_PROBE398_TYPE = "1" *) (* LC_PROBE398_WIDTH = "1" *) 
(* LC_PROBE399_IS_DATA = "1'b0" *) (* LC_PROBE399_IS_TRIG = "1'b0" *) (* LC_PROBE399_MU_CNT = "1" *) 
(* LC_PROBE399_PID = "16'b0000000110001111" *) (* LC_PROBE399_TYPE = "1" *) (* LC_PROBE399_WIDTH = "1" *) 
(* LC_PROBE39_IS_DATA = "1'b0" *) (* LC_PROBE39_IS_TRIG = "1'b0" *) (* LC_PROBE39_MU_CNT = "1" *) 
(* LC_PROBE39_PID = "16'b0000000000100111" *) (* LC_PROBE39_TYPE = "1" *) (* LC_PROBE39_WIDTH = "1" *) 
(* LC_PROBE3_IS_DATA = "1'b0" *) (* LC_PROBE3_IS_TRIG = "1'b0" *) (* LC_PROBE3_MU_CNT = "1" *) 
(* LC_PROBE3_PID = "16'b0000000000000011" *) (* LC_PROBE3_TYPE = "1" *) (* LC_PROBE3_WIDTH = "1" *) 
(* LC_PROBE400_IS_DATA = "1'b0" *) (* LC_PROBE400_IS_TRIG = "1'b0" *) (* LC_PROBE400_MU_CNT = "1" *) 
(* LC_PROBE400_PID = "16'b0000000110010000" *) (* LC_PROBE400_TYPE = "1" *) (* LC_PROBE400_WIDTH = "1" *) 
(* LC_PROBE401_IS_DATA = "1'b0" *) (* LC_PROBE401_IS_TRIG = "1'b0" *) (* LC_PROBE401_MU_CNT = "1" *) 
(* LC_PROBE401_PID = "16'b0000000110010001" *) (* LC_PROBE401_TYPE = "1" *) (* LC_PROBE401_WIDTH = "1" *) 
(* LC_PROBE402_IS_DATA = "1'b0" *) (* LC_PROBE402_IS_TRIG = "1'b0" *) (* LC_PROBE402_MU_CNT = "1" *) 
(* LC_PROBE402_PID = "16'b0000000110010010" *) (* LC_PROBE402_TYPE = "1" *) (* LC_PROBE402_WIDTH = "1" *) 
(* LC_PROBE403_IS_DATA = "1'b0" *) (* LC_PROBE403_IS_TRIG = "1'b0" *) (* LC_PROBE403_MU_CNT = "1" *) 
(* LC_PROBE403_PID = "16'b0000000110010011" *) (* LC_PROBE403_TYPE = "1" *) (* LC_PROBE403_WIDTH = "1" *) 
(* LC_PROBE404_IS_DATA = "1'b0" *) (* LC_PROBE404_IS_TRIG = "1'b0" *) (* LC_PROBE404_MU_CNT = "1" *) 
(* LC_PROBE404_PID = "16'b0000000110010100" *) (* LC_PROBE404_TYPE = "1" *) (* LC_PROBE404_WIDTH = "1" *) 
(* LC_PROBE405_IS_DATA = "1'b0" *) (* LC_PROBE405_IS_TRIG = "1'b0" *) (* LC_PROBE405_MU_CNT = "1" *) 
(* LC_PROBE405_PID = "16'b0000000110010101" *) (* LC_PROBE405_TYPE = "1" *) (* LC_PROBE405_WIDTH = "1" *) 
(* LC_PROBE406_IS_DATA = "1'b0" *) (* LC_PROBE406_IS_TRIG = "1'b0" *) (* LC_PROBE406_MU_CNT = "1" *) 
(* LC_PROBE406_PID = "16'b0000000110010110" *) (* LC_PROBE406_TYPE = "1" *) (* LC_PROBE406_WIDTH = "1" *) 
(* LC_PROBE407_IS_DATA = "1'b0" *) (* LC_PROBE407_IS_TRIG = "1'b0" *) (* LC_PROBE407_MU_CNT = "1" *) 
(* LC_PROBE407_PID = "16'b0000000110010111" *) (* LC_PROBE407_TYPE = "1" *) (* LC_PROBE407_WIDTH = "1" *) 
(* LC_PROBE408_IS_DATA = "1'b0" *) (* LC_PROBE408_IS_TRIG = "1'b0" *) (* LC_PROBE408_MU_CNT = "1" *) 
(* LC_PROBE408_PID = "16'b0000000110011000" *) (* LC_PROBE408_TYPE = "1" *) (* LC_PROBE408_WIDTH = "1" *) 
(* LC_PROBE409_IS_DATA = "1'b0" *) (* LC_PROBE409_IS_TRIG = "1'b0" *) (* LC_PROBE409_MU_CNT = "1" *) 
(* LC_PROBE409_PID = "16'b0000000110011001" *) (* LC_PROBE409_TYPE = "1" *) (* LC_PROBE409_WIDTH = "1" *) 
(* LC_PROBE40_IS_DATA = "1'b0" *) (* LC_PROBE40_IS_TRIG = "1'b0" *) (* LC_PROBE40_MU_CNT = "1" *) 
(* LC_PROBE40_PID = "16'b0000000000101000" *) (* LC_PROBE40_TYPE = "1" *) (* LC_PROBE40_WIDTH = "1" *) 
(* LC_PROBE410_IS_DATA = "1'b0" *) (* LC_PROBE410_IS_TRIG = "1'b0" *) (* LC_PROBE410_MU_CNT = "1" *) 
(* LC_PROBE410_PID = "16'b0000000110011010" *) (* LC_PROBE410_TYPE = "1" *) (* LC_PROBE410_WIDTH = "1" *) 
(* LC_PROBE411_IS_DATA = "1'b0" *) (* LC_PROBE411_IS_TRIG = "1'b0" *) (* LC_PROBE411_MU_CNT = "1" *) 
(* LC_PROBE411_PID = "16'b0000000110011011" *) (* LC_PROBE411_TYPE = "1" *) (* LC_PROBE411_WIDTH = "1" *) 
(* LC_PROBE412_IS_DATA = "1'b0" *) (* LC_PROBE412_IS_TRIG = "1'b0" *) (* LC_PROBE412_MU_CNT = "1" *) 
(* LC_PROBE412_PID = "16'b0000000110011100" *) (* LC_PROBE412_TYPE = "1" *) (* LC_PROBE412_WIDTH = "1" *) 
(* LC_PROBE413_IS_DATA = "1'b0" *) (* LC_PROBE413_IS_TRIG = "1'b0" *) (* LC_PROBE413_MU_CNT = "1" *) 
(* LC_PROBE413_PID = "16'b0000000110011101" *) (* LC_PROBE413_TYPE = "1" *) (* LC_PROBE413_WIDTH = "1" *) 
(* LC_PROBE414_IS_DATA = "1'b0" *) (* LC_PROBE414_IS_TRIG = "1'b0" *) (* LC_PROBE414_MU_CNT = "1" *) 
(* LC_PROBE414_PID = "16'b0000000110011110" *) (* LC_PROBE414_TYPE = "1" *) (* LC_PROBE414_WIDTH = "1" *) 
(* LC_PROBE415_IS_DATA = "1'b0" *) (* LC_PROBE415_IS_TRIG = "1'b0" *) (* LC_PROBE415_MU_CNT = "1" *) 
(* LC_PROBE415_PID = "16'b0000000110011111" *) (* LC_PROBE415_TYPE = "1" *) (* LC_PROBE415_WIDTH = "1" *) 
(* LC_PROBE416_IS_DATA = "1'b0" *) (* LC_PROBE416_IS_TRIG = "1'b0" *) (* LC_PROBE416_MU_CNT = "1" *) 
(* LC_PROBE416_PID = "16'b0000000110100000" *) (* LC_PROBE416_TYPE = "1" *) (* LC_PROBE416_WIDTH = "1" *) 
(* LC_PROBE417_IS_DATA = "1'b0" *) (* LC_PROBE417_IS_TRIG = "1'b0" *) (* LC_PROBE417_MU_CNT = "1" *) 
(* LC_PROBE417_PID = "16'b0000000110100001" *) (* LC_PROBE417_TYPE = "1" *) (* LC_PROBE417_WIDTH = "1" *) 
(* LC_PROBE418_IS_DATA = "1'b0" *) (* LC_PROBE418_IS_TRIG = "1'b0" *) (* LC_PROBE418_MU_CNT = "1" *) 
(* LC_PROBE418_PID = "16'b0000000110100010" *) (* LC_PROBE418_TYPE = "1" *) (* LC_PROBE418_WIDTH = "1" *) 
(* LC_PROBE419_IS_DATA = "1'b0" *) (* LC_PROBE419_IS_TRIG = "1'b0" *) (* LC_PROBE419_MU_CNT = "1" *) 
(* LC_PROBE419_PID = "16'b0000000110100011" *) (* LC_PROBE419_TYPE = "1" *) (* LC_PROBE419_WIDTH = "1" *) 
(* LC_PROBE41_IS_DATA = "1'b0" *) (* LC_PROBE41_IS_TRIG = "1'b0" *) (* LC_PROBE41_MU_CNT = "1" *) 
(* LC_PROBE41_PID = "16'b0000000000101001" *) (* LC_PROBE41_TYPE = "1" *) (* LC_PROBE41_WIDTH = "1" *) 
(* LC_PROBE420_IS_DATA = "1'b0" *) (* LC_PROBE420_IS_TRIG = "1'b0" *) (* LC_PROBE420_MU_CNT = "1" *) 
(* LC_PROBE420_PID = "16'b0000000110100100" *) (* LC_PROBE420_TYPE = "1" *) (* LC_PROBE420_WIDTH = "1" *) 
(* LC_PROBE421_IS_DATA = "1'b0" *) (* LC_PROBE421_IS_TRIG = "1'b0" *) (* LC_PROBE421_MU_CNT = "1" *) 
(* LC_PROBE421_PID = "16'b0000000110100101" *) (* LC_PROBE421_TYPE = "1" *) (* LC_PROBE421_WIDTH = "1" *) 
(* LC_PROBE422_IS_DATA = "1'b0" *) (* LC_PROBE422_IS_TRIG = "1'b0" *) (* LC_PROBE422_MU_CNT = "1" *) 
(* LC_PROBE422_PID = "16'b0000000110100110" *) (* LC_PROBE422_TYPE = "1" *) (* LC_PROBE422_WIDTH = "1" *) 
(* LC_PROBE423_IS_DATA = "1'b0" *) (* LC_PROBE423_IS_TRIG = "1'b0" *) (* LC_PROBE423_MU_CNT = "1" *) 
(* LC_PROBE423_PID = "16'b0000000110100111" *) (* LC_PROBE423_TYPE = "1" *) (* LC_PROBE423_WIDTH = "1" *) 
(* LC_PROBE424_IS_DATA = "1'b0" *) (* LC_PROBE424_IS_TRIG = "1'b0" *) (* LC_PROBE424_MU_CNT = "1" *) 
(* LC_PROBE424_PID = "16'b0000000110101000" *) (* LC_PROBE424_TYPE = "1" *) (* LC_PROBE424_WIDTH = "1" *) 
(* LC_PROBE425_IS_DATA = "1'b0" *) (* LC_PROBE425_IS_TRIG = "1'b0" *) (* LC_PROBE425_MU_CNT = "1" *) 
(* LC_PROBE425_PID = "16'b0000000110101001" *) (* LC_PROBE425_TYPE = "1" *) (* LC_PROBE425_WIDTH = "1" *) 
(* LC_PROBE426_IS_DATA = "1'b0" *) (* LC_PROBE426_IS_TRIG = "1'b0" *) (* LC_PROBE426_MU_CNT = "1" *) 
(* LC_PROBE426_PID = "16'b0000000110101010" *) (* LC_PROBE426_TYPE = "1" *) (* LC_PROBE426_WIDTH = "1" *) 
(* LC_PROBE427_IS_DATA = "1'b0" *) (* LC_PROBE427_IS_TRIG = "1'b0" *) (* LC_PROBE427_MU_CNT = "1" *) 
(* LC_PROBE427_PID = "16'b0000000110101011" *) (* LC_PROBE427_TYPE = "1" *) (* LC_PROBE427_WIDTH = "1" *) 
(* LC_PROBE428_IS_DATA = "1'b0" *) (* LC_PROBE428_IS_TRIG = "1'b0" *) (* LC_PROBE428_MU_CNT = "1" *) 
(* LC_PROBE428_PID = "16'b0000000110101100" *) (* LC_PROBE428_TYPE = "1" *) (* LC_PROBE428_WIDTH = "1" *) 
(* LC_PROBE429_IS_DATA = "1'b0" *) (* LC_PROBE429_IS_TRIG = "1'b0" *) (* LC_PROBE429_MU_CNT = "1" *) 
(* LC_PROBE429_PID = "16'b0000000110101101" *) (* LC_PROBE429_TYPE = "1" *) (* LC_PROBE429_WIDTH = "1" *) 
(* LC_PROBE42_IS_DATA = "1'b0" *) (* LC_PROBE42_IS_TRIG = "1'b0" *) (* LC_PROBE42_MU_CNT = "1" *) 
(* LC_PROBE42_PID = "16'b0000000000101010" *) (* LC_PROBE42_TYPE = "1" *) (* LC_PROBE42_WIDTH = "1" *) 
(* LC_PROBE430_IS_DATA = "1'b0" *) (* LC_PROBE430_IS_TRIG = "1'b0" *) (* LC_PROBE430_MU_CNT = "1" *) 
(* LC_PROBE430_PID = "16'b0000000110101110" *) (* LC_PROBE430_TYPE = "1" *) (* LC_PROBE430_WIDTH = "1" *) 
(* LC_PROBE431_IS_DATA = "1'b0" *) (* LC_PROBE431_IS_TRIG = "1'b0" *) (* LC_PROBE431_MU_CNT = "1" *) 
(* LC_PROBE431_PID = "16'b0000000110101111" *) (* LC_PROBE431_TYPE = "1" *) (* LC_PROBE431_WIDTH = "1" *) 
(* LC_PROBE432_IS_DATA = "1'b0" *) (* LC_PROBE432_IS_TRIG = "1'b0" *) (* LC_PROBE432_MU_CNT = "1" *) 
(* LC_PROBE432_PID = "16'b0000000110110000" *) (* LC_PROBE432_TYPE = "1" *) (* LC_PROBE432_WIDTH = "1" *) 
(* LC_PROBE433_IS_DATA = "1'b0" *) (* LC_PROBE433_IS_TRIG = "1'b0" *) (* LC_PROBE433_MU_CNT = "1" *) 
(* LC_PROBE433_PID = "16'b0000000110110001" *) (* LC_PROBE433_TYPE = "1" *) (* LC_PROBE433_WIDTH = "1" *) 
(* LC_PROBE434_IS_DATA = "1'b0" *) (* LC_PROBE434_IS_TRIG = "1'b0" *) (* LC_PROBE434_MU_CNT = "1" *) 
(* LC_PROBE434_PID = "16'b0000000110110010" *) (* LC_PROBE434_TYPE = "1" *) (* LC_PROBE434_WIDTH = "1" *) 
(* LC_PROBE435_IS_DATA = "1'b0" *) (* LC_PROBE435_IS_TRIG = "1'b0" *) (* LC_PROBE435_MU_CNT = "1" *) 
(* LC_PROBE435_PID = "16'b0000000110110011" *) (* LC_PROBE435_TYPE = "1" *) (* LC_PROBE435_WIDTH = "1" *) 
(* LC_PROBE436_IS_DATA = "1'b0" *) (* LC_PROBE436_IS_TRIG = "1'b0" *) (* LC_PROBE436_MU_CNT = "1" *) 
(* LC_PROBE436_PID = "16'b0000000110110100" *) (* LC_PROBE436_TYPE = "1" *) (* LC_PROBE436_WIDTH = "1" *) 
(* LC_PROBE437_IS_DATA = "1'b0" *) (* LC_PROBE437_IS_TRIG = "1'b0" *) (* LC_PROBE437_MU_CNT = "1" *) 
(* LC_PROBE437_PID = "16'b0000000110110101" *) (* LC_PROBE437_TYPE = "1" *) (* LC_PROBE437_WIDTH = "1" *) 
(* LC_PROBE438_IS_DATA = "1'b0" *) (* LC_PROBE438_IS_TRIG = "1'b0" *) (* LC_PROBE438_MU_CNT = "1" *) 
(* LC_PROBE438_PID = "16'b0000000110110110" *) (* LC_PROBE438_TYPE = "1" *) (* LC_PROBE438_WIDTH = "1" *) 
(* LC_PROBE439_IS_DATA = "1'b0" *) (* LC_PROBE439_IS_TRIG = "1'b0" *) (* LC_PROBE439_MU_CNT = "1" *) 
(* LC_PROBE439_PID = "16'b0000000110110111" *) (* LC_PROBE439_TYPE = "1" *) (* LC_PROBE439_WIDTH = "1" *) 
(* LC_PROBE43_IS_DATA = "1'b0" *) (* LC_PROBE43_IS_TRIG = "1'b0" *) (* LC_PROBE43_MU_CNT = "1" *) 
(* LC_PROBE43_PID = "16'b0000000000101011" *) (* LC_PROBE43_TYPE = "1" *) (* LC_PROBE43_WIDTH = "1" *) 
(* LC_PROBE440_IS_DATA = "1'b0" *) (* LC_PROBE440_IS_TRIG = "1'b0" *) (* LC_PROBE440_MU_CNT = "1" *) 
(* LC_PROBE440_PID = "16'b0000000110111000" *) (* LC_PROBE440_TYPE = "1" *) (* LC_PROBE440_WIDTH = "1" *) 
(* LC_PROBE441_IS_DATA = "1'b0" *) (* LC_PROBE441_IS_TRIG = "1'b0" *) (* LC_PROBE441_MU_CNT = "1" *) 
(* LC_PROBE441_PID = "16'b0000000110111001" *) (* LC_PROBE441_TYPE = "1" *) (* LC_PROBE441_WIDTH = "1" *) 
(* LC_PROBE442_IS_DATA = "1'b0" *) (* LC_PROBE442_IS_TRIG = "1'b0" *) (* LC_PROBE442_MU_CNT = "1" *) 
(* LC_PROBE442_PID = "16'b0000000110111010" *) (* LC_PROBE442_TYPE = "1" *) (* LC_PROBE442_WIDTH = "1" *) 
(* LC_PROBE443_IS_DATA = "1'b0" *) (* LC_PROBE443_IS_TRIG = "1'b0" *) (* LC_PROBE443_MU_CNT = "1" *) 
(* LC_PROBE443_PID = "16'b0000000110111011" *) (* LC_PROBE443_TYPE = "1" *) (* LC_PROBE443_WIDTH = "1" *) 
(* LC_PROBE444_IS_DATA = "1'b0" *) (* LC_PROBE444_IS_TRIG = "1'b0" *) (* LC_PROBE444_MU_CNT = "1" *) 
(* LC_PROBE444_PID = "16'b0000000110111100" *) (* LC_PROBE444_TYPE = "1" *) (* LC_PROBE444_WIDTH = "1" *) 
(* LC_PROBE445_IS_DATA = "1'b0" *) (* LC_PROBE445_IS_TRIG = "1'b0" *) (* LC_PROBE445_MU_CNT = "1" *) 
(* LC_PROBE445_PID = "16'b0000000110111101" *) (* LC_PROBE445_TYPE = "1" *) (* LC_PROBE445_WIDTH = "1" *) 
(* LC_PROBE446_IS_DATA = "1'b0" *) (* LC_PROBE446_IS_TRIG = "1'b0" *) (* LC_PROBE446_MU_CNT = "1" *) 
(* LC_PROBE446_PID = "16'b0000000110111110" *) (* LC_PROBE446_TYPE = "1" *) (* LC_PROBE446_WIDTH = "1" *) 
(* LC_PROBE447_IS_DATA = "1'b0" *) (* LC_PROBE447_IS_TRIG = "1'b0" *) (* LC_PROBE447_MU_CNT = "1" *) 
(* LC_PROBE447_PID = "16'b0000000110111111" *) (* LC_PROBE447_TYPE = "1" *) (* LC_PROBE447_WIDTH = "1" *) 
(* LC_PROBE448_IS_DATA = "1'b0" *) (* LC_PROBE448_IS_TRIG = "1'b0" *) (* LC_PROBE448_MU_CNT = "1" *) 
(* LC_PROBE448_PID = "16'b0000000111000000" *) (* LC_PROBE448_TYPE = "1" *) (* LC_PROBE448_WIDTH = "1" *) 
(* LC_PROBE449_IS_DATA = "1'b0" *) (* LC_PROBE449_IS_TRIG = "1'b0" *) (* LC_PROBE449_MU_CNT = "1" *) 
(* LC_PROBE449_PID = "16'b0000000111000001" *) (* LC_PROBE449_TYPE = "1" *) (* LC_PROBE449_WIDTH = "1" *) 
(* LC_PROBE44_IS_DATA = "1'b0" *) (* LC_PROBE44_IS_TRIG = "1'b0" *) (* LC_PROBE44_MU_CNT = "1" *) 
(* LC_PROBE44_PID = "16'b0000000000101100" *) (* LC_PROBE44_TYPE = "1" *) (* LC_PROBE44_WIDTH = "1" *) 
(* LC_PROBE450_IS_DATA = "1'b0" *) (* LC_PROBE450_IS_TRIG = "1'b0" *) (* LC_PROBE450_MU_CNT = "1" *) 
(* LC_PROBE450_PID = "16'b0000000111000010" *) (* LC_PROBE450_TYPE = "1" *) (* LC_PROBE450_WIDTH = "1" *) 
(* LC_PROBE451_IS_DATA = "1'b0" *) (* LC_PROBE451_IS_TRIG = "1'b0" *) (* LC_PROBE451_MU_CNT = "1" *) 
(* LC_PROBE451_PID = "16'b0000000111000011" *) (* LC_PROBE451_TYPE = "1" *) (* LC_PROBE451_WIDTH = "1" *) 
(* LC_PROBE452_IS_DATA = "1'b0" *) (* LC_PROBE452_IS_TRIG = "1'b0" *) (* LC_PROBE452_MU_CNT = "1" *) 
(* LC_PROBE452_PID = "16'b0000000111000100" *) (* LC_PROBE452_TYPE = "1" *) (* LC_PROBE452_WIDTH = "1" *) 
(* LC_PROBE453_IS_DATA = "1'b0" *) (* LC_PROBE453_IS_TRIG = "1'b0" *) (* LC_PROBE453_MU_CNT = "1" *) 
(* LC_PROBE453_PID = "16'b0000000111000101" *) (* LC_PROBE453_TYPE = "1" *) (* LC_PROBE453_WIDTH = "1" *) 
(* LC_PROBE454_IS_DATA = "1'b0" *) (* LC_PROBE454_IS_TRIG = "1'b0" *) (* LC_PROBE454_MU_CNT = "1" *) 
(* LC_PROBE454_PID = "16'b0000000111000110" *) (* LC_PROBE454_TYPE = "1" *) (* LC_PROBE454_WIDTH = "1" *) 
(* LC_PROBE455_IS_DATA = "1'b0" *) (* LC_PROBE455_IS_TRIG = "1'b0" *) (* LC_PROBE455_MU_CNT = "1" *) 
(* LC_PROBE455_PID = "16'b0000000111000111" *) (* LC_PROBE455_TYPE = "1" *) (* LC_PROBE455_WIDTH = "1" *) 
(* LC_PROBE456_IS_DATA = "1'b0" *) (* LC_PROBE456_IS_TRIG = "1'b0" *) (* LC_PROBE456_MU_CNT = "1" *) 
(* LC_PROBE456_PID = "16'b0000000111001000" *) (* LC_PROBE456_TYPE = "1" *) (* LC_PROBE456_WIDTH = "1" *) 
(* LC_PROBE457_IS_DATA = "1'b0" *) (* LC_PROBE457_IS_TRIG = "1'b0" *) (* LC_PROBE457_MU_CNT = "1" *) 
(* LC_PROBE457_PID = "16'b0000000111001001" *) (* LC_PROBE457_TYPE = "1" *) (* LC_PROBE457_WIDTH = "1" *) 
(* LC_PROBE458_IS_DATA = "1'b0" *) (* LC_PROBE458_IS_TRIG = "1'b0" *) (* LC_PROBE458_MU_CNT = "1" *) 
(* LC_PROBE458_PID = "16'b0000000111001010" *) (* LC_PROBE458_TYPE = "1" *) (* LC_PROBE458_WIDTH = "1" *) 
(* LC_PROBE459_IS_DATA = "1'b0" *) (* LC_PROBE459_IS_TRIG = "1'b0" *) (* LC_PROBE459_MU_CNT = "1" *) 
(* LC_PROBE459_PID = "16'b0000000111001011" *) (* LC_PROBE459_TYPE = "1" *) (* LC_PROBE459_WIDTH = "1" *) 
(* LC_PROBE45_IS_DATA = "1'b0" *) (* LC_PROBE45_IS_TRIG = "1'b0" *) (* LC_PROBE45_MU_CNT = "1" *) 
(* LC_PROBE45_PID = "16'b0000000000101101" *) (* LC_PROBE45_TYPE = "1" *) (* LC_PROBE45_WIDTH = "1" *) 
(* LC_PROBE460_IS_DATA = "1'b0" *) (* LC_PROBE460_IS_TRIG = "1'b0" *) (* LC_PROBE460_MU_CNT = "1" *) 
(* LC_PROBE460_PID = "16'b0000000111001100" *) (* LC_PROBE460_TYPE = "1" *) (* LC_PROBE460_WIDTH = "1" *) 
(* LC_PROBE461_IS_DATA = "1'b0" *) (* LC_PROBE461_IS_TRIG = "1'b0" *) (* LC_PROBE461_MU_CNT = "1" *) 
(* LC_PROBE461_PID = "16'b0000000111001101" *) (* LC_PROBE461_TYPE = "1" *) (* LC_PROBE461_WIDTH = "1" *) 
(* LC_PROBE462_IS_DATA = "1'b0" *) (* LC_PROBE462_IS_TRIG = "1'b0" *) (* LC_PROBE462_MU_CNT = "1" *) 
(* LC_PROBE462_PID = "16'b0000000111001110" *) (* LC_PROBE462_TYPE = "1" *) (* LC_PROBE462_WIDTH = "1" *) 
(* LC_PROBE463_IS_DATA = "1'b0" *) (* LC_PROBE463_IS_TRIG = "1'b0" *) (* LC_PROBE463_MU_CNT = "1" *) 
(* LC_PROBE463_PID = "16'b0000000111001111" *) (* LC_PROBE463_TYPE = "1" *) (* LC_PROBE463_WIDTH = "1" *) 
(* LC_PROBE464_IS_DATA = "1'b0" *) (* LC_PROBE464_IS_TRIG = "1'b0" *) (* LC_PROBE464_MU_CNT = "1" *) 
(* LC_PROBE464_PID = "16'b0000000111010000" *) (* LC_PROBE464_TYPE = "1" *) (* LC_PROBE464_WIDTH = "1" *) 
(* LC_PROBE465_IS_DATA = "1'b0" *) (* LC_PROBE465_IS_TRIG = "1'b0" *) (* LC_PROBE465_MU_CNT = "1" *) 
(* LC_PROBE465_PID = "16'b0000000111010001" *) (* LC_PROBE465_TYPE = "1" *) (* LC_PROBE465_WIDTH = "1" *) 
(* LC_PROBE466_IS_DATA = "1'b0" *) (* LC_PROBE466_IS_TRIG = "1'b0" *) (* LC_PROBE466_MU_CNT = "1" *) 
(* LC_PROBE466_PID = "16'b0000000111010010" *) (* LC_PROBE466_TYPE = "1" *) (* LC_PROBE466_WIDTH = "1" *) 
(* LC_PROBE467_IS_DATA = "1'b0" *) (* LC_PROBE467_IS_TRIG = "1'b0" *) (* LC_PROBE467_MU_CNT = "1" *) 
(* LC_PROBE467_PID = "16'b0000000111010011" *) (* LC_PROBE467_TYPE = "1" *) (* LC_PROBE467_WIDTH = "1" *) 
(* LC_PROBE468_IS_DATA = "1'b0" *) (* LC_PROBE468_IS_TRIG = "1'b0" *) (* LC_PROBE468_MU_CNT = "1" *) 
(* LC_PROBE468_PID = "16'b0000000111010100" *) (* LC_PROBE468_TYPE = "1" *) (* LC_PROBE468_WIDTH = "1" *) 
(* LC_PROBE469_IS_DATA = "1'b0" *) (* LC_PROBE469_IS_TRIG = "1'b0" *) (* LC_PROBE469_MU_CNT = "1" *) 
(* LC_PROBE469_PID = "16'b0000000111010101" *) (* LC_PROBE469_TYPE = "1" *) (* LC_PROBE469_WIDTH = "1" *) 
(* LC_PROBE46_IS_DATA = "1'b0" *) (* LC_PROBE46_IS_TRIG = "1'b0" *) (* LC_PROBE46_MU_CNT = "1" *) 
(* LC_PROBE46_PID = "16'b0000000000101110" *) (* LC_PROBE46_TYPE = "1" *) (* LC_PROBE46_WIDTH = "1" *) 
(* LC_PROBE470_IS_DATA = "1'b0" *) (* LC_PROBE470_IS_TRIG = "1'b0" *) (* LC_PROBE470_MU_CNT = "1" *) 
(* LC_PROBE470_PID = "16'b0000000111010110" *) (* LC_PROBE470_TYPE = "1" *) (* LC_PROBE470_WIDTH = "1" *) 
(* LC_PROBE471_IS_DATA = "1'b0" *) (* LC_PROBE471_IS_TRIG = "1'b0" *) (* LC_PROBE471_MU_CNT = "1" *) 
(* LC_PROBE471_PID = "16'b0000000111010111" *) (* LC_PROBE471_TYPE = "1" *) (* LC_PROBE471_WIDTH = "1" *) 
(* LC_PROBE472_IS_DATA = "1'b0" *) (* LC_PROBE472_IS_TRIG = "1'b0" *) (* LC_PROBE472_MU_CNT = "1" *) 
(* LC_PROBE472_PID = "16'b0000000111011000" *) (* LC_PROBE472_TYPE = "1" *) (* LC_PROBE472_WIDTH = "1" *) 
(* LC_PROBE473_IS_DATA = "1'b0" *) (* LC_PROBE473_IS_TRIG = "1'b0" *) (* LC_PROBE473_MU_CNT = "1" *) 
(* LC_PROBE473_PID = "16'b0000000111011001" *) (* LC_PROBE473_TYPE = "1" *) (* LC_PROBE473_WIDTH = "1" *) 
(* LC_PROBE474_IS_DATA = "1'b0" *) (* LC_PROBE474_IS_TRIG = "1'b0" *) (* LC_PROBE474_MU_CNT = "1" *) 
(* LC_PROBE474_PID = "16'b0000000111011010" *) (* LC_PROBE474_TYPE = "1" *) (* LC_PROBE474_WIDTH = "1" *) 
(* LC_PROBE475_IS_DATA = "1'b0" *) (* LC_PROBE475_IS_TRIG = "1'b0" *) (* LC_PROBE475_MU_CNT = "1" *) 
(* LC_PROBE475_PID = "16'b0000000111011011" *) (* LC_PROBE475_TYPE = "1" *) (* LC_PROBE475_WIDTH = "1" *) 
(* LC_PROBE476_IS_DATA = "1'b0" *) (* LC_PROBE476_IS_TRIG = "1'b0" *) (* LC_PROBE476_MU_CNT = "1" *) 
(* LC_PROBE476_PID = "16'b0000000111011100" *) (* LC_PROBE476_TYPE = "1" *) (* LC_PROBE476_WIDTH = "1" *) 
(* LC_PROBE477_IS_DATA = "1'b0" *) (* LC_PROBE477_IS_TRIG = "1'b0" *) (* LC_PROBE477_MU_CNT = "1" *) 
(* LC_PROBE477_PID = "16'b0000000111011101" *) (* LC_PROBE477_TYPE = "1" *) (* LC_PROBE477_WIDTH = "1" *) 
(* LC_PROBE478_IS_DATA = "1'b0" *) (* LC_PROBE478_IS_TRIG = "1'b0" *) (* LC_PROBE478_MU_CNT = "1" *) 
(* LC_PROBE478_PID = "16'b0000000111011110" *) (* LC_PROBE478_TYPE = "1" *) (* LC_PROBE478_WIDTH = "1" *) 
(* LC_PROBE479_IS_DATA = "1'b0" *) (* LC_PROBE479_IS_TRIG = "1'b0" *) (* LC_PROBE479_MU_CNT = "1" *) 
(* LC_PROBE479_PID = "16'b0000000111011111" *) (* LC_PROBE479_TYPE = "1" *) (* LC_PROBE479_WIDTH = "1" *) 
(* LC_PROBE47_IS_DATA = "1'b0" *) (* LC_PROBE47_IS_TRIG = "1'b0" *) (* LC_PROBE47_MU_CNT = "1" *) 
(* LC_PROBE47_PID = "16'b0000000000101111" *) (* LC_PROBE47_TYPE = "1" *) (* LC_PROBE47_WIDTH = "1" *) 
(* LC_PROBE480_IS_DATA = "1'b0" *) (* LC_PROBE480_IS_TRIG = "1'b0" *) (* LC_PROBE480_MU_CNT = "1" *) 
(* LC_PROBE480_PID = "16'b0000000111100000" *) (* LC_PROBE480_TYPE = "1" *) (* LC_PROBE480_WIDTH = "1" *) 
(* LC_PROBE481_IS_DATA = "1'b0" *) (* LC_PROBE481_IS_TRIG = "1'b0" *) (* LC_PROBE481_MU_CNT = "1" *) 
(* LC_PROBE481_PID = "16'b0000000111100001" *) (* LC_PROBE481_TYPE = "1" *) (* LC_PROBE481_WIDTH = "1" *) 
(* LC_PROBE482_IS_DATA = "1'b0" *) (* LC_PROBE482_IS_TRIG = "1'b0" *) (* LC_PROBE482_MU_CNT = "1" *) 
(* LC_PROBE482_PID = "16'b0000000111100010" *) (* LC_PROBE482_TYPE = "1" *) (* LC_PROBE482_WIDTH = "1" *) 
(* LC_PROBE483_IS_DATA = "1'b0" *) (* LC_PROBE483_IS_TRIG = "1'b0" *) (* LC_PROBE483_MU_CNT = "1" *) 
(* LC_PROBE483_PID = "16'b0000000111100011" *) (* LC_PROBE483_TYPE = "1" *) (* LC_PROBE483_WIDTH = "1" *) 
(* LC_PROBE484_IS_DATA = "1'b0" *) (* LC_PROBE484_IS_TRIG = "1'b0" *) (* LC_PROBE484_MU_CNT = "1" *) 
(* LC_PROBE484_PID = "16'b0000000111100100" *) (* LC_PROBE484_TYPE = "1" *) (* LC_PROBE484_WIDTH = "1" *) 
(* LC_PROBE485_IS_DATA = "1'b0" *) (* LC_PROBE485_IS_TRIG = "1'b0" *) (* LC_PROBE485_MU_CNT = "1" *) 
(* LC_PROBE485_PID = "16'b0000000111100101" *) (* LC_PROBE485_TYPE = "1" *) (* LC_PROBE485_WIDTH = "1" *) 
(* LC_PROBE486_IS_DATA = "1'b0" *) (* LC_PROBE486_IS_TRIG = "1'b0" *) (* LC_PROBE486_MU_CNT = "1" *) 
(* LC_PROBE486_PID = "16'b0000000111100110" *) (* LC_PROBE486_TYPE = "1" *) (* LC_PROBE486_WIDTH = "1" *) 
(* LC_PROBE487_IS_DATA = "1'b0" *) (* LC_PROBE487_IS_TRIG = "1'b0" *) (* LC_PROBE487_MU_CNT = "1" *) 
(* LC_PROBE487_PID = "16'b0000000111100111" *) (* LC_PROBE487_TYPE = "1" *) (* LC_PROBE487_WIDTH = "1" *) 
(* LC_PROBE488_IS_DATA = "1'b0" *) (* LC_PROBE488_IS_TRIG = "1'b0" *) (* LC_PROBE488_MU_CNT = "1" *) 
(* LC_PROBE488_PID = "16'b0000000111101000" *) (* LC_PROBE488_TYPE = "1" *) (* LC_PROBE488_WIDTH = "1" *) 
(* LC_PROBE489_IS_DATA = "1'b0" *) (* LC_PROBE489_IS_TRIG = "1'b0" *) (* LC_PROBE489_MU_CNT = "1" *) 
(* LC_PROBE489_PID = "16'b0000000111101001" *) (* LC_PROBE489_TYPE = "1" *) (* LC_PROBE489_WIDTH = "1" *) 
(* LC_PROBE48_IS_DATA = "1'b0" *) (* LC_PROBE48_IS_TRIG = "1'b0" *) (* LC_PROBE48_MU_CNT = "1" *) 
(* LC_PROBE48_PID = "16'b0000000000110000" *) (* LC_PROBE48_TYPE = "1" *) (* LC_PROBE48_WIDTH = "1" *) 
(* LC_PROBE490_IS_DATA = "1'b0" *) (* LC_PROBE490_IS_TRIG = "1'b0" *) (* LC_PROBE490_MU_CNT = "1" *) 
(* LC_PROBE490_PID = "16'b0000000111101010" *) (* LC_PROBE490_TYPE = "1" *) (* LC_PROBE490_WIDTH = "1" *) 
(* LC_PROBE491_IS_DATA = "1'b0" *) (* LC_PROBE491_IS_TRIG = "1'b0" *) (* LC_PROBE491_MU_CNT = "1" *) 
(* LC_PROBE491_PID = "16'b0000000111101011" *) (* LC_PROBE491_TYPE = "1" *) (* LC_PROBE491_WIDTH = "1" *) 
(* LC_PROBE492_IS_DATA = "1'b0" *) (* LC_PROBE492_IS_TRIG = "1'b0" *) (* LC_PROBE492_MU_CNT = "1" *) 
(* LC_PROBE492_PID = "16'b0000000111101100" *) (* LC_PROBE492_TYPE = "1" *) (* LC_PROBE492_WIDTH = "1" *) 
(* LC_PROBE493_IS_DATA = "1'b0" *) (* LC_PROBE493_IS_TRIG = "1'b0" *) (* LC_PROBE493_MU_CNT = "1" *) 
(* LC_PROBE493_PID = "16'b0000000111101101" *) (* LC_PROBE493_TYPE = "1" *) (* LC_PROBE493_WIDTH = "1" *) 
(* LC_PROBE494_IS_DATA = "1'b0" *) (* LC_PROBE494_IS_TRIG = "1'b0" *) (* LC_PROBE494_MU_CNT = "1" *) 
(* LC_PROBE494_PID = "16'b0000000111101110" *) (* LC_PROBE494_TYPE = "1" *) (* LC_PROBE494_WIDTH = "1" *) 
(* LC_PROBE495_IS_DATA = "1'b0" *) (* LC_PROBE495_IS_TRIG = "1'b0" *) (* LC_PROBE495_MU_CNT = "1" *) 
(* LC_PROBE495_PID = "16'b0000000111101111" *) (* LC_PROBE495_TYPE = "1" *) (* LC_PROBE495_WIDTH = "1" *) 
(* LC_PROBE496_IS_DATA = "1'b0" *) (* LC_PROBE496_IS_TRIG = "1'b0" *) (* LC_PROBE496_MU_CNT = "1" *) 
(* LC_PROBE496_PID = "16'b0000000111110000" *) (* LC_PROBE496_TYPE = "1" *) (* LC_PROBE496_WIDTH = "1" *) 
(* LC_PROBE497_IS_DATA = "1'b0" *) (* LC_PROBE497_IS_TRIG = "1'b0" *) (* LC_PROBE497_MU_CNT = "1" *) 
(* LC_PROBE497_PID = "16'b0000000111110001" *) (* LC_PROBE497_TYPE = "1" *) (* LC_PROBE497_WIDTH = "1" *) 
(* LC_PROBE498_IS_DATA = "1'b0" *) (* LC_PROBE498_IS_TRIG = "1'b0" *) (* LC_PROBE498_MU_CNT = "1" *) 
(* LC_PROBE498_PID = "16'b0000000111110010" *) (* LC_PROBE498_TYPE = "1" *) (* LC_PROBE498_WIDTH = "1" *) 
(* LC_PROBE499_IS_DATA = "1'b0" *) (* LC_PROBE499_IS_TRIG = "1'b0" *) (* LC_PROBE499_MU_CNT = "1" *) 
(* LC_PROBE499_PID = "16'b0000000111110011" *) (* LC_PROBE499_TYPE = "1" *) (* LC_PROBE499_WIDTH = "1" *) 
(* LC_PROBE49_IS_DATA = "1'b0" *) (* LC_PROBE49_IS_TRIG = "1'b0" *) (* LC_PROBE49_MU_CNT = "1" *) 
(* LC_PROBE49_PID = "16'b0000000000110001" *) (* LC_PROBE49_TYPE = "1" *) (* LC_PROBE49_WIDTH = "1" *) 
(* LC_PROBE4_IS_DATA = "1'b0" *) (* LC_PROBE4_IS_TRIG = "1'b0" *) (* LC_PROBE4_MU_CNT = "1" *) 
(* LC_PROBE4_PID = "16'b0000000000000100" *) (* LC_PROBE4_TYPE = "1" *) (* LC_PROBE4_WIDTH = "1" *) 
(* LC_PROBE500_IS_DATA = "1'b0" *) (* LC_PROBE500_IS_TRIG = "1'b0" *) (* LC_PROBE500_MU_CNT = "1" *) 
(* LC_PROBE500_PID = "16'b0000000111110100" *) (* LC_PROBE500_TYPE = "1" *) (* LC_PROBE500_WIDTH = "1" *) 
(* LC_PROBE501_IS_DATA = "1'b0" *) (* LC_PROBE501_IS_TRIG = "1'b0" *) (* LC_PROBE501_MU_CNT = "1" *) 
(* LC_PROBE501_PID = "16'b0000000111110101" *) (* LC_PROBE501_TYPE = "1" *) (* LC_PROBE501_WIDTH = "1" *) 
(* LC_PROBE502_IS_DATA = "1'b0" *) (* LC_PROBE502_IS_TRIG = "1'b0" *) (* LC_PROBE502_MU_CNT = "1" *) 
(* LC_PROBE502_PID = "16'b0000000111110110" *) (* LC_PROBE502_TYPE = "1" *) (* LC_PROBE502_WIDTH = "1" *) 
(* LC_PROBE503_IS_DATA = "1'b0" *) (* LC_PROBE503_IS_TRIG = "1'b0" *) (* LC_PROBE503_MU_CNT = "1" *) 
(* LC_PROBE503_PID = "16'b0000000111110111" *) (* LC_PROBE503_TYPE = "1" *) (* LC_PROBE503_WIDTH = "1" *) 
(* LC_PROBE504_IS_DATA = "1'b0" *) (* LC_PROBE504_IS_TRIG = "1'b0" *) (* LC_PROBE504_MU_CNT = "1" *) 
(* LC_PROBE504_PID = "16'b0000000111111000" *) (* LC_PROBE504_TYPE = "1" *) (* LC_PROBE504_WIDTH = "1" *) 
(* LC_PROBE505_IS_DATA = "1'b0" *) (* LC_PROBE505_IS_TRIG = "1'b0" *) (* LC_PROBE505_MU_CNT = "1" *) 
(* LC_PROBE505_PID = "16'b0000000111111001" *) (* LC_PROBE505_TYPE = "1" *) (* LC_PROBE505_WIDTH = "1" *) 
(* LC_PROBE506_IS_DATA = "1'b0" *) (* LC_PROBE506_IS_TRIG = "1'b0" *) (* LC_PROBE506_MU_CNT = "1" *) 
(* LC_PROBE506_PID = "16'b0000000111111010" *) (* LC_PROBE506_TYPE = "1" *) (* LC_PROBE506_WIDTH = "1" *) 
(* LC_PROBE507_IS_DATA = "1'b0" *) (* LC_PROBE507_IS_TRIG = "1'b0" *) (* LC_PROBE507_MU_CNT = "1" *) 
(* LC_PROBE507_PID = "16'b0000000111111011" *) (* LC_PROBE507_TYPE = "1" *) (* LC_PROBE507_WIDTH = "1" *) 
(* LC_PROBE508_IS_DATA = "1'b0" *) (* LC_PROBE508_IS_TRIG = "1'b0" *) (* LC_PROBE508_MU_CNT = "1" *) 
(* LC_PROBE508_PID = "16'b0000000111111100" *) (* LC_PROBE508_TYPE = "1" *) (* LC_PROBE508_WIDTH = "1" *) 
(* LC_PROBE509_IS_DATA = "1'b0" *) (* LC_PROBE509_IS_TRIG = "1'b0" *) (* LC_PROBE509_MU_CNT = "1" *) 
(* LC_PROBE509_PID = "16'b0000000111111101" *) (* LC_PROBE509_TYPE = "1" *) (* LC_PROBE509_WIDTH = "1" *) 
(* LC_PROBE50_IS_DATA = "1'b0" *) (* LC_PROBE50_IS_TRIG = "1'b0" *) (* LC_PROBE50_MU_CNT = "1" *) 
(* LC_PROBE50_PID = "16'b0000000000110010" *) (* LC_PROBE50_TYPE = "1" *) (* LC_PROBE50_WIDTH = "1" *) 
(* LC_PROBE510_IS_DATA = "1'b0" *) (* LC_PROBE510_IS_TRIG = "1'b0" *) (* LC_PROBE510_MU_CNT = "1" *) 
(* LC_PROBE510_PID = "16'b0000000111111110" *) (* LC_PROBE510_TYPE = "1" *) (* LC_PROBE510_WIDTH = "1" *) 
(* LC_PROBE511_IS_DATA = "1'b0" *) (* LC_PROBE511_IS_TRIG = "1'b0" *) (* LC_PROBE511_MU_CNT = "1" *) 
(* LC_PROBE511_PID = "16'b0000000111111111" *) (* LC_PROBE511_TYPE = "1" *) (* LC_PROBE511_WIDTH = "1" *) 
(* LC_PROBE512_IS_DATA = "1'b0" *) (* LC_PROBE512_IS_TRIG = "1'b0" *) (* LC_PROBE512_MU_CNT = "1" *) 
(* LC_PROBE512_PID = "16'b0000001000000000" *) (* LC_PROBE512_TYPE = "1" *) (* LC_PROBE512_WIDTH = "1" *) 
(* LC_PROBE513_IS_DATA = "1'b0" *) (* LC_PROBE513_IS_TRIG = "1'b0" *) (* LC_PROBE513_MU_CNT = "1" *) 
(* LC_PROBE513_PID = "16'b0000001000000001" *) (* LC_PROBE513_TYPE = "1" *) (* LC_PROBE513_WIDTH = "1" *) 
(* LC_PROBE514_IS_DATA = "1'b0" *) (* LC_PROBE514_IS_TRIG = "1'b0" *) (* LC_PROBE514_MU_CNT = "1" *) 
(* LC_PROBE514_PID = "16'b0000001000000010" *) (* LC_PROBE514_TYPE = "1" *) (* LC_PROBE514_WIDTH = "1" *) 
(* LC_PROBE515_IS_DATA = "1'b0" *) (* LC_PROBE515_IS_TRIG = "1'b0" *) (* LC_PROBE515_MU_CNT = "1" *) 
(* LC_PROBE515_PID = "16'b0000001000000011" *) (* LC_PROBE515_TYPE = "1" *) (* LC_PROBE515_WIDTH = "1" *) 
(* LC_PROBE516_IS_DATA = "1'b0" *) (* LC_PROBE516_IS_TRIG = "1'b0" *) (* LC_PROBE516_MU_CNT = "1" *) 
(* LC_PROBE516_PID = "16'b0000001000000100" *) (* LC_PROBE516_TYPE = "1" *) (* LC_PROBE516_WIDTH = "1" *) 
(* LC_PROBE517_IS_DATA = "1'b0" *) (* LC_PROBE517_IS_TRIG = "1'b0" *) (* LC_PROBE517_MU_CNT = "1" *) 
(* LC_PROBE517_PID = "16'b0000001000000101" *) (* LC_PROBE517_TYPE = "1" *) (* LC_PROBE517_WIDTH = "1" *) 
(* LC_PROBE518_IS_DATA = "1'b0" *) (* LC_PROBE518_IS_TRIG = "1'b0" *) (* LC_PROBE518_MU_CNT = "1" *) 
(* LC_PROBE518_PID = "16'b0000001000000110" *) (* LC_PROBE518_TYPE = "1" *) (* LC_PROBE518_WIDTH = "1" *) 
(* LC_PROBE519_IS_DATA = "1'b0" *) (* LC_PROBE519_IS_TRIG = "1'b0" *) (* LC_PROBE519_MU_CNT = "1" *) 
(* LC_PROBE519_PID = "16'b0000001000000111" *) (* LC_PROBE519_TYPE = "1" *) (* LC_PROBE519_WIDTH = "1" *) 
(* LC_PROBE51_IS_DATA = "1'b0" *) (* LC_PROBE51_IS_TRIG = "1'b0" *) (* LC_PROBE51_MU_CNT = "1" *) 
(* LC_PROBE51_PID = "16'b0000000000110011" *) (* LC_PROBE51_TYPE = "1" *) (* LC_PROBE51_WIDTH = "1" *) 
(* LC_PROBE520_IS_DATA = "1'b0" *) (* LC_PROBE520_IS_TRIG = "1'b0" *) (* LC_PROBE520_MU_CNT = "1" *) 
(* LC_PROBE520_PID = "16'b0000001000001000" *) (* LC_PROBE520_TYPE = "1" *) (* LC_PROBE520_WIDTH = "1" *) 
(* LC_PROBE521_IS_DATA = "1'b0" *) (* LC_PROBE521_IS_TRIG = "1'b0" *) (* LC_PROBE521_MU_CNT = "1" *) 
(* LC_PROBE521_PID = "16'b0000001000001001" *) (* LC_PROBE521_TYPE = "1" *) (* LC_PROBE521_WIDTH = "1" *) 
(* LC_PROBE522_IS_DATA = "1'b0" *) (* LC_PROBE522_IS_TRIG = "1'b0" *) (* LC_PROBE522_MU_CNT = "1" *) 
(* LC_PROBE522_PID = "16'b0000001000001010" *) (* LC_PROBE522_TYPE = "1" *) (* LC_PROBE522_WIDTH = "1" *) 
(* LC_PROBE523_IS_DATA = "1'b0" *) (* LC_PROBE523_IS_TRIG = "1'b0" *) (* LC_PROBE523_MU_CNT = "1" *) 
(* LC_PROBE523_PID = "16'b0000001000001011" *) (* LC_PROBE523_TYPE = "1" *) (* LC_PROBE523_WIDTH = "1" *) 
(* LC_PROBE524_IS_DATA = "1'b0" *) (* LC_PROBE524_IS_TRIG = "1'b0" *) (* LC_PROBE524_MU_CNT = "1" *) 
(* LC_PROBE524_PID = "16'b0000001000001100" *) (* LC_PROBE524_TYPE = "1" *) (* LC_PROBE524_WIDTH = "1" *) 
(* LC_PROBE525_IS_DATA = "1'b0" *) (* LC_PROBE525_IS_TRIG = "1'b0" *) (* LC_PROBE525_MU_CNT = "1" *) 
(* LC_PROBE525_PID = "16'b0000001000001101" *) (* LC_PROBE525_TYPE = "1" *) (* LC_PROBE525_WIDTH = "1" *) 
(* LC_PROBE526_IS_DATA = "1'b0" *) (* LC_PROBE526_IS_TRIG = "1'b0" *) (* LC_PROBE526_MU_CNT = "1" *) 
(* LC_PROBE526_PID = "16'b0000001000001110" *) (* LC_PROBE526_TYPE = "1" *) (* LC_PROBE526_WIDTH = "1" *) 
(* LC_PROBE527_IS_DATA = "1'b0" *) (* LC_PROBE527_IS_TRIG = "1'b0" *) (* LC_PROBE527_MU_CNT = "1" *) 
(* LC_PROBE527_PID = "16'b0000001000001111" *) (* LC_PROBE527_TYPE = "1" *) (* LC_PROBE527_WIDTH = "1" *) 
(* LC_PROBE528_IS_DATA = "1'b0" *) (* LC_PROBE528_IS_TRIG = "1'b0" *) (* LC_PROBE528_MU_CNT = "1" *) 
(* LC_PROBE528_PID = "16'b0000001000010000" *) (* LC_PROBE528_TYPE = "1" *) (* LC_PROBE528_WIDTH = "1" *) 
(* LC_PROBE529_IS_DATA = "1'b0" *) (* LC_PROBE529_IS_TRIG = "1'b0" *) (* LC_PROBE529_MU_CNT = "1" *) 
(* LC_PROBE529_PID = "16'b0000001000010001" *) (* LC_PROBE529_TYPE = "1" *) (* LC_PROBE529_WIDTH = "1" *) 
(* LC_PROBE52_IS_DATA = "1'b0" *) (* LC_PROBE52_IS_TRIG = "1'b0" *) (* LC_PROBE52_MU_CNT = "1" *) 
(* LC_PROBE52_PID = "16'b0000000000110100" *) (* LC_PROBE52_TYPE = "1" *) (* LC_PROBE52_WIDTH = "1" *) 
(* LC_PROBE530_IS_DATA = "1'b0" *) (* LC_PROBE530_IS_TRIG = "1'b0" *) (* LC_PROBE530_MU_CNT = "1" *) 
(* LC_PROBE530_PID = "16'b0000001000010010" *) (* LC_PROBE530_TYPE = "1" *) (* LC_PROBE530_WIDTH = "1" *) 
(* LC_PROBE531_IS_DATA = "1'b0" *) (* LC_PROBE531_IS_TRIG = "1'b0" *) (* LC_PROBE531_MU_CNT = "1" *) 
(* LC_PROBE531_PID = "16'b0000001000010011" *) (* LC_PROBE531_TYPE = "1" *) (* LC_PROBE531_WIDTH = "1" *) 
(* LC_PROBE532_IS_DATA = "1'b0" *) (* LC_PROBE532_IS_TRIG = "1'b0" *) (* LC_PROBE532_MU_CNT = "1" *) 
(* LC_PROBE532_PID = "16'b0000001000010100" *) (* LC_PROBE532_TYPE = "1" *) (* LC_PROBE532_WIDTH = "1" *) 
(* LC_PROBE533_IS_DATA = "1'b0" *) (* LC_PROBE533_IS_TRIG = "1'b0" *) (* LC_PROBE533_MU_CNT = "1" *) 
(* LC_PROBE533_PID = "16'b0000001000010101" *) (* LC_PROBE533_TYPE = "1" *) (* LC_PROBE533_WIDTH = "1" *) 
(* LC_PROBE534_IS_DATA = "1'b0" *) (* LC_PROBE534_IS_TRIG = "1'b0" *) (* LC_PROBE534_MU_CNT = "1" *) 
(* LC_PROBE534_PID = "16'b0000001000010110" *) (* LC_PROBE534_TYPE = "1" *) (* LC_PROBE534_WIDTH = "1" *) 
(* LC_PROBE535_IS_DATA = "1'b0" *) (* LC_PROBE535_IS_TRIG = "1'b0" *) (* LC_PROBE535_MU_CNT = "1" *) 
(* LC_PROBE535_PID = "16'b0000001000010111" *) (* LC_PROBE535_TYPE = "1" *) (* LC_PROBE535_WIDTH = "1" *) 
(* LC_PROBE536_IS_DATA = "1'b0" *) (* LC_PROBE536_IS_TRIG = "1'b0" *) (* LC_PROBE536_MU_CNT = "1" *) 
(* LC_PROBE536_PID = "16'b0000001000011000" *) (* LC_PROBE536_TYPE = "1" *) (* LC_PROBE536_WIDTH = "1" *) 
(* LC_PROBE537_IS_DATA = "1'b0" *) (* LC_PROBE537_IS_TRIG = "1'b0" *) (* LC_PROBE537_MU_CNT = "1" *) 
(* LC_PROBE537_PID = "16'b0000001000011001" *) (* LC_PROBE537_TYPE = "1" *) (* LC_PROBE537_WIDTH = "1" *) 
(* LC_PROBE538_IS_DATA = "1'b0" *) (* LC_PROBE538_IS_TRIG = "1'b0" *) (* LC_PROBE538_MU_CNT = "1" *) 
(* LC_PROBE538_PID = "16'b0000001000011010" *) (* LC_PROBE538_TYPE = "1" *) (* LC_PROBE538_WIDTH = "1" *) 
(* LC_PROBE539_IS_DATA = "1'b0" *) (* LC_PROBE539_IS_TRIG = "1'b0" *) (* LC_PROBE539_MU_CNT = "1" *) 
(* LC_PROBE539_PID = "16'b0000001000011011" *) (* LC_PROBE539_TYPE = "1" *) (* LC_PROBE539_WIDTH = "1" *) 
(* LC_PROBE53_IS_DATA = "1'b0" *) (* LC_PROBE53_IS_TRIG = "1'b0" *) (* LC_PROBE53_MU_CNT = "1" *) 
(* LC_PROBE53_PID = "16'b0000000000110101" *) (* LC_PROBE53_TYPE = "1" *) (* LC_PROBE53_WIDTH = "1" *) 
(* LC_PROBE540_IS_DATA = "1'b0" *) (* LC_PROBE540_IS_TRIG = "1'b0" *) (* LC_PROBE540_MU_CNT = "1" *) 
(* LC_PROBE540_PID = "16'b0000001000011100" *) (* LC_PROBE540_TYPE = "1" *) (* LC_PROBE540_WIDTH = "1" *) 
(* LC_PROBE541_IS_DATA = "1'b0" *) (* LC_PROBE541_IS_TRIG = "1'b0" *) (* LC_PROBE541_MU_CNT = "1" *) 
(* LC_PROBE541_PID = "16'b0000001000011101" *) (* LC_PROBE541_TYPE = "1" *) (* LC_PROBE541_WIDTH = "1" *) 
(* LC_PROBE542_IS_DATA = "1'b0" *) (* LC_PROBE542_IS_TRIG = "1'b0" *) (* LC_PROBE542_MU_CNT = "1" *) 
(* LC_PROBE542_PID = "16'b0000001000011110" *) (* LC_PROBE542_TYPE = "1" *) (* LC_PROBE542_WIDTH = "1" *) 
(* LC_PROBE543_IS_DATA = "1'b0" *) (* LC_PROBE543_IS_TRIG = "1'b0" *) (* LC_PROBE543_MU_CNT = "1" *) 
(* LC_PROBE543_PID = "16'b0000001000011111" *) (* LC_PROBE543_TYPE = "1" *) (* LC_PROBE543_WIDTH = "1" *) 
(* LC_PROBE544_IS_DATA = "1'b0" *) (* LC_PROBE544_IS_TRIG = "1'b0" *) (* LC_PROBE544_MU_CNT = "1" *) 
(* LC_PROBE544_PID = "16'b0000001000100000" *) (* LC_PROBE544_TYPE = "1" *) (* LC_PROBE544_WIDTH = "1" *) 
(* LC_PROBE545_IS_DATA = "1'b0" *) (* LC_PROBE545_IS_TRIG = "1'b0" *) (* LC_PROBE545_MU_CNT = "1" *) 
(* LC_PROBE545_PID = "16'b0000001000100001" *) (* LC_PROBE545_TYPE = "1" *) (* LC_PROBE545_WIDTH = "1" *) 
(* LC_PROBE546_IS_DATA = "1'b0" *) (* LC_PROBE546_IS_TRIG = "1'b0" *) (* LC_PROBE546_MU_CNT = "1" *) 
(* LC_PROBE546_PID = "16'b0000001000100010" *) (* LC_PROBE546_TYPE = "1" *) (* LC_PROBE546_WIDTH = "1" *) 
(* LC_PROBE547_IS_DATA = "1'b0" *) (* LC_PROBE547_IS_TRIG = "1'b0" *) (* LC_PROBE547_MU_CNT = "1" *) 
(* LC_PROBE547_PID = "16'b0000001000100011" *) (* LC_PROBE547_TYPE = "1" *) (* LC_PROBE547_WIDTH = "1" *) 
(* LC_PROBE548_IS_DATA = "1'b0" *) (* LC_PROBE548_IS_TRIG = "1'b0" *) (* LC_PROBE548_MU_CNT = "1" *) 
(* LC_PROBE548_PID = "16'b0000001000100100" *) (* LC_PROBE548_TYPE = "1" *) (* LC_PROBE548_WIDTH = "1" *) 
(* LC_PROBE549_IS_DATA = "1'b0" *) (* LC_PROBE549_IS_TRIG = "1'b0" *) (* LC_PROBE549_MU_CNT = "1" *) 
(* LC_PROBE549_PID = "16'b0000001000100101" *) (* LC_PROBE549_TYPE = "1" *) (* LC_PROBE549_WIDTH = "1" *) 
(* LC_PROBE54_IS_DATA = "1'b0" *) (* LC_PROBE54_IS_TRIG = "1'b0" *) (* LC_PROBE54_MU_CNT = "1" *) 
(* LC_PROBE54_PID = "16'b0000000000110110" *) (* LC_PROBE54_TYPE = "1" *) (* LC_PROBE54_WIDTH = "1" *) 
(* LC_PROBE550_IS_DATA = "1'b0" *) (* LC_PROBE550_IS_TRIG = "1'b0" *) (* LC_PROBE550_MU_CNT = "1" *) 
(* LC_PROBE550_PID = "16'b0000001000100110" *) (* LC_PROBE550_TYPE = "1" *) (* LC_PROBE550_WIDTH = "1" *) 
(* LC_PROBE551_IS_DATA = "1'b0" *) (* LC_PROBE551_IS_TRIG = "1'b0" *) (* LC_PROBE551_MU_CNT = "1" *) 
(* LC_PROBE551_PID = "16'b0000001000100111" *) (* LC_PROBE551_TYPE = "1" *) (* LC_PROBE551_WIDTH = "1" *) 
(* LC_PROBE552_IS_DATA = "1'b0" *) (* LC_PROBE552_IS_TRIG = "1'b0" *) (* LC_PROBE552_MU_CNT = "1" *) 
(* LC_PROBE552_PID = "16'b0000001000101000" *) (* LC_PROBE552_TYPE = "1" *) (* LC_PROBE552_WIDTH = "1" *) 
(* LC_PROBE553_IS_DATA = "1'b0" *) (* LC_PROBE553_IS_TRIG = "1'b0" *) (* LC_PROBE553_MU_CNT = "1" *) 
(* LC_PROBE553_PID = "16'b0000001000101001" *) (* LC_PROBE553_TYPE = "1" *) (* LC_PROBE553_WIDTH = "1" *) 
(* LC_PROBE554_IS_DATA = "1'b0" *) (* LC_PROBE554_IS_TRIG = "1'b0" *) (* LC_PROBE554_MU_CNT = "1" *) 
(* LC_PROBE554_PID = "16'b0000001000101010" *) (* LC_PROBE554_TYPE = "1" *) (* LC_PROBE554_WIDTH = "1" *) 
(* LC_PROBE555_IS_DATA = "1'b0" *) (* LC_PROBE555_IS_TRIG = "1'b0" *) (* LC_PROBE555_MU_CNT = "1" *) 
(* LC_PROBE555_PID = "16'b0000001000101011" *) (* LC_PROBE555_TYPE = "1" *) (* LC_PROBE555_WIDTH = "1" *) 
(* LC_PROBE556_IS_DATA = "1'b0" *) (* LC_PROBE556_IS_TRIG = "1'b0" *) (* LC_PROBE556_MU_CNT = "1" *) 
(* LC_PROBE556_PID = "16'b0000001000101100" *) (* LC_PROBE556_TYPE = "1" *) (* LC_PROBE556_WIDTH = "1" *) 
(* LC_PROBE557_IS_DATA = "1'b0" *) (* LC_PROBE557_IS_TRIG = "1'b0" *) (* LC_PROBE557_MU_CNT = "1" *) 
(* LC_PROBE557_PID = "16'b0000001000101101" *) (* LC_PROBE557_TYPE = "1" *) (* LC_PROBE557_WIDTH = "1" *) 
(* LC_PROBE558_IS_DATA = "1'b0" *) (* LC_PROBE558_IS_TRIG = "1'b0" *) (* LC_PROBE558_MU_CNT = "1" *) 
(* LC_PROBE558_PID = "16'b0000001000101110" *) (* LC_PROBE558_TYPE = "1" *) (* LC_PROBE558_WIDTH = "1" *) 
(* LC_PROBE559_IS_DATA = "1'b0" *) (* LC_PROBE559_IS_TRIG = "1'b0" *) (* LC_PROBE559_MU_CNT = "1" *) 
(* LC_PROBE559_PID = "16'b0000001000101111" *) (* LC_PROBE559_TYPE = "1" *) (* LC_PROBE559_WIDTH = "1" *) 
(* LC_PROBE55_IS_DATA = "1'b0" *) (* LC_PROBE55_IS_TRIG = "1'b0" *) (* LC_PROBE55_MU_CNT = "1" *) 
(* LC_PROBE55_PID = "16'b0000000000110111" *) (* LC_PROBE55_TYPE = "1" *) (* LC_PROBE55_WIDTH = "1" *) 
(* LC_PROBE560_IS_DATA = "1'b0" *) (* LC_PROBE560_IS_TRIG = "1'b0" *) (* LC_PROBE560_MU_CNT = "1" *) 
(* LC_PROBE560_PID = "16'b0000001000110000" *) (* LC_PROBE560_TYPE = "1" *) (* LC_PROBE560_WIDTH = "1" *) 
(* LC_PROBE561_IS_DATA = "1'b0" *) (* LC_PROBE561_IS_TRIG = "1'b0" *) (* LC_PROBE561_MU_CNT = "1" *) 
(* LC_PROBE561_PID = "16'b0000001000110001" *) (* LC_PROBE561_TYPE = "1" *) (* LC_PROBE561_WIDTH = "1" *) 
(* LC_PROBE562_IS_DATA = "1'b0" *) (* LC_PROBE562_IS_TRIG = "1'b0" *) (* LC_PROBE562_MU_CNT = "1" *) 
(* LC_PROBE562_PID = "16'b0000001000110010" *) (* LC_PROBE562_TYPE = "1" *) (* LC_PROBE562_WIDTH = "1" *) 
(* LC_PROBE563_IS_DATA = "1'b0" *) (* LC_PROBE563_IS_TRIG = "1'b0" *) (* LC_PROBE563_MU_CNT = "1" *) 
(* LC_PROBE563_PID = "16'b0000001000110011" *) (* LC_PROBE563_TYPE = "1" *) (* LC_PROBE563_WIDTH = "1" *) 
(* LC_PROBE564_IS_DATA = "1'b0" *) (* LC_PROBE564_IS_TRIG = "1'b0" *) (* LC_PROBE564_MU_CNT = "1" *) 
(* LC_PROBE564_PID = "16'b0000001000110100" *) (* LC_PROBE564_TYPE = "1" *) (* LC_PROBE564_WIDTH = "1" *) 
(* LC_PROBE565_IS_DATA = "1'b0" *) (* LC_PROBE565_IS_TRIG = "1'b0" *) (* LC_PROBE565_MU_CNT = "1" *) 
(* LC_PROBE565_PID = "16'b0000001000110101" *) (* LC_PROBE565_TYPE = "1" *) (* LC_PROBE565_WIDTH = "1" *) 
(* LC_PROBE566_IS_DATA = "1'b0" *) (* LC_PROBE566_IS_TRIG = "1'b0" *) (* LC_PROBE566_MU_CNT = "1" *) 
(* LC_PROBE566_PID = "16'b0000001000110110" *) (* LC_PROBE566_TYPE = "1" *) (* LC_PROBE566_WIDTH = "1" *) 
(* LC_PROBE567_IS_DATA = "1'b0" *) (* LC_PROBE567_IS_TRIG = "1'b0" *) (* LC_PROBE567_MU_CNT = "1" *) 
(* LC_PROBE567_PID = "16'b0000001000110111" *) (* LC_PROBE567_TYPE = "1" *) (* LC_PROBE567_WIDTH = "1" *) 
(* LC_PROBE568_IS_DATA = "1'b0" *) (* LC_PROBE568_IS_TRIG = "1'b0" *) (* LC_PROBE568_MU_CNT = "1" *) 
(* LC_PROBE568_PID = "16'b0000001000111000" *) (* LC_PROBE568_TYPE = "1" *) (* LC_PROBE568_WIDTH = "1" *) 
(* LC_PROBE569_IS_DATA = "1'b0" *) (* LC_PROBE569_IS_TRIG = "1'b0" *) (* LC_PROBE569_MU_CNT = "1" *) 
(* LC_PROBE569_PID = "16'b0000001000111001" *) (* LC_PROBE569_TYPE = "1" *) (* LC_PROBE569_WIDTH = "1" *) 
(* LC_PROBE56_IS_DATA = "1'b0" *) (* LC_PROBE56_IS_TRIG = "1'b0" *) (* LC_PROBE56_MU_CNT = "1" *) 
(* LC_PROBE56_PID = "16'b0000000000111000" *) (* LC_PROBE56_TYPE = "1" *) (* LC_PROBE56_WIDTH = "1" *) 
(* LC_PROBE570_IS_DATA = "1'b0" *) (* LC_PROBE570_IS_TRIG = "1'b0" *) (* LC_PROBE570_MU_CNT = "1" *) 
(* LC_PROBE570_PID = "16'b0000001000111010" *) (* LC_PROBE570_TYPE = "1" *) (* LC_PROBE570_WIDTH = "1" *) 
(* LC_PROBE571_IS_DATA = "1'b0" *) (* LC_PROBE571_IS_TRIG = "1'b0" *) (* LC_PROBE571_MU_CNT = "1" *) 
(* LC_PROBE571_PID = "16'b0000001000111011" *) (* LC_PROBE571_TYPE = "1" *) (* LC_PROBE571_WIDTH = "1" *) 
(* LC_PROBE572_IS_DATA = "1'b0" *) (* LC_PROBE572_IS_TRIG = "1'b0" *) (* LC_PROBE572_MU_CNT = "1" *) 
(* LC_PROBE572_PID = "16'b0000001000111100" *) (* LC_PROBE572_TYPE = "1" *) (* LC_PROBE572_WIDTH = "1" *) 
(* LC_PROBE573_IS_DATA = "1'b0" *) (* LC_PROBE573_IS_TRIG = "1'b0" *) (* LC_PROBE573_MU_CNT = "1" *) 
(* LC_PROBE573_PID = "16'b0000001000111101" *) (* LC_PROBE573_TYPE = "1" *) (* LC_PROBE573_WIDTH = "1" *) 
(* LC_PROBE574_IS_DATA = "1'b0" *) (* LC_PROBE574_IS_TRIG = "1'b0" *) (* LC_PROBE574_MU_CNT = "1" *) 
(* LC_PROBE574_PID = "16'b0000001000111110" *) (* LC_PROBE574_TYPE = "1" *) (* LC_PROBE574_WIDTH = "1" *) 
(* LC_PROBE575_IS_DATA = "1'b0" *) (* LC_PROBE575_IS_TRIG = "1'b0" *) (* LC_PROBE575_MU_CNT = "1" *) 
(* LC_PROBE575_PID = "16'b0000001000111111" *) (* LC_PROBE575_TYPE = "1" *) (* LC_PROBE575_WIDTH = "1" *) 
(* LC_PROBE576_IS_DATA = "1'b0" *) (* LC_PROBE576_IS_TRIG = "1'b0" *) (* LC_PROBE576_MU_CNT = "1" *) 
(* LC_PROBE576_PID = "16'b0000001001000000" *) (* LC_PROBE576_TYPE = "1" *) (* LC_PROBE576_WIDTH = "1" *) 
(* LC_PROBE577_IS_DATA = "1'b0" *) (* LC_PROBE577_IS_TRIG = "1'b0" *) (* LC_PROBE577_MU_CNT = "1" *) 
(* LC_PROBE577_PID = "16'b0000001001000001" *) (* LC_PROBE577_TYPE = "1" *) (* LC_PROBE577_WIDTH = "1" *) 
(* LC_PROBE578_IS_DATA = "1'b0" *) (* LC_PROBE578_IS_TRIG = "1'b0" *) (* LC_PROBE578_MU_CNT = "1" *) 
(* LC_PROBE578_PID = "16'b0000001001000010" *) (* LC_PROBE578_TYPE = "1" *) (* LC_PROBE578_WIDTH = "1" *) 
(* LC_PROBE579_IS_DATA = "1'b0" *) (* LC_PROBE579_IS_TRIG = "1'b0" *) (* LC_PROBE579_MU_CNT = "1" *) 
(* LC_PROBE579_PID = "16'b0000001001000011" *) (* LC_PROBE579_TYPE = "1" *) (* LC_PROBE579_WIDTH = "1" *) 
(* LC_PROBE57_IS_DATA = "1'b0" *) (* LC_PROBE57_IS_TRIG = "1'b0" *) (* LC_PROBE57_MU_CNT = "1" *) 
(* LC_PROBE57_PID = "16'b0000000000111001" *) (* LC_PROBE57_TYPE = "1" *) (* LC_PROBE57_WIDTH = "1" *) 
(* LC_PROBE580_IS_DATA = "1'b0" *) (* LC_PROBE580_IS_TRIG = "1'b0" *) (* LC_PROBE580_MU_CNT = "1" *) 
(* LC_PROBE580_PID = "16'b0000001001000100" *) (* LC_PROBE580_TYPE = "1" *) (* LC_PROBE580_WIDTH = "1" *) 
(* LC_PROBE581_IS_DATA = "1'b0" *) (* LC_PROBE581_IS_TRIG = "1'b0" *) (* LC_PROBE581_MU_CNT = "1" *) 
(* LC_PROBE581_PID = "16'b0000001001000101" *) (* LC_PROBE581_TYPE = "1" *) (* LC_PROBE581_WIDTH = "1" *) 
(* LC_PROBE582_IS_DATA = "1'b0" *) (* LC_PROBE582_IS_TRIG = "1'b0" *) (* LC_PROBE582_MU_CNT = "1" *) 
(* LC_PROBE582_PID = "16'b0000001001000110" *) (* LC_PROBE582_TYPE = "1" *) (* LC_PROBE582_WIDTH = "1" *) 
(* LC_PROBE583_IS_DATA = "1'b0" *) (* LC_PROBE583_IS_TRIG = "1'b0" *) (* LC_PROBE583_MU_CNT = "1" *) 
(* LC_PROBE583_PID = "16'b0000001001000111" *) (* LC_PROBE583_TYPE = "1" *) (* LC_PROBE583_WIDTH = "1" *) 
(* LC_PROBE584_IS_DATA = "1'b0" *) (* LC_PROBE584_IS_TRIG = "1'b0" *) (* LC_PROBE584_MU_CNT = "1" *) 
(* LC_PROBE584_PID = "16'b0000001001001000" *) (* LC_PROBE584_TYPE = "1" *) (* LC_PROBE584_WIDTH = "1" *) 
(* LC_PROBE585_IS_DATA = "1'b0" *) (* LC_PROBE585_IS_TRIG = "1'b0" *) (* LC_PROBE585_MU_CNT = "1" *) 
(* LC_PROBE585_PID = "16'b0000001001001001" *) (* LC_PROBE585_TYPE = "1" *) (* LC_PROBE585_WIDTH = "1" *) 
(* LC_PROBE586_IS_DATA = "1'b0" *) (* LC_PROBE586_IS_TRIG = "1'b0" *) (* LC_PROBE586_MU_CNT = "1" *) 
(* LC_PROBE586_PID = "16'b0000001001001010" *) (* LC_PROBE586_TYPE = "1" *) (* LC_PROBE586_WIDTH = "1" *) 
(* LC_PROBE587_IS_DATA = "1'b0" *) (* LC_PROBE587_IS_TRIG = "1'b0" *) (* LC_PROBE587_MU_CNT = "1" *) 
(* LC_PROBE587_PID = "16'b0000001001001011" *) (* LC_PROBE587_TYPE = "1" *) (* LC_PROBE587_WIDTH = "1" *) 
(* LC_PROBE588_IS_DATA = "1'b0" *) (* LC_PROBE588_IS_TRIG = "1'b0" *) (* LC_PROBE588_MU_CNT = "1" *) 
(* LC_PROBE588_PID = "16'b0000001001001100" *) (* LC_PROBE588_TYPE = "1" *) (* LC_PROBE588_WIDTH = "1" *) 
(* LC_PROBE589_IS_DATA = "1'b0" *) (* LC_PROBE589_IS_TRIG = "1'b0" *) (* LC_PROBE589_MU_CNT = "1" *) 
(* LC_PROBE589_PID = "16'b0000001001001101" *) (* LC_PROBE589_TYPE = "1" *) (* LC_PROBE589_WIDTH = "1" *) 
(* LC_PROBE58_IS_DATA = "1'b0" *) (* LC_PROBE58_IS_TRIG = "1'b0" *) (* LC_PROBE58_MU_CNT = "1" *) 
(* LC_PROBE58_PID = "16'b0000000000111010" *) (* LC_PROBE58_TYPE = "1" *) (* LC_PROBE58_WIDTH = "1" *) 
(* LC_PROBE590_IS_DATA = "1'b0" *) (* LC_PROBE590_IS_TRIG = "1'b0" *) (* LC_PROBE590_MU_CNT = "1" *) 
(* LC_PROBE590_PID = "16'b0000001001001110" *) (* LC_PROBE590_TYPE = "1" *) (* LC_PROBE590_WIDTH = "1" *) 
(* LC_PROBE591_IS_DATA = "1'b0" *) (* LC_PROBE591_IS_TRIG = "1'b0" *) (* LC_PROBE591_MU_CNT = "1" *) 
(* LC_PROBE591_PID = "16'b0000001001001111" *) (* LC_PROBE591_TYPE = "1" *) (* LC_PROBE591_WIDTH = "1" *) 
(* LC_PROBE592_IS_DATA = "1'b0" *) (* LC_PROBE592_IS_TRIG = "1'b0" *) (* LC_PROBE592_MU_CNT = "1" *) 
(* LC_PROBE592_PID = "16'b0000001001010000" *) (* LC_PROBE592_TYPE = "1" *) (* LC_PROBE592_WIDTH = "1" *) 
(* LC_PROBE593_IS_DATA = "1'b0" *) (* LC_PROBE593_IS_TRIG = "1'b0" *) (* LC_PROBE593_MU_CNT = "1" *) 
(* LC_PROBE593_PID = "16'b0000001001010001" *) (* LC_PROBE593_TYPE = "1" *) (* LC_PROBE593_WIDTH = "1" *) 
(* LC_PROBE594_IS_DATA = "1'b0" *) (* LC_PROBE594_IS_TRIG = "1'b0" *) (* LC_PROBE594_MU_CNT = "1" *) 
(* LC_PROBE594_PID = "16'b0000001001010010" *) (* LC_PROBE594_TYPE = "1" *) (* LC_PROBE594_WIDTH = "1" *) 
(* LC_PROBE595_IS_DATA = "1'b0" *) (* LC_PROBE595_IS_TRIG = "1'b0" *) (* LC_PROBE595_MU_CNT = "1" *) 
(* LC_PROBE595_PID = "16'b0000001001010011" *) (* LC_PROBE595_TYPE = "1" *) (* LC_PROBE595_WIDTH = "1" *) 
(* LC_PROBE596_IS_DATA = "1'b0" *) (* LC_PROBE596_IS_TRIG = "1'b0" *) (* LC_PROBE596_MU_CNT = "1" *) 
(* LC_PROBE596_PID = "16'b0000001001010100" *) (* LC_PROBE596_TYPE = "1" *) (* LC_PROBE596_WIDTH = "1" *) 
(* LC_PROBE597_IS_DATA = "1'b0" *) (* LC_PROBE597_IS_TRIG = "1'b0" *) (* LC_PROBE597_MU_CNT = "1" *) 
(* LC_PROBE597_PID = "16'b0000001001010101" *) (* LC_PROBE597_TYPE = "1" *) (* LC_PROBE597_WIDTH = "1" *) 
(* LC_PROBE598_IS_DATA = "1'b0" *) (* LC_PROBE598_IS_TRIG = "1'b0" *) (* LC_PROBE598_MU_CNT = "1" *) 
(* LC_PROBE598_PID = "16'b0000001001010110" *) (* LC_PROBE598_TYPE = "1" *) (* LC_PROBE598_WIDTH = "1" *) 
(* LC_PROBE599_IS_DATA = "1'b0" *) (* LC_PROBE599_IS_TRIG = "1'b0" *) (* LC_PROBE599_MU_CNT = "1" *) 
(* LC_PROBE599_PID = "16'b0000001001010111" *) (* LC_PROBE599_TYPE = "1" *) (* LC_PROBE599_WIDTH = "1" *) 
(* LC_PROBE59_IS_DATA = "1'b0" *) (* LC_PROBE59_IS_TRIG = "1'b0" *) (* LC_PROBE59_MU_CNT = "1" *) 
(* LC_PROBE59_PID = "16'b0000000000111011" *) (* LC_PROBE59_TYPE = "1" *) (* LC_PROBE59_WIDTH = "1" *) 
(* LC_PROBE5_IS_DATA = "1'b0" *) (* LC_PROBE5_IS_TRIG = "1'b0" *) (* LC_PROBE5_MU_CNT = "1" *) 
(* LC_PROBE5_PID = "16'b0000000000000101" *) (* LC_PROBE5_TYPE = "1" *) (* LC_PROBE5_WIDTH = "1" *) 
(* LC_PROBE600_IS_DATA = "1'b0" *) (* LC_PROBE600_IS_TRIG = "1'b0" *) (* LC_PROBE600_MU_CNT = "1" *) 
(* LC_PROBE600_PID = "16'b0000001001011000" *) (* LC_PROBE600_TYPE = "1" *) (* LC_PROBE600_WIDTH = "1" *) 
(* LC_PROBE601_IS_DATA = "1'b0" *) (* LC_PROBE601_IS_TRIG = "1'b0" *) (* LC_PROBE601_MU_CNT = "1" *) 
(* LC_PROBE601_PID = "16'b0000001001011001" *) (* LC_PROBE601_TYPE = "1" *) (* LC_PROBE601_WIDTH = "1" *) 
(* LC_PROBE602_IS_DATA = "1'b0" *) (* LC_PROBE602_IS_TRIG = "1'b0" *) (* LC_PROBE602_MU_CNT = "1" *) 
(* LC_PROBE602_PID = "16'b0000001001011010" *) (* LC_PROBE602_TYPE = "1" *) (* LC_PROBE602_WIDTH = "1" *) 
(* LC_PROBE603_IS_DATA = "1'b0" *) (* LC_PROBE603_IS_TRIG = "1'b0" *) (* LC_PROBE603_MU_CNT = "1" *) 
(* LC_PROBE603_PID = "16'b0000001001011011" *) (* LC_PROBE603_TYPE = "1" *) (* LC_PROBE603_WIDTH = "1" *) 
(* LC_PROBE604_IS_DATA = "1'b0" *) (* LC_PROBE604_IS_TRIG = "1'b0" *) (* LC_PROBE604_MU_CNT = "1" *) 
(* LC_PROBE604_PID = "16'b0000001001011100" *) (* LC_PROBE604_TYPE = "1" *) (* LC_PROBE604_WIDTH = "1" *) 
(* LC_PROBE605_IS_DATA = "1'b0" *) (* LC_PROBE605_IS_TRIG = "1'b0" *) (* LC_PROBE605_MU_CNT = "1" *) 
(* LC_PROBE605_PID = "16'b0000001001011101" *) (* LC_PROBE605_TYPE = "1" *) (* LC_PROBE605_WIDTH = "1" *) 
(* LC_PROBE606_IS_DATA = "1'b0" *) (* LC_PROBE606_IS_TRIG = "1'b0" *) (* LC_PROBE606_MU_CNT = "1" *) 
(* LC_PROBE606_PID = "16'b0000001001011110" *) (* LC_PROBE606_TYPE = "1" *) (* LC_PROBE606_WIDTH = "1" *) 
(* LC_PROBE607_IS_DATA = "1'b0" *) (* LC_PROBE607_IS_TRIG = "1'b0" *) (* LC_PROBE607_MU_CNT = "1" *) 
(* LC_PROBE607_PID = "16'b0000001001011111" *) (* LC_PROBE607_TYPE = "1" *) (* LC_PROBE607_WIDTH = "1" *) 
(* LC_PROBE608_IS_DATA = "1'b0" *) (* LC_PROBE608_IS_TRIG = "1'b0" *) (* LC_PROBE608_MU_CNT = "1" *) 
(* LC_PROBE608_PID = "16'b0000001001100000" *) (* LC_PROBE608_TYPE = "1" *) (* LC_PROBE608_WIDTH = "1" *) 
(* LC_PROBE609_IS_DATA = "1'b0" *) (* LC_PROBE609_IS_TRIG = "1'b0" *) (* LC_PROBE609_MU_CNT = "1" *) 
(* LC_PROBE609_PID = "16'b0000001001100001" *) (* LC_PROBE609_TYPE = "1" *) (* LC_PROBE609_WIDTH = "1" *) 
(* LC_PROBE60_IS_DATA = "1'b0" *) (* LC_PROBE60_IS_TRIG = "1'b0" *) (* LC_PROBE60_MU_CNT = "1" *) 
(* LC_PROBE60_PID = "16'b0000000000111100" *) (* LC_PROBE60_TYPE = "1" *) (* LC_PROBE60_WIDTH = "1" *) 
(* LC_PROBE610_IS_DATA = "1'b0" *) (* LC_PROBE610_IS_TRIG = "1'b0" *) (* LC_PROBE610_MU_CNT = "1" *) 
(* LC_PROBE610_PID = "16'b0000001001100010" *) (* LC_PROBE610_TYPE = "1" *) (* LC_PROBE610_WIDTH = "1" *) 
(* LC_PROBE611_IS_DATA = "1'b0" *) (* LC_PROBE611_IS_TRIG = "1'b0" *) (* LC_PROBE611_MU_CNT = "1" *) 
(* LC_PROBE611_PID = "16'b0000001001100011" *) (* LC_PROBE611_TYPE = "1" *) (* LC_PROBE611_WIDTH = "1" *) 
(* LC_PROBE612_IS_DATA = "1'b0" *) (* LC_PROBE612_IS_TRIG = "1'b0" *) (* LC_PROBE612_MU_CNT = "1" *) 
(* LC_PROBE612_PID = "16'b0000001001100100" *) (* LC_PROBE612_TYPE = "1" *) (* LC_PROBE612_WIDTH = "1" *) 
(* LC_PROBE613_IS_DATA = "1'b0" *) (* LC_PROBE613_IS_TRIG = "1'b0" *) (* LC_PROBE613_MU_CNT = "1" *) 
(* LC_PROBE613_PID = "16'b0000001001100101" *) (* LC_PROBE613_TYPE = "1" *) (* LC_PROBE613_WIDTH = "1" *) 
(* LC_PROBE614_IS_DATA = "1'b0" *) (* LC_PROBE614_IS_TRIG = "1'b0" *) (* LC_PROBE614_MU_CNT = "1" *) 
(* LC_PROBE614_PID = "16'b0000001001100110" *) (* LC_PROBE614_TYPE = "1" *) (* LC_PROBE614_WIDTH = "1" *) 
(* LC_PROBE615_IS_DATA = "1'b0" *) (* LC_PROBE615_IS_TRIG = "1'b0" *) (* LC_PROBE615_MU_CNT = "1" *) 
(* LC_PROBE615_PID = "16'b0000001001100111" *) (* LC_PROBE615_TYPE = "1" *) (* LC_PROBE615_WIDTH = "1" *) 
(* LC_PROBE616_IS_DATA = "1'b0" *) (* LC_PROBE616_IS_TRIG = "1'b0" *) (* LC_PROBE616_MU_CNT = "1" *) 
(* LC_PROBE616_PID = "16'b0000001001101000" *) (* LC_PROBE616_TYPE = "1" *) (* LC_PROBE616_WIDTH = "1" *) 
(* LC_PROBE617_IS_DATA = "1'b0" *) (* LC_PROBE617_IS_TRIG = "1'b0" *) (* LC_PROBE617_MU_CNT = "1" *) 
(* LC_PROBE617_PID = "16'b0000001001101001" *) (* LC_PROBE617_TYPE = "1" *) (* LC_PROBE617_WIDTH = "1" *) 
(* LC_PROBE618_IS_DATA = "1'b0" *) (* LC_PROBE618_IS_TRIG = "1'b0" *) (* LC_PROBE618_MU_CNT = "1" *) 
(* LC_PROBE618_PID = "16'b0000001001101010" *) (* LC_PROBE618_TYPE = "1" *) (* LC_PROBE618_WIDTH = "1" *) 
(* LC_PROBE619_IS_DATA = "1'b0" *) (* LC_PROBE619_IS_TRIG = "1'b0" *) (* LC_PROBE619_MU_CNT = "1" *) 
(* LC_PROBE619_PID = "16'b0000001001101011" *) (* LC_PROBE619_TYPE = "1" *) (* LC_PROBE619_WIDTH = "1" *) 
(* LC_PROBE61_IS_DATA = "1'b0" *) (* LC_PROBE61_IS_TRIG = "1'b0" *) (* LC_PROBE61_MU_CNT = "1" *) 
(* LC_PROBE61_PID = "16'b0000000000111101" *) (* LC_PROBE61_TYPE = "1" *) (* LC_PROBE61_WIDTH = "1" *) 
(* LC_PROBE620_IS_DATA = "1'b0" *) (* LC_PROBE620_IS_TRIG = "1'b0" *) (* LC_PROBE620_MU_CNT = "1" *) 
(* LC_PROBE620_PID = "16'b0000001001101100" *) (* LC_PROBE620_TYPE = "1" *) (* LC_PROBE620_WIDTH = "1" *) 
(* LC_PROBE621_IS_DATA = "1'b0" *) (* LC_PROBE621_IS_TRIG = "1'b0" *) (* LC_PROBE621_MU_CNT = "1" *) 
(* LC_PROBE621_PID = "16'b0000001001101101" *) (* LC_PROBE621_TYPE = "1" *) (* LC_PROBE621_WIDTH = "1" *) 
(* LC_PROBE622_IS_DATA = "1'b0" *) (* LC_PROBE622_IS_TRIG = "1'b0" *) (* LC_PROBE622_MU_CNT = "1" *) 
(* LC_PROBE622_PID = "16'b0000001001101110" *) (* LC_PROBE622_TYPE = "1" *) (* LC_PROBE622_WIDTH = "1" *) 
(* LC_PROBE623_IS_DATA = "1'b0" *) (* LC_PROBE623_IS_TRIG = "1'b0" *) (* LC_PROBE623_MU_CNT = "1" *) 
(* LC_PROBE623_PID = "16'b0000001001101111" *) (* LC_PROBE623_TYPE = "1" *) (* LC_PROBE623_WIDTH = "1" *) 
(* LC_PROBE624_IS_DATA = "1'b0" *) (* LC_PROBE624_IS_TRIG = "1'b0" *) (* LC_PROBE624_MU_CNT = "1" *) 
(* LC_PROBE624_PID = "16'b0000001001110000" *) (* LC_PROBE624_TYPE = "1" *) (* LC_PROBE624_WIDTH = "1" *) 
(* LC_PROBE625_IS_DATA = "1'b0" *) (* LC_PROBE625_IS_TRIG = "1'b0" *) (* LC_PROBE625_MU_CNT = "1" *) 
(* LC_PROBE625_PID = "16'b0000001001110001" *) (* LC_PROBE625_TYPE = "1" *) (* LC_PROBE625_WIDTH = "1" *) 
(* LC_PROBE626_IS_DATA = "1'b0" *) (* LC_PROBE626_IS_TRIG = "1'b0" *) (* LC_PROBE626_MU_CNT = "1" *) 
(* LC_PROBE626_PID = "16'b0000001001110010" *) (* LC_PROBE626_TYPE = "1" *) (* LC_PROBE626_WIDTH = "1" *) 
(* LC_PROBE627_IS_DATA = "1'b0" *) (* LC_PROBE627_IS_TRIG = "1'b0" *) (* LC_PROBE627_MU_CNT = "1" *) 
(* LC_PROBE627_PID = "16'b0000001001110011" *) (* LC_PROBE627_TYPE = "1" *) (* LC_PROBE627_WIDTH = "1" *) 
(* LC_PROBE628_IS_DATA = "1'b0" *) (* LC_PROBE628_IS_TRIG = "1'b0" *) (* LC_PROBE628_MU_CNT = "1" *) 
(* LC_PROBE628_PID = "16'b0000001001110100" *) (* LC_PROBE628_TYPE = "1" *) (* LC_PROBE628_WIDTH = "1" *) 
(* LC_PROBE629_IS_DATA = "1'b0" *) (* LC_PROBE629_IS_TRIG = "1'b0" *) (* LC_PROBE629_MU_CNT = "1" *) 
(* LC_PROBE629_PID = "16'b0000001001110101" *) (* LC_PROBE629_TYPE = "1" *) (* LC_PROBE629_WIDTH = "1" *) 
(* LC_PROBE62_IS_DATA = "1'b0" *) (* LC_PROBE62_IS_TRIG = "1'b0" *) (* LC_PROBE62_MU_CNT = "1" *) 
(* LC_PROBE62_PID = "16'b0000000000111110" *) (* LC_PROBE62_TYPE = "1" *) (* LC_PROBE62_WIDTH = "1" *) 
(* LC_PROBE630_IS_DATA = "1'b0" *) (* LC_PROBE630_IS_TRIG = "1'b0" *) (* LC_PROBE630_MU_CNT = "1" *) 
(* LC_PROBE630_PID = "16'b0000001001110110" *) (* LC_PROBE630_TYPE = "1" *) (* LC_PROBE630_WIDTH = "1" *) 
(* LC_PROBE631_IS_DATA = "1'b0" *) (* LC_PROBE631_IS_TRIG = "1'b0" *) (* LC_PROBE631_MU_CNT = "1" *) 
(* LC_PROBE631_PID = "16'b0000001001110111" *) (* LC_PROBE631_TYPE = "1" *) (* LC_PROBE631_WIDTH = "1" *) 
(* LC_PROBE632_IS_DATA = "1'b0" *) (* LC_PROBE632_IS_TRIG = "1'b0" *) (* LC_PROBE632_MU_CNT = "1" *) 
(* LC_PROBE632_PID = "16'b0000001001111000" *) (* LC_PROBE632_TYPE = "1" *) (* LC_PROBE632_WIDTH = "1" *) 
(* LC_PROBE633_IS_DATA = "1'b0" *) (* LC_PROBE633_IS_TRIG = "1'b0" *) (* LC_PROBE633_MU_CNT = "1" *) 
(* LC_PROBE633_PID = "16'b0000001001111001" *) (* LC_PROBE633_TYPE = "1" *) (* LC_PROBE633_WIDTH = "1" *) 
(* LC_PROBE634_IS_DATA = "1'b0" *) (* LC_PROBE634_IS_TRIG = "1'b0" *) (* LC_PROBE634_MU_CNT = "1" *) 
(* LC_PROBE634_PID = "16'b0000001001111010" *) (* LC_PROBE634_TYPE = "1" *) (* LC_PROBE634_WIDTH = "1" *) 
(* LC_PROBE635_IS_DATA = "1'b0" *) (* LC_PROBE635_IS_TRIG = "1'b0" *) (* LC_PROBE635_MU_CNT = "1" *) 
(* LC_PROBE635_PID = "16'b0000001001111011" *) (* LC_PROBE635_TYPE = "1" *) (* LC_PROBE635_WIDTH = "1" *) 
(* LC_PROBE636_IS_DATA = "1'b0" *) (* LC_PROBE636_IS_TRIG = "1'b0" *) (* LC_PROBE636_MU_CNT = "1" *) 
(* LC_PROBE636_PID = "16'b0000001001111100" *) (* LC_PROBE636_TYPE = "1" *) (* LC_PROBE636_WIDTH = "1" *) 
(* LC_PROBE637_IS_DATA = "1'b0" *) (* LC_PROBE637_IS_TRIG = "1'b0" *) (* LC_PROBE637_MU_CNT = "1" *) 
(* LC_PROBE637_PID = "16'b0000001001111101" *) (* LC_PROBE637_TYPE = "1" *) (* LC_PROBE637_WIDTH = "1" *) 
(* LC_PROBE638_IS_DATA = "1'b0" *) (* LC_PROBE638_IS_TRIG = "1'b0" *) (* LC_PROBE638_MU_CNT = "1" *) 
(* LC_PROBE638_PID = "16'b0000001001111110" *) (* LC_PROBE638_TYPE = "1" *) (* LC_PROBE638_WIDTH = "1" *) 
(* LC_PROBE639_IS_DATA = "1'b0" *) (* LC_PROBE639_IS_TRIG = "1'b0" *) (* LC_PROBE639_MU_CNT = "1" *) 
(* LC_PROBE639_PID = "16'b0000001001111111" *) (* LC_PROBE639_TYPE = "1" *) (* LC_PROBE639_WIDTH = "1" *) 
(* LC_PROBE63_IS_DATA = "1'b0" *) (* LC_PROBE63_IS_TRIG = "1'b0" *) (* LC_PROBE63_MU_CNT = "1" *) 
(* LC_PROBE63_PID = "16'b0000000000111111" *) (* LC_PROBE63_TYPE = "1" *) (* LC_PROBE63_WIDTH = "1" *) 
(* LC_PROBE640_IS_DATA = "1'b0" *) (* LC_PROBE640_IS_TRIG = "1'b0" *) (* LC_PROBE640_MU_CNT = "1" *) 
(* LC_PROBE640_PID = "16'b0000001010000000" *) (* LC_PROBE640_TYPE = "1" *) (* LC_PROBE640_WIDTH = "1" *) 
(* LC_PROBE641_IS_DATA = "1'b0" *) (* LC_PROBE641_IS_TRIG = "1'b0" *) (* LC_PROBE641_MU_CNT = "1" *) 
(* LC_PROBE641_PID = "16'b0000001010000001" *) (* LC_PROBE641_TYPE = "1" *) (* LC_PROBE641_WIDTH = "1" *) 
(* LC_PROBE642_IS_DATA = "1'b0" *) (* LC_PROBE642_IS_TRIG = "1'b0" *) (* LC_PROBE642_MU_CNT = "1" *) 
(* LC_PROBE642_PID = "16'b0000001010000010" *) (* LC_PROBE642_TYPE = "1" *) (* LC_PROBE642_WIDTH = "1" *) 
(* LC_PROBE643_IS_DATA = "1'b0" *) (* LC_PROBE643_IS_TRIG = "1'b0" *) (* LC_PROBE643_MU_CNT = "1" *) 
(* LC_PROBE643_PID = "16'b0000001010000011" *) (* LC_PROBE643_TYPE = "1" *) (* LC_PROBE643_WIDTH = "1" *) 
(* LC_PROBE644_IS_DATA = "1'b0" *) (* LC_PROBE644_IS_TRIG = "1'b0" *) (* LC_PROBE644_MU_CNT = "1" *) 
(* LC_PROBE644_PID = "16'b0000001010000100" *) (* LC_PROBE644_TYPE = "1" *) (* LC_PROBE644_WIDTH = "1" *) 
(* LC_PROBE645_IS_DATA = "1'b0" *) (* LC_PROBE645_IS_TRIG = "1'b0" *) (* LC_PROBE645_MU_CNT = "1" *) 
(* LC_PROBE645_PID = "16'b0000001010000101" *) (* LC_PROBE645_TYPE = "1" *) (* LC_PROBE645_WIDTH = "1" *) 
(* LC_PROBE646_IS_DATA = "1'b0" *) (* LC_PROBE646_IS_TRIG = "1'b0" *) (* LC_PROBE646_MU_CNT = "1" *) 
(* LC_PROBE646_PID = "16'b0000001010000110" *) (* LC_PROBE646_TYPE = "1" *) (* LC_PROBE646_WIDTH = "1" *) 
(* LC_PROBE647_IS_DATA = "1'b0" *) (* LC_PROBE647_IS_TRIG = "1'b0" *) (* LC_PROBE647_MU_CNT = "1" *) 
(* LC_PROBE647_PID = "16'b0000001010000111" *) (* LC_PROBE647_TYPE = "1" *) (* LC_PROBE647_WIDTH = "1" *) 
(* LC_PROBE648_IS_DATA = "1'b0" *) (* LC_PROBE648_IS_TRIG = "1'b0" *) (* LC_PROBE648_MU_CNT = "1" *) 
(* LC_PROBE648_PID = "16'b0000001010001000" *) (* LC_PROBE648_TYPE = "1" *) (* LC_PROBE648_WIDTH = "1" *) 
(* LC_PROBE649_IS_DATA = "1'b0" *) (* LC_PROBE649_IS_TRIG = "1'b0" *) (* LC_PROBE649_MU_CNT = "1" *) 
(* LC_PROBE649_PID = "16'b0000001010001001" *) (* LC_PROBE649_TYPE = "1" *) (* LC_PROBE649_WIDTH = "1" *) 
(* LC_PROBE64_IS_DATA = "1'b0" *) (* LC_PROBE64_IS_TRIG = "1'b0" *) (* LC_PROBE64_MU_CNT = "1" *) 
(* LC_PROBE64_PID = "16'b0000000001000000" *) (* LC_PROBE64_TYPE = "1" *) (* LC_PROBE64_WIDTH = "1" *) 
(* LC_PROBE650_IS_DATA = "1'b0" *) (* LC_PROBE650_IS_TRIG = "1'b0" *) (* LC_PROBE650_MU_CNT = "1" *) 
(* LC_PROBE650_PID = "16'b0000001010001010" *) (* LC_PROBE650_TYPE = "1" *) (* LC_PROBE650_WIDTH = "1" *) 
(* LC_PROBE651_IS_DATA = "1'b0" *) (* LC_PROBE651_IS_TRIG = "1'b0" *) (* LC_PROBE651_MU_CNT = "1" *) 
(* LC_PROBE651_PID = "16'b0000001010001011" *) (* LC_PROBE651_TYPE = "1" *) (* LC_PROBE651_WIDTH = "1" *) 
(* LC_PROBE652_IS_DATA = "1'b0" *) (* LC_PROBE652_IS_TRIG = "1'b0" *) (* LC_PROBE652_MU_CNT = "1" *) 
(* LC_PROBE652_PID = "16'b0000001010001100" *) (* LC_PROBE652_TYPE = "1" *) (* LC_PROBE652_WIDTH = "1" *) 
(* LC_PROBE653_IS_DATA = "1'b0" *) (* LC_PROBE653_IS_TRIG = "1'b0" *) (* LC_PROBE653_MU_CNT = "1" *) 
(* LC_PROBE653_PID = "16'b0000001010001101" *) (* LC_PROBE653_TYPE = "1" *) (* LC_PROBE653_WIDTH = "1" *) 
(* LC_PROBE654_IS_DATA = "1'b0" *) (* LC_PROBE654_IS_TRIG = "1'b0" *) (* LC_PROBE654_MU_CNT = "1" *) 
(* LC_PROBE654_PID = "16'b0000001010001110" *) (* LC_PROBE654_TYPE = "1" *) (* LC_PROBE654_WIDTH = "1" *) 
(* LC_PROBE655_IS_DATA = "1'b0" *) (* LC_PROBE655_IS_TRIG = "1'b0" *) (* LC_PROBE655_MU_CNT = "1" *) 
(* LC_PROBE655_PID = "16'b0000001010001111" *) (* LC_PROBE655_TYPE = "1" *) (* LC_PROBE655_WIDTH = "1" *) 
(* LC_PROBE656_IS_DATA = "1'b0" *) (* LC_PROBE656_IS_TRIG = "1'b0" *) (* LC_PROBE656_MU_CNT = "1" *) 
(* LC_PROBE656_PID = "16'b0000001010010000" *) (* LC_PROBE656_TYPE = "1" *) (* LC_PROBE656_WIDTH = "1" *) 
(* LC_PROBE657_IS_DATA = "1'b0" *) (* LC_PROBE657_IS_TRIG = "1'b0" *) (* LC_PROBE657_MU_CNT = "1" *) 
(* LC_PROBE657_PID = "16'b0000001010010001" *) (* LC_PROBE657_TYPE = "1" *) (* LC_PROBE657_WIDTH = "1" *) 
(* LC_PROBE658_IS_DATA = "1'b0" *) (* LC_PROBE658_IS_TRIG = "1'b0" *) (* LC_PROBE658_MU_CNT = "1" *) 
(* LC_PROBE658_PID = "16'b0000001010010010" *) (* LC_PROBE658_TYPE = "1" *) (* LC_PROBE658_WIDTH = "1" *) 
(* LC_PROBE659_IS_DATA = "1'b0" *) (* LC_PROBE659_IS_TRIG = "1'b0" *) (* LC_PROBE659_MU_CNT = "1" *) 
(* LC_PROBE659_PID = "16'b0000001010010011" *) (* LC_PROBE659_TYPE = "1" *) (* LC_PROBE659_WIDTH = "1" *) 
(* LC_PROBE65_IS_DATA = "1'b0" *) (* LC_PROBE65_IS_TRIG = "1'b0" *) (* LC_PROBE65_MU_CNT = "1" *) 
(* LC_PROBE65_PID = "16'b0000000001000001" *) (* LC_PROBE65_TYPE = "1" *) (* LC_PROBE65_WIDTH = "1" *) 
(* LC_PROBE660_IS_DATA = "1'b0" *) (* LC_PROBE660_IS_TRIG = "1'b0" *) (* LC_PROBE660_MU_CNT = "1" *) 
(* LC_PROBE660_PID = "16'b0000001010010100" *) (* LC_PROBE660_TYPE = "1" *) (* LC_PROBE660_WIDTH = "1" *) 
(* LC_PROBE661_IS_DATA = "1'b0" *) (* LC_PROBE661_IS_TRIG = "1'b0" *) (* LC_PROBE661_MU_CNT = "1" *) 
(* LC_PROBE661_PID = "16'b0000001010010101" *) (* LC_PROBE661_TYPE = "1" *) (* LC_PROBE661_WIDTH = "1" *) 
(* LC_PROBE662_IS_DATA = "1'b0" *) (* LC_PROBE662_IS_TRIG = "1'b0" *) (* LC_PROBE662_MU_CNT = "1" *) 
(* LC_PROBE662_PID = "16'b0000001010010110" *) (* LC_PROBE662_TYPE = "1" *) (* LC_PROBE662_WIDTH = "1" *) 
(* LC_PROBE663_IS_DATA = "1'b0" *) (* LC_PROBE663_IS_TRIG = "1'b0" *) (* LC_PROBE663_MU_CNT = "1" *) 
(* LC_PROBE663_PID = "16'b0000001010010111" *) (* LC_PROBE663_TYPE = "1" *) (* LC_PROBE663_WIDTH = "1" *) 
(* LC_PROBE664_IS_DATA = "1'b0" *) (* LC_PROBE664_IS_TRIG = "1'b0" *) (* LC_PROBE664_MU_CNT = "1" *) 
(* LC_PROBE664_PID = "16'b0000001010011000" *) (* LC_PROBE664_TYPE = "1" *) (* LC_PROBE664_WIDTH = "1" *) 
(* LC_PROBE665_IS_DATA = "1'b0" *) (* LC_PROBE665_IS_TRIG = "1'b0" *) (* LC_PROBE665_MU_CNT = "1" *) 
(* LC_PROBE665_PID = "16'b0000001010011001" *) (* LC_PROBE665_TYPE = "1" *) (* LC_PROBE665_WIDTH = "1" *) 
(* LC_PROBE666_IS_DATA = "1'b0" *) (* LC_PROBE666_IS_TRIG = "1'b0" *) (* LC_PROBE666_MU_CNT = "1" *) 
(* LC_PROBE666_PID = "16'b0000001010011010" *) (* LC_PROBE666_TYPE = "1" *) (* LC_PROBE666_WIDTH = "1" *) 
(* LC_PROBE667_IS_DATA = "1'b0" *) (* LC_PROBE667_IS_TRIG = "1'b0" *) (* LC_PROBE667_MU_CNT = "1" *) 
(* LC_PROBE667_PID = "16'b0000001010011011" *) (* LC_PROBE667_TYPE = "1" *) (* LC_PROBE667_WIDTH = "1" *) 
(* LC_PROBE668_IS_DATA = "1'b0" *) (* LC_PROBE668_IS_TRIG = "1'b0" *) (* LC_PROBE668_MU_CNT = "1" *) 
(* LC_PROBE668_PID = "16'b0000001010011100" *) (* LC_PROBE668_TYPE = "1" *) (* LC_PROBE668_WIDTH = "1" *) 
(* LC_PROBE669_IS_DATA = "1'b0" *) (* LC_PROBE669_IS_TRIG = "1'b0" *) (* LC_PROBE669_MU_CNT = "1" *) 
(* LC_PROBE669_PID = "16'b0000001010011101" *) (* LC_PROBE669_TYPE = "1" *) (* LC_PROBE669_WIDTH = "1" *) 
(* LC_PROBE66_IS_DATA = "1'b0" *) (* LC_PROBE66_IS_TRIG = "1'b0" *) (* LC_PROBE66_MU_CNT = "1" *) 
(* LC_PROBE66_PID = "16'b0000000001000010" *) (* LC_PROBE66_TYPE = "1" *) (* LC_PROBE66_WIDTH = "1" *) 
(* LC_PROBE670_IS_DATA = "1'b0" *) (* LC_PROBE670_IS_TRIG = "1'b0" *) (* LC_PROBE670_MU_CNT = "1" *) 
(* LC_PROBE670_PID = "16'b0000001010011110" *) (* LC_PROBE670_TYPE = "1" *) (* LC_PROBE670_WIDTH = "1" *) 
(* LC_PROBE671_IS_DATA = "1'b0" *) (* LC_PROBE671_IS_TRIG = "1'b0" *) (* LC_PROBE671_MU_CNT = "1" *) 
(* LC_PROBE671_PID = "16'b0000001010011111" *) (* LC_PROBE671_TYPE = "1" *) (* LC_PROBE671_WIDTH = "1" *) 
(* LC_PROBE672_IS_DATA = "1'b0" *) (* LC_PROBE672_IS_TRIG = "1'b0" *) (* LC_PROBE672_MU_CNT = "1" *) 
(* LC_PROBE672_PID = "16'b0000001010100000" *) (* LC_PROBE672_TYPE = "1" *) (* LC_PROBE672_WIDTH = "1" *) 
(* LC_PROBE673_IS_DATA = "1'b0" *) (* LC_PROBE673_IS_TRIG = "1'b0" *) (* LC_PROBE673_MU_CNT = "1" *) 
(* LC_PROBE673_PID = "16'b0000001010100001" *) (* LC_PROBE673_TYPE = "1" *) (* LC_PROBE673_WIDTH = "1" *) 
(* LC_PROBE674_IS_DATA = "1'b0" *) (* LC_PROBE674_IS_TRIG = "1'b0" *) (* LC_PROBE674_MU_CNT = "1" *) 
(* LC_PROBE674_PID = "16'b0000001010100010" *) (* LC_PROBE674_TYPE = "1" *) (* LC_PROBE674_WIDTH = "1" *) 
(* LC_PROBE675_IS_DATA = "1'b0" *) (* LC_PROBE675_IS_TRIG = "1'b0" *) (* LC_PROBE675_MU_CNT = "1" *) 
(* LC_PROBE675_PID = "16'b0000001010100011" *) (* LC_PROBE675_TYPE = "1" *) (* LC_PROBE675_WIDTH = "1" *) 
(* LC_PROBE676_IS_DATA = "1'b0" *) (* LC_PROBE676_IS_TRIG = "1'b0" *) (* LC_PROBE676_MU_CNT = "1" *) 
(* LC_PROBE676_PID = "16'b0000001010100100" *) (* LC_PROBE676_TYPE = "1" *) (* LC_PROBE676_WIDTH = "1" *) 
(* LC_PROBE677_IS_DATA = "1'b0" *) (* LC_PROBE677_IS_TRIG = "1'b0" *) (* LC_PROBE677_MU_CNT = "1" *) 
(* LC_PROBE677_PID = "16'b0000001010100101" *) (* LC_PROBE677_TYPE = "1" *) (* LC_PROBE677_WIDTH = "1" *) 
(* LC_PROBE678_IS_DATA = "1'b0" *) (* LC_PROBE678_IS_TRIG = "1'b0" *) (* LC_PROBE678_MU_CNT = "1" *) 
(* LC_PROBE678_PID = "16'b0000001010100110" *) (* LC_PROBE678_TYPE = "1" *) (* LC_PROBE678_WIDTH = "1" *) 
(* LC_PROBE679_IS_DATA = "1'b0" *) (* LC_PROBE679_IS_TRIG = "1'b0" *) (* LC_PROBE679_MU_CNT = "1" *) 
(* LC_PROBE679_PID = "16'b0000001010100111" *) (* LC_PROBE679_TYPE = "1" *) (* LC_PROBE679_WIDTH = "1" *) 
(* LC_PROBE67_IS_DATA = "1'b0" *) (* LC_PROBE67_IS_TRIG = "1'b0" *) (* LC_PROBE67_MU_CNT = "1" *) 
(* LC_PROBE67_PID = "16'b0000000001000011" *) (* LC_PROBE67_TYPE = "1" *) (* LC_PROBE67_WIDTH = "1" *) 
(* LC_PROBE680_IS_DATA = "1'b0" *) (* LC_PROBE680_IS_TRIG = "1'b0" *) (* LC_PROBE680_MU_CNT = "1" *) 
(* LC_PROBE680_PID = "16'b0000001010101000" *) (* LC_PROBE680_TYPE = "1" *) (* LC_PROBE680_WIDTH = "1" *) 
(* LC_PROBE681_IS_DATA = "1'b0" *) (* LC_PROBE681_IS_TRIG = "1'b0" *) (* LC_PROBE681_MU_CNT = "1" *) 
(* LC_PROBE681_PID = "16'b0000001010101001" *) (* LC_PROBE681_TYPE = "1" *) (* LC_PROBE681_WIDTH = "1" *) 
(* LC_PROBE682_IS_DATA = "1'b0" *) (* LC_PROBE682_IS_TRIG = "1'b0" *) (* LC_PROBE682_MU_CNT = "1" *) 
(* LC_PROBE682_PID = "16'b0000001010101010" *) (* LC_PROBE682_TYPE = "1" *) (* LC_PROBE682_WIDTH = "1" *) 
(* LC_PROBE683_IS_DATA = "1'b0" *) (* LC_PROBE683_IS_TRIG = "1'b0" *) (* LC_PROBE683_MU_CNT = "1" *) 
(* LC_PROBE683_PID = "16'b0000001010101011" *) (* LC_PROBE683_TYPE = "1" *) (* LC_PROBE683_WIDTH = "1" *) 
(* LC_PROBE684_IS_DATA = "1'b0" *) (* LC_PROBE684_IS_TRIG = "1'b0" *) (* LC_PROBE684_MU_CNT = "1" *) 
(* LC_PROBE684_PID = "16'b0000001010101100" *) (* LC_PROBE684_TYPE = "1" *) (* LC_PROBE684_WIDTH = "1" *) 
(* LC_PROBE685_IS_DATA = "1'b0" *) (* LC_PROBE685_IS_TRIG = "1'b0" *) (* LC_PROBE685_MU_CNT = "1" *) 
(* LC_PROBE685_PID = "16'b0000001010101101" *) (* LC_PROBE685_TYPE = "1" *) (* LC_PROBE685_WIDTH = "1" *) 
(* LC_PROBE686_IS_DATA = "1'b0" *) (* LC_PROBE686_IS_TRIG = "1'b0" *) (* LC_PROBE686_MU_CNT = "1" *) 
(* LC_PROBE686_PID = "16'b0000001010101110" *) (* LC_PROBE686_TYPE = "1" *) (* LC_PROBE686_WIDTH = "1" *) 
(* LC_PROBE687_IS_DATA = "1'b0" *) (* LC_PROBE687_IS_TRIG = "1'b0" *) (* LC_PROBE687_MU_CNT = "1" *) 
(* LC_PROBE687_PID = "16'b0000001010101111" *) (* LC_PROBE687_TYPE = "1" *) (* LC_PROBE687_WIDTH = "1" *) 
(* LC_PROBE688_IS_DATA = "1'b0" *) (* LC_PROBE688_IS_TRIG = "1'b0" *) (* LC_PROBE688_MU_CNT = "1" *) 
(* LC_PROBE688_PID = "16'b0000001010110000" *) (* LC_PROBE688_TYPE = "1" *) (* LC_PROBE688_WIDTH = "1" *) 
(* LC_PROBE689_IS_DATA = "1'b0" *) (* LC_PROBE689_IS_TRIG = "1'b0" *) (* LC_PROBE689_MU_CNT = "1" *) 
(* LC_PROBE689_PID = "16'b0000001010110001" *) (* LC_PROBE689_TYPE = "1" *) (* LC_PROBE689_WIDTH = "1" *) 
(* LC_PROBE68_IS_DATA = "1'b0" *) (* LC_PROBE68_IS_TRIG = "1'b0" *) (* LC_PROBE68_MU_CNT = "1" *) 
(* LC_PROBE68_PID = "16'b0000000001000100" *) (* LC_PROBE68_TYPE = "1" *) (* LC_PROBE68_WIDTH = "1" *) 
(* LC_PROBE690_IS_DATA = "1'b0" *) (* LC_PROBE690_IS_TRIG = "1'b0" *) (* LC_PROBE690_MU_CNT = "1" *) 
(* LC_PROBE690_PID = "16'b0000001010110010" *) (* LC_PROBE690_TYPE = "1" *) (* LC_PROBE690_WIDTH = "1" *) 
(* LC_PROBE691_IS_DATA = "1'b0" *) (* LC_PROBE691_IS_TRIG = "1'b0" *) (* LC_PROBE691_MU_CNT = "1" *) 
(* LC_PROBE691_PID = "16'b0000001010110011" *) (* LC_PROBE691_TYPE = "1" *) (* LC_PROBE691_WIDTH = "1" *) 
(* LC_PROBE692_IS_DATA = "1'b0" *) (* LC_PROBE692_IS_TRIG = "1'b0" *) (* LC_PROBE692_MU_CNT = "1" *) 
(* LC_PROBE692_PID = "16'b0000001010110100" *) (* LC_PROBE692_TYPE = "1" *) (* LC_PROBE692_WIDTH = "1" *) 
(* LC_PROBE693_IS_DATA = "1'b0" *) (* LC_PROBE693_IS_TRIG = "1'b0" *) (* LC_PROBE693_MU_CNT = "1" *) 
(* LC_PROBE693_PID = "16'b0000001010110101" *) (* LC_PROBE693_TYPE = "1" *) (* LC_PROBE693_WIDTH = "1" *) 
(* LC_PROBE694_IS_DATA = "1'b0" *) (* LC_PROBE694_IS_TRIG = "1'b0" *) (* LC_PROBE694_MU_CNT = "1" *) 
(* LC_PROBE694_PID = "16'b0000001010110110" *) (* LC_PROBE694_TYPE = "1" *) (* LC_PROBE694_WIDTH = "1" *) 
(* LC_PROBE695_IS_DATA = "1'b0" *) (* LC_PROBE695_IS_TRIG = "1'b0" *) (* LC_PROBE695_MU_CNT = "1" *) 
(* LC_PROBE695_PID = "16'b0000001010110111" *) (* LC_PROBE695_TYPE = "1" *) (* LC_PROBE695_WIDTH = "1" *) 
(* LC_PROBE696_IS_DATA = "1'b0" *) (* LC_PROBE696_IS_TRIG = "1'b0" *) (* LC_PROBE696_MU_CNT = "1" *) 
(* LC_PROBE696_PID = "16'b0000001010111000" *) (* LC_PROBE696_TYPE = "1" *) (* LC_PROBE696_WIDTH = "1" *) 
(* LC_PROBE697_IS_DATA = "1'b0" *) (* LC_PROBE697_IS_TRIG = "1'b0" *) (* LC_PROBE697_MU_CNT = "1" *) 
(* LC_PROBE697_PID = "16'b0000001010111001" *) (* LC_PROBE697_TYPE = "1" *) (* LC_PROBE697_WIDTH = "1" *) 
(* LC_PROBE698_IS_DATA = "1'b0" *) (* LC_PROBE698_IS_TRIG = "1'b0" *) (* LC_PROBE698_MU_CNT = "1" *) 
(* LC_PROBE698_PID = "16'b0000001010111010" *) (* LC_PROBE698_TYPE = "1" *) (* LC_PROBE698_WIDTH = "1" *) 
(* LC_PROBE699_IS_DATA = "1'b0" *) (* LC_PROBE699_IS_TRIG = "1'b0" *) (* LC_PROBE699_MU_CNT = "1" *) 
(* LC_PROBE699_PID = "16'b0000001010111011" *) (* LC_PROBE699_TYPE = "1" *) (* LC_PROBE699_WIDTH = "1" *) 
(* LC_PROBE69_IS_DATA = "1'b0" *) (* LC_PROBE69_IS_TRIG = "1'b0" *) (* LC_PROBE69_MU_CNT = "1" *) 
(* LC_PROBE69_PID = "16'b0000000001000101" *) (* LC_PROBE69_TYPE = "1" *) (* LC_PROBE69_WIDTH = "1" *) 
(* LC_PROBE6_IS_DATA = "1'b0" *) (* LC_PROBE6_IS_TRIG = "1'b0" *) (* LC_PROBE6_MU_CNT = "1" *) 
(* LC_PROBE6_PID = "16'b0000000000000110" *) (* LC_PROBE6_TYPE = "1" *) (* LC_PROBE6_WIDTH = "1" *) 
(* LC_PROBE700_IS_DATA = "1'b0" *) (* LC_PROBE700_IS_TRIG = "1'b0" *) (* LC_PROBE700_MU_CNT = "1" *) 
(* LC_PROBE700_PID = "16'b0000001010111100" *) (* LC_PROBE700_TYPE = "1" *) (* LC_PROBE700_WIDTH = "1" *) 
(* LC_PROBE701_IS_DATA = "1'b0" *) (* LC_PROBE701_IS_TRIG = "1'b0" *) (* LC_PROBE701_MU_CNT = "1" *) 
(* LC_PROBE701_PID = "16'b0000001010111101" *) (* LC_PROBE701_TYPE = "1" *) (* LC_PROBE701_WIDTH = "1" *) 
(* LC_PROBE702_IS_DATA = "1'b0" *) (* LC_PROBE702_IS_TRIG = "1'b0" *) (* LC_PROBE702_MU_CNT = "1" *) 
(* LC_PROBE702_PID = "16'b0000001010111110" *) (* LC_PROBE702_TYPE = "1" *) (* LC_PROBE702_WIDTH = "1" *) 
(* LC_PROBE703_IS_DATA = "1'b0" *) (* LC_PROBE703_IS_TRIG = "1'b0" *) (* LC_PROBE703_MU_CNT = "1" *) 
(* LC_PROBE703_PID = "16'b0000001010111111" *) (* LC_PROBE703_TYPE = "1" *) (* LC_PROBE703_WIDTH = "1" *) 
(* LC_PROBE704_IS_DATA = "1'b0" *) (* LC_PROBE704_IS_TRIG = "1'b0" *) (* LC_PROBE704_MU_CNT = "1" *) 
(* LC_PROBE704_PID = "16'b0000001011000000" *) (* LC_PROBE704_TYPE = "1" *) (* LC_PROBE704_WIDTH = "1" *) 
(* LC_PROBE705_IS_DATA = "1'b0" *) (* LC_PROBE705_IS_TRIG = "1'b0" *) (* LC_PROBE705_MU_CNT = "1" *) 
(* LC_PROBE705_PID = "16'b0000001011000001" *) (* LC_PROBE705_TYPE = "1" *) (* LC_PROBE705_WIDTH = "1" *) 
(* LC_PROBE706_IS_DATA = "1'b0" *) (* LC_PROBE706_IS_TRIG = "1'b0" *) (* LC_PROBE706_MU_CNT = "1" *) 
(* LC_PROBE706_PID = "16'b0000001011000010" *) (* LC_PROBE706_TYPE = "1" *) (* LC_PROBE706_WIDTH = "1" *) 
(* LC_PROBE707_IS_DATA = "1'b0" *) (* LC_PROBE707_IS_TRIG = "1'b0" *) (* LC_PROBE707_MU_CNT = "1" *) 
(* LC_PROBE707_PID = "16'b0000001011000011" *) (* LC_PROBE707_TYPE = "1" *) (* LC_PROBE707_WIDTH = "1" *) 
(* LC_PROBE708_IS_DATA = "1'b0" *) (* LC_PROBE708_IS_TRIG = "1'b0" *) (* LC_PROBE708_MU_CNT = "1" *) 
(* LC_PROBE708_PID = "16'b0000001011000100" *) (* LC_PROBE708_TYPE = "1" *) (* LC_PROBE708_WIDTH = "1" *) 
(* LC_PROBE709_IS_DATA = "1'b0" *) (* LC_PROBE709_IS_TRIG = "1'b0" *) (* LC_PROBE709_MU_CNT = "1" *) 
(* LC_PROBE709_PID = "16'b0000001011000101" *) (* LC_PROBE709_TYPE = "1" *) (* LC_PROBE709_WIDTH = "1" *) 
(* LC_PROBE70_IS_DATA = "1'b0" *) (* LC_PROBE70_IS_TRIG = "1'b0" *) (* LC_PROBE70_MU_CNT = "1" *) 
(* LC_PROBE70_PID = "16'b0000000001000110" *) (* LC_PROBE70_TYPE = "1" *) (* LC_PROBE70_WIDTH = "1" *) 
(* LC_PROBE710_IS_DATA = "1'b0" *) (* LC_PROBE710_IS_TRIG = "1'b0" *) (* LC_PROBE710_MU_CNT = "1" *) 
(* LC_PROBE710_PID = "16'b0000001011000110" *) (* LC_PROBE710_TYPE = "1" *) (* LC_PROBE710_WIDTH = "1" *) 
(* LC_PROBE711_IS_DATA = "1'b0" *) (* LC_PROBE711_IS_TRIG = "1'b0" *) (* LC_PROBE711_MU_CNT = "1" *) 
(* LC_PROBE711_PID = "16'b0000001011000111" *) (* LC_PROBE711_TYPE = "1" *) (* LC_PROBE711_WIDTH = "1" *) 
(* LC_PROBE712_IS_DATA = "1'b0" *) (* LC_PROBE712_IS_TRIG = "1'b0" *) (* LC_PROBE712_MU_CNT = "1" *) 
(* LC_PROBE712_PID = "16'b0000001011001000" *) (* LC_PROBE712_TYPE = "1" *) (* LC_PROBE712_WIDTH = "1" *) 
(* LC_PROBE713_IS_DATA = "1'b0" *) (* LC_PROBE713_IS_TRIG = "1'b0" *) (* LC_PROBE713_MU_CNT = "1" *) 
(* LC_PROBE713_PID = "16'b0000001011001001" *) (* LC_PROBE713_TYPE = "1" *) (* LC_PROBE713_WIDTH = "1" *) 
(* LC_PROBE714_IS_DATA = "1'b0" *) (* LC_PROBE714_IS_TRIG = "1'b0" *) (* LC_PROBE714_MU_CNT = "1" *) 
(* LC_PROBE714_PID = "16'b0000001011001010" *) (* LC_PROBE714_TYPE = "1" *) (* LC_PROBE714_WIDTH = "1" *) 
(* LC_PROBE715_IS_DATA = "1'b0" *) (* LC_PROBE715_IS_TRIG = "1'b0" *) (* LC_PROBE715_MU_CNT = "1" *) 
(* LC_PROBE715_PID = "16'b0000001011001011" *) (* LC_PROBE715_TYPE = "1" *) (* LC_PROBE715_WIDTH = "1" *) 
(* LC_PROBE716_IS_DATA = "1'b0" *) (* LC_PROBE716_IS_TRIG = "1'b0" *) (* LC_PROBE716_MU_CNT = "1" *) 
(* LC_PROBE716_PID = "16'b0000001011001100" *) (* LC_PROBE716_TYPE = "1" *) (* LC_PROBE716_WIDTH = "1" *) 
(* LC_PROBE717_IS_DATA = "1'b0" *) (* LC_PROBE717_IS_TRIG = "1'b0" *) (* LC_PROBE717_MU_CNT = "1" *) 
(* LC_PROBE717_PID = "16'b0000001011001101" *) (* LC_PROBE717_TYPE = "1" *) (* LC_PROBE717_WIDTH = "1" *) 
(* LC_PROBE718_IS_DATA = "1'b0" *) (* LC_PROBE718_IS_TRIG = "1'b0" *) (* LC_PROBE718_MU_CNT = "1" *) 
(* LC_PROBE718_PID = "16'b0000001011001110" *) (* LC_PROBE718_TYPE = "1" *) (* LC_PROBE718_WIDTH = "1" *) 
(* LC_PROBE719_IS_DATA = "1'b0" *) (* LC_PROBE719_IS_TRIG = "1'b0" *) (* LC_PROBE719_MU_CNT = "1" *) 
(* LC_PROBE719_PID = "16'b0000001011001111" *) (* LC_PROBE719_TYPE = "1" *) (* LC_PROBE719_WIDTH = "1" *) 
(* LC_PROBE71_IS_DATA = "1'b0" *) (* LC_PROBE71_IS_TRIG = "1'b0" *) (* LC_PROBE71_MU_CNT = "1" *) 
(* LC_PROBE71_PID = "16'b0000000001000111" *) (* LC_PROBE71_TYPE = "1" *) (* LC_PROBE71_WIDTH = "1" *) 
(* LC_PROBE720_IS_DATA = "1'b0" *) (* LC_PROBE720_IS_TRIG = "1'b0" *) (* LC_PROBE720_MU_CNT = "1" *) 
(* LC_PROBE720_PID = "16'b0000001011010000" *) (* LC_PROBE720_TYPE = "1" *) (* LC_PROBE720_WIDTH = "1" *) 
(* LC_PROBE721_IS_DATA = "1'b0" *) (* LC_PROBE721_IS_TRIG = "1'b0" *) (* LC_PROBE721_MU_CNT = "1" *) 
(* LC_PROBE721_PID = "16'b0000001011010001" *) (* LC_PROBE721_TYPE = "1" *) (* LC_PROBE721_WIDTH = "1" *) 
(* LC_PROBE722_IS_DATA = "1'b0" *) (* LC_PROBE722_IS_TRIG = "1'b0" *) (* LC_PROBE722_MU_CNT = "1" *) 
(* LC_PROBE722_PID = "16'b0000001011010010" *) (* LC_PROBE722_TYPE = "1" *) (* LC_PROBE722_WIDTH = "1" *) 
(* LC_PROBE723_IS_DATA = "1'b0" *) (* LC_PROBE723_IS_TRIG = "1'b0" *) (* LC_PROBE723_MU_CNT = "1" *) 
(* LC_PROBE723_PID = "16'b0000001011010011" *) (* LC_PROBE723_TYPE = "1" *) (* LC_PROBE723_WIDTH = "1" *) 
(* LC_PROBE724_IS_DATA = "1'b0" *) (* LC_PROBE724_IS_TRIG = "1'b0" *) (* LC_PROBE724_MU_CNT = "1" *) 
(* LC_PROBE724_PID = "16'b0000001011010100" *) (* LC_PROBE724_TYPE = "1" *) (* LC_PROBE724_WIDTH = "1" *) 
(* LC_PROBE725_IS_DATA = "1'b0" *) (* LC_PROBE725_IS_TRIG = "1'b0" *) (* LC_PROBE725_MU_CNT = "1" *) 
(* LC_PROBE725_PID = "16'b0000001011010101" *) (* LC_PROBE725_TYPE = "1" *) (* LC_PROBE725_WIDTH = "1" *) 
(* LC_PROBE726_IS_DATA = "1'b0" *) (* LC_PROBE726_IS_TRIG = "1'b0" *) (* LC_PROBE726_MU_CNT = "1" *) 
(* LC_PROBE726_PID = "16'b0000001011010110" *) (* LC_PROBE726_TYPE = "1" *) (* LC_PROBE726_WIDTH = "1" *) 
(* LC_PROBE727_IS_DATA = "1'b0" *) (* LC_PROBE727_IS_TRIG = "1'b0" *) (* LC_PROBE727_MU_CNT = "1" *) 
(* LC_PROBE727_PID = "16'b0000001011010111" *) (* LC_PROBE727_TYPE = "1" *) (* LC_PROBE727_WIDTH = "1" *) 
(* LC_PROBE728_IS_DATA = "1'b0" *) (* LC_PROBE728_IS_TRIG = "1'b0" *) (* LC_PROBE728_MU_CNT = "1" *) 
(* LC_PROBE728_PID = "16'b0000001011011000" *) (* LC_PROBE728_TYPE = "1" *) (* LC_PROBE728_WIDTH = "1" *) 
(* LC_PROBE729_IS_DATA = "1'b0" *) (* LC_PROBE729_IS_TRIG = "1'b0" *) (* LC_PROBE729_MU_CNT = "1" *) 
(* LC_PROBE729_PID = "16'b0000001011011001" *) (* LC_PROBE729_TYPE = "1" *) (* LC_PROBE729_WIDTH = "1" *) 
(* LC_PROBE72_IS_DATA = "1'b0" *) (* LC_PROBE72_IS_TRIG = "1'b0" *) (* LC_PROBE72_MU_CNT = "1" *) 
(* LC_PROBE72_PID = "16'b0000000001001000" *) (* LC_PROBE72_TYPE = "1" *) (* LC_PROBE72_WIDTH = "1" *) 
(* LC_PROBE730_IS_DATA = "1'b0" *) (* LC_PROBE730_IS_TRIG = "1'b0" *) (* LC_PROBE730_MU_CNT = "1" *) 
(* LC_PROBE730_PID = "16'b0000001011011010" *) (* LC_PROBE730_TYPE = "1" *) (* LC_PROBE730_WIDTH = "1" *) 
(* LC_PROBE731_IS_DATA = "1'b0" *) (* LC_PROBE731_IS_TRIG = "1'b0" *) (* LC_PROBE731_MU_CNT = "1" *) 
(* LC_PROBE731_PID = "16'b0000001011011011" *) (* LC_PROBE731_TYPE = "1" *) (* LC_PROBE731_WIDTH = "1" *) 
(* LC_PROBE732_IS_DATA = "1'b0" *) (* LC_PROBE732_IS_TRIG = "1'b0" *) (* LC_PROBE732_MU_CNT = "1" *) 
(* LC_PROBE732_PID = "16'b0000001011011100" *) (* LC_PROBE732_TYPE = "1" *) (* LC_PROBE732_WIDTH = "1" *) 
(* LC_PROBE733_IS_DATA = "1'b0" *) (* LC_PROBE733_IS_TRIG = "1'b0" *) (* LC_PROBE733_MU_CNT = "1" *) 
(* LC_PROBE733_PID = "16'b0000001011011101" *) (* LC_PROBE733_TYPE = "1" *) (* LC_PROBE733_WIDTH = "1" *) 
(* LC_PROBE734_IS_DATA = "1'b0" *) (* LC_PROBE734_IS_TRIG = "1'b0" *) (* LC_PROBE734_MU_CNT = "1" *) 
(* LC_PROBE734_PID = "16'b0000001011011110" *) (* LC_PROBE734_TYPE = "1" *) (* LC_PROBE734_WIDTH = "1" *) 
(* LC_PROBE735_IS_DATA = "1'b0" *) (* LC_PROBE735_IS_TRIG = "1'b0" *) (* LC_PROBE735_MU_CNT = "1" *) 
(* LC_PROBE735_PID = "16'b0000001011011111" *) (* LC_PROBE735_TYPE = "1" *) (* LC_PROBE735_WIDTH = "1" *) 
(* LC_PROBE736_IS_DATA = "1'b0" *) (* LC_PROBE736_IS_TRIG = "1'b0" *) (* LC_PROBE736_MU_CNT = "1" *) 
(* LC_PROBE736_PID = "16'b0000001011100000" *) (* LC_PROBE736_TYPE = "1" *) (* LC_PROBE736_WIDTH = "1" *) 
(* LC_PROBE737_IS_DATA = "1'b0" *) (* LC_PROBE737_IS_TRIG = "1'b0" *) (* LC_PROBE737_MU_CNT = "1" *) 
(* LC_PROBE737_PID = "16'b0000001011100001" *) (* LC_PROBE737_TYPE = "1" *) (* LC_PROBE737_WIDTH = "1" *) 
(* LC_PROBE738_IS_DATA = "1'b0" *) (* LC_PROBE738_IS_TRIG = "1'b0" *) (* LC_PROBE738_MU_CNT = "1" *) 
(* LC_PROBE738_PID = "16'b0000001011100010" *) (* LC_PROBE738_TYPE = "1" *) (* LC_PROBE738_WIDTH = "1" *) 
(* LC_PROBE739_IS_DATA = "1'b0" *) (* LC_PROBE739_IS_TRIG = "1'b0" *) (* LC_PROBE739_MU_CNT = "1" *) 
(* LC_PROBE739_PID = "16'b0000001011100011" *) (* LC_PROBE739_TYPE = "1" *) (* LC_PROBE739_WIDTH = "1" *) 
(* LC_PROBE73_IS_DATA = "1'b0" *) (* LC_PROBE73_IS_TRIG = "1'b0" *) (* LC_PROBE73_MU_CNT = "1" *) 
(* LC_PROBE73_PID = "16'b0000000001001001" *) (* LC_PROBE73_TYPE = "1" *) (* LC_PROBE73_WIDTH = "1" *) 
(* LC_PROBE740_IS_DATA = "1'b0" *) (* LC_PROBE740_IS_TRIG = "1'b0" *) (* LC_PROBE740_MU_CNT = "1" *) 
(* LC_PROBE740_PID = "16'b0000001011100100" *) (* LC_PROBE740_TYPE = "1" *) (* LC_PROBE740_WIDTH = "1" *) 
(* LC_PROBE741_IS_DATA = "1'b0" *) (* LC_PROBE741_IS_TRIG = "1'b0" *) (* LC_PROBE741_MU_CNT = "1" *) 
(* LC_PROBE741_PID = "16'b0000001011100101" *) (* LC_PROBE741_TYPE = "1" *) (* LC_PROBE741_WIDTH = "1" *) 
(* LC_PROBE742_IS_DATA = "1'b0" *) (* LC_PROBE742_IS_TRIG = "1'b0" *) (* LC_PROBE742_MU_CNT = "1" *) 
(* LC_PROBE742_PID = "16'b0000001011100110" *) (* LC_PROBE742_TYPE = "1" *) (* LC_PROBE742_WIDTH = "1" *) 
(* LC_PROBE743_IS_DATA = "1'b0" *) (* LC_PROBE743_IS_TRIG = "1'b0" *) (* LC_PROBE743_MU_CNT = "1" *) 
(* LC_PROBE743_PID = "16'b0000001011100111" *) (* LC_PROBE743_TYPE = "1" *) (* LC_PROBE743_WIDTH = "1" *) 
(* LC_PROBE744_IS_DATA = "1'b0" *) (* LC_PROBE744_IS_TRIG = "1'b0" *) (* LC_PROBE744_MU_CNT = "1" *) 
(* LC_PROBE744_PID = "16'b0000001011101000" *) (* LC_PROBE744_TYPE = "1" *) (* LC_PROBE744_WIDTH = "1" *) 
(* LC_PROBE745_IS_DATA = "1'b0" *) (* LC_PROBE745_IS_TRIG = "1'b0" *) (* LC_PROBE745_MU_CNT = "1" *) 
(* LC_PROBE745_PID = "16'b0000001011101001" *) (* LC_PROBE745_TYPE = "1" *) (* LC_PROBE745_WIDTH = "1" *) 
(* LC_PROBE746_IS_DATA = "1'b0" *) (* LC_PROBE746_IS_TRIG = "1'b0" *) (* LC_PROBE746_MU_CNT = "1" *) 
(* LC_PROBE746_PID = "16'b0000001011101010" *) (* LC_PROBE746_TYPE = "1" *) (* LC_PROBE746_WIDTH = "1" *) 
(* LC_PROBE747_IS_DATA = "1'b0" *) (* LC_PROBE747_IS_TRIG = "1'b0" *) (* LC_PROBE747_MU_CNT = "1" *) 
(* LC_PROBE747_PID = "16'b0000001011101011" *) (* LC_PROBE747_TYPE = "1" *) (* LC_PROBE747_WIDTH = "1" *) 
(* LC_PROBE748_IS_DATA = "1'b0" *) (* LC_PROBE748_IS_TRIG = "1'b0" *) (* LC_PROBE748_MU_CNT = "1" *) 
(* LC_PROBE748_PID = "16'b0000001011101100" *) (* LC_PROBE748_TYPE = "1" *) (* LC_PROBE748_WIDTH = "1" *) 
(* LC_PROBE749_IS_DATA = "1'b0" *) (* LC_PROBE749_IS_TRIG = "1'b0" *) (* LC_PROBE749_MU_CNT = "1" *) 
(* LC_PROBE749_PID = "16'b0000001011101101" *) (* LC_PROBE749_TYPE = "1" *) (* LC_PROBE749_WIDTH = "1" *) 
(* LC_PROBE74_IS_DATA = "1'b0" *) (* LC_PROBE74_IS_TRIG = "1'b0" *) (* LC_PROBE74_MU_CNT = "1" *) 
(* LC_PROBE74_PID = "16'b0000000001001010" *) (* LC_PROBE74_TYPE = "1" *) (* LC_PROBE74_WIDTH = "1" *) 
(* LC_PROBE750_IS_DATA = "1'b0" *) (* LC_PROBE750_IS_TRIG = "1'b0" *) (* LC_PROBE750_MU_CNT = "1" *) 
(* LC_PROBE750_PID = "16'b0000001011101110" *) (* LC_PROBE750_TYPE = "1" *) (* LC_PROBE750_WIDTH = "1" *) 
(* LC_PROBE751_IS_DATA = "1'b0" *) (* LC_PROBE751_IS_TRIG = "1'b0" *) (* LC_PROBE751_MU_CNT = "1" *) 
(* LC_PROBE751_PID = "16'b0000001011101111" *) (* LC_PROBE751_TYPE = "1" *) (* LC_PROBE751_WIDTH = "1" *) 
(* LC_PROBE752_IS_DATA = "1'b0" *) (* LC_PROBE752_IS_TRIG = "1'b0" *) (* LC_PROBE752_MU_CNT = "1" *) 
(* LC_PROBE752_PID = "16'b0000001011110000" *) (* LC_PROBE752_TYPE = "1" *) (* LC_PROBE752_WIDTH = "1" *) 
(* LC_PROBE753_IS_DATA = "1'b0" *) (* LC_PROBE753_IS_TRIG = "1'b0" *) (* LC_PROBE753_MU_CNT = "1" *) 
(* LC_PROBE753_PID = "16'b0000001011110001" *) (* LC_PROBE753_TYPE = "1" *) (* LC_PROBE753_WIDTH = "1" *) 
(* LC_PROBE754_IS_DATA = "1'b0" *) (* LC_PROBE754_IS_TRIG = "1'b0" *) (* LC_PROBE754_MU_CNT = "1" *) 
(* LC_PROBE754_PID = "16'b0000001011110010" *) (* LC_PROBE754_TYPE = "1" *) (* LC_PROBE754_WIDTH = "1" *) 
(* LC_PROBE755_IS_DATA = "1'b0" *) (* LC_PROBE755_IS_TRIG = "1'b0" *) (* LC_PROBE755_MU_CNT = "1" *) 
(* LC_PROBE755_PID = "16'b0000001011110011" *) (* LC_PROBE755_TYPE = "1" *) (* LC_PROBE755_WIDTH = "1" *) 
(* LC_PROBE756_IS_DATA = "1'b0" *) (* LC_PROBE756_IS_TRIG = "1'b0" *) (* LC_PROBE756_MU_CNT = "1" *) 
(* LC_PROBE756_PID = "16'b0000001011110100" *) (* LC_PROBE756_TYPE = "1" *) (* LC_PROBE756_WIDTH = "1" *) 
(* LC_PROBE757_IS_DATA = "1'b0" *) (* LC_PROBE757_IS_TRIG = "1'b0" *) (* LC_PROBE757_MU_CNT = "1" *) 
(* LC_PROBE757_PID = "16'b0000001011110101" *) (* LC_PROBE757_TYPE = "1" *) (* LC_PROBE757_WIDTH = "1" *) 
(* LC_PROBE758_IS_DATA = "1'b0" *) (* LC_PROBE758_IS_TRIG = "1'b0" *) (* LC_PROBE758_MU_CNT = "1" *) 
(* LC_PROBE758_PID = "16'b0000001011110110" *) (* LC_PROBE758_TYPE = "1" *) (* LC_PROBE758_WIDTH = "1" *) 
(* LC_PROBE759_IS_DATA = "1'b0" *) (* LC_PROBE759_IS_TRIG = "1'b0" *) (* LC_PROBE759_MU_CNT = "1" *) 
(* LC_PROBE759_PID = "16'b0000001011110111" *) (* LC_PROBE759_TYPE = "1" *) (* LC_PROBE759_WIDTH = "1" *) 
(* LC_PROBE75_IS_DATA = "1'b0" *) (* LC_PROBE75_IS_TRIG = "1'b0" *) (* LC_PROBE75_MU_CNT = "1" *) 
(* LC_PROBE75_PID = "16'b0000000001001011" *) (* LC_PROBE75_TYPE = "1" *) (* LC_PROBE75_WIDTH = "1" *) 
(* LC_PROBE760_IS_DATA = "1'b0" *) (* LC_PROBE760_IS_TRIG = "1'b0" *) (* LC_PROBE760_MU_CNT = "1" *) 
(* LC_PROBE760_PID = "16'b0000001011111000" *) (* LC_PROBE760_TYPE = "1" *) (* LC_PROBE760_WIDTH = "1" *) 
(* LC_PROBE761_IS_DATA = "1'b0" *) (* LC_PROBE761_IS_TRIG = "1'b0" *) (* LC_PROBE761_MU_CNT = "1" *) 
(* LC_PROBE761_PID = "16'b0000001011111001" *) (* LC_PROBE761_TYPE = "1" *) (* LC_PROBE761_WIDTH = "1" *) 
(* LC_PROBE762_IS_DATA = "1'b0" *) (* LC_PROBE762_IS_TRIG = "1'b0" *) (* LC_PROBE762_MU_CNT = "1" *) 
(* LC_PROBE762_PID = "16'b0000001011111010" *) (* LC_PROBE762_TYPE = "1" *) (* LC_PROBE762_WIDTH = "1" *) 
(* LC_PROBE763_IS_DATA = "1'b0" *) (* LC_PROBE763_IS_TRIG = "1'b0" *) (* LC_PROBE763_MU_CNT = "1" *) 
(* LC_PROBE763_PID = "16'b0000001011111011" *) (* LC_PROBE763_TYPE = "1" *) (* LC_PROBE763_WIDTH = "1" *) 
(* LC_PROBE764_IS_DATA = "1'b0" *) (* LC_PROBE764_IS_TRIG = "1'b0" *) (* LC_PROBE764_MU_CNT = "1" *) 
(* LC_PROBE764_PID = "16'b0000001011111100" *) (* LC_PROBE764_TYPE = "1" *) (* LC_PROBE764_WIDTH = "1" *) 
(* LC_PROBE765_IS_DATA = "1'b0" *) (* LC_PROBE765_IS_TRIG = "1'b0" *) (* LC_PROBE765_MU_CNT = "1" *) 
(* LC_PROBE765_PID = "16'b0000001011111101" *) (* LC_PROBE765_TYPE = "1" *) (* LC_PROBE765_WIDTH = "1" *) 
(* LC_PROBE766_IS_DATA = "1'b0" *) (* LC_PROBE766_IS_TRIG = "1'b0" *) (* LC_PROBE766_MU_CNT = "1" *) 
(* LC_PROBE766_PID = "16'b0000001011111110" *) (* LC_PROBE766_TYPE = "1" *) (* LC_PROBE766_WIDTH = "1" *) 
(* LC_PROBE767_IS_DATA = "1'b0" *) (* LC_PROBE767_IS_TRIG = "1'b0" *) (* LC_PROBE767_MU_CNT = "1" *) 
(* LC_PROBE767_PID = "16'b0000001011111111" *) (* LC_PROBE767_TYPE = "1" *) (* LC_PROBE767_WIDTH = "1" *) 
(* LC_PROBE768_IS_DATA = "1'b0" *) (* LC_PROBE768_IS_TRIG = "1'b0" *) (* LC_PROBE768_MU_CNT = "1" *) 
(* LC_PROBE768_PID = "16'b0000001100000000" *) (* LC_PROBE768_TYPE = "1" *) (* LC_PROBE768_WIDTH = "1" *) 
(* LC_PROBE769_IS_DATA = "1'b0" *) (* LC_PROBE769_IS_TRIG = "1'b0" *) (* LC_PROBE769_MU_CNT = "1" *) 
(* LC_PROBE769_PID = "16'b0000001100000001" *) (* LC_PROBE769_TYPE = "1" *) (* LC_PROBE769_WIDTH = "1" *) 
(* LC_PROBE76_IS_DATA = "1'b0" *) (* LC_PROBE76_IS_TRIG = "1'b0" *) (* LC_PROBE76_MU_CNT = "1" *) 
(* LC_PROBE76_PID = "16'b0000000001001100" *) (* LC_PROBE76_TYPE = "1" *) (* LC_PROBE76_WIDTH = "1" *) 
(* LC_PROBE770_IS_DATA = "1'b0" *) (* LC_PROBE770_IS_TRIG = "1'b0" *) (* LC_PROBE770_MU_CNT = "1" *) 
(* LC_PROBE770_PID = "16'b0000001100000010" *) (* LC_PROBE770_TYPE = "1" *) (* LC_PROBE770_WIDTH = "1" *) 
(* LC_PROBE771_IS_DATA = "1'b0" *) (* LC_PROBE771_IS_TRIG = "1'b0" *) (* LC_PROBE771_MU_CNT = "1" *) 
(* LC_PROBE771_PID = "16'b0000001100000011" *) (* LC_PROBE771_TYPE = "1" *) (* LC_PROBE771_WIDTH = "1" *) 
(* LC_PROBE772_IS_DATA = "1'b0" *) (* LC_PROBE772_IS_TRIG = "1'b0" *) (* LC_PROBE772_MU_CNT = "1" *) 
(* LC_PROBE772_PID = "16'b0000001100000100" *) (* LC_PROBE772_TYPE = "1" *) (* LC_PROBE772_WIDTH = "1" *) 
(* LC_PROBE773_IS_DATA = "1'b0" *) (* LC_PROBE773_IS_TRIG = "1'b0" *) (* LC_PROBE773_MU_CNT = "1" *) 
(* LC_PROBE773_PID = "16'b0000001100000101" *) (* LC_PROBE773_TYPE = "1" *) (* LC_PROBE773_WIDTH = "1" *) 
(* LC_PROBE774_IS_DATA = "1'b0" *) (* LC_PROBE774_IS_TRIG = "1'b0" *) (* LC_PROBE774_MU_CNT = "1" *) 
(* LC_PROBE774_PID = "16'b0000001100000110" *) (* LC_PROBE774_TYPE = "1" *) (* LC_PROBE774_WIDTH = "1" *) 
(* LC_PROBE775_IS_DATA = "1'b0" *) (* LC_PROBE775_IS_TRIG = "1'b0" *) (* LC_PROBE775_MU_CNT = "1" *) 
(* LC_PROBE775_PID = "16'b0000001100000111" *) (* LC_PROBE775_TYPE = "1" *) (* LC_PROBE775_WIDTH = "1" *) 
(* LC_PROBE776_IS_DATA = "1'b0" *) (* LC_PROBE776_IS_TRIG = "1'b0" *) (* LC_PROBE776_MU_CNT = "1" *) 
(* LC_PROBE776_PID = "16'b0000001100001000" *) (* LC_PROBE776_TYPE = "1" *) (* LC_PROBE776_WIDTH = "1" *) 
(* LC_PROBE777_IS_DATA = "1'b0" *) (* LC_PROBE777_IS_TRIG = "1'b0" *) (* LC_PROBE777_MU_CNT = "1" *) 
(* LC_PROBE777_PID = "16'b0000001100001001" *) (* LC_PROBE777_TYPE = "1" *) (* LC_PROBE777_WIDTH = "1" *) 
(* LC_PROBE778_IS_DATA = "1'b0" *) (* LC_PROBE778_IS_TRIG = "1'b0" *) (* LC_PROBE778_MU_CNT = "1" *) 
(* LC_PROBE778_PID = "16'b0000001100001010" *) (* LC_PROBE778_TYPE = "1" *) (* LC_PROBE778_WIDTH = "1" *) 
(* LC_PROBE779_IS_DATA = "1'b0" *) (* LC_PROBE779_IS_TRIG = "1'b0" *) (* LC_PROBE779_MU_CNT = "1" *) 
(* LC_PROBE779_PID = "16'b0000001100001011" *) (* LC_PROBE779_TYPE = "1" *) (* LC_PROBE779_WIDTH = "1" *) 
(* LC_PROBE77_IS_DATA = "1'b0" *) (* LC_PROBE77_IS_TRIG = "1'b0" *) (* LC_PROBE77_MU_CNT = "1" *) 
(* LC_PROBE77_PID = "16'b0000000001001101" *) (* LC_PROBE77_TYPE = "1" *) (* LC_PROBE77_WIDTH = "1" *) 
(* LC_PROBE780_IS_DATA = "1'b0" *) (* LC_PROBE780_IS_TRIG = "1'b0" *) (* LC_PROBE780_MU_CNT = "1" *) 
(* LC_PROBE780_PID = "16'b0000001100001100" *) (* LC_PROBE780_TYPE = "1" *) (* LC_PROBE780_WIDTH = "1" *) 
(* LC_PROBE781_IS_DATA = "1'b0" *) (* LC_PROBE781_IS_TRIG = "1'b0" *) (* LC_PROBE781_MU_CNT = "1" *) 
(* LC_PROBE781_PID = "16'b0000001100001101" *) (* LC_PROBE781_TYPE = "1" *) (* LC_PROBE781_WIDTH = "1" *) 
(* LC_PROBE782_IS_DATA = "1'b0" *) (* LC_PROBE782_IS_TRIG = "1'b0" *) (* LC_PROBE782_MU_CNT = "1" *) 
(* LC_PROBE782_PID = "16'b0000001100001110" *) (* LC_PROBE782_TYPE = "1" *) (* LC_PROBE782_WIDTH = "1" *) 
(* LC_PROBE783_IS_DATA = "1'b0" *) (* LC_PROBE783_IS_TRIG = "1'b0" *) (* LC_PROBE783_MU_CNT = "1" *) 
(* LC_PROBE783_PID = "16'b0000001100001111" *) (* LC_PROBE783_TYPE = "1" *) (* LC_PROBE783_WIDTH = "1" *) 
(* LC_PROBE784_IS_DATA = "1'b0" *) (* LC_PROBE784_IS_TRIG = "1'b0" *) (* LC_PROBE784_MU_CNT = "1" *) 
(* LC_PROBE784_PID = "16'b0000001100010000" *) (* LC_PROBE784_TYPE = "1" *) (* LC_PROBE784_WIDTH = "1" *) 
(* LC_PROBE785_IS_DATA = "1'b0" *) (* LC_PROBE785_IS_TRIG = "1'b0" *) (* LC_PROBE785_MU_CNT = "1" *) 
(* LC_PROBE785_PID = "16'b0000001100010001" *) (* LC_PROBE785_TYPE = "1" *) (* LC_PROBE785_WIDTH = "1" *) 
(* LC_PROBE786_IS_DATA = "1'b0" *) (* LC_PROBE786_IS_TRIG = "1'b0" *) (* LC_PROBE786_MU_CNT = "1" *) 
(* LC_PROBE786_PID = "16'b0000001100010010" *) (* LC_PROBE786_TYPE = "1" *) (* LC_PROBE786_WIDTH = "1" *) 
(* LC_PROBE787_IS_DATA = "1'b0" *) (* LC_PROBE787_IS_TRIG = "1'b0" *) (* LC_PROBE787_MU_CNT = "1" *) 
(* LC_PROBE787_PID = "16'b0000001100010011" *) (* LC_PROBE787_TYPE = "1" *) (* LC_PROBE787_WIDTH = "1" *) 
(* LC_PROBE788_IS_DATA = "1'b0" *) (* LC_PROBE788_IS_TRIG = "1'b0" *) (* LC_PROBE788_MU_CNT = "1" *) 
(* LC_PROBE788_PID = "16'b0000001100010100" *) (* LC_PROBE788_TYPE = "1" *) (* LC_PROBE788_WIDTH = "1" *) 
(* LC_PROBE789_IS_DATA = "1'b0" *) (* LC_PROBE789_IS_TRIG = "1'b0" *) (* LC_PROBE789_MU_CNT = "1" *) 
(* LC_PROBE789_PID = "16'b0000001100010101" *) (* LC_PROBE789_TYPE = "1" *) (* LC_PROBE789_WIDTH = "1" *) 
(* LC_PROBE78_IS_DATA = "1'b0" *) (* LC_PROBE78_IS_TRIG = "1'b0" *) (* LC_PROBE78_MU_CNT = "1" *) 
(* LC_PROBE78_PID = "16'b0000000001001110" *) (* LC_PROBE78_TYPE = "1" *) (* LC_PROBE78_WIDTH = "1" *) 
(* LC_PROBE790_IS_DATA = "1'b0" *) (* LC_PROBE790_IS_TRIG = "1'b0" *) (* LC_PROBE790_MU_CNT = "1" *) 
(* LC_PROBE790_PID = "16'b0000001100010110" *) (* LC_PROBE790_TYPE = "1" *) (* LC_PROBE790_WIDTH = "1" *) 
(* LC_PROBE791_IS_DATA = "1'b0" *) (* LC_PROBE791_IS_TRIG = "1'b0" *) (* LC_PROBE791_MU_CNT = "1" *) 
(* LC_PROBE791_PID = "16'b0000001100010111" *) (* LC_PROBE791_TYPE = "1" *) (* LC_PROBE791_WIDTH = "1" *) 
(* LC_PROBE792_IS_DATA = "1'b0" *) (* LC_PROBE792_IS_TRIG = "1'b0" *) (* LC_PROBE792_MU_CNT = "1" *) 
(* LC_PROBE792_PID = "16'b0000001100011000" *) (* LC_PROBE792_TYPE = "1" *) (* LC_PROBE792_WIDTH = "1" *) 
(* LC_PROBE793_IS_DATA = "1'b0" *) (* LC_PROBE793_IS_TRIG = "1'b0" *) (* LC_PROBE793_MU_CNT = "1" *) 
(* LC_PROBE793_PID = "16'b0000001100011001" *) (* LC_PROBE793_TYPE = "1" *) (* LC_PROBE793_WIDTH = "1" *) 
(* LC_PROBE794_IS_DATA = "1'b0" *) (* LC_PROBE794_IS_TRIG = "1'b0" *) (* LC_PROBE794_MU_CNT = "1" *) 
(* LC_PROBE794_PID = "16'b0000001100011010" *) (* LC_PROBE794_TYPE = "1" *) (* LC_PROBE794_WIDTH = "1" *) 
(* LC_PROBE795_IS_DATA = "1'b0" *) (* LC_PROBE795_IS_TRIG = "1'b0" *) (* LC_PROBE795_MU_CNT = "1" *) 
(* LC_PROBE795_PID = "16'b0000001100011011" *) (* LC_PROBE795_TYPE = "1" *) (* LC_PROBE795_WIDTH = "1" *) 
(* LC_PROBE796_IS_DATA = "1'b0" *) (* LC_PROBE796_IS_TRIG = "1'b0" *) (* LC_PROBE796_MU_CNT = "1" *) 
(* LC_PROBE796_PID = "16'b0000001100011100" *) (* LC_PROBE796_TYPE = "1" *) (* LC_PROBE796_WIDTH = "1" *) 
(* LC_PROBE797_IS_DATA = "1'b0" *) (* LC_PROBE797_IS_TRIG = "1'b0" *) (* LC_PROBE797_MU_CNT = "1" *) 
(* LC_PROBE797_PID = "16'b0000001100011101" *) (* LC_PROBE797_TYPE = "1" *) (* LC_PROBE797_WIDTH = "1" *) 
(* LC_PROBE798_IS_DATA = "1'b0" *) (* LC_PROBE798_IS_TRIG = "1'b0" *) (* LC_PROBE798_MU_CNT = "1" *) 
(* LC_PROBE798_PID = "16'b0000001100011110" *) (* LC_PROBE798_TYPE = "1" *) (* LC_PROBE798_WIDTH = "1" *) 
(* LC_PROBE799_IS_DATA = "1'b0" *) (* LC_PROBE799_IS_TRIG = "1'b0" *) (* LC_PROBE799_MU_CNT = "1" *) 
(* LC_PROBE799_PID = "16'b0000001100011111" *) (* LC_PROBE799_TYPE = "1" *) (* LC_PROBE799_WIDTH = "1" *) 
(* LC_PROBE79_IS_DATA = "1'b0" *) (* LC_PROBE79_IS_TRIG = "1'b0" *) (* LC_PROBE79_MU_CNT = "1" *) 
(* LC_PROBE79_PID = "16'b0000000001001111" *) (* LC_PROBE79_TYPE = "1" *) (* LC_PROBE79_WIDTH = "1" *) 
(* LC_PROBE7_IS_DATA = "1'b0" *) (* LC_PROBE7_IS_TRIG = "1'b0" *) (* LC_PROBE7_MU_CNT = "1" *) 
(* LC_PROBE7_PID = "16'b0000000000000111" *) (* LC_PROBE7_TYPE = "1" *) (* LC_PROBE7_WIDTH = "1" *) 
(* LC_PROBE800_IS_DATA = "1'b0" *) (* LC_PROBE800_IS_TRIG = "1'b0" *) (* LC_PROBE800_MU_CNT = "1" *) 
(* LC_PROBE800_PID = "16'b0000001100100000" *) (* LC_PROBE800_TYPE = "1" *) (* LC_PROBE800_WIDTH = "1" *) 
(* LC_PROBE801_IS_DATA = "1'b0" *) (* LC_PROBE801_IS_TRIG = "1'b0" *) (* LC_PROBE801_MU_CNT = "1" *) 
(* LC_PROBE801_PID = "16'b0000001100100001" *) (* LC_PROBE801_TYPE = "1" *) (* LC_PROBE801_WIDTH = "1" *) 
(* LC_PROBE802_IS_DATA = "1'b0" *) (* LC_PROBE802_IS_TRIG = "1'b0" *) (* LC_PROBE802_MU_CNT = "1" *) 
(* LC_PROBE802_PID = "16'b0000001100100010" *) (* LC_PROBE802_TYPE = "1" *) (* LC_PROBE802_WIDTH = "1" *) 
(* LC_PROBE803_IS_DATA = "1'b0" *) (* LC_PROBE803_IS_TRIG = "1'b0" *) (* LC_PROBE803_MU_CNT = "1" *) 
(* LC_PROBE803_PID = "16'b0000001100100011" *) (* LC_PROBE803_TYPE = "1" *) (* LC_PROBE803_WIDTH = "1" *) 
(* LC_PROBE804_IS_DATA = "1'b0" *) (* LC_PROBE804_IS_TRIG = "1'b0" *) (* LC_PROBE804_MU_CNT = "1" *) 
(* LC_PROBE804_PID = "16'b0000001100100100" *) (* LC_PROBE804_TYPE = "1" *) (* LC_PROBE804_WIDTH = "1" *) 
(* LC_PROBE805_IS_DATA = "1'b0" *) (* LC_PROBE805_IS_TRIG = "1'b0" *) (* LC_PROBE805_MU_CNT = "1" *) 
(* LC_PROBE805_PID = "16'b0000001100100101" *) (* LC_PROBE805_TYPE = "1" *) (* LC_PROBE805_WIDTH = "1" *) 
(* LC_PROBE806_IS_DATA = "1'b0" *) (* LC_PROBE806_IS_TRIG = "1'b0" *) (* LC_PROBE806_MU_CNT = "1" *) 
(* LC_PROBE806_PID = "16'b0000001100100110" *) (* LC_PROBE806_TYPE = "1" *) (* LC_PROBE806_WIDTH = "1" *) 
(* LC_PROBE807_IS_DATA = "1'b0" *) (* LC_PROBE807_IS_TRIG = "1'b0" *) (* LC_PROBE807_MU_CNT = "1" *) 
(* LC_PROBE807_PID = "16'b0000001100100111" *) (* LC_PROBE807_TYPE = "1" *) (* LC_PROBE807_WIDTH = "1" *) 
(* LC_PROBE808_IS_DATA = "1'b0" *) (* LC_PROBE808_IS_TRIG = "1'b0" *) (* LC_PROBE808_MU_CNT = "1" *) 
(* LC_PROBE808_PID = "16'b0000001100101000" *) (* LC_PROBE808_TYPE = "1" *) (* LC_PROBE808_WIDTH = "1" *) 
(* LC_PROBE809_IS_DATA = "1'b0" *) (* LC_PROBE809_IS_TRIG = "1'b0" *) (* LC_PROBE809_MU_CNT = "1" *) 
(* LC_PROBE809_PID = "16'b0000001100101001" *) (* LC_PROBE809_TYPE = "1" *) (* LC_PROBE809_WIDTH = "1" *) 
(* LC_PROBE80_IS_DATA = "1'b0" *) (* LC_PROBE80_IS_TRIG = "1'b0" *) (* LC_PROBE80_MU_CNT = "1" *) 
(* LC_PROBE80_PID = "16'b0000000001010000" *) (* LC_PROBE80_TYPE = "1" *) (* LC_PROBE80_WIDTH = "1" *) 
(* LC_PROBE810_IS_DATA = "1'b0" *) (* LC_PROBE810_IS_TRIG = "1'b0" *) (* LC_PROBE810_MU_CNT = "1" *) 
(* LC_PROBE810_PID = "16'b0000001100101010" *) (* LC_PROBE810_TYPE = "1" *) (* LC_PROBE810_WIDTH = "1" *) 
(* LC_PROBE811_IS_DATA = "1'b0" *) (* LC_PROBE811_IS_TRIG = "1'b0" *) (* LC_PROBE811_MU_CNT = "1" *) 
(* LC_PROBE811_PID = "16'b0000001100101011" *) (* LC_PROBE811_TYPE = "1" *) (* LC_PROBE811_WIDTH = "1" *) 
(* LC_PROBE812_IS_DATA = "1'b0" *) (* LC_PROBE812_IS_TRIG = "1'b0" *) (* LC_PROBE812_MU_CNT = "1" *) 
(* LC_PROBE812_PID = "16'b0000001100101100" *) (* LC_PROBE812_TYPE = "1" *) (* LC_PROBE812_WIDTH = "1" *) 
(* LC_PROBE813_IS_DATA = "1'b0" *) (* LC_PROBE813_IS_TRIG = "1'b0" *) (* LC_PROBE813_MU_CNT = "1" *) 
(* LC_PROBE813_PID = "16'b0000001100101101" *) (* LC_PROBE813_TYPE = "1" *) (* LC_PROBE813_WIDTH = "1" *) 
(* LC_PROBE814_IS_DATA = "1'b0" *) (* LC_PROBE814_IS_TRIG = "1'b0" *) (* LC_PROBE814_MU_CNT = "1" *) 
(* LC_PROBE814_PID = "16'b0000001100101110" *) (* LC_PROBE814_TYPE = "1" *) (* LC_PROBE814_WIDTH = "1" *) 
(* LC_PROBE815_IS_DATA = "1'b0" *) (* LC_PROBE815_IS_TRIG = "1'b0" *) (* LC_PROBE815_MU_CNT = "1" *) 
(* LC_PROBE815_PID = "16'b0000001100101111" *) (* LC_PROBE815_TYPE = "1" *) (* LC_PROBE815_WIDTH = "1" *) 
(* LC_PROBE816_IS_DATA = "1'b0" *) (* LC_PROBE816_IS_TRIG = "1'b0" *) (* LC_PROBE816_MU_CNT = "1" *) 
(* LC_PROBE816_PID = "16'b0000001100110000" *) (* LC_PROBE816_TYPE = "1" *) (* LC_PROBE816_WIDTH = "1" *) 
(* LC_PROBE817_IS_DATA = "1'b0" *) (* LC_PROBE817_IS_TRIG = "1'b0" *) (* LC_PROBE817_MU_CNT = "1" *) 
(* LC_PROBE817_PID = "16'b0000001100110001" *) (* LC_PROBE817_TYPE = "1" *) (* LC_PROBE817_WIDTH = "1" *) 
(* LC_PROBE818_IS_DATA = "1'b0" *) (* LC_PROBE818_IS_TRIG = "1'b0" *) (* LC_PROBE818_MU_CNT = "1" *) 
(* LC_PROBE818_PID = "16'b0000001100110010" *) (* LC_PROBE818_TYPE = "1" *) (* LC_PROBE818_WIDTH = "1" *) 
(* LC_PROBE819_IS_DATA = "1'b0" *) (* LC_PROBE819_IS_TRIG = "1'b0" *) (* LC_PROBE819_MU_CNT = "1" *) 
(* LC_PROBE819_PID = "16'b0000001100110011" *) (* LC_PROBE819_TYPE = "1" *) (* LC_PROBE819_WIDTH = "1" *) 
(* LC_PROBE81_IS_DATA = "1'b0" *) (* LC_PROBE81_IS_TRIG = "1'b0" *) (* LC_PROBE81_MU_CNT = "1" *) 
(* LC_PROBE81_PID = "16'b0000000001010001" *) (* LC_PROBE81_TYPE = "1" *) (* LC_PROBE81_WIDTH = "1" *) 
(* LC_PROBE820_IS_DATA = "1'b0" *) (* LC_PROBE820_IS_TRIG = "1'b0" *) (* LC_PROBE820_MU_CNT = "1" *) 
(* LC_PROBE820_PID = "16'b0000001100110100" *) (* LC_PROBE820_TYPE = "1" *) (* LC_PROBE820_WIDTH = "1" *) 
(* LC_PROBE821_IS_DATA = "1'b0" *) (* LC_PROBE821_IS_TRIG = "1'b0" *) (* LC_PROBE821_MU_CNT = "1" *) 
(* LC_PROBE821_PID = "16'b0000001100110101" *) (* LC_PROBE821_TYPE = "1" *) (* LC_PROBE821_WIDTH = "1" *) 
(* LC_PROBE822_IS_DATA = "1'b0" *) (* LC_PROBE822_IS_TRIG = "1'b0" *) (* LC_PROBE822_MU_CNT = "1" *) 
(* LC_PROBE822_PID = "16'b0000001100110110" *) (* LC_PROBE822_TYPE = "1" *) (* LC_PROBE822_WIDTH = "1" *) 
(* LC_PROBE823_IS_DATA = "1'b0" *) (* LC_PROBE823_IS_TRIG = "1'b0" *) (* LC_PROBE823_MU_CNT = "1" *) 
(* LC_PROBE823_PID = "16'b0000001100110111" *) (* LC_PROBE823_TYPE = "1" *) (* LC_PROBE823_WIDTH = "1" *) 
(* LC_PROBE824_IS_DATA = "1'b0" *) (* LC_PROBE824_IS_TRIG = "1'b0" *) (* LC_PROBE824_MU_CNT = "1" *) 
(* LC_PROBE824_PID = "16'b0000001100111000" *) (* LC_PROBE824_TYPE = "1" *) (* LC_PROBE824_WIDTH = "1" *) 
(* LC_PROBE825_IS_DATA = "1'b0" *) (* LC_PROBE825_IS_TRIG = "1'b0" *) (* LC_PROBE825_MU_CNT = "1" *) 
(* LC_PROBE825_PID = "16'b0000001100111001" *) (* LC_PROBE825_TYPE = "1" *) (* LC_PROBE825_WIDTH = "1" *) 
(* LC_PROBE826_IS_DATA = "1'b0" *) (* LC_PROBE826_IS_TRIG = "1'b0" *) (* LC_PROBE826_MU_CNT = "1" *) 
(* LC_PROBE826_PID = "16'b0000001100111010" *) (* LC_PROBE826_TYPE = "1" *) (* LC_PROBE826_WIDTH = "1" *) 
(* LC_PROBE827_IS_DATA = "1'b0" *) (* LC_PROBE827_IS_TRIG = "1'b0" *) (* LC_PROBE827_MU_CNT = "1" *) 
(* LC_PROBE827_PID = "16'b0000001100111011" *) (* LC_PROBE827_TYPE = "1" *) (* LC_PROBE827_WIDTH = "1" *) 
(* LC_PROBE828_IS_DATA = "1'b0" *) (* LC_PROBE828_IS_TRIG = "1'b0" *) (* LC_PROBE828_MU_CNT = "1" *) 
(* LC_PROBE828_PID = "16'b0000001100111100" *) (* LC_PROBE828_TYPE = "1" *) (* LC_PROBE828_WIDTH = "1" *) 
(* LC_PROBE829_IS_DATA = "1'b0" *) (* LC_PROBE829_IS_TRIG = "1'b0" *) (* LC_PROBE829_MU_CNT = "1" *) 
(* LC_PROBE829_PID = "16'b0000001100111101" *) (* LC_PROBE829_TYPE = "1" *) (* LC_PROBE829_WIDTH = "1" *) 
(* LC_PROBE82_IS_DATA = "1'b0" *) (* LC_PROBE82_IS_TRIG = "1'b0" *) (* LC_PROBE82_MU_CNT = "1" *) 
(* LC_PROBE82_PID = "16'b0000000001010010" *) (* LC_PROBE82_TYPE = "1" *) (* LC_PROBE82_WIDTH = "1" *) 
(* LC_PROBE830_IS_DATA = "1'b0" *) (* LC_PROBE830_IS_TRIG = "1'b0" *) (* LC_PROBE830_MU_CNT = "1" *) 
(* LC_PROBE830_PID = "16'b0000001100111110" *) (* LC_PROBE830_TYPE = "1" *) (* LC_PROBE830_WIDTH = "1" *) 
(* LC_PROBE831_IS_DATA = "1'b0" *) (* LC_PROBE831_IS_TRIG = "1'b0" *) (* LC_PROBE831_MU_CNT = "1" *) 
(* LC_PROBE831_PID = "16'b0000001100111111" *) (* LC_PROBE831_TYPE = "1" *) (* LC_PROBE831_WIDTH = "1" *) 
(* LC_PROBE832_IS_DATA = "1'b0" *) (* LC_PROBE832_IS_TRIG = "1'b0" *) (* LC_PROBE832_MU_CNT = "1" *) 
(* LC_PROBE832_PID = "16'b0000001101000000" *) (* LC_PROBE832_TYPE = "1" *) (* LC_PROBE832_WIDTH = "1" *) 
(* LC_PROBE833_IS_DATA = "1'b0" *) (* LC_PROBE833_IS_TRIG = "1'b0" *) (* LC_PROBE833_MU_CNT = "1" *) 
(* LC_PROBE833_PID = "16'b0000001101000001" *) (* LC_PROBE833_TYPE = "1" *) (* LC_PROBE833_WIDTH = "1" *) 
(* LC_PROBE834_IS_DATA = "1'b0" *) (* LC_PROBE834_IS_TRIG = "1'b0" *) (* LC_PROBE834_MU_CNT = "1" *) 
(* LC_PROBE834_PID = "16'b0000001101000010" *) (* LC_PROBE834_TYPE = "1" *) (* LC_PROBE834_WIDTH = "1" *) 
(* LC_PROBE835_IS_DATA = "1'b0" *) (* LC_PROBE835_IS_TRIG = "1'b0" *) (* LC_PROBE835_MU_CNT = "1" *) 
(* LC_PROBE835_PID = "16'b0000001101000011" *) (* LC_PROBE835_TYPE = "1" *) (* LC_PROBE835_WIDTH = "1" *) 
(* LC_PROBE836_IS_DATA = "1'b0" *) (* LC_PROBE836_IS_TRIG = "1'b0" *) (* LC_PROBE836_MU_CNT = "1" *) 
(* LC_PROBE836_PID = "16'b0000001101000100" *) (* LC_PROBE836_TYPE = "1" *) (* LC_PROBE836_WIDTH = "1" *) 
(* LC_PROBE837_IS_DATA = "1'b0" *) (* LC_PROBE837_IS_TRIG = "1'b0" *) (* LC_PROBE837_MU_CNT = "1" *) 
(* LC_PROBE837_PID = "16'b0000001101000101" *) (* LC_PROBE837_TYPE = "1" *) (* LC_PROBE837_WIDTH = "1" *) 
(* LC_PROBE838_IS_DATA = "1'b0" *) (* LC_PROBE838_IS_TRIG = "1'b0" *) (* LC_PROBE838_MU_CNT = "1" *) 
(* LC_PROBE838_PID = "16'b0000001101000110" *) (* LC_PROBE838_TYPE = "1" *) (* LC_PROBE838_WIDTH = "1" *) 
(* LC_PROBE839_IS_DATA = "1'b0" *) (* LC_PROBE839_IS_TRIG = "1'b0" *) (* LC_PROBE839_MU_CNT = "1" *) 
(* LC_PROBE839_PID = "16'b0000001101000111" *) (* LC_PROBE839_TYPE = "1" *) (* LC_PROBE839_WIDTH = "1" *) 
(* LC_PROBE83_IS_DATA = "1'b0" *) (* LC_PROBE83_IS_TRIG = "1'b0" *) (* LC_PROBE83_MU_CNT = "1" *) 
(* LC_PROBE83_PID = "16'b0000000001010011" *) (* LC_PROBE83_TYPE = "1" *) (* LC_PROBE83_WIDTH = "1" *) 
(* LC_PROBE840_IS_DATA = "1'b0" *) (* LC_PROBE840_IS_TRIG = "1'b0" *) (* LC_PROBE840_MU_CNT = "1" *) 
(* LC_PROBE840_PID = "16'b0000001101001000" *) (* LC_PROBE840_TYPE = "1" *) (* LC_PROBE840_WIDTH = "1" *) 
(* LC_PROBE841_IS_DATA = "1'b0" *) (* LC_PROBE841_IS_TRIG = "1'b0" *) (* LC_PROBE841_MU_CNT = "1" *) 
(* LC_PROBE841_PID = "16'b0000001101001001" *) (* LC_PROBE841_TYPE = "1" *) (* LC_PROBE841_WIDTH = "1" *) 
(* LC_PROBE842_IS_DATA = "1'b0" *) (* LC_PROBE842_IS_TRIG = "1'b0" *) (* LC_PROBE842_MU_CNT = "1" *) 
(* LC_PROBE842_PID = "16'b0000001101001010" *) (* LC_PROBE842_TYPE = "1" *) (* LC_PROBE842_WIDTH = "1" *) 
(* LC_PROBE843_IS_DATA = "1'b0" *) (* LC_PROBE843_IS_TRIG = "1'b0" *) (* LC_PROBE843_MU_CNT = "1" *) 
(* LC_PROBE843_PID = "16'b0000001101001011" *) (* LC_PROBE843_TYPE = "1" *) (* LC_PROBE843_WIDTH = "1" *) 
(* LC_PROBE844_IS_DATA = "1'b0" *) (* LC_PROBE844_IS_TRIG = "1'b0" *) (* LC_PROBE844_MU_CNT = "1" *) 
(* LC_PROBE844_PID = "16'b0000001101001100" *) (* LC_PROBE844_TYPE = "1" *) (* LC_PROBE844_WIDTH = "1" *) 
(* LC_PROBE845_IS_DATA = "1'b0" *) (* LC_PROBE845_IS_TRIG = "1'b0" *) (* LC_PROBE845_MU_CNT = "1" *) 
(* LC_PROBE845_PID = "16'b0000001101001101" *) (* LC_PROBE845_TYPE = "1" *) (* LC_PROBE845_WIDTH = "1" *) 
(* LC_PROBE846_IS_DATA = "1'b0" *) (* LC_PROBE846_IS_TRIG = "1'b0" *) (* LC_PROBE846_MU_CNT = "1" *) 
(* LC_PROBE846_PID = "16'b0000001101001110" *) (* LC_PROBE846_TYPE = "1" *) (* LC_PROBE846_WIDTH = "1" *) 
(* LC_PROBE847_IS_DATA = "1'b0" *) (* LC_PROBE847_IS_TRIG = "1'b0" *) (* LC_PROBE847_MU_CNT = "1" *) 
(* LC_PROBE847_PID = "16'b0000001101001111" *) (* LC_PROBE847_TYPE = "1" *) (* LC_PROBE847_WIDTH = "1" *) 
(* LC_PROBE848_IS_DATA = "1'b0" *) (* LC_PROBE848_IS_TRIG = "1'b0" *) (* LC_PROBE848_MU_CNT = "1" *) 
(* LC_PROBE848_PID = "16'b0000001101010000" *) (* LC_PROBE848_TYPE = "1" *) (* LC_PROBE848_WIDTH = "1" *) 
(* LC_PROBE849_IS_DATA = "1'b0" *) (* LC_PROBE849_IS_TRIG = "1'b0" *) (* LC_PROBE849_MU_CNT = "1" *) 
(* LC_PROBE849_PID = "16'b0000001101010001" *) (* LC_PROBE849_TYPE = "1" *) (* LC_PROBE849_WIDTH = "1" *) 
(* LC_PROBE84_IS_DATA = "1'b0" *) (* LC_PROBE84_IS_TRIG = "1'b0" *) (* LC_PROBE84_MU_CNT = "1" *) 
(* LC_PROBE84_PID = "16'b0000000001010100" *) (* LC_PROBE84_TYPE = "1" *) (* LC_PROBE84_WIDTH = "1" *) 
(* LC_PROBE850_IS_DATA = "1'b0" *) (* LC_PROBE850_IS_TRIG = "1'b0" *) (* LC_PROBE850_MU_CNT = "1" *) 
(* LC_PROBE850_PID = "16'b0000001101010010" *) (* LC_PROBE850_TYPE = "1" *) (* LC_PROBE850_WIDTH = "1" *) 
(* LC_PROBE851_IS_DATA = "1'b0" *) (* LC_PROBE851_IS_TRIG = "1'b0" *) (* LC_PROBE851_MU_CNT = "1" *) 
(* LC_PROBE851_PID = "16'b0000001101010011" *) (* LC_PROBE851_TYPE = "1" *) (* LC_PROBE851_WIDTH = "1" *) 
(* LC_PROBE852_IS_DATA = "1'b0" *) (* LC_PROBE852_IS_TRIG = "1'b0" *) (* LC_PROBE852_MU_CNT = "1" *) 
(* LC_PROBE852_PID = "16'b0000001101010100" *) (* LC_PROBE852_TYPE = "1" *) (* LC_PROBE852_WIDTH = "1" *) 
(* LC_PROBE853_IS_DATA = "1'b0" *) (* LC_PROBE853_IS_TRIG = "1'b0" *) (* LC_PROBE853_MU_CNT = "1" *) 
(* LC_PROBE853_PID = "16'b0000001101010101" *) (* LC_PROBE853_TYPE = "1" *) (* LC_PROBE853_WIDTH = "1" *) 
(* LC_PROBE854_IS_DATA = "1'b0" *) (* LC_PROBE854_IS_TRIG = "1'b0" *) (* LC_PROBE854_MU_CNT = "1" *) 
(* LC_PROBE854_PID = "16'b0000001101010110" *) (* LC_PROBE854_TYPE = "1" *) (* LC_PROBE854_WIDTH = "1" *) 
(* LC_PROBE855_IS_DATA = "1'b0" *) (* LC_PROBE855_IS_TRIG = "1'b0" *) (* LC_PROBE855_MU_CNT = "1" *) 
(* LC_PROBE855_PID = "16'b0000001101010111" *) (* LC_PROBE855_TYPE = "1" *) (* LC_PROBE855_WIDTH = "1" *) 
(* LC_PROBE856_IS_DATA = "1'b0" *) (* LC_PROBE856_IS_TRIG = "1'b0" *) (* LC_PROBE856_MU_CNT = "1" *) 
(* LC_PROBE856_PID = "16'b0000001101011000" *) (* LC_PROBE856_TYPE = "1" *) (* LC_PROBE856_WIDTH = "1" *) 
(* LC_PROBE857_IS_DATA = "1'b0" *) (* LC_PROBE857_IS_TRIG = "1'b0" *) (* LC_PROBE857_MU_CNT = "1" *) 
(* LC_PROBE857_PID = "16'b0000001101011001" *) (* LC_PROBE857_TYPE = "1" *) (* LC_PROBE857_WIDTH = "1" *) 
(* LC_PROBE858_IS_DATA = "1'b0" *) (* LC_PROBE858_IS_TRIG = "1'b0" *) (* LC_PROBE858_MU_CNT = "1" *) 
(* LC_PROBE858_PID = "16'b0000001101011010" *) (* LC_PROBE858_TYPE = "1" *) (* LC_PROBE858_WIDTH = "1" *) 
(* LC_PROBE859_IS_DATA = "1'b0" *) (* LC_PROBE859_IS_TRIG = "1'b0" *) (* LC_PROBE859_MU_CNT = "1" *) 
(* LC_PROBE859_PID = "16'b0000001101011011" *) (* LC_PROBE859_TYPE = "1" *) (* LC_PROBE859_WIDTH = "1" *) 
(* LC_PROBE85_IS_DATA = "1'b0" *) (* LC_PROBE85_IS_TRIG = "1'b0" *) (* LC_PROBE85_MU_CNT = "1" *) 
(* LC_PROBE85_PID = "16'b0000000001010101" *) (* LC_PROBE85_TYPE = "1" *) (* LC_PROBE85_WIDTH = "1" *) 
(* LC_PROBE860_IS_DATA = "1'b0" *) (* LC_PROBE860_IS_TRIG = "1'b0" *) (* LC_PROBE860_MU_CNT = "1" *) 
(* LC_PROBE860_PID = "16'b0000001101011100" *) (* LC_PROBE860_TYPE = "1" *) (* LC_PROBE860_WIDTH = "1" *) 
(* LC_PROBE861_IS_DATA = "1'b0" *) (* LC_PROBE861_IS_TRIG = "1'b0" *) (* LC_PROBE861_MU_CNT = "1" *) 
(* LC_PROBE861_PID = "16'b0000001101011101" *) (* LC_PROBE861_TYPE = "1" *) (* LC_PROBE861_WIDTH = "1" *) 
(* LC_PROBE862_IS_DATA = "1'b0" *) (* LC_PROBE862_IS_TRIG = "1'b0" *) (* LC_PROBE862_MU_CNT = "1" *) 
(* LC_PROBE862_PID = "16'b0000001101011110" *) (* LC_PROBE862_TYPE = "1" *) (* LC_PROBE862_WIDTH = "1" *) 
(* LC_PROBE863_IS_DATA = "1'b0" *) (* LC_PROBE863_IS_TRIG = "1'b0" *) (* LC_PROBE863_MU_CNT = "1" *) 
(* LC_PROBE863_PID = "16'b0000001101011111" *) (* LC_PROBE863_TYPE = "1" *) (* LC_PROBE863_WIDTH = "1" *) 
(* LC_PROBE864_IS_DATA = "1'b0" *) (* LC_PROBE864_IS_TRIG = "1'b0" *) (* LC_PROBE864_MU_CNT = "1" *) 
(* LC_PROBE864_PID = "16'b0000001101100000" *) (* LC_PROBE864_TYPE = "1" *) (* LC_PROBE864_WIDTH = "1" *) 
(* LC_PROBE865_IS_DATA = "1'b0" *) (* LC_PROBE865_IS_TRIG = "1'b0" *) (* LC_PROBE865_MU_CNT = "1" *) 
(* LC_PROBE865_PID = "16'b0000001101100001" *) (* LC_PROBE865_TYPE = "1" *) (* LC_PROBE865_WIDTH = "1" *) 
(* LC_PROBE866_IS_DATA = "1'b0" *) (* LC_PROBE866_IS_TRIG = "1'b0" *) (* LC_PROBE866_MU_CNT = "1" *) 
(* LC_PROBE866_PID = "16'b0000001101100010" *) (* LC_PROBE866_TYPE = "1" *) (* LC_PROBE866_WIDTH = "1" *) 
(* LC_PROBE867_IS_DATA = "1'b0" *) (* LC_PROBE867_IS_TRIG = "1'b0" *) (* LC_PROBE867_MU_CNT = "1" *) 
(* LC_PROBE867_PID = "16'b0000001101100011" *) (* LC_PROBE867_TYPE = "1" *) (* LC_PROBE867_WIDTH = "1" *) 
(* LC_PROBE868_IS_DATA = "1'b0" *) (* LC_PROBE868_IS_TRIG = "1'b0" *) (* LC_PROBE868_MU_CNT = "1" *) 
(* LC_PROBE868_PID = "16'b0000001101100100" *) (* LC_PROBE868_TYPE = "1" *) (* LC_PROBE868_WIDTH = "1" *) 
(* LC_PROBE869_IS_DATA = "1'b0" *) (* LC_PROBE869_IS_TRIG = "1'b0" *) (* LC_PROBE869_MU_CNT = "1" *) 
(* LC_PROBE869_PID = "16'b0000001101100101" *) (* LC_PROBE869_TYPE = "1" *) (* LC_PROBE869_WIDTH = "1" *) 
(* LC_PROBE86_IS_DATA = "1'b0" *) (* LC_PROBE86_IS_TRIG = "1'b0" *) (* LC_PROBE86_MU_CNT = "1" *) 
(* LC_PROBE86_PID = "16'b0000000001010110" *) (* LC_PROBE86_TYPE = "1" *) (* LC_PROBE86_WIDTH = "1" *) 
(* LC_PROBE870_IS_DATA = "1'b0" *) (* LC_PROBE870_IS_TRIG = "1'b0" *) (* LC_PROBE870_MU_CNT = "1" *) 
(* LC_PROBE870_PID = "16'b0000001101100110" *) (* LC_PROBE870_TYPE = "1" *) (* LC_PROBE870_WIDTH = "1" *) 
(* LC_PROBE871_IS_DATA = "1'b0" *) (* LC_PROBE871_IS_TRIG = "1'b0" *) (* LC_PROBE871_MU_CNT = "1" *) 
(* LC_PROBE871_PID = "16'b0000001101100111" *) (* LC_PROBE871_TYPE = "1" *) (* LC_PROBE871_WIDTH = "1" *) 
(* LC_PROBE872_IS_DATA = "1'b0" *) (* LC_PROBE872_IS_TRIG = "1'b0" *) (* LC_PROBE872_MU_CNT = "1" *) 
(* LC_PROBE872_PID = "16'b0000001101101000" *) (* LC_PROBE872_TYPE = "1" *) (* LC_PROBE872_WIDTH = "1" *) 
(* LC_PROBE873_IS_DATA = "1'b0" *) (* LC_PROBE873_IS_TRIG = "1'b0" *) (* LC_PROBE873_MU_CNT = "1" *) 
(* LC_PROBE873_PID = "16'b0000001101101001" *) (* LC_PROBE873_TYPE = "1" *) (* LC_PROBE873_WIDTH = "1" *) 
(* LC_PROBE874_IS_DATA = "1'b0" *) (* LC_PROBE874_IS_TRIG = "1'b0" *) (* LC_PROBE874_MU_CNT = "1" *) 
(* LC_PROBE874_PID = "16'b0000001101101010" *) (* LC_PROBE874_TYPE = "1" *) (* LC_PROBE874_WIDTH = "1" *) 
(* LC_PROBE875_IS_DATA = "1'b0" *) (* LC_PROBE875_IS_TRIG = "1'b0" *) (* LC_PROBE875_MU_CNT = "1" *) 
(* LC_PROBE875_PID = "16'b0000001101101011" *) (* LC_PROBE875_TYPE = "1" *) (* LC_PROBE875_WIDTH = "1" *) 
(* LC_PROBE876_IS_DATA = "1'b0" *) (* LC_PROBE876_IS_TRIG = "1'b0" *) (* LC_PROBE876_MU_CNT = "1" *) 
(* LC_PROBE876_PID = "16'b0000001101101100" *) (* LC_PROBE876_TYPE = "1" *) (* LC_PROBE876_WIDTH = "1" *) 
(* LC_PROBE877_IS_DATA = "1'b0" *) (* LC_PROBE877_IS_TRIG = "1'b0" *) (* LC_PROBE877_MU_CNT = "1" *) 
(* LC_PROBE877_PID = "16'b0000001101101101" *) (* LC_PROBE877_TYPE = "1" *) (* LC_PROBE877_WIDTH = "1" *) 
(* LC_PROBE878_IS_DATA = "1'b0" *) (* LC_PROBE878_IS_TRIG = "1'b0" *) (* LC_PROBE878_MU_CNT = "1" *) 
(* LC_PROBE878_PID = "16'b0000001101101110" *) (* LC_PROBE878_TYPE = "1" *) (* LC_PROBE878_WIDTH = "1" *) 
(* LC_PROBE879_IS_DATA = "1'b0" *) (* LC_PROBE879_IS_TRIG = "1'b0" *) (* LC_PROBE879_MU_CNT = "1" *) 
(* LC_PROBE879_PID = "16'b0000001101101111" *) (* LC_PROBE879_TYPE = "1" *) (* LC_PROBE879_WIDTH = "1" *) 
(* LC_PROBE87_IS_DATA = "1'b0" *) (* LC_PROBE87_IS_TRIG = "1'b0" *) (* LC_PROBE87_MU_CNT = "1" *) 
(* LC_PROBE87_PID = "16'b0000000001010111" *) (* LC_PROBE87_TYPE = "1" *) (* LC_PROBE87_WIDTH = "1" *) 
(* LC_PROBE880_IS_DATA = "1'b0" *) (* LC_PROBE880_IS_TRIG = "1'b0" *) (* LC_PROBE880_MU_CNT = "1" *) 
(* LC_PROBE880_PID = "16'b0000001101110000" *) (* LC_PROBE880_TYPE = "1" *) (* LC_PROBE880_WIDTH = "1" *) 
(* LC_PROBE881_IS_DATA = "1'b0" *) (* LC_PROBE881_IS_TRIG = "1'b0" *) (* LC_PROBE881_MU_CNT = "1" *) 
(* LC_PROBE881_PID = "16'b0000001101110001" *) (* LC_PROBE881_TYPE = "1" *) (* LC_PROBE881_WIDTH = "1" *) 
(* LC_PROBE882_IS_DATA = "1'b0" *) (* LC_PROBE882_IS_TRIG = "1'b0" *) (* LC_PROBE882_MU_CNT = "1" *) 
(* LC_PROBE882_PID = "16'b0000001101110010" *) (* LC_PROBE882_TYPE = "1" *) (* LC_PROBE882_WIDTH = "1" *) 
(* LC_PROBE883_IS_DATA = "1'b0" *) (* LC_PROBE883_IS_TRIG = "1'b0" *) (* LC_PROBE883_MU_CNT = "1" *) 
(* LC_PROBE883_PID = "16'b0000001101110011" *) (* LC_PROBE883_TYPE = "1" *) (* LC_PROBE883_WIDTH = "1" *) 
(* LC_PROBE884_IS_DATA = "1'b0" *) (* LC_PROBE884_IS_TRIG = "1'b0" *) (* LC_PROBE884_MU_CNT = "1" *) 
(* LC_PROBE884_PID = "16'b0000001101110100" *) (* LC_PROBE884_TYPE = "1" *) (* LC_PROBE884_WIDTH = "1" *) 
(* LC_PROBE885_IS_DATA = "1'b0" *) (* LC_PROBE885_IS_TRIG = "1'b0" *) (* LC_PROBE885_MU_CNT = "1" *) 
(* LC_PROBE885_PID = "16'b0000001101110101" *) (* LC_PROBE885_TYPE = "1" *) (* LC_PROBE885_WIDTH = "1" *) 
(* LC_PROBE886_IS_DATA = "1'b0" *) (* LC_PROBE886_IS_TRIG = "1'b0" *) (* LC_PROBE886_MU_CNT = "1" *) 
(* LC_PROBE886_PID = "16'b0000001101110110" *) (* LC_PROBE886_TYPE = "1" *) (* LC_PROBE886_WIDTH = "1" *) 
(* LC_PROBE887_IS_DATA = "1'b0" *) (* LC_PROBE887_IS_TRIG = "1'b0" *) (* LC_PROBE887_MU_CNT = "1" *) 
(* LC_PROBE887_PID = "16'b0000001101110111" *) (* LC_PROBE887_TYPE = "1" *) (* LC_PROBE887_WIDTH = "1" *) 
(* LC_PROBE888_IS_DATA = "1'b0" *) (* LC_PROBE888_IS_TRIG = "1'b0" *) (* LC_PROBE888_MU_CNT = "1" *) 
(* LC_PROBE888_PID = "16'b0000001101111000" *) (* LC_PROBE888_TYPE = "1" *) (* LC_PROBE888_WIDTH = "1" *) 
(* LC_PROBE889_IS_DATA = "1'b0" *) (* LC_PROBE889_IS_TRIG = "1'b0" *) (* LC_PROBE889_MU_CNT = "1" *) 
(* LC_PROBE889_PID = "16'b0000001101111001" *) (* LC_PROBE889_TYPE = "1" *) (* LC_PROBE889_WIDTH = "1" *) 
(* LC_PROBE88_IS_DATA = "1'b0" *) (* LC_PROBE88_IS_TRIG = "1'b0" *) (* LC_PROBE88_MU_CNT = "1" *) 
(* LC_PROBE88_PID = "16'b0000000001011000" *) (* LC_PROBE88_TYPE = "1" *) (* LC_PROBE88_WIDTH = "1" *) 
(* LC_PROBE890_IS_DATA = "1'b0" *) (* LC_PROBE890_IS_TRIG = "1'b0" *) (* LC_PROBE890_MU_CNT = "1" *) 
(* LC_PROBE890_PID = "16'b0000001101111010" *) (* LC_PROBE890_TYPE = "1" *) (* LC_PROBE890_WIDTH = "1" *) 
(* LC_PROBE891_IS_DATA = "1'b0" *) (* LC_PROBE891_IS_TRIG = "1'b0" *) (* LC_PROBE891_MU_CNT = "1" *) 
(* LC_PROBE891_PID = "16'b0000001101111011" *) (* LC_PROBE891_TYPE = "1" *) (* LC_PROBE891_WIDTH = "1" *) 
(* LC_PROBE892_IS_DATA = "1'b0" *) (* LC_PROBE892_IS_TRIG = "1'b0" *) (* LC_PROBE892_MU_CNT = "1" *) 
(* LC_PROBE892_PID = "16'b0000001101111100" *) (* LC_PROBE892_TYPE = "1" *) (* LC_PROBE892_WIDTH = "1" *) 
(* LC_PROBE893_IS_DATA = "1'b0" *) (* LC_PROBE893_IS_TRIG = "1'b0" *) (* LC_PROBE893_MU_CNT = "1" *) 
(* LC_PROBE893_PID = "16'b0000001101111101" *) (* LC_PROBE893_TYPE = "1" *) (* LC_PROBE893_WIDTH = "1" *) 
(* LC_PROBE894_IS_DATA = "1'b0" *) (* LC_PROBE894_IS_TRIG = "1'b0" *) (* LC_PROBE894_MU_CNT = "1" *) 
(* LC_PROBE894_PID = "16'b0000001101111110" *) (* LC_PROBE894_TYPE = "1" *) (* LC_PROBE894_WIDTH = "1" *) 
(* LC_PROBE895_IS_DATA = "1'b0" *) (* LC_PROBE895_IS_TRIG = "1'b0" *) (* LC_PROBE895_MU_CNT = "1" *) 
(* LC_PROBE895_PID = "16'b0000001101111111" *) (* LC_PROBE895_TYPE = "1" *) (* LC_PROBE895_WIDTH = "1" *) 
(* LC_PROBE896_IS_DATA = "1'b0" *) (* LC_PROBE896_IS_TRIG = "1'b0" *) (* LC_PROBE896_MU_CNT = "1" *) 
(* LC_PROBE896_PID = "16'b0000001110000000" *) (* LC_PROBE896_TYPE = "1" *) (* LC_PROBE896_WIDTH = "1" *) 
(* LC_PROBE897_IS_DATA = "1'b0" *) (* LC_PROBE897_IS_TRIG = "1'b0" *) (* LC_PROBE897_MU_CNT = "1" *) 
(* LC_PROBE897_PID = "16'b0000001110000001" *) (* LC_PROBE897_TYPE = "1" *) (* LC_PROBE897_WIDTH = "1" *) 
(* LC_PROBE898_IS_DATA = "1'b0" *) (* LC_PROBE898_IS_TRIG = "1'b0" *) (* LC_PROBE898_MU_CNT = "1" *) 
(* LC_PROBE898_PID = "16'b0000001110000010" *) (* LC_PROBE898_TYPE = "1" *) (* LC_PROBE898_WIDTH = "1" *) 
(* LC_PROBE899_IS_DATA = "1'b0" *) (* LC_PROBE899_IS_TRIG = "1'b0" *) (* LC_PROBE899_MU_CNT = "1" *) 
(* LC_PROBE899_PID = "16'b0000001110000011" *) (* LC_PROBE899_TYPE = "1" *) (* LC_PROBE899_WIDTH = "1" *) 
(* LC_PROBE89_IS_DATA = "1'b0" *) (* LC_PROBE89_IS_TRIG = "1'b0" *) (* LC_PROBE89_MU_CNT = "1" *) 
(* LC_PROBE89_PID = "16'b0000000001011001" *) (* LC_PROBE89_TYPE = "1" *) (* LC_PROBE89_WIDTH = "1" *) 
(* LC_PROBE8_IS_DATA = "1'b0" *) (* LC_PROBE8_IS_TRIG = "1'b0" *) (* LC_PROBE8_MU_CNT = "1" *) 
(* LC_PROBE8_PID = "16'b0000000000001000" *) (* LC_PROBE8_TYPE = "1" *) (* LC_PROBE8_WIDTH = "1" *) 
(* LC_PROBE900_IS_DATA = "1'b0" *) (* LC_PROBE900_IS_TRIG = "1'b0" *) (* LC_PROBE900_MU_CNT = "1" *) 
(* LC_PROBE900_PID = "16'b0000001110000100" *) (* LC_PROBE900_TYPE = "1" *) (* LC_PROBE900_WIDTH = "1" *) 
(* LC_PROBE901_IS_DATA = "1'b0" *) (* LC_PROBE901_IS_TRIG = "1'b0" *) (* LC_PROBE901_MU_CNT = "1" *) 
(* LC_PROBE901_PID = "16'b0000001110000101" *) (* LC_PROBE901_TYPE = "1" *) (* LC_PROBE901_WIDTH = "1" *) 
(* LC_PROBE902_IS_DATA = "1'b0" *) (* LC_PROBE902_IS_TRIG = "1'b0" *) (* LC_PROBE902_MU_CNT = "1" *) 
(* LC_PROBE902_PID = "16'b0000001110000110" *) (* LC_PROBE902_TYPE = "1" *) (* LC_PROBE902_WIDTH = "1" *) 
(* LC_PROBE903_IS_DATA = "1'b0" *) (* LC_PROBE903_IS_TRIG = "1'b0" *) (* LC_PROBE903_MU_CNT = "1" *) 
(* LC_PROBE903_PID = "16'b0000001110000111" *) (* LC_PROBE903_TYPE = "1" *) (* LC_PROBE903_WIDTH = "1" *) 
(* LC_PROBE904_IS_DATA = "1'b0" *) (* LC_PROBE904_IS_TRIG = "1'b0" *) (* LC_PROBE904_MU_CNT = "1" *) 
(* LC_PROBE904_PID = "16'b0000001110001000" *) (* LC_PROBE904_TYPE = "1" *) (* LC_PROBE904_WIDTH = "1" *) 
(* LC_PROBE905_IS_DATA = "1'b0" *) (* LC_PROBE905_IS_TRIG = "1'b0" *) (* LC_PROBE905_MU_CNT = "1" *) 
(* LC_PROBE905_PID = "16'b0000001110001001" *) (* LC_PROBE905_TYPE = "1" *) (* LC_PROBE905_WIDTH = "1" *) 
(* LC_PROBE906_IS_DATA = "1'b0" *) (* LC_PROBE906_IS_TRIG = "1'b0" *) (* LC_PROBE906_MU_CNT = "1" *) 
(* LC_PROBE906_PID = "16'b0000001110001010" *) (* LC_PROBE906_TYPE = "1" *) (* LC_PROBE906_WIDTH = "1" *) 
(* LC_PROBE907_IS_DATA = "1'b0" *) (* LC_PROBE907_IS_TRIG = "1'b0" *) (* LC_PROBE907_MU_CNT = "1" *) 
(* LC_PROBE907_PID = "16'b0000001110001011" *) (* LC_PROBE907_TYPE = "1" *) (* LC_PROBE907_WIDTH = "1" *) 
(* LC_PROBE908_IS_DATA = "1'b0" *) (* LC_PROBE908_IS_TRIG = "1'b0" *) (* LC_PROBE908_MU_CNT = "1" *) 
(* LC_PROBE908_PID = "16'b0000001110001100" *) (* LC_PROBE908_TYPE = "1" *) (* LC_PROBE908_WIDTH = "1" *) 
(* LC_PROBE909_IS_DATA = "1'b0" *) (* LC_PROBE909_IS_TRIG = "1'b0" *) (* LC_PROBE909_MU_CNT = "1" *) 
(* LC_PROBE909_PID = "16'b0000001110001101" *) (* LC_PROBE909_TYPE = "1" *) (* LC_PROBE909_WIDTH = "1" *) 
(* LC_PROBE90_IS_DATA = "1'b0" *) (* LC_PROBE90_IS_TRIG = "1'b0" *) (* LC_PROBE90_MU_CNT = "1" *) 
(* LC_PROBE90_PID = "16'b0000000001011010" *) (* LC_PROBE90_TYPE = "1" *) (* LC_PROBE90_WIDTH = "1" *) 
(* LC_PROBE910_IS_DATA = "1'b0" *) (* LC_PROBE910_IS_TRIG = "1'b0" *) (* LC_PROBE910_MU_CNT = "1" *) 
(* LC_PROBE910_PID = "16'b0000001110001110" *) (* LC_PROBE910_TYPE = "1" *) (* LC_PROBE910_WIDTH = "1" *) 
(* LC_PROBE911_IS_DATA = "1'b0" *) (* LC_PROBE911_IS_TRIG = "1'b0" *) (* LC_PROBE911_MU_CNT = "1" *) 
(* LC_PROBE911_PID = "16'b0000001110001111" *) (* LC_PROBE911_TYPE = "1" *) (* LC_PROBE911_WIDTH = "1" *) 
(* LC_PROBE912_IS_DATA = "1'b0" *) (* LC_PROBE912_IS_TRIG = "1'b0" *) (* LC_PROBE912_MU_CNT = "1" *) 
(* LC_PROBE912_PID = "16'b0000001110010000" *) (* LC_PROBE912_TYPE = "1" *) (* LC_PROBE912_WIDTH = "1" *) 
(* LC_PROBE913_IS_DATA = "1'b0" *) (* LC_PROBE913_IS_TRIG = "1'b0" *) (* LC_PROBE913_MU_CNT = "1" *) 
(* LC_PROBE913_PID = "16'b0000001110010001" *) (* LC_PROBE913_TYPE = "1" *) (* LC_PROBE913_WIDTH = "1" *) 
(* LC_PROBE914_IS_DATA = "1'b0" *) (* LC_PROBE914_IS_TRIG = "1'b0" *) (* LC_PROBE914_MU_CNT = "1" *) 
(* LC_PROBE914_PID = "16'b0000001110010010" *) (* LC_PROBE914_TYPE = "1" *) (* LC_PROBE914_WIDTH = "1" *) 
(* LC_PROBE915_IS_DATA = "1'b0" *) (* LC_PROBE915_IS_TRIG = "1'b0" *) (* LC_PROBE915_MU_CNT = "1" *) 
(* LC_PROBE915_PID = "16'b0000001110010011" *) (* LC_PROBE915_TYPE = "1" *) (* LC_PROBE915_WIDTH = "1" *) 
(* LC_PROBE916_IS_DATA = "1'b0" *) (* LC_PROBE916_IS_TRIG = "1'b0" *) (* LC_PROBE916_MU_CNT = "1" *) 
(* LC_PROBE916_PID = "16'b0000001110010100" *) (* LC_PROBE916_TYPE = "1" *) (* LC_PROBE916_WIDTH = "1" *) 
(* LC_PROBE917_IS_DATA = "1'b0" *) (* LC_PROBE917_IS_TRIG = "1'b0" *) (* LC_PROBE917_MU_CNT = "1" *) 
(* LC_PROBE917_PID = "16'b0000001110010101" *) (* LC_PROBE917_TYPE = "1" *) (* LC_PROBE917_WIDTH = "1" *) 
(* LC_PROBE918_IS_DATA = "1'b0" *) (* LC_PROBE918_IS_TRIG = "1'b0" *) (* LC_PROBE918_MU_CNT = "1" *) 
(* LC_PROBE918_PID = "16'b0000001110010110" *) (* LC_PROBE918_TYPE = "1" *) (* LC_PROBE918_WIDTH = "1" *) 
(* LC_PROBE919_IS_DATA = "1'b0" *) (* LC_PROBE919_IS_TRIG = "1'b0" *) (* LC_PROBE919_MU_CNT = "1" *) 
(* LC_PROBE919_PID = "16'b0000001110010111" *) (* LC_PROBE919_TYPE = "1" *) (* LC_PROBE919_WIDTH = "1" *) 
(* LC_PROBE91_IS_DATA = "1'b0" *) (* LC_PROBE91_IS_TRIG = "1'b0" *) (* LC_PROBE91_MU_CNT = "1" *) 
(* LC_PROBE91_PID = "16'b0000000001011011" *) (* LC_PROBE91_TYPE = "1" *) (* LC_PROBE91_WIDTH = "1" *) 
(* LC_PROBE920_IS_DATA = "1'b0" *) (* LC_PROBE920_IS_TRIG = "1'b0" *) (* LC_PROBE920_MU_CNT = "1" *) 
(* LC_PROBE920_PID = "16'b0000001110011000" *) (* LC_PROBE920_TYPE = "1" *) (* LC_PROBE920_WIDTH = "1" *) 
(* LC_PROBE921_IS_DATA = "1'b0" *) (* LC_PROBE921_IS_TRIG = "1'b0" *) (* LC_PROBE921_MU_CNT = "1" *) 
(* LC_PROBE921_PID = "16'b0000001110011001" *) (* LC_PROBE921_TYPE = "1" *) (* LC_PROBE921_WIDTH = "1" *) 
(* LC_PROBE922_IS_DATA = "1'b0" *) (* LC_PROBE922_IS_TRIG = "1'b0" *) (* LC_PROBE922_MU_CNT = "1" *) 
(* LC_PROBE922_PID = "16'b0000001110011010" *) (* LC_PROBE922_TYPE = "1" *) (* LC_PROBE922_WIDTH = "1" *) 
(* LC_PROBE923_IS_DATA = "1'b0" *) (* LC_PROBE923_IS_TRIG = "1'b0" *) (* LC_PROBE923_MU_CNT = "1" *) 
(* LC_PROBE923_PID = "16'b0000001110011011" *) (* LC_PROBE923_TYPE = "1" *) (* LC_PROBE923_WIDTH = "1" *) 
(* LC_PROBE924_IS_DATA = "1'b0" *) (* LC_PROBE924_IS_TRIG = "1'b0" *) (* LC_PROBE924_MU_CNT = "1" *) 
(* LC_PROBE924_PID = "16'b0000001110011100" *) (* LC_PROBE924_TYPE = "1" *) (* LC_PROBE924_WIDTH = "1" *) 
(* LC_PROBE925_IS_DATA = "1'b0" *) (* LC_PROBE925_IS_TRIG = "1'b0" *) (* LC_PROBE925_MU_CNT = "1" *) 
(* LC_PROBE925_PID = "16'b0000001110011101" *) (* LC_PROBE925_TYPE = "1" *) (* LC_PROBE925_WIDTH = "1" *) 
(* LC_PROBE926_IS_DATA = "1'b0" *) (* LC_PROBE926_IS_TRIG = "1'b0" *) (* LC_PROBE926_MU_CNT = "1" *) 
(* LC_PROBE926_PID = "16'b0000001110011110" *) (* LC_PROBE926_TYPE = "1" *) (* LC_PROBE926_WIDTH = "1" *) 
(* LC_PROBE927_IS_DATA = "1'b0" *) (* LC_PROBE927_IS_TRIG = "1'b0" *) (* LC_PROBE927_MU_CNT = "1" *) 
(* LC_PROBE927_PID = "16'b0000001110011111" *) (* LC_PROBE927_TYPE = "1" *) (* LC_PROBE927_WIDTH = "1" *) 
(* LC_PROBE928_IS_DATA = "1'b0" *) (* LC_PROBE928_IS_TRIG = "1'b0" *) (* LC_PROBE928_MU_CNT = "1" *) 
(* LC_PROBE928_PID = "16'b0000001110100000" *) (* LC_PROBE928_TYPE = "1" *) (* LC_PROBE928_WIDTH = "1" *) 
(* LC_PROBE929_IS_DATA = "1'b0" *) (* LC_PROBE929_IS_TRIG = "1'b0" *) (* LC_PROBE929_MU_CNT = "1" *) 
(* LC_PROBE929_PID = "16'b0000001110100001" *) (* LC_PROBE929_TYPE = "1" *) (* LC_PROBE929_WIDTH = "1" *) 
(* LC_PROBE92_IS_DATA = "1'b0" *) (* LC_PROBE92_IS_TRIG = "1'b0" *) (* LC_PROBE92_MU_CNT = "1" *) 
(* LC_PROBE92_PID = "16'b0000000001011100" *) (* LC_PROBE92_TYPE = "1" *) (* LC_PROBE92_WIDTH = "1" *) 
(* LC_PROBE930_IS_DATA = "1'b0" *) (* LC_PROBE930_IS_TRIG = "1'b0" *) (* LC_PROBE930_MU_CNT = "1" *) 
(* LC_PROBE930_PID = "16'b0000001110100010" *) (* LC_PROBE930_TYPE = "1" *) (* LC_PROBE930_WIDTH = "1" *) 
(* LC_PROBE931_IS_DATA = "1'b0" *) (* LC_PROBE931_IS_TRIG = "1'b0" *) (* LC_PROBE931_MU_CNT = "1" *) 
(* LC_PROBE931_PID = "16'b0000001110100011" *) (* LC_PROBE931_TYPE = "1" *) (* LC_PROBE931_WIDTH = "1" *) 
(* LC_PROBE932_IS_DATA = "1'b0" *) (* LC_PROBE932_IS_TRIG = "1'b0" *) (* LC_PROBE932_MU_CNT = "1" *) 
(* LC_PROBE932_PID = "16'b0000001110100100" *) (* LC_PROBE932_TYPE = "1" *) (* LC_PROBE932_WIDTH = "1" *) 
(* LC_PROBE933_IS_DATA = "1'b0" *) (* LC_PROBE933_IS_TRIG = "1'b0" *) (* LC_PROBE933_MU_CNT = "1" *) 
(* LC_PROBE933_PID = "16'b0000001110100101" *) (* LC_PROBE933_TYPE = "1" *) (* LC_PROBE933_WIDTH = "1" *) 
(* LC_PROBE934_IS_DATA = "1'b0" *) (* LC_PROBE934_IS_TRIG = "1'b0" *) (* LC_PROBE934_MU_CNT = "1" *) 
(* LC_PROBE934_PID = "16'b0000001110100110" *) (* LC_PROBE934_TYPE = "1" *) (* LC_PROBE934_WIDTH = "1" *) 
(* LC_PROBE935_IS_DATA = "1'b0" *) (* LC_PROBE935_IS_TRIG = "1'b0" *) (* LC_PROBE935_MU_CNT = "1" *) 
(* LC_PROBE935_PID = "16'b0000001110100111" *) (* LC_PROBE935_TYPE = "1" *) (* LC_PROBE935_WIDTH = "1" *) 
(* LC_PROBE936_IS_DATA = "1'b0" *) (* LC_PROBE936_IS_TRIG = "1'b0" *) (* LC_PROBE936_MU_CNT = "1" *) 
(* LC_PROBE936_PID = "16'b0000001110101000" *) (* LC_PROBE936_TYPE = "1" *) (* LC_PROBE936_WIDTH = "1" *) 
(* LC_PROBE937_IS_DATA = "1'b0" *) (* LC_PROBE937_IS_TRIG = "1'b0" *) (* LC_PROBE937_MU_CNT = "1" *) 
(* LC_PROBE937_PID = "16'b0000001110101001" *) (* LC_PROBE937_TYPE = "1" *) (* LC_PROBE937_WIDTH = "1" *) 
(* LC_PROBE938_IS_DATA = "1'b0" *) (* LC_PROBE938_IS_TRIG = "1'b0" *) (* LC_PROBE938_MU_CNT = "1" *) 
(* LC_PROBE938_PID = "16'b0000001110101010" *) (* LC_PROBE938_TYPE = "1" *) (* LC_PROBE938_WIDTH = "1" *) 
(* LC_PROBE939_IS_DATA = "1'b0" *) (* LC_PROBE939_IS_TRIG = "1'b0" *) (* LC_PROBE939_MU_CNT = "1" *) 
(* LC_PROBE939_PID = "16'b0000001110101011" *) (* LC_PROBE939_TYPE = "1" *) (* LC_PROBE939_WIDTH = "1" *) 
(* LC_PROBE93_IS_DATA = "1'b0" *) (* LC_PROBE93_IS_TRIG = "1'b0" *) (* LC_PROBE93_MU_CNT = "1" *) 
(* LC_PROBE93_PID = "16'b0000000001011101" *) (* LC_PROBE93_TYPE = "1" *) (* LC_PROBE93_WIDTH = "1" *) 
(* LC_PROBE940_IS_DATA = "1'b0" *) (* LC_PROBE940_IS_TRIG = "1'b0" *) (* LC_PROBE940_MU_CNT = "1" *) 
(* LC_PROBE940_PID = "16'b0000001110101100" *) (* LC_PROBE940_TYPE = "1" *) (* LC_PROBE940_WIDTH = "1" *) 
(* LC_PROBE941_IS_DATA = "1'b0" *) (* LC_PROBE941_IS_TRIG = "1'b0" *) (* LC_PROBE941_MU_CNT = "1" *) 
(* LC_PROBE941_PID = "16'b0000001110101101" *) (* LC_PROBE941_TYPE = "1" *) (* LC_PROBE941_WIDTH = "1" *) 
(* LC_PROBE942_IS_DATA = "1'b0" *) (* LC_PROBE942_IS_TRIG = "1'b0" *) (* LC_PROBE942_MU_CNT = "1" *) 
(* LC_PROBE942_PID = "16'b0000001110101110" *) (* LC_PROBE942_TYPE = "1" *) (* LC_PROBE942_WIDTH = "1" *) 
(* LC_PROBE943_IS_DATA = "1'b0" *) (* LC_PROBE943_IS_TRIG = "1'b0" *) (* LC_PROBE943_MU_CNT = "1" *) 
(* LC_PROBE943_PID = "16'b0000001110101111" *) (* LC_PROBE943_TYPE = "1" *) (* LC_PROBE943_WIDTH = "1" *) 
(* LC_PROBE944_IS_DATA = "1'b0" *) (* LC_PROBE944_IS_TRIG = "1'b0" *) (* LC_PROBE944_MU_CNT = "1" *) 
(* LC_PROBE944_PID = "16'b0000001110110000" *) (* LC_PROBE944_TYPE = "1" *) (* LC_PROBE944_WIDTH = "1" *) 
(* LC_PROBE945_IS_DATA = "1'b0" *) (* LC_PROBE945_IS_TRIG = "1'b0" *) (* LC_PROBE945_MU_CNT = "1" *) 
(* LC_PROBE945_PID = "16'b0000001110110001" *) (* LC_PROBE945_TYPE = "1" *) (* LC_PROBE945_WIDTH = "1" *) 
(* LC_PROBE946_IS_DATA = "1'b0" *) (* LC_PROBE946_IS_TRIG = "1'b0" *) (* LC_PROBE946_MU_CNT = "1" *) 
(* LC_PROBE946_PID = "16'b0000001110110010" *) (* LC_PROBE946_TYPE = "1" *) (* LC_PROBE946_WIDTH = "1" *) 
(* LC_PROBE947_IS_DATA = "1'b0" *) (* LC_PROBE947_IS_TRIG = "1'b0" *) (* LC_PROBE947_MU_CNT = "1" *) 
(* LC_PROBE947_PID = "16'b0000001110110011" *) (* LC_PROBE947_TYPE = "1" *) (* LC_PROBE947_WIDTH = "1" *) 
(* LC_PROBE948_IS_DATA = "1'b0" *) (* LC_PROBE948_IS_TRIG = "1'b0" *) (* LC_PROBE948_MU_CNT = "1" *) 
(* LC_PROBE948_PID = "16'b0000001110110100" *) (* LC_PROBE948_TYPE = "1" *) (* LC_PROBE948_WIDTH = "1" *) 
(* LC_PROBE949_IS_DATA = "1'b0" *) (* LC_PROBE949_IS_TRIG = "1'b0" *) (* LC_PROBE949_MU_CNT = "1" *) 
(* LC_PROBE949_PID = "16'b0000001110110101" *) (* LC_PROBE949_TYPE = "1" *) (* LC_PROBE949_WIDTH = "1" *) 
(* LC_PROBE94_IS_DATA = "1'b0" *) (* LC_PROBE94_IS_TRIG = "1'b0" *) (* LC_PROBE94_MU_CNT = "1" *) 
(* LC_PROBE94_PID = "16'b0000000001011110" *) (* LC_PROBE94_TYPE = "1" *) (* LC_PROBE94_WIDTH = "1" *) 
(* LC_PROBE950_IS_DATA = "1'b0" *) (* LC_PROBE950_IS_TRIG = "1'b0" *) (* LC_PROBE950_MU_CNT = "1" *) 
(* LC_PROBE950_PID = "16'b0000001110110110" *) (* LC_PROBE950_TYPE = "1" *) (* LC_PROBE950_WIDTH = "1" *) 
(* LC_PROBE951_IS_DATA = "1'b0" *) (* LC_PROBE951_IS_TRIG = "1'b0" *) (* LC_PROBE951_MU_CNT = "1" *) 
(* LC_PROBE951_PID = "16'b0000001110110111" *) (* LC_PROBE951_TYPE = "1" *) (* LC_PROBE951_WIDTH = "1" *) 
(* LC_PROBE952_IS_DATA = "1'b0" *) (* LC_PROBE952_IS_TRIG = "1'b0" *) (* LC_PROBE952_MU_CNT = "1" *) 
(* LC_PROBE952_PID = "16'b0000001110111000" *) (* LC_PROBE952_TYPE = "1" *) (* LC_PROBE952_WIDTH = "1" *) 
(* LC_PROBE953_IS_DATA = "1'b0" *) (* LC_PROBE953_IS_TRIG = "1'b0" *) (* LC_PROBE953_MU_CNT = "1" *) 
(* LC_PROBE953_PID = "16'b0000001110111001" *) (* LC_PROBE953_TYPE = "1" *) (* LC_PROBE953_WIDTH = "1" *) 
(* LC_PROBE954_IS_DATA = "1'b0" *) (* LC_PROBE954_IS_TRIG = "1'b0" *) (* LC_PROBE954_MU_CNT = "1" *) 
(* LC_PROBE954_PID = "16'b0000001110111010" *) (* LC_PROBE954_TYPE = "1" *) (* LC_PROBE954_WIDTH = "1" *) 
(* LC_PROBE955_IS_DATA = "1'b0" *) (* LC_PROBE955_IS_TRIG = "1'b0" *) (* LC_PROBE955_MU_CNT = "1" *) 
(* LC_PROBE955_PID = "16'b0000001110111011" *) (* LC_PROBE955_TYPE = "1" *) (* LC_PROBE955_WIDTH = "1" *) 
(* LC_PROBE956_IS_DATA = "1'b0" *) (* LC_PROBE956_IS_TRIG = "1'b0" *) (* LC_PROBE956_MU_CNT = "1" *) 
(* LC_PROBE956_PID = "16'b0000001110111100" *) (* LC_PROBE956_TYPE = "1" *) (* LC_PROBE956_WIDTH = "1" *) 
(* LC_PROBE957_IS_DATA = "1'b0" *) (* LC_PROBE957_IS_TRIG = "1'b0" *) (* LC_PROBE957_MU_CNT = "1" *) 
(* LC_PROBE957_PID = "16'b0000001110111101" *) (* LC_PROBE957_TYPE = "1" *) (* LC_PROBE957_WIDTH = "1" *) 
(* LC_PROBE958_IS_DATA = "1'b0" *) (* LC_PROBE958_IS_TRIG = "1'b0" *) (* LC_PROBE958_MU_CNT = "1" *) 
(* LC_PROBE958_PID = "16'b0000001110111110" *) (* LC_PROBE958_TYPE = "1" *) (* LC_PROBE958_WIDTH = "1" *) 
(* LC_PROBE959_IS_DATA = "1'b0" *) (* LC_PROBE959_IS_TRIG = "1'b0" *) (* LC_PROBE959_MU_CNT = "1" *) 
(* LC_PROBE959_PID = "16'b0000001110111111" *) (* LC_PROBE959_TYPE = "1" *) (* LC_PROBE959_WIDTH = "1" *) 
(* LC_PROBE95_IS_DATA = "1'b0" *) (* LC_PROBE95_IS_TRIG = "1'b0" *) (* LC_PROBE95_MU_CNT = "1" *) 
(* LC_PROBE95_PID = "16'b0000000001011111" *) (* LC_PROBE95_TYPE = "1" *) (* LC_PROBE95_WIDTH = "1" *) 
(* LC_PROBE960_IS_DATA = "1'b0" *) (* LC_PROBE960_IS_TRIG = "1'b0" *) (* LC_PROBE960_MU_CNT = "1" *) 
(* LC_PROBE960_PID = "16'b0000001111000000" *) (* LC_PROBE960_TYPE = "1" *) (* LC_PROBE960_WIDTH = "1" *) 
(* LC_PROBE961_IS_DATA = "1'b0" *) (* LC_PROBE961_IS_TRIG = "1'b0" *) (* LC_PROBE961_MU_CNT = "1" *) 
(* LC_PROBE961_PID = "16'b0000001111000001" *) (* LC_PROBE961_TYPE = "1" *) (* LC_PROBE961_WIDTH = "1" *) 
(* LC_PROBE962_IS_DATA = "1'b0" *) (* LC_PROBE962_IS_TRIG = "1'b0" *) (* LC_PROBE962_MU_CNT = "1" *) 
(* LC_PROBE962_PID = "16'b0000001111000010" *) (* LC_PROBE962_TYPE = "1" *) (* LC_PROBE962_WIDTH = "1" *) 
(* LC_PROBE963_IS_DATA = "1'b0" *) (* LC_PROBE963_IS_TRIG = "1'b0" *) (* LC_PROBE963_MU_CNT = "1" *) 
(* LC_PROBE963_PID = "16'b0000001111000011" *) (* LC_PROBE963_TYPE = "1" *) (* LC_PROBE963_WIDTH = "1" *) 
(* LC_PROBE964_IS_DATA = "1'b0" *) (* LC_PROBE964_IS_TRIG = "1'b0" *) (* LC_PROBE964_MU_CNT = "1" *) 
(* LC_PROBE964_PID = "16'b0000001111000100" *) (* LC_PROBE964_TYPE = "1" *) (* LC_PROBE964_WIDTH = "1" *) 
(* LC_PROBE965_IS_DATA = "1'b0" *) (* LC_PROBE965_IS_TRIG = "1'b0" *) (* LC_PROBE965_MU_CNT = "1" *) 
(* LC_PROBE965_PID = "16'b0000001111000101" *) (* LC_PROBE965_TYPE = "1" *) (* LC_PROBE965_WIDTH = "1" *) 
(* LC_PROBE966_IS_DATA = "1'b0" *) (* LC_PROBE966_IS_TRIG = "1'b0" *) (* LC_PROBE966_MU_CNT = "1" *) 
(* LC_PROBE966_PID = "16'b0000001111000110" *) (* LC_PROBE966_TYPE = "1" *) (* LC_PROBE966_WIDTH = "1" *) 
(* LC_PROBE967_IS_DATA = "1'b0" *) (* LC_PROBE967_IS_TRIG = "1'b0" *) (* LC_PROBE967_MU_CNT = "1" *) 
(* LC_PROBE967_PID = "16'b0000001111000111" *) (* LC_PROBE967_TYPE = "1" *) (* LC_PROBE967_WIDTH = "1" *) 
(* LC_PROBE968_IS_DATA = "1'b0" *) (* LC_PROBE968_IS_TRIG = "1'b0" *) (* LC_PROBE968_MU_CNT = "1" *) 
(* LC_PROBE968_PID = "16'b0000001111001000" *) (* LC_PROBE968_TYPE = "1" *) (* LC_PROBE968_WIDTH = "1" *) 
(* LC_PROBE969_IS_DATA = "1'b0" *) (* LC_PROBE969_IS_TRIG = "1'b0" *) (* LC_PROBE969_MU_CNT = "1" *) 
(* LC_PROBE969_PID = "16'b0000001111001001" *) (* LC_PROBE969_TYPE = "1" *) (* LC_PROBE969_WIDTH = "1" *) 
(* LC_PROBE96_IS_DATA = "1'b0" *) (* LC_PROBE96_IS_TRIG = "1'b0" *) (* LC_PROBE96_MU_CNT = "1" *) 
(* LC_PROBE96_PID = "16'b0000000001100000" *) (* LC_PROBE96_TYPE = "1" *) (* LC_PROBE96_WIDTH = "1" *) 
(* LC_PROBE970_IS_DATA = "1'b0" *) (* LC_PROBE970_IS_TRIG = "1'b0" *) (* LC_PROBE970_MU_CNT = "1" *) 
(* LC_PROBE970_PID = "16'b0000001111001010" *) (* LC_PROBE970_TYPE = "1" *) (* LC_PROBE970_WIDTH = "1" *) 
(* LC_PROBE971_IS_DATA = "1'b0" *) (* LC_PROBE971_IS_TRIG = "1'b0" *) (* LC_PROBE971_MU_CNT = "1" *) 
(* LC_PROBE971_PID = "16'b0000001111001011" *) (* LC_PROBE971_TYPE = "1" *) (* LC_PROBE971_WIDTH = "1" *) 
(* LC_PROBE972_IS_DATA = "1'b0" *) (* LC_PROBE972_IS_TRIG = "1'b0" *) (* LC_PROBE972_MU_CNT = "1" *) 
(* LC_PROBE972_PID = "16'b0000001111001100" *) (* LC_PROBE972_TYPE = "1" *) (* LC_PROBE972_WIDTH = "1" *) 
(* LC_PROBE973_IS_DATA = "1'b0" *) (* LC_PROBE973_IS_TRIG = "1'b0" *) (* LC_PROBE973_MU_CNT = "1" *) 
(* LC_PROBE973_PID = "16'b0000001111001101" *) (* LC_PROBE973_TYPE = "1" *) (* LC_PROBE973_WIDTH = "1" *) 
(* LC_PROBE974_IS_DATA = "1'b0" *) (* LC_PROBE974_IS_TRIG = "1'b0" *) (* LC_PROBE974_MU_CNT = "1" *) 
(* LC_PROBE974_PID = "16'b0000001111001110" *) (* LC_PROBE974_TYPE = "1" *) (* LC_PROBE974_WIDTH = "1" *) 
(* LC_PROBE975_IS_DATA = "1'b0" *) (* LC_PROBE975_IS_TRIG = "1'b0" *) (* LC_PROBE975_MU_CNT = "1" *) 
(* LC_PROBE975_PID = "16'b0000001111001111" *) (* LC_PROBE975_TYPE = "1" *) (* LC_PROBE975_WIDTH = "1" *) 
(* LC_PROBE976_IS_DATA = "1'b0" *) (* LC_PROBE976_IS_TRIG = "1'b0" *) (* LC_PROBE976_MU_CNT = "1" *) 
(* LC_PROBE976_PID = "16'b0000001111010000" *) (* LC_PROBE976_TYPE = "1" *) (* LC_PROBE976_WIDTH = "1" *) 
(* LC_PROBE977_IS_DATA = "1'b0" *) (* LC_PROBE977_IS_TRIG = "1'b0" *) (* LC_PROBE977_MU_CNT = "1" *) 
(* LC_PROBE977_PID = "16'b0000001111010001" *) (* LC_PROBE977_TYPE = "1" *) (* LC_PROBE977_WIDTH = "1" *) 
(* LC_PROBE978_IS_DATA = "1'b0" *) (* LC_PROBE978_IS_TRIG = "1'b0" *) (* LC_PROBE978_MU_CNT = "1" *) 
(* LC_PROBE978_PID = "16'b0000001111010010" *) (* LC_PROBE978_TYPE = "1" *) (* LC_PROBE978_WIDTH = "1" *) 
(* LC_PROBE979_IS_DATA = "1'b0" *) (* LC_PROBE979_IS_TRIG = "1'b0" *) (* LC_PROBE979_MU_CNT = "1" *) 
(* LC_PROBE979_PID = "16'b0000001111010011" *) (* LC_PROBE979_TYPE = "1" *) (* LC_PROBE979_WIDTH = "1" *) 
(* LC_PROBE97_IS_DATA = "1'b0" *) (* LC_PROBE97_IS_TRIG = "1'b0" *) (* LC_PROBE97_MU_CNT = "1" *) 
(* LC_PROBE97_PID = "16'b0000000001100001" *) (* LC_PROBE97_TYPE = "1" *) (* LC_PROBE97_WIDTH = "1" *) 
(* LC_PROBE980_IS_DATA = "1'b0" *) (* LC_PROBE980_IS_TRIG = "1'b0" *) (* LC_PROBE980_MU_CNT = "1" *) 
(* LC_PROBE980_PID = "16'b0000001111010100" *) (* LC_PROBE980_TYPE = "1" *) (* LC_PROBE980_WIDTH = "1" *) 
(* LC_PROBE981_IS_DATA = "1'b0" *) (* LC_PROBE981_IS_TRIG = "1'b0" *) (* LC_PROBE981_MU_CNT = "1" *) 
(* LC_PROBE981_PID = "16'b0000001111010101" *) (* LC_PROBE981_TYPE = "1" *) (* LC_PROBE981_WIDTH = "1" *) 
(* LC_PROBE982_IS_DATA = "1'b0" *) (* LC_PROBE982_IS_TRIG = "1'b0" *) (* LC_PROBE982_MU_CNT = "1" *) 
(* LC_PROBE982_PID = "16'b0000001111010110" *) (* LC_PROBE982_TYPE = "1" *) (* LC_PROBE982_WIDTH = "1" *) 
(* LC_PROBE983_IS_DATA = "1'b0" *) (* LC_PROBE983_IS_TRIG = "1'b0" *) (* LC_PROBE983_MU_CNT = "1" *) 
(* LC_PROBE983_PID = "16'b0000001111010111" *) (* LC_PROBE983_TYPE = "1" *) (* LC_PROBE983_WIDTH = "1" *) 
(* LC_PROBE984_IS_DATA = "1'b0" *) (* LC_PROBE984_IS_TRIG = "1'b0" *) (* LC_PROBE984_MU_CNT = "1" *) 
(* LC_PROBE984_PID = "16'b0000001111011000" *) (* LC_PROBE984_TYPE = "1" *) (* LC_PROBE984_WIDTH = "1" *) 
(* LC_PROBE985_IS_DATA = "1'b0" *) (* LC_PROBE985_IS_TRIG = "1'b0" *) (* LC_PROBE985_MU_CNT = "1" *) 
(* LC_PROBE985_PID = "16'b0000001111011001" *) (* LC_PROBE985_TYPE = "1" *) (* LC_PROBE985_WIDTH = "1" *) 
(* LC_PROBE986_IS_DATA = "1'b0" *) (* LC_PROBE986_IS_TRIG = "1'b0" *) (* LC_PROBE986_MU_CNT = "1" *) 
(* LC_PROBE986_PID = "16'b0000001111011010" *) (* LC_PROBE986_TYPE = "1" *) (* LC_PROBE986_WIDTH = "1" *) 
(* LC_PROBE987_IS_DATA = "1'b0" *) (* LC_PROBE987_IS_TRIG = "1'b0" *) (* LC_PROBE987_MU_CNT = "1" *) 
(* LC_PROBE987_PID = "16'b0000001111011011" *) (* LC_PROBE987_TYPE = "1" *) (* LC_PROBE987_WIDTH = "1" *) 
(* LC_PROBE988_IS_DATA = "1'b0" *) (* LC_PROBE988_IS_TRIG = "1'b0" *) (* LC_PROBE988_MU_CNT = "1" *) 
(* LC_PROBE988_PID = "16'b0000001111011100" *) (* LC_PROBE988_TYPE = "1" *) (* LC_PROBE988_WIDTH = "1" *) 
(* LC_PROBE989_IS_DATA = "1'b0" *) (* LC_PROBE989_IS_TRIG = "1'b0" *) (* LC_PROBE989_MU_CNT = "1" *) 
(* LC_PROBE989_PID = "16'b0000001111011101" *) (* LC_PROBE989_TYPE = "1" *) (* LC_PROBE989_WIDTH = "1" *) 
(* LC_PROBE98_IS_DATA = "1'b0" *) (* LC_PROBE98_IS_TRIG = "1'b0" *) (* LC_PROBE98_MU_CNT = "1" *) 
(* LC_PROBE98_PID = "16'b0000000001100010" *) (* LC_PROBE98_TYPE = "1" *) (* LC_PROBE98_WIDTH = "1" *) 
(* LC_PROBE990_IS_DATA = "1'b0" *) (* LC_PROBE990_IS_TRIG = "1'b0" *) (* LC_PROBE990_MU_CNT = "1" *) 
(* LC_PROBE990_PID = "16'b0000001111011110" *) (* LC_PROBE990_TYPE = "1" *) (* LC_PROBE990_WIDTH = "1" *) 
(* LC_PROBE991_IS_DATA = "1'b0" *) (* LC_PROBE991_IS_TRIG = "1'b0" *) (* LC_PROBE991_MU_CNT = "1" *) 
(* LC_PROBE991_PID = "16'b0000001111011111" *) (* LC_PROBE991_TYPE = "1" *) (* LC_PROBE991_WIDTH = "1" *) 
(* LC_PROBE992_IS_DATA = "1'b0" *) (* LC_PROBE992_IS_TRIG = "1'b0" *) (* LC_PROBE992_MU_CNT = "1" *) 
(* LC_PROBE992_PID = "16'b0000001111100000" *) (* LC_PROBE992_TYPE = "1" *) (* LC_PROBE992_WIDTH = "1" *) 
(* LC_PROBE993_IS_DATA = "1'b0" *) (* LC_PROBE993_IS_TRIG = "1'b0" *) (* LC_PROBE993_MU_CNT = "1" *) 
(* LC_PROBE993_PID = "16'b0000001111100001" *) (* LC_PROBE993_TYPE = "1" *) (* LC_PROBE993_WIDTH = "1" *) 
(* LC_PROBE994_IS_DATA = "1'b0" *) (* LC_PROBE994_IS_TRIG = "1'b0" *) (* LC_PROBE994_MU_CNT = "1" *) 
(* LC_PROBE994_PID = "16'b0000001111100010" *) (* LC_PROBE994_TYPE = "1" *) (* LC_PROBE994_WIDTH = "1" *) 
(* LC_PROBE995_IS_DATA = "1'b0" *) (* LC_PROBE995_IS_TRIG = "1'b0" *) (* LC_PROBE995_MU_CNT = "1" *) 
(* LC_PROBE995_PID = "16'b0000001111100011" *) (* LC_PROBE995_TYPE = "1" *) (* LC_PROBE995_WIDTH = "1" *) 
(* LC_PROBE996_IS_DATA = "1'b0" *) (* LC_PROBE996_IS_TRIG = "1'b0" *) (* LC_PROBE996_MU_CNT = "1" *) 
(* LC_PROBE996_PID = "16'b0000001111100100" *) (* LC_PROBE996_TYPE = "1" *) (* LC_PROBE996_WIDTH = "1" *) 
(* LC_PROBE997_IS_DATA = "1'b0" *) (* LC_PROBE997_IS_TRIG = "1'b0" *) (* LC_PROBE997_MU_CNT = "1" *) 
(* LC_PROBE997_PID = "16'b0000001111100101" *) (* LC_PROBE997_TYPE = "1" *) (* LC_PROBE997_WIDTH = "1" *) 
(* LC_PROBE998_IS_DATA = "1'b0" *) (* LC_PROBE998_IS_TRIG = "1'b0" *) (* LC_PROBE998_MU_CNT = "1" *) 
(* LC_PROBE998_PID = "16'b0000001111100110" *) (* LC_PROBE998_TYPE = "1" *) (* LC_PROBE998_WIDTH = "1" *) 
(* LC_PROBE999_IS_DATA = "1'b0" *) (* LC_PROBE999_IS_TRIG = "1'b0" *) (* LC_PROBE999_MU_CNT = "1" *) 
(* LC_PROBE999_PID = "16'b0000001111100111" *) (* LC_PROBE999_TYPE = "1" *) (* LC_PROBE999_WIDTH = "1" *) 
(* LC_PROBE99_IS_DATA = "1'b0" *) (* LC_PROBE99_IS_TRIG = "1'b0" *) (* LC_PROBE99_MU_CNT = "1" *) 
(* LC_PROBE99_PID = "16'b0000000001100011" *) (* LC_PROBE99_TYPE = "1" *) (* LC_PROBE99_WIDTH = "1" *) 
(* LC_PROBE9_IS_DATA = "1'b0" *) (* LC_PROBE9_IS_TRIG = "1'b0" *) (* LC_PROBE9_MU_CNT = "1" *) 
(* LC_PROBE9_PID = "16'b0000000000001001" *) (* LC_PROBE9_TYPE = "1" *) (* LC_PROBE9_WIDTH = "1" *) 
(* LC_PROBES_WIDTH = "65" *) (* LC_PROBE_IS_DATA_STRING = "1024'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111" *) (* LC_PROBE_IS_TRIG_STRING = "4096' " *) 
(* LC_PROBE_WIDTH_STRING = "16384' " *) (* LC_TIME_TAG_MU_CNT = "2" *) (* LC_TIME_TAG_TYPE = "0" *) 
(* LC_TIME_TAG_WIDTH = "1" *) (* LC_TRIG_WIDTH = "65" *) (* dont_touch = "true" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila
   (clk,
    clk_nobuf,
    clkdiv_out,
    sl_iport0,
    sl_oport0,
    trig_in,
    trig_in_ack,
    trig_out,
    trig_out_ack,
    probe0,
    probe1,
    probe2,
    probe3,
    probe4,
    probe5,
    probe6,
    probe7,
    probe8,
    probe9,
    probe10,
    probe11,
    probe12,
    probe13,
    probe14,
    probe15,
    probe16,
    probe17,
    probe18,
    probe19,
    probe20,
    probe21,
    probe22,
    probe23,
    probe24,
    probe25,
    probe26,
    probe27,
    probe28,
    probe29,
    probe30,
    probe31,
    probe32,
    probe33,
    probe34,
    probe35,
    probe36,
    probe37,
    probe38,
    probe39,
    probe40,
    probe41,
    probe42,
    probe43,
    probe44,
    probe45,
    probe46,
    probe47,
    probe48,
    probe49,
    probe50,
    probe51,
    probe52,
    probe53,
    probe54,
    probe55,
    probe56,
    probe57,
    probe58,
    probe59,
    probe60,
    probe61,
    probe62,
    probe63,
    probe64,
    probe65,
    probe66,
    probe67,
    probe68,
    probe69,
    probe70,
    probe71,
    probe72,
    probe73,
    probe74,
    probe75,
    probe76,
    probe77,
    probe78,
    probe79,
    probe80,
    probe81,
    probe82,
    probe83,
    probe84,
    probe85,
    probe86,
    probe87,
    probe88,
    probe89,
    probe90,
    probe91,
    probe92,
    probe93,
    probe94,
    probe95,
    probe96,
    probe97,
    probe98,
    probe99,
    probe100,
    probe101,
    probe102,
    probe103,
    probe104,
    probe105,
    probe106,
    probe107,
    probe108,
    probe109,
    probe110,
    probe111,
    probe112,
    probe113,
    probe114,
    probe115,
    probe116,
    probe117,
    probe118,
    probe119,
    probe120,
    probe121,
    probe122,
    probe123,
    probe124,
    probe125,
    probe126,
    probe127,
    probe128,
    probe129,
    probe130,
    probe131,
    probe132,
    probe133,
    probe134,
    probe135,
    probe136,
    probe137,
    probe138,
    probe139,
    probe140,
    probe141,
    probe142,
    probe143,
    probe144,
    probe145,
    probe146,
    probe147,
    probe148,
    probe149,
    probe150,
    probe151,
    probe152,
    probe153,
    probe154,
    probe155,
    probe156,
    probe157,
    probe158,
    probe159,
    probe160,
    probe161,
    probe162,
    probe163,
    probe164,
    probe165,
    probe166,
    probe167,
    probe168,
    probe169,
    probe170,
    probe171,
    probe172,
    probe173,
    probe174,
    probe175,
    probe176,
    probe177,
    probe178,
    probe179,
    probe180,
    probe181,
    probe182,
    probe183,
    probe184,
    probe185,
    probe186,
    probe187,
    probe188,
    probe189,
    probe190,
    probe191,
    probe192,
    probe193,
    probe194,
    probe195,
    probe196,
    probe197,
    probe198,
    probe199,
    probe200,
    probe201,
    probe202,
    probe203,
    probe204,
    probe205,
    probe206,
    probe207,
    probe208,
    probe209,
    probe210,
    probe211,
    probe212,
    probe213,
    probe214,
    probe215,
    probe216,
    probe217,
    probe218,
    probe219,
    probe220,
    probe221,
    probe222,
    probe223,
    probe224,
    probe225,
    probe226,
    probe227,
    probe228,
    probe229,
    probe230,
    probe231,
    probe232,
    probe233,
    probe234,
    probe235,
    probe236,
    probe237,
    probe238,
    probe239,
    probe240,
    probe241,
    probe242,
    probe243,
    probe244,
    probe245,
    probe246,
    probe247,
    probe248,
    probe249,
    probe250,
    probe251,
    probe252,
    probe253,
    probe254,
    probe255,
    probe256,
    probe257,
    probe258,
    probe259,
    probe260,
    probe261,
    probe262,
    probe263,
    probe264,
    probe265,
    probe266,
    probe267,
    probe268,
    probe269,
    probe270,
    probe271,
    probe272,
    probe273,
    probe274,
    probe275,
    probe276,
    probe277,
    probe278,
    probe279,
    probe280,
    probe281,
    probe282,
    probe283,
    probe284,
    probe285,
    probe286,
    probe287,
    probe288,
    probe289,
    probe290,
    probe291,
    probe292,
    probe293,
    probe294,
    probe295,
    probe296,
    probe297,
    probe298,
    probe299,
    probe300,
    probe301,
    probe302,
    probe303,
    probe304,
    probe305,
    probe306,
    probe307,
    probe308,
    probe309,
    probe310,
    probe311,
    probe312,
    probe313,
    probe314,
    probe315,
    probe316,
    probe317,
    probe318,
    probe319,
    probe320,
    probe321,
    probe322,
    probe323,
    probe324,
    probe325,
    probe326,
    probe327,
    probe328,
    probe329,
    probe330,
    probe331,
    probe332,
    probe333,
    probe334,
    probe335,
    probe336,
    probe337,
    probe338,
    probe339,
    probe340,
    probe341,
    probe342,
    probe343,
    probe344,
    probe345,
    probe346,
    probe347,
    probe348,
    probe349,
    probe350,
    probe351,
    probe352,
    probe353,
    probe354,
    probe355,
    probe356,
    probe357,
    probe358,
    probe359,
    probe360,
    probe361,
    probe362,
    probe363,
    probe364,
    probe365,
    probe366,
    probe367,
    probe368,
    probe369,
    probe370,
    probe371,
    probe372,
    probe373,
    probe374,
    probe375,
    probe376,
    probe377,
    probe378,
    probe379,
    probe380,
    probe381,
    probe382,
    probe383,
    probe384,
    probe385,
    probe386,
    probe387,
    probe388,
    probe389,
    probe390,
    probe391,
    probe392,
    probe393,
    probe394,
    probe395,
    probe396,
    probe397,
    probe398,
    probe399,
    probe400,
    probe401,
    probe402,
    probe403,
    probe404,
    probe405,
    probe406,
    probe407,
    probe408,
    probe409,
    probe410,
    probe411,
    probe412,
    probe413,
    probe414,
    probe415,
    probe416,
    probe417,
    probe418,
    probe419,
    probe420,
    probe421,
    probe422,
    probe423,
    probe424,
    probe425,
    probe426,
    probe427,
    probe428,
    probe429,
    probe430,
    probe431,
    probe432,
    probe433,
    probe434,
    probe435,
    probe436,
    probe437,
    probe438,
    probe439,
    probe440,
    probe441,
    probe442,
    probe443,
    probe444,
    probe445,
    probe446,
    probe447,
    probe448,
    probe449,
    probe450,
    probe451,
    probe452,
    probe453,
    probe454,
    probe455,
    probe456,
    probe457,
    probe458,
    probe459,
    probe460,
    probe461,
    probe462,
    probe463,
    probe464,
    probe465,
    probe466,
    probe467,
    probe468,
    probe469,
    probe470,
    probe471,
    probe472,
    probe473,
    probe474,
    probe475,
    probe476,
    probe477,
    probe478,
    probe479,
    probe480,
    probe481,
    probe482,
    probe483,
    probe484,
    probe485,
    probe486,
    probe487,
    probe488,
    probe489,
    probe490,
    probe491,
    probe492,
    probe493,
    probe494,
    probe495,
    probe496,
    probe497,
    probe498,
    probe499,
    probe500,
    probe501,
    probe502,
    probe503,
    probe504,
    probe505,
    probe506,
    probe507,
    probe508,
    probe509,
    probe510,
    probe511,
    probe512,
    probe513,
    probe514,
    probe515,
    probe516,
    probe517,
    probe518,
    probe519,
    probe520,
    probe521,
    probe522,
    probe523,
    probe524,
    probe525,
    probe526,
    probe527,
    probe528,
    probe529,
    probe530,
    probe531,
    probe532,
    probe533,
    probe534,
    probe535,
    probe536,
    probe537,
    probe538,
    probe539,
    probe540,
    probe541,
    probe542,
    probe543,
    probe544,
    probe545,
    probe546,
    probe547,
    probe548,
    probe549,
    probe550,
    probe551,
    probe552,
    probe553,
    probe554,
    probe555,
    probe556,
    probe557,
    probe558,
    probe559,
    probe560,
    probe561,
    probe562,
    probe563,
    probe564,
    probe565,
    probe566,
    probe567,
    probe568,
    probe569,
    probe570,
    probe571,
    probe572,
    probe573,
    probe574,
    probe575,
    probe576,
    probe577,
    probe578,
    probe579,
    probe580,
    probe581,
    probe582,
    probe583,
    probe584,
    probe585,
    probe586,
    probe587,
    probe588,
    probe589,
    probe590,
    probe591,
    probe592,
    probe593,
    probe594,
    probe595,
    probe596,
    probe597,
    probe598,
    probe599,
    probe600,
    probe601,
    probe602,
    probe603,
    probe604,
    probe605,
    probe606,
    probe607,
    probe608,
    probe609,
    probe610,
    probe611,
    probe612,
    probe613,
    probe614,
    probe615,
    probe616,
    probe617,
    probe618,
    probe619,
    probe620,
    probe621,
    probe622,
    probe623,
    probe624,
    probe625,
    probe626,
    probe627,
    probe628,
    probe629,
    probe630,
    probe631,
    probe632,
    probe633,
    probe634,
    probe635,
    probe636,
    probe637,
    probe638,
    probe639,
    probe640,
    probe641,
    probe642,
    probe643,
    probe644,
    probe645,
    probe646,
    probe647,
    probe648,
    probe649,
    probe650,
    probe651,
    probe652,
    probe653,
    probe654,
    probe655,
    probe656,
    probe657,
    probe658,
    probe659,
    probe660,
    probe661,
    probe662,
    probe663,
    probe664,
    probe665,
    probe666,
    probe667,
    probe668,
    probe669,
    probe670,
    probe671,
    probe672,
    probe673,
    probe674,
    probe675,
    probe676,
    probe677,
    probe678,
    probe679,
    probe680,
    probe681,
    probe682,
    probe683,
    probe684,
    probe685,
    probe686,
    probe687,
    probe688,
    probe689,
    probe690,
    probe691,
    probe692,
    probe693,
    probe694,
    probe695,
    probe696,
    probe697,
    probe698,
    probe699,
    probe700,
    probe701,
    probe702,
    probe703,
    probe704,
    probe705,
    probe706,
    probe707,
    probe708,
    probe709,
    probe710,
    probe711,
    probe712,
    probe713,
    probe714,
    probe715,
    probe716,
    probe717,
    probe718,
    probe719,
    probe720,
    probe721,
    probe722,
    probe723,
    probe724,
    probe725,
    probe726,
    probe727,
    probe728,
    probe729,
    probe730,
    probe731,
    probe732,
    probe733,
    probe734,
    probe735,
    probe736,
    probe737,
    probe738,
    probe739,
    probe740,
    probe741,
    probe742,
    probe743,
    probe744,
    probe745,
    probe746,
    probe747,
    probe748,
    probe749,
    probe750,
    probe751,
    probe752,
    probe753,
    probe754,
    probe755,
    probe756,
    probe757,
    probe758,
    probe759,
    probe760,
    probe761,
    probe762,
    probe763,
    probe764,
    probe765,
    probe766,
    probe767,
    probe768,
    probe769,
    probe770,
    probe771,
    probe772,
    probe773,
    probe774,
    probe775,
    probe776,
    probe777,
    probe778,
    probe779,
    probe780,
    probe781,
    probe782,
    probe783,
    probe784,
    probe785,
    probe786,
    probe787,
    probe788,
    probe789,
    probe790,
    probe791,
    probe792,
    probe793,
    probe794,
    probe795,
    probe796,
    probe797,
    probe798,
    probe799,
    probe800,
    probe801,
    probe802,
    probe803,
    probe804,
    probe805,
    probe806,
    probe807,
    probe808,
    probe809,
    probe810,
    probe811,
    probe812,
    probe813,
    probe814,
    probe815,
    probe816,
    probe817,
    probe818,
    probe819,
    probe820,
    probe821,
    probe822,
    probe823,
    probe824,
    probe825,
    probe826,
    probe827,
    probe828,
    probe829,
    probe830,
    probe831,
    probe832,
    probe833,
    probe834,
    probe835,
    probe836,
    probe837,
    probe838,
    probe839,
    probe840,
    probe841,
    probe842,
    probe843,
    probe844,
    probe845,
    probe846,
    probe847,
    probe848,
    probe849,
    probe850,
    probe851,
    probe852,
    probe853,
    probe854,
    probe855,
    probe856,
    probe857,
    probe858,
    probe859,
    probe860,
    probe861,
    probe862,
    probe863,
    probe864,
    probe865,
    probe866,
    probe867,
    probe868,
    probe869,
    probe870,
    probe871,
    probe872,
    probe873,
    probe874,
    probe875,
    probe876,
    probe877,
    probe878,
    probe879,
    probe880,
    probe881,
    probe882,
    probe883,
    probe884,
    probe885,
    probe886,
    probe887,
    probe888,
    probe889,
    probe890,
    probe891,
    probe892,
    probe893,
    probe894,
    probe895,
    probe896,
    probe897,
    probe898,
    probe899,
    probe900,
    probe901,
    probe902,
    probe903,
    probe904,
    probe905,
    probe906,
    probe907,
    probe908,
    probe909,
    probe910,
    probe911,
    probe912,
    probe913,
    probe914,
    probe915,
    probe916,
    probe917,
    probe918,
    probe919,
    probe920,
    probe921,
    probe922,
    probe923,
    probe924,
    probe925,
    probe926,
    probe927,
    probe928,
    probe929,
    probe930,
    probe931,
    probe932,
    probe933,
    probe934,
    probe935,
    probe936,
    probe937,
    probe938,
    probe939,
    probe940,
    probe941,
    probe942,
    probe943,
    probe944,
    probe945,
    probe946,
    probe947,
    probe948,
    probe949,
    probe950,
    probe951,
    probe952,
    probe953,
    probe954,
    probe955,
    probe956,
    probe957,
    probe958,
    probe959,
    probe960,
    probe961,
    probe962,
    probe963,
    probe964,
    probe965,
    probe966,
    probe967,
    probe968,
    probe969,
    probe970,
    probe971,
    probe972,
    probe973,
    probe974,
    probe975,
    probe976,
    probe977,
    probe978,
    probe979,
    probe980,
    probe981,
    probe982,
    probe983,
    probe984,
    probe985,
    probe986,
    probe987,
    probe988,
    probe989,
    probe990,
    probe991,
    probe992,
    probe993,
    probe994,
    probe995,
    probe996,
    probe997,
    probe998,
    probe999,
    probe1000,
    probe1001,
    probe1002,
    probe1003,
    probe1004,
    probe1005,
    probe1006,
    probe1007,
    probe1008,
    probe1009,
    probe1010,
    probe1011,
    probe1012,
    probe1013,
    probe1014,
    probe1015,
    probe1016,
    probe1017,
    probe1018,
    probe1019,
    probe1020,
    probe1021,
    probe1022,
    probe1023);
  input clk;
  input clk_nobuf;
  output clkdiv_out;
  (* dont_touch = "true" *) input [36:0]sl_iport0;
  (* dont_touch = "true" *) output [16:0]sl_oport0;
  input trig_in;
  output trig_in_ack;
  output trig_out;
  input trig_out_ack;
  input [20:0]probe0;
  input [21:0]probe1;
  input [21:0]probe2;
  input [0:0]probe3;
  input [0:0]probe4;
  input [0:0]probe5;
  input [0:0]probe6;
  input [0:0]probe7;
  input [0:0]probe8;
  input [0:0]probe9;
  input [0:0]probe10;
  input [0:0]probe11;
  input [0:0]probe12;
  input [0:0]probe13;
  input [0:0]probe14;
  input [0:0]probe15;
  input [0:0]probe16;
  input [0:0]probe17;
  input [0:0]probe18;
  input [0:0]probe19;
  input [0:0]probe20;
  input [0:0]probe21;
  input [0:0]probe22;
  input [0:0]probe23;
  input [0:0]probe24;
  input [0:0]probe25;
  input [0:0]probe26;
  input [0:0]probe27;
  input [0:0]probe28;
  input [0:0]probe29;
  input [0:0]probe30;
  input [0:0]probe31;
  input [0:0]probe32;
  input [0:0]probe33;
  input [0:0]probe34;
  input [0:0]probe35;
  input [0:0]probe36;
  input [0:0]probe37;
  input [0:0]probe38;
  input [0:0]probe39;
  input [0:0]probe40;
  input [0:0]probe41;
  input [0:0]probe42;
  input [0:0]probe43;
  input [0:0]probe44;
  input [0:0]probe45;
  input [0:0]probe46;
  input [0:0]probe47;
  input [0:0]probe48;
  input [0:0]probe49;
  input [0:0]probe50;
  input [0:0]probe51;
  input [0:0]probe52;
  input [0:0]probe53;
  input [0:0]probe54;
  input [0:0]probe55;
  input [0:0]probe56;
  input [0:0]probe57;
  input [0:0]probe58;
  input [0:0]probe59;
  input [0:0]probe60;
  input [0:0]probe61;
  input [0:0]probe62;
  input [0:0]probe63;
  input [0:0]probe64;
  input [0:0]probe65;
  input [0:0]probe66;
  input [0:0]probe67;
  input [0:0]probe68;
  input [0:0]probe69;
  input [0:0]probe70;
  input [0:0]probe71;
  input [0:0]probe72;
  input [0:0]probe73;
  input [0:0]probe74;
  input [0:0]probe75;
  input [0:0]probe76;
  input [0:0]probe77;
  input [0:0]probe78;
  input [0:0]probe79;
  input [0:0]probe80;
  input [0:0]probe81;
  input [0:0]probe82;
  input [0:0]probe83;
  input [0:0]probe84;
  input [0:0]probe85;
  input [0:0]probe86;
  input [0:0]probe87;
  input [0:0]probe88;
  input [0:0]probe89;
  input [0:0]probe90;
  input [0:0]probe91;
  input [0:0]probe92;
  input [0:0]probe93;
  input [0:0]probe94;
  input [0:0]probe95;
  input [0:0]probe96;
  input [0:0]probe97;
  input [0:0]probe98;
  input [0:0]probe99;
  input [0:0]probe100;
  input [0:0]probe101;
  input [0:0]probe102;
  input [0:0]probe103;
  input [0:0]probe104;
  input [0:0]probe105;
  input [0:0]probe106;
  input [0:0]probe107;
  input [0:0]probe108;
  input [0:0]probe109;
  input [0:0]probe110;
  input [0:0]probe111;
  input [0:0]probe112;
  input [0:0]probe113;
  input [0:0]probe114;
  input [0:0]probe115;
  input [0:0]probe116;
  input [0:0]probe117;
  input [0:0]probe118;
  input [0:0]probe119;
  input [0:0]probe120;
  input [0:0]probe121;
  input [0:0]probe122;
  input [0:0]probe123;
  input [0:0]probe124;
  input [0:0]probe125;
  input [0:0]probe126;
  input [0:0]probe127;
  input [0:0]probe128;
  input [0:0]probe129;
  input [0:0]probe130;
  input [0:0]probe131;
  input [0:0]probe132;
  input [0:0]probe133;
  input [0:0]probe134;
  input [0:0]probe135;
  input [0:0]probe136;
  input [0:0]probe137;
  input [0:0]probe138;
  input [0:0]probe139;
  input [0:0]probe140;
  input [0:0]probe141;
  input [0:0]probe142;
  input [0:0]probe143;
  input [0:0]probe144;
  input [0:0]probe145;
  input [0:0]probe146;
  input [0:0]probe147;
  input [0:0]probe148;
  input [0:0]probe149;
  input [0:0]probe150;
  input [0:0]probe151;
  input [0:0]probe152;
  input [0:0]probe153;
  input [0:0]probe154;
  input [0:0]probe155;
  input [0:0]probe156;
  input [0:0]probe157;
  input [0:0]probe158;
  input [0:0]probe159;
  input [0:0]probe160;
  input [0:0]probe161;
  input [0:0]probe162;
  input [0:0]probe163;
  input [0:0]probe164;
  input [0:0]probe165;
  input [0:0]probe166;
  input [0:0]probe167;
  input [0:0]probe168;
  input [0:0]probe169;
  input [0:0]probe170;
  input [0:0]probe171;
  input [0:0]probe172;
  input [0:0]probe173;
  input [0:0]probe174;
  input [0:0]probe175;
  input [0:0]probe176;
  input [0:0]probe177;
  input [0:0]probe178;
  input [0:0]probe179;
  input [0:0]probe180;
  input [0:0]probe181;
  input [0:0]probe182;
  input [0:0]probe183;
  input [0:0]probe184;
  input [0:0]probe185;
  input [0:0]probe186;
  input [0:0]probe187;
  input [0:0]probe188;
  input [0:0]probe189;
  input [0:0]probe190;
  input [0:0]probe191;
  input [0:0]probe192;
  input [0:0]probe193;
  input [0:0]probe194;
  input [0:0]probe195;
  input [0:0]probe196;
  input [0:0]probe197;
  input [0:0]probe198;
  input [0:0]probe199;
  input [0:0]probe200;
  input [0:0]probe201;
  input [0:0]probe202;
  input [0:0]probe203;
  input [0:0]probe204;
  input [0:0]probe205;
  input [0:0]probe206;
  input [0:0]probe207;
  input [0:0]probe208;
  input [0:0]probe209;
  input [0:0]probe210;
  input [0:0]probe211;
  input [0:0]probe212;
  input [0:0]probe213;
  input [0:0]probe214;
  input [0:0]probe215;
  input [0:0]probe216;
  input [0:0]probe217;
  input [0:0]probe218;
  input [0:0]probe219;
  input [0:0]probe220;
  input [0:0]probe221;
  input [0:0]probe222;
  input [0:0]probe223;
  input [0:0]probe224;
  input [0:0]probe225;
  input [0:0]probe226;
  input [0:0]probe227;
  input [0:0]probe228;
  input [0:0]probe229;
  input [0:0]probe230;
  input [0:0]probe231;
  input [0:0]probe232;
  input [0:0]probe233;
  input [0:0]probe234;
  input [0:0]probe235;
  input [0:0]probe236;
  input [0:0]probe237;
  input [0:0]probe238;
  input [0:0]probe239;
  input [0:0]probe240;
  input [0:0]probe241;
  input [0:0]probe242;
  input [0:0]probe243;
  input [0:0]probe244;
  input [0:0]probe245;
  input [0:0]probe246;
  input [0:0]probe247;
  input [0:0]probe248;
  input [0:0]probe249;
  input [0:0]probe250;
  input [0:0]probe251;
  input [0:0]probe252;
  input [0:0]probe253;
  input [0:0]probe254;
  input [0:0]probe255;
  input [0:0]probe256;
  input [0:0]probe257;
  input [0:0]probe258;
  input [0:0]probe259;
  input [0:0]probe260;
  input [0:0]probe261;
  input [0:0]probe262;
  input [0:0]probe263;
  input [0:0]probe264;
  input [0:0]probe265;
  input [0:0]probe266;
  input [0:0]probe267;
  input [0:0]probe268;
  input [0:0]probe269;
  input [0:0]probe270;
  input [0:0]probe271;
  input [0:0]probe272;
  input [0:0]probe273;
  input [0:0]probe274;
  input [0:0]probe275;
  input [0:0]probe276;
  input [0:0]probe277;
  input [0:0]probe278;
  input [0:0]probe279;
  input [0:0]probe280;
  input [0:0]probe281;
  input [0:0]probe282;
  input [0:0]probe283;
  input [0:0]probe284;
  input [0:0]probe285;
  input [0:0]probe286;
  input [0:0]probe287;
  input [0:0]probe288;
  input [0:0]probe289;
  input [0:0]probe290;
  input [0:0]probe291;
  input [0:0]probe292;
  input [0:0]probe293;
  input [0:0]probe294;
  input [0:0]probe295;
  input [0:0]probe296;
  input [0:0]probe297;
  input [0:0]probe298;
  input [0:0]probe299;
  input [0:0]probe300;
  input [0:0]probe301;
  input [0:0]probe302;
  input [0:0]probe303;
  input [0:0]probe304;
  input [0:0]probe305;
  input [0:0]probe306;
  input [0:0]probe307;
  input [0:0]probe308;
  input [0:0]probe309;
  input [0:0]probe310;
  input [0:0]probe311;
  input [0:0]probe312;
  input [0:0]probe313;
  input [0:0]probe314;
  input [0:0]probe315;
  input [0:0]probe316;
  input [0:0]probe317;
  input [0:0]probe318;
  input [0:0]probe319;
  input [0:0]probe320;
  input [0:0]probe321;
  input [0:0]probe322;
  input [0:0]probe323;
  input [0:0]probe324;
  input [0:0]probe325;
  input [0:0]probe326;
  input [0:0]probe327;
  input [0:0]probe328;
  input [0:0]probe329;
  input [0:0]probe330;
  input [0:0]probe331;
  input [0:0]probe332;
  input [0:0]probe333;
  input [0:0]probe334;
  input [0:0]probe335;
  input [0:0]probe336;
  input [0:0]probe337;
  input [0:0]probe338;
  input [0:0]probe339;
  input [0:0]probe340;
  input [0:0]probe341;
  input [0:0]probe342;
  input [0:0]probe343;
  input [0:0]probe344;
  input [0:0]probe345;
  input [0:0]probe346;
  input [0:0]probe347;
  input [0:0]probe348;
  input [0:0]probe349;
  input [0:0]probe350;
  input [0:0]probe351;
  input [0:0]probe352;
  input [0:0]probe353;
  input [0:0]probe354;
  input [0:0]probe355;
  input [0:0]probe356;
  input [0:0]probe357;
  input [0:0]probe358;
  input [0:0]probe359;
  input [0:0]probe360;
  input [0:0]probe361;
  input [0:0]probe362;
  input [0:0]probe363;
  input [0:0]probe364;
  input [0:0]probe365;
  input [0:0]probe366;
  input [0:0]probe367;
  input [0:0]probe368;
  input [0:0]probe369;
  input [0:0]probe370;
  input [0:0]probe371;
  input [0:0]probe372;
  input [0:0]probe373;
  input [0:0]probe374;
  input [0:0]probe375;
  input [0:0]probe376;
  input [0:0]probe377;
  input [0:0]probe378;
  input [0:0]probe379;
  input [0:0]probe380;
  input [0:0]probe381;
  input [0:0]probe382;
  input [0:0]probe383;
  input [0:0]probe384;
  input [0:0]probe385;
  input [0:0]probe386;
  input [0:0]probe387;
  input [0:0]probe388;
  input [0:0]probe389;
  input [0:0]probe390;
  input [0:0]probe391;
  input [0:0]probe392;
  input [0:0]probe393;
  input [0:0]probe394;
  input [0:0]probe395;
  input [0:0]probe396;
  input [0:0]probe397;
  input [0:0]probe398;
  input [0:0]probe399;
  input [0:0]probe400;
  input [0:0]probe401;
  input [0:0]probe402;
  input [0:0]probe403;
  input [0:0]probe404;
  input [0:0]probe405;
  input [0:0]probe406;
  input [0:0]probe407;
  input [0:0]probe408;
  input [0:0]probe409;
  input [0:0]probe410;
  input [0:0]probe411;
  input [0:0]probe412;
  input [0:0]probe413;
  input [0:0]probe414;
  input [0:0]probe415;
  input [0:0]probe416;
  input [0:0]probe417;
  input [0:0]probe418;
  input [0:0]probe419;
  input [0:0]probe420;
  input [0:0]probe421;
  input [0:0]probe422;
  input [0:0]probe423;
  input [0:0]probe424;
  input [0:0]probe425;
  input [0:0]probe426;
  input [0:0]probe427;
  input [0:0]probe428;
  input [0:0]probe429;
  input [0:0]probe430;
  input [0:0]probe431;
  input [0:0]probe432;
  input [0:0]probe433;
  input [0:0]probe434;
  input [0:0]probe435;
  input [0:0]probe436;
  input [0:0]probe437;
  input [0:0]probe438;
  input [0:0]probe439;
  input [0:0]probe440;
  input [0:0]probe441;
  input [0:0]probe442;
  input [0:0]probe443;
  input [0:0]probe444;
  input [0:0]probe445;
  input [0:0]probe446;
  input [0:0]probe447;
  input [0:0]probe448;
  input [0:0]probe449;
  input [0:0]probe450;
  input [0:0]probe451;
  input [0:0]probe452;
  input [0:0]probe453;
  input [0:0]probe454;
  input [0:0]probe455;
  input [0:0]probe456;
  input [0:0]probe457;
  input [0:0]probe458;
  input [0:0]probe459;
  input [0:0]probe460;
  input [0:0]probe461;
  input [0:0]probe462;
  input [0:0]probe463;
  input [0:0]probe464;
  input [0:0]probe465;
  input [0:0]probe466;
  input [0:0]probe467;
  input [0:0]probe468;
  input [0:0]probe469;
  input [0:0]probe470;
  input [0:0]probe471;
  input [0:0]probe472;
  input [0:0]probe473;
  input [0:0]probe474;
  input [0:0]probe475;
  input [0:0]probe476;
  input [0:0]probe477;
  input [0:0]probe478;
  input [0:0]probe479;
  input [0:0]probe480;
  input [0:0]probe481;
  input [0:0]probe482;
  input [0:0]probe483;
  input [0:0]probe484;
  input [0:0]probe485;
  input [0:0]probe486;
  input [0:0]probe487;
  input [0:0]probe488;
  input [0:0]probe489;
  input [0:0]probe490;
  input [0:0]probe491;
  input [0:0]probe492;
  input [0:0]probe493;
  input [0:0]probe494;
  input [0:0]probe495;
  input [0:0]probe496;
  input [0:0]probe497;
  input [0:0]probe498;
  input [0:0]probe499;
  input [0:0]probe500;
  input [0:0]probe501;
  input [0:0]probe502;
  input [0:0]probe503;
  input [0:0]probe504;
  input [0:0]probe505;
  input [0:0]probe506;
  input [0:0]probe507;
  input [0:0]probe508;
  input [0:0]probe509;
  input [0:0]probe510;
  input [0:0]probe511;
  input [0:0]probe512;
  input [0:0]probe513;
  input [0:0]probe514;
  input [0:0]probe515;
  input [0:0]probe516;
  input [0:0]probe517;
  input [0:0]probe518;
  input [0:0]probe519;
  input [0:0]probe520;
  input [0:0]probe521;
  input [0:0]probe522;
  input [0:0]probe523;
  input [0:0]probe524;
  input [0:0]probe525;
  input [0:0]probe526;
  input [0:0]probe527;
  input [0:0]probe528;
  input [0:0]probe529;
  input [0:0]probe530;
  input [0:0]probe531;
  input [0:0]probe532;
  input [0:0]probe533;
  input [0:0]probe534;
  input [0:0]probe535;
  input [0:0]probe536;
  input [0:0]probe537;
  input [0:0]probe538;
  input [0:0]probe539;
  input [0:0]probe540;
  input [0:0]probe541;
  input [0:0]probe542;
  input [0:0]probe543;
  input [0:0]probe544;
  input [0:0]probe545;
  input [0:0]probe546;
  input [0:0]probe547;
  input [0:0]probe548;
  input [0:0]probe549;
  input [0:0]probe550;
  input [0:0]probe551;
  input [0:0]probe552;
  input [0:0]probe553;
  input [0:0]probe554;
  input [0:0]probe555;
  input [0:0]probe556;
  input [0:0]probe557;
  input [0:0]probe558;
  input [0:0]probe559;
  input [0:0]probe560;
  input [0:0]probe561;
  input [0:0]probe562;
  input [0:0]probe563;
  input [0:0]probe564;
  input [0:0]probe565;
  input [0:0]probe566;
  input [0:0]probe567;
  input [0:0]probe568;
  input [0:0]probe569;
  input [0:0]probe570;
  input [0:0]probe571;
  input [0:0]probe572;
  input [0:0]probe573;
  input [0:0]probe574;
  input [0:0]probe575;
  input [0:0]probe576;
  input [0:0]probe577;
  input [0:0]probe578;
  input [0:0]probe579;
  input [0:0]probe580;
  input [0:0]probe581;
  input [0:0]probe582;
  input [0:0]probe583;
  input [0:0]probe584;
  input [0:0]probe585;
  input [0:0]probe586;
  input [0:0]probe587;
  input [0:0]probe588;
  input [0:0]probe589;
  input [0:0]probe590;
  input [0:0]probe591;
  input [0:0]probe592;
  input [0:0]probe593;
  input [0:0]probe594;
  input [0:0]probe595;
  input [0:0]probe596;
  input [0:0]probe597;
  input [0:0]probe598;
  input [0:0]probe599;
  input [0:0]probe600;
  input [0:0]probe601;
  input [0:0]probe602;
  input [0:0]probe603;
  input [0:0]probe604;
  input [0:0]probe605;
  input [0:0]probe606;
  input [0:0]probe607;
  input [0:0]probe608;
  input [0:0]probe609;
  input [0:0]probe610;
  input [0:0]probe611;
  input [0:0]probe612;
  input [0:0]probe613;
  input [0:0]probe614;
  input [0:0]probe615;
  input [0:0]probe616;
  input [0:0]probe617;
  input [0:0]probe618;
  input [0:0]probe619;
  input [0:0]probe620;
  input [0:0]probe621;
  input [0:0]probe622;
  input [0:0]probe623;
  input [0:0]probe624;
  input [0:0]probe625;
  input [0:0]probe626;
  input [0:0]probe627;
  input [0:0]probe628;
  input [0:0]probe629;
  input [0:0]probe630;
  input [0:0]probe631;
  input [0:0]probe632;
  input [0:0]probe633;
  input [0:0]probe634;
  input [0:0]probe635;
  input [0:0]probe636;
  input [0:0]probe637;
  input [0:0]probe638;
  input [0:0]probe639;
  input [0:0]probe640;
  input [0:0]probe641;
  input [0:0]probe642;
  input [0:0]probe643;
  input [0:0]probe644;
  input [0:0]probe645;
  input [0:0]probe646;
  input [0:0]probe647;
  input [0:0]probe648;
  input [0:0]probe649;
  input [0:0]probe650;
  input [0:0]probe651;
  input [0:0]probe652;
  input [0:0]probe653;
  input [0:0]probe654;
  input [0:0]probe655;
  input [0:0]probe656;
  input [0:0]probe657;
  input [0:0]probe658;
  input [0:0]probe659;
  input [0:0]probe660;
  input [0:0]probe661;
  input [0:0]probe662;
  input [0:0]probe663;
  input [0:0]probe664;
  input [0:0]probe665;
  input [0:0]probe666;
  input [0:0]probe667;
  input [0:0]probe668;
  input [0:0]probe669;
  input [0:0]probe670;
  input [0:0]probe671;
  input [0:0]probe672;
  input [0:0]probe673;
  input [0:0]probe674;
  input [0:0]probe675;
  input [0:0]probe676;
  input [0:0]probe677;
  input [0:0]probe678;
  input [0:0]probe679;
  input [0:0]probe680;
  input [0:0]probe681;
  input [0:0]probe682;
  input [0:0]probe683;
  input [0:0]probe684;
  input [0:0]probe685;
  input [0:0]probe686;
  input [0:0]probe687;
  input [0:0]probe688;
  input [0:0]probe689;
  input [0:0]probe690;
  input [0:0]probe691;
  input [0:0]probe692;
  input [0:0]probe693;
  input [0:0]probe694;
  input [0:0]probe695;
  input [0:0]probe696;
  input [0:0]probe697;
  input [0:0]probe698;
  input [0:0]probe699;
  input [0:0]probe700;
  input [0:0]probe701;
  input [0:0]probe702;
  input [0:0]probe703;
  input [0:0]probe704;
  input [0:0]probe705;
  input [0:0]probe706;
  input [0:0]probe707;
  input [0:0]probe708;
  input [0:0]probe709;
  input [0:0]probe710;
  input [0:0]probe711;
  input [0:0]probe712;
  input [0:0]probe713;
  input [0:0]probe714;
  input [0:0]probe715;
  input [0:0]probe716;
  input [0:0]probe717;
  input [0:0]probe718;
  input [0:0]probe719;
  input [0:0]probe720;
  input [0:0]probe721;
  input [0:0]probe722;
  input [0:0]probe723;
  input [0:0]probe724;
  input [0:0]probe725;
  input [0:0]probe726;
  input [0:0]probe727;
  input [0:0]probe728;
  input [0:0]probe729;
  input [0:0]probe730;
  input [0:0]probe731;
  input [0:0]probe732;
  input [0:0]probe733;
  input [0:0]probe734;
  input [0:0]probe735;
  input [0:0]probe736;
  input [0:0]probe737;
  input [0:0]probe738;
  input [0:0]probe739;
  input [0:0]probe740;
  input [0:0]probe741;
  input [0:0]probe742;
  input [0:0]probe743;
  input [0:0]probe744;
  input [0:0]probe745;
  input [0:0]probe746;
  input [0:0]probe747;
  input [0:0]probe748;
  input [0:0]probe749;
  input [0:0]probe750;
  input [0:0]probe751;
  input [0:0]probe752;
  input [0:0]probe753;
  input [0:0]probe754;
  input [0:0]probe755;
  input [0:0]probe756;
  input [0:0]probe757;
  input [0:0]probe758;
  input [0:0]probe759;
  input [0:0]probe760;
  input [0:0]probe761;
  input [0:0]probe762;
  input [0:0]probe763;
  input [0:0]probe764;
  input [0:0]probe765;
  input [0:0]probe766;
  input [0:0]probe767;
  input [0:0]probe768;
  input [0:0]probe769;
  input [0:0]probe770;
  input [0:0]probe771;
  input [0:0]probe772;
  input [0:0]probe773;
  input [0:0]probe774;
  input [0:0]probe775;
  input [0:0]probe776;
  input [0:0]probe777;
  input [0:0]probe778;
  input [0:0]probe779;
  input [0:0]probe780;
  input [0:0]probe781;
  input [0:0]probe782;
  input [0:0]probe783;
  input [0:0]probe784;
  input [0:0]probe785;
  input [0:0]probe786;
  input [0:0]probe787;
  input [0:0]probe788;
  input [0:0]probe789;
  input [0:0]probe790;
  input [0:0]probe791;
  input [0:0]probe792;
  input [0:0]probe793;
  input [0:0]probe794;
  input [0:0]probe795;
  input [0:0]probe796;
  input [0:0]probe797;
  input [0:0]probe798;
  input [0:0]probe799;
  input [0:0]probe800;
  input [0:0]probe801;
  input [0:0]probe802;
  input [0:0]probe803;
  input [0:0]probe804;
  input [0:0]probe805;
  input [0:0]probe806;
  input [0:0]probe807;
  input [0:0]probe808;
  input [0:0]probe809;
  input [0:0]probe810;
  input [0:0]probe811;
  input [0:0]probe812;
  input [0:0]probe813;
  input [0:0]probe814;
  input [0:0]probe815;
  input [0:0]probe816;
  input [0:0]probe817;
  input [0:0]probe818;
  input [0:0]probe819;
  input [0:0]probe820;
  input [0:0]probe821;
  input [0:0]probe822;
  input [0:0]probe823;
  input [0:0]probe824;
  input [0:0]probe825;
  input [0:0]probe826;
  input [0:0]probe827;
  input [0:0]probe828;
  input [0:0]probe829;
  input [0:0]probe830;
  input [0:0]probe831;
  input [0:0]probe832;
  input [0:0]probe833;
  input [0:0]probe834;
  input [0:0]probe835;
  input [0:0]probe836;
  input [0:0]probe837;
  input [0:0]probe838;
  input [0:0]probe839;
  input [0:0]probe840;
  input [0:0]probe841;
  input [0:0]probe842;
  input [0:0]probe843;
  input [0:0]probe844;
  input [0:0]probe845;
  input [0:0]probe846;
  input [0:0]probe847;
  input [0:0]probe848;
  input [0:0]probe849;
  input [0:0]probe850;
  input [0:0]probe851;
  input [0:0]probe852;
  input [0:0]probe853;
  input [0:0]probe854;
  input [0:0]probe855;
  input [0:0]probe856;
  input [0:0]probe857;
  input [0:0]probe858;
  input [0:0]probe859;
  input [0:0]probe860;
  input [0:0]probe861;
  input [0:0]probe862;
  input [0:0]probe863;
  input [0:0]probe864;
  input [0:0]probe865;
  input [0:0]probe866;
  input [0:0]probe867;
  input [0:0]probe868;
  input [0:0]probe869;
  input [0:0]probe870;
  input [0:0]probe871;
  input [0:0]probe872;
  input [0:0]probe873;
  input [0:0]probe874;
  input [0:0]probe875;
  input [0:0]probe876;
  input [0:0]probe877;
  input [0:0]probe878;
  input [0:0]probe879;
  input [0:0]probe880;
  input [0:0]probe881;
  input [0:0]probe882;
  input [0:0]probe883;
  input [0:0]probe884;
  input [0:0]probe885;
  input [0:0]probe886;
  input [0:0]probe887;
  input [0:0]probe888;
  input [0:0]probe889;
  input [0:0]probe890;
  input [0:0]probe891;
  input [0:0]probe892;
  input [0:0]probe893;
  input [0:0]probe894;
  input [0:0]probe895;
  input [0:0]probe896;
  input [0:0]probe897;
  input [0:0]probe898;
  input [0:0]probe899;
  input [0:0]probe900;
  input [0:0]probe901;
  input [0:0]probe902;
  input [0:0]probe903;
  input [0:0]probe904;
  input [0:0]probe905;
  input [0:0]probe906;
  input [0:0]probe907;
  input [0:0]probe908;
  input [0:0]probe909;
  input [0:0]probe910;
  input [0:0]probe911;
  input [0:0]probe912;
  input [0:0]probe913;
  input [0:0]probe914;
  input [0:0]probe915;
  input [0:0]probe916;
  input [0:0]probe917;
  input [0:0]probe918;
  input [0:0]probe919;
  input [0:0]probe920;
  input [0:0]probe921;
  input [0:0]probe922;
  input [0:0]probe923;
  input [0:0]probe924;
  input [0:0]probe925;
  input [0:0]probe926;
  input [0:0]probe927;
  input [0:0]probe928;
  input [0:0]probe929;
  input [0:0]probe930;
  input [0:0]probe931;
  input [0:0]probe932;
  input [0:0]probe933;
  input [0:0]probe934;
  input [0:0]probe935;
  input [0:0]probe936;
  input [0:0]probe937;
  input [0:0]probe938;
  input [0:0]probe939;
  input [0:0]probe940;
  input [0:0]probe941;
  input [0:0]probe942;
  input [0:0]probe943;
  input [0:0]probe944;
  input [0:0]probe945;
  input [0:0]probe946;
  input [0:0]probe947;
  input [0:0]probe948;
  input [0:0]probe949;
  input [0:0]probe950;
  input [0:0]probe951;
  input [0:0]probe952;
  input [0:0]probe953;
  input [0:0]probe954;
  input [0:0]probe955;
  input [0:0]probe956;
  input [0:0]probe957;
  input [0:0]probe958;
  input [0:0]probe959;
  input [0:0]probe960;
  input [0:0]probe961;
  input [0:0]probe962;
  input [0:0]probe963;
  input [0:0]probe964;
  input [0:0]probe965;
  input [0:0]probe966;
  input [0:0]probe967;
  input [0:0]probe968;
  input [0:0]probe969;
  input [0:0]probe970;
  input [0:0]probe971;
  input [0:0]probe972;
  input [0:0]probe973;
  input [0:0]probe974;
  input [0:0]probe975;
  input [0:0]probe976;
  input [0:0]probe977;
  input [0:0]probe978;
  input [0:0]probe979;
  input [0:0]probe980;
  input [0:0]probe981;
  input [0:0]probe982;
  input [0:0]probe983;
  input [0:0]probe984;
  input [0:0]probe985;
  input [0:0]probe986;
  input [0:0]probe987;
  input [0:0]probe988;
  input [0:0]probe989;
  input [0:0]probe990;
  input [0:0]probe991;
  input [0:0]probe992;
  input [0:0]probe993;
  input [0:0]probe994;
  input [0:0]probe995;
  input [0:0]probe996;
  input [0:0]probe997;
  input [0:0]probe998;
  input [0:0]probe999;
  input [0:0]probe1000;
  input [0:0]probe1001;
  input [0:0]probe1002;
  input [0:0]probe1003;
  input [0:0]probe1004;
  input [0:0]probe1005;
  input [0:0]probe1006;
  input [0:0]probe1007;
  input [0:0]probe1008;
  input [0:0]probe1009;
  input [0:0]probe1010;
  input [0:0]probe1011;
  input [0:0]probe1012;
  input [0:0]probe1013;
  input [0:0]probe1014;
  input [0:0]probe1015;
  input [0:0]probe1016;
  input [0:0]probe1017;
  input [0:0]probe1018;
  input [0:0]probe1019;
  input [0:0]probe1020;
  input [0:0]probe1021;
  input [0:0]probe1022;
  input [0:0]probe1023;

  wire \<const0> ;
  (* DONT_TOUCH *) wire ack_reg1;
  (* DONT_TOUCH *) wire ack_reg2;
  (* RTL_KEEP = "true" *) wire clk1x;
  (* DONT_TOUCH *) wire dummy;
  wire [20:0]probe0;
  wire [21:0]probe1;
  wire [21:0]probe2;
  (* DONT_TOUCH *) wire [36:0]sl_iport0;
  (* DONT_TOUCH *) wire [16:0]sl_oport0;
  (* DONT_TOUCH *) wire sync_reg1;
  (* DONT_TOUCH *) wire sync_reg2;
  wire trig_in;
  (* DONT_TOUCH *) wire trig_in_reg;
  wire trig_out_ack;
  (* DONT_TOUCH *) wire trig_out_ack_reg;

  assign clk1x = clk;
  assign clkdiv_out = \<const0> ;
  assign trig_in_ack = \<const0> ;
  assign trig_out = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ack_reg1_reg[0] 
       (.C(clk1x),
        .CE(1'b1),
        .D(trig_out_ack),
        .Q(ack_reg1),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ack_reg2_reg[0] 
       (.C(clk1x),
        .CE(1'b1),
        .D(ack_reg1),
        .Q(ack_reg2),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(dummy));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_core ila_core_inst
       (.DUMMY_I(dummy),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (clk1x),
        .SL_OPORT_O(sl_oport0),
        .out(sl_iport0),
        .probe0(probe0),
        .probe1(probe1),
        .probe2(probe2));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \sync_reg1_reg[0] 
       (.C(clk1x),
        .CE(1'b1),
        .D(trig_in),
        .Q(sync_reg1),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \sync_reg2_reg[0] 
       (.C(clk1x),
        .CE(1'b1),
        .D(sync_reg1),
        .Q(sync_reg2),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE trig_in_reg_reg
       (.C(clk1x),
        .CE(1'b1),
        .D(sync_reg2),
        .Q(trig_in_reg),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE trig_out_ack_reg_reg
       (.C(clk1x),
        .CE(1'b1),
        .D(ack_reg2),
        .Q(trig_out_ack_reg),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_adv_trigger_sequencer
   (trig_out_fsm,
    capture_fsm,
    flag0_temp,
    flag1_temp,
    flag2_temp,
    flag3_temp,
    current_state,
    CNT_CTRL,
    A,
    douta0,
    \CFG_BRAM_RD_DATA_reg[23]_0 ,
    SEQUENCER_STATE_O,
    COUNTER_EQ,
    toggle_rd,
    out,
    bram_rd_en,
    E,
    bram_en,
    trigger_reg_0,
    \SEQUENCER_STATE_O_reg[0]_0 ,
    CAPTURE_O_reg_0,
    \current_state_reg[0]_0 ,
    Q,
    \SEQUENCER_STATE_O_reg[0]_1 ,
    O_reg,
    u_wcnt_lcmp_q,
    basic_trigger,
    \current_state_reg[0]_1 ,
    \cntcmpsel_reg[1]_0 ,
    CFG_BRAM_DATA,
    ADDRA,
    \SEQUENCER_STATE_O_reg[8]_0 ,
    \SEQUENCER_STATE_O_reg[0]_2 );
  output trig_out_fsm;
  output capture_fsm;
  output flag0_temp;
  output flag1_temp;
  output flag2_temp;
  output flag3_temp;
  output [3:0]current_state;
  output [7:0]CNT_CTRL;
  output [0:0]A;
  output [1:0]douta0;
  output [23:0]\CFG_BRAM_RD_DATA_reg[23]_0 ;
  output [15:0]SEQUENCER_STATE_O;
  input [3:0]COUNTER_EQ;
  input toggle_rd;
  input [0:0]out;
  input bram_rd_en;
  input [0:0]E;
  input bram_en;
  input trigger_reg_0;
  input \SEQUENCER_STATE_O_reg[0]_0 ;
  input CAPTURE_O_reg_0;
  input \current_state_reg[0]_0 ;
  input [1:0]Q;
  input \SEQUENCER_STATE_O_reg[0]_1 ;
  input O_reg;
  input u_wcnt_lcmp_q;
  input basic_trigger;
  input \current_state_reg[0]_1 ;
  input \cntcmpsel_reg[1]_0 ;
  input [23:0]CFG_BRAM_DATA;
  input [1:0]ADDRA;
  input \SEQUENCER_STATE_O_reg[8]_0 ;
  input \SEQUENCER_STATE_O_reg[0]_2 ;

  wire [0:0]A;
  wire [1:0]ADDRA;
  wire CAPTURE_O_reg_0;
  wire [23:0]CFG_BRAM_DATA;
  wire [23:0]CFG_BRAM_RD_DATA0;
  wire \CFG_BRAM_RD_DATA[23]_i_1_n_0 ;
  wire [23:0]\CFG_BRAM_RD_DATA_reg[23]_0 ;
  wire [7:0]CNT_CTRL;
  wire [3:0]COUNTER_EQ;
  wire [0:0]E;
  wire FLAG0_O010_out;
  wire FLAG0_O18_out;
  wire FLAG0_O_i_1_n_0;
  wire FLAG1_O0__0;
  wire FLAG1_O1__0;
  wire FLAG1_O_i_1_n_0;
  wire FLAG2_O0__0;
  wire FLAG2_O1__0;
  wire FLAG2_O_i_1_n_0;
  wire FLAG3_O0__0;
  wire FLAG3_O1__0;
  wire FLAG3_O_i_1_n_0;
  wire O_reg;
  wire [1:0]Q;
  wire [15:0]SEQUENCER_STATE_O;
  wire \SEQUENCER_STATE_O[10]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[11]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[12]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[13]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[14]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[15]_i_2_n_0 ;
  wire \SEQUENCER_STATE_O[7]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[8]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O[9]_i_1_n_0 ;
  wire \SEQUENCER_STATE_O_reg[0]_0 ;
  wire \SEQUENCER_STATE_O_reg[0]_1 ;
  wire \SEQUENCER_STATE_O_reg[0]_2 ;
  wire \SEQUENCER_STATE_O_reg[8]_0 ;
  wire [0:0]addra__0;
  wire basic_trigger;
  wire \bram_addr[6]_i_1_n_0 ;
  wire \bram_addr[6]_i_3_n_0 ;
  wire [6:0]bram_addr_reg;
  wire bram_en;
  wire bram_en_1;
  wire \bram_rd_addr[6]_i_2_n_0 ;
  wire [6:0]bram_rd_addr_reg;
  wire bram_rd_en;
  wire bram_rd_en_0;
  wire bram_rd_we;
  wire bram_we;
  wire capture_fsm;
  wire [1:0]cntcmpsel;
  wire \cntcmpsel_reg[1]_0 ;
  wire [3:0]current_state;
  wire \current_state_reg[0]_0 ;
  wire \current_state_reg[0]_1 ;
  wire [13:0]douta;
  wire [1:0]douta0;
  wire flag0_temp;
  wire flag1_temp;
  wire flag2_temp;
  wire flag3_temp;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_n_1;
  wire fsm_mem_data_reg_r1_0_63_0_2_n_2;
  wire fsm_mem_data_reg_r1_0_63_12_14_n_0;
  wire fsm_mem_data_reg_r1_0_63_12_14_n_1;
  wire fsm_mem_data_reg_r1_0_63_12_14_n_2;
  wire fsm_mem_data_reg_r1_0_63_15_17_n_0;
  wire fsm_mem_data_reg_r1_0_63_15_17_n_1;
  wire fsm_mem_data_reg_r1_0_63_15_17_n_2;
  wire fsm_mem_data_reg_r1_0_63_18_20_n_0;
  wire fsm_mem_data_reg_r1_0_63_18_20_n_1;
  wire fsm_mem_data_reg_r1_0_63_18_20_n_2;
  wire fsm_mem_data_reg_r1_0_63_21_23_n_0;
  wire fsm_mem_data_reg_r1_0_63_21_23_n_1;
  wire fsm_mem_data_reg_r1_0_63_21_23_n_2;
  wire fsm_mem_data_reg_r1_0_63_3_5_n_0;
  wire fsm_mem_data_reg_r1_0_63_3_5_n_1;
  wire fsm_mem_data_reg_r1_0_63_3_5_n_2;
  wire fsm_mem_data_reg_r1_0_63_6_8_n_0;
  wire fsm_mem_data_reg_r1_0_63_6_8_n_1;
  wire fsm_mem_data_reg_r1_0_63_6_8_n_2;
  wire fsm_mem_data_reg_r1_0_63_9_11_n_0;
  wire fsm_mem_data_reg_r1_0_63_9_11_n_1;
  wire fsm_mem_data_reg_r1_0_63_9_11_n_2;
  wire fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0;
  wire fsm_mem_data_reg_r1_64_127_0_2_n_0;
  wire fsm_mem_data_reg_r1_64_127_0_2_n_1;
  wire fsm_mem_data_reg_r1_64_127_0_2_n_2;
  wire fsm_mem_data_reg_r1_64_127_12_14_n_0;
  wire fsm_mem_data_reg_r1_64_127_12_14_n_1;
  wire fsm_mem_data_reg_r1_64_127_12_14_n_2;
  wire fsm_mem_data_reg_r1_64_127_15_17_n_0;
  wire fsm_mem_data_reg_r1_64_127_15_17_n_1;
  wire fsm_mem_data_reg_r1_64_127_15_17_n_2;
  wire fsm_mem_data_reg_r1_64_127_18_20_n_0;
  wire fsm_mem_data_reg_r1_64_127_18_20_n_1;
  wire fsm_mem_data_reg_r1_64_127_18_20_n_2;
  wire fsm_mem_data_reg_r1_64_127_21_23_n_0;
  wire fsm_mem_data_reg_r1_64_127_21_23_n_1;
  wire fsm_mem_data_reg_r1_64_127_21_23_n_2;
  wire fsm_mem_data_reg_r1_64_127_3_5_n_0;
  wire fsm_mem_data_reg_r1_64_127_3_5_n_1;
  wire fsm_mem_data_reg_r1_64_127_3_5_n_2;
  wire fsm_mem_data_reg_r1_64_127_6_8_n_0;
  wire fsm_mem_data_reg_r1_64_127_6_8_n_1;
  wire fsm_mem_data_reg_r1_64_127_6_8_n_2;
  wire fsm_mem_data_reg_r1_64_127_9_11_n_0;
  wire fsm_mem_data_reg_r1_64_127_9_11_n_1;
  wire fsm_mem_data_reg_r1_64_127_9_11_n_2;
  wire fsm_mem_data_reg_r2_0_63_0_2_n_0;
  wire fsm_mem_data_reg_r2_0_63_0_2_n_1;
  wire fsm_mem_data_reg_r2_0_63_0_2_n_2;
  wire fsm_mem_data_reg_r2_0_63_12_14_n_0;
  wire fsm_mem_data_reg_r2_0_63_12_14_n_1;
  wire fsm_mem_data_reg_r2_0_63_12_14_n_2;
  wire fsm_mem_data_reg_r2_0_63_15_17_n_0;
  wire fsm_mem_data_reg_r2_0_63_15_17_n_1;
  wire fsm_mem_data_reg_r2_0_63_15_17_n_2;
  wire fsm_mem_data_reg_r2_0_63_18_20_n_0;
  wire fsm_mem_data_reg_r2_0_63_18_20_n_1;
  wire fsm_mem_data_reg_r2_0_63_18_20_n_2;
  wire fsm_mem_data_reg_r2_0_63_21_23_n_0;
  wire fsm_mem_data_reg_r2_0_63_21_23_n_1;
  wire fsm_mem_data_reg_r2_0_63_21_23_n_2;
  wire fsm_mem_data_reg_r2_0_63_3_5_n_0;
  wire fsm_mem_data_reg_r2_0_63_3_5_n_1;
  wire fsm_mem_data_reg_r2_0_63_3_5_n_2;
  wire fsm_mem_data_reg_r2_0_63_6_8_n_0;
  wire fsm_mem_data_reg_r2_0_63_6_8_n_1;
  wire fsm_mem_data_reg_r2_0_63_6_8_n_2;
  wire fsm_mem_data_reg_r2_0_63_9_11_n_0;
  wire fsm_mem_data_reg_r2_0_63_9_11_n_1;
  wire fsm_mem_data_reg_r2_0_63_9_11_n_2;
  wire fsm_mem_data_reg_r2_64_127_0_2_n_0;
  wire fsm_mem_data_reg_r2_64_127_0_2_n_1;
  wire fsm_mem_data_reg_r2_64_127_0_2_n_2;
  wire fsm_mem_data_reg_r2_64_127_12_14_n_0;
  wire fsm_mem_data_reg_r2_64_127_12_14_n_1;
  wire fsm_mem_data_reg_r2_64_127_12_14_n_2;
  wire fsm_mem_data_reg_r2_64_127_15_17_n_0;
  wire fsm_mem_data_reg_r2_64_127_15_17_n_1;
  wire fsm_mem_data_reg_r2_64_127_15_17_n_2;
  wire fsm_mem_data_reg_r2_64_127_18_20_n_0;
  wire fsm_mem_data_reg_r2_64_127_18_20_n_1;
  wire fsm_mem_data_reg_r2_64_127_18_20_n_2;
  wire fsm_mem_data_reg_r2_64_127_21_23_n_0;
  wire fsm_mem_data_reg_r2_64_127_21_23_n_1;
  wire fsm_mem_data_reg_r2_64_127_21_23_n_2;
  wire fsm_mem_data_reg_r2_64_127_3_5_n_0;
  wire fsm_mem_data_reg_r2_64_127_3_5_n_1;
  wire fsm_mem_data_reg_r2_64_127_3_5_n_2;
  wire fsm_mem_data_reg_r2_64_127_6_8_n_0;
  wire fsm_mem_data_reg_r2_64_127_6_8_n_1;
  wire fsm_mem_data_reg_r2_64_127_6_8_n_2;
  wire fsm_mem_data_reg_r2_64_127_9_11_n_0;
  wire fsm_mem_data_reg_r2_64_127_9_11_n_1;
  wire fsm_mem_data_reg_r2_64_127_9_11_n_2;
  wire [0:0]out;
  wire [6:0]p_0_in;
  wire [6:0]p_0_in__0;
  wire toggle_rd;
  wire trig_out_fsm;
  wire trigger_reg_0;
  wire u_wcnt_lcmp_q;
  wire NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    CAPTURE_O_i_2
       (.I0(fsm_mem_data_reg_r1_64_127_18_20_n_0),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_18_20_n_0),
        .O(douta0[0]));
  FDRE CAPTURE_O_reg
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(1'b1),
        .D(CAPTURE_O_reg_0),
        .Q(capture_fsm),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[0]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_0_2_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_0_2_n_0),
        .O(CFG_BRAM_RD_DATA0[0]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[10]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_9_11_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_9_11_n_1),
        .O(CFG_BRAM_RD_DATA0[10]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[11]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_9_11_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_9_11_n_2),
        .O(CFG_BRAM_RD_DATA0[11]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[12]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_12_14_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_12_14_n_0),
        .O(CFG_BRAM_RD_DATA0[12]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[13]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_12_14_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_12_14_n_1),
        .O(CFG_BRAM_RD_DATA0[13]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[14]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_12_14_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_12_14_n_2),
        .O(CFG_BRAM_RD_DATA0[14]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[15]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_15_17_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_15_17_n_0),
        .O(CFG_BRAM_RD_DATA0[15]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[16]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_15_17_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_15_17_n_1),
        .O(CFG_BRAM_RD_DATA0[16]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[17]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_15_17_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_15_17_n_2),
        .O(CFG_BRAM_RD_DATA0[17]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[18]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_18_20_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_18_20_n_0),
        .O(CFG_BRAM_RD_DATA0[18]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[19]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_18_20_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_18_20_n_1),
        .O(CFG_BRAM_RD_DATA0[19]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[1]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_0_2_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_0_2_n_1),
        .O(CFG_BRAM_RD_DATA0[1]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[20]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_18_20_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_18_20_n_2),
        .O(CFG_BRAM_RD_DATA0[20]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[21]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_21_23_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_21_23_n_0),
        .O(CFG_BRAM_RD_DATA0[21]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[22]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_21_23_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_21_23_n_1),
        .O(CFG_BRAM_RD_DATA0[22]));
  LUT2 #(
    .INIT(4'h2)) 
    \CFG_BRAM_RD_DATA[23]_i_1 
       (.I0(bram_rd_en_0),
        .I1(bram_rd_we),
        .O(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[23]_i_2 
       (.I0(fsm_mem_data_reg_r2_64_127_21_23_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_21_23_n_2),
        .O(CFG_BRAM_RD_DATA0[23]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[2]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_0_2_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_0_2_n_2),
        .O(CFG_BRAM_RD_DATA0[2]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[3]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_3_5_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_3_5_n_0),
        .O(CFG_BRAM_RD_DATA0[3]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[4]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_3_5_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_3_5_n_1),
        .O(CFG_BRAM_RD_DATA0[4]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[5]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_3_5_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_3_5_n_2),
        .O(CFG_BRAM_RD_DATA0[5]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[6]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_6_8_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_6_8_n_0),
        .O(CFG_BRAM_RD_DATA0[6]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[7]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_6_8_n_1),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_6_8_n_1),
        .O(CFG_BRAM_RD_DATA0[7]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[8]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_6_8_n_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_6_8_n_2),
        .O(CFG_BRAM_RD_DATA0[8]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_BRAM_RD_DATA[9]_i_1 
       (.I0(fsm_mem_data_reg_r2_64_127_9_11_n_0),
        .I1(bram_rd_addr_reg[6]),
        .I2(fsm_mem_data_reg_r2_0_63_9_11_n_0),
        .O(CFG_BRAM_RD_DATA0[9]));
  FDRE \CFG_BRAM_RD_DATA_reg[0] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[0]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [0]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[10] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[10]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [10]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[11] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[11]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [11]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[12] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[12]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [12]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[13] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[13]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [13]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[14] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[14]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [14]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[15] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[15]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [15]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[16] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[16]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [16]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[17] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[17]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [17]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[18] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[18]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [18]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[19] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[19]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [19]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[1] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[1]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [1]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[20] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[20]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [20]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[21] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[21]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [21]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[22] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[22]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [22]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[23] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[23]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [23]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[2] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[2]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [2]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[3] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[3]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [3]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[4] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[4]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [4]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[5] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[5]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [5]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[6] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[6]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [6]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[7] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[7]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [7]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[8] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[8]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [8]),
        .R(1'b0));
  FDRE \CFG_BRAM_RD_DATA_reg[9] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(CFG_BRAM_RD_DATA0[9]),
        .Q(\CFG_BRAM_RD_DATA_reg[23]_0 [9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF4500)) 
    FLAG0_O_i_1
       (.I0(FLAG0_O18_out),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(flag0_temp),
        .I4(FLAG0_O010_out),
        .O(FLAG0_O_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG0_O_i_2
       (.I0(fsm_mem_data_reg_r1_64_127_18_20_n_2),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_18_20_n_2),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG0_O18_out));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG0_O_i_3
       (.I0(fsm_mem_data_reg_r1_64_127_12_14_n_2),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_12_14_n_2),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG0_O010_out));
  FDRE FLAG0_O_reg
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(1'b1),
        .D(FLAG0_O_i_1_n_0),
        .Q(flag0_temp),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF4500)) 
    FLAG1_O_i_1
       (.I0(FLAG1_O1__0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(flag1_temp),
        .I4(FLAG1_O0__0),
        .O(FLAG1_O_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG1_O_i_2
       (.I0(fsm_mem_data_reg_r1_64_127_21_23_n_0),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_21_23_n_0),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG1_O1__0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG1_O_i_3
       (.I0(fsm_mem_data_reg_r1_64_127_15_17_n_0),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_15_17_n_0),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG1_O0__0));
  FDRE FLAG1_O_reg
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(1'b1),
        .D(FLAG1_O_i_1_n_0),
        .Q(flag1_temp),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF4500)) 
    FLAG2_O_i_1
       (.I0(FLAG2_O1__0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(flag2_temp),
        .I4(FLAG2_O0__0),
        .O(FLAG2_O_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG2_O_i_2
       (.I0(fsm_mem_data_reg_r1_64_127_21_23_n_1),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_21_23_n_1),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG2_O1__0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG2_O_i_3
       (.I0(fsm_mem_data_reg_r1_64_127_15_17_n_1),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_15_17_n_1),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG2_O0__0));
  FDRE FLAG2_O_reg
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(1'b1),
        .D(FLAG2_O_i_1_n_0),
        .Q(flag2_temp),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF4500)) 
    FLAG3_O_i_1
       (.I0(FLAG3_O1__0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(flag3_temp),
        .I4(FLAG3_O0__0),
        .O(FLAG3_O_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG3_O_i_2
       (.I0(fsm_mem_data_reg_r1_64_127_21_23_n_2),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_21_23_n_2),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG3_O1__0));
  LUT6 #(
    .INIT(64'h0000B80000000000)) 
    FLAG3_O_i_3
       (.I0(fsm_mem_data_reg_r1_64_127_15_17_n_2),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_15_17_n_2),
        .I3(\current_state_reg[0]_0 ),
        .I4(\SEQUENCER_STATE_O_reg[0]_1 ),
        .I5(O_reg),
        .O(FLAG3_O0__0));
  FDRE FLAG3_O_reg
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(1'b1),
        .D(FLAG3_O_i_1_n_0),
        .Q(flag3_temp),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[0].U_COUNTER_i_2 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_3_5_n_2),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_3_5_n_2),
        .O(CNT_CTRL[1]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[0].U_COUNTER_i_3 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_3_5_n_1),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_3_5_n_1),
        .O(CNT_CTRL[0]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[1].U_COUNTER_i_1 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_6_8_n_1),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_6_8_n_1),
        .O(CNT_CTRL[3]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[1].U_COUNTER_i_2 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_6_8_n_0),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_6_8_n_0),
        .O(CNT_CTRL[2]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[2].U_COUNTER_i_1 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_9_11_n_0),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_9_11_n_0),
        .O(CNT_CTRL[5]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[2].U_COUNTER_i_2 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_6_8_n_2),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_6_8_n_2),
        .O(CNT_CTRL[4]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[3].U_COUNTER_i_1 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_9_11_n_2),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_9_11_n_2),
        .O(CNT_CTRL[7]));
  LUT4 #(
    .INIT(16'hA808)) 
    \G_COUNTER[3].U_COUNTER_i_2 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_9_11_n_1),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_9_11_n_1),
        .O(CNT_CTRL[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \I_YESLUT6.U_SRL32_D_i_2 
       (.I0(trig_out_fsm),
        .I1(u_wcnt_lcmp_q),
        .I2(basic_trigger),
        .O(A));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \SEQUENCER_STATE_O[10]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .O(\SEQUENCER_STATE_O[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \SEQUENCER_STATE_O[11]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .O(\SEQUENCER_STATE_O[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \SEQUENCER_STATE_O[12]_i_1 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[1]),
        .O(\SEQUENCER_STATE_O[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \SEQUENCER_STATE_O[13]_i_1 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[0]),
        .O(\SEQUENCER_STATE_O[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \SEQUENCER_STATE_O[14]_i_1 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[1]),
        .O(\SEQUENCER_STATE_O[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \SEQUENCER_STATE_O[15]_i_2 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[1]),
        .O(\SEQUENCER_STATE_O[15]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \SEQUENCER_STATE_O[7]_i_1 
       (.I0(current_state[3]),
        .I1(\SEQUENCER_STATE_O_reg[0]_2 ),
        .I2(\SEQUENCER_STATE_O_reg[0]_1 ),
        .O(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \SEQUENCER_STATE_O[8]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .O(\SEQUENCER_STATE_O[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \SEQUENCER_STATE_O[9]_i_1 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .O(\SEQUENCER_STATE_O[9]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[0] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[8]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[0]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[10] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[10]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[10]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[11] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[11]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[11]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[12] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[12]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[12]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[13] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[13]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[13]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[14] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[14]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[14]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[15] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[15]_i_2_n_0 ),
        .Q(SEQUENCER_STATE_O[15]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[1] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[9]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[1]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[2] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[10]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[2]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[3] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[11]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[3]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[4] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[12]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[4]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[5] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[13]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[5]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[6] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[14]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[6]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[7] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[15]_i_2_n_0 ),
        .Q(SEQUENCER_STATE_O[7]),
        .R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
  FDRE \SEQUENCER_STATE_O_reg[8] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[8]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[8]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  FDRE \SEQUENCER_STATE_O_reg[9] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(\SEQUENCER_STATE_O[9]_i_1_n_0 ),
        .Q(SEQUENCER_STATE_O[9]),
        .R(\SEQUENCER_STATE_O_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    addra
       (.I0(COUNTER_EQ[1]),
        .I1(COUNTER_EQ[0]),
        .I2(COUNTER_EQ[3]),
        .I3(cntcmpsel[1]),
        .I4(cntcmpsel[0]),
        .I5(COUNTER_EQ[2]),
        .O(addra__0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \bram_addr[0]_i_1 
       (.I0(bram_addr_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \bram_addr[1]_i_1 
       (.I0(bram_addr_reg[0]),
        .I1(bram_addr_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \bram_addr[2]_i_1 
       (.I0(bram_addr_reg[0]),
        .I1(bram_addr_reg[1]),
        .I2(bram_addr_reg[2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \bram_addr[3]_i_1 
       (.I0(bram_addr_reg[1]),
        .I1(bram_addr_reg[0]),
        .I2(bram_addr_reg[2]),
        .I3(bram_addr_reg[3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \bram_addr[4]_i_1 
       (.I0(bram_addr_reg[2]),
        .I1(bram_addr_reg[0]),
        .I2(bram_addr_reg[1]),
        .I3(bram_addr_reg[3]),
        .I4(bram_addr_reg[4]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \bram_addr[5]_i_1 
       (.I0(bram_addr_reg[3]),
        .I1(bram_addr_reg[1]),
        .I2(bram_addr_reg[0]),
        .I3(bram_addr_reg[2]),
        .I4(bram_addr_reg[4]),
        .I5(bram_addr_reg[5]),
        .O(p_0_in__0[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \bram_addr[6]_i_1 
       (.I0(bram_en_1),
        .I1(bram_we),
        .O(\bram_addr[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \bram_addr[6]_i_2 
       (.I0(\bram_addr[6]_i_3_n_0 ),
        .I1(bram_addr_reg[5]),
        .I2(bram_addr_reg[6]),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \bram_addr[6]_i_3 
       (.I0(bram_addr_reg[4]),
        .I1(bram_addr_reg[2]),
        .I2(bram_addr_reg[0]),
        .I3(bram_addr_reg[1]),
        .I4(bram_addr_reg[3]),
        .O(\bram_addr[6]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[0] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[0]),
        .Q(bram_addr_reg[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[1] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[1]),
        .Q(bram_addr_reg[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[2] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[2]),
        .Q(bram_addr_reg[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[3] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[3]),
        .Q(bram_addr_reg[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[4] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[4]),
        .Q(bram_addr_reg[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[5] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[5]),
        .Q(bram_addr_reg[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_addr_reg[6] 
       (.C(out),
        .CE(\bram_addr[6]_i_1_n_0 ),
        .D(p_0_in__0[6]),
        .Q(bram_addr_reg[6]),
        .R(1'b0));
  FDRE bram_en_reg
       (.C(out),
        .CE(1'b1),
        .D(bram_en),
        .Q(bram_en_1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \bram_rd_addr[0]_i_1 
       (.I0(bram_rd_addr_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \bram_rd_addr[1]_i_1 
       (.I0(bram_rd_addr_reg[0]),
        .I1(bram_rd_addr_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \bram_rd_addr[2]_i_1 
       (.I0(bram_rd_addr_reg[0]),
        .I1(bram_rd_addr_reg[1]),
        .I2(bram_rd_addr_reg[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \bram_rd_addr[3]_i_1 
       (.I0(bram_rd_addr_reg[1]),
        .I1(bram_rd_addr_reg[0]),
        .I2(bram_rd_addr_reg[2]),
        .I3(bram_rd_addr_reg[3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \bram_rd_addr[4]_i_1 
       (.I0(bram_rd_addr_reg[2]),
        .I1(bram_rd_addr_reg[0]),
        .I2(bram_rd_addr_reg[1]),
        .I3(bram_rd_addr_reg[3]),
        .I4(bram_rd_addr_reg[4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \bram_rd_addr[5]_i_1 
       (.I0(bram_rd_addr_reg[3]),
        .I1(bram_rd_addr_reg[1]),
        .I2(bram_rd_addr_reg[0]),
        .I3(bram_rd_addr_reg[2]),
        .I4(bram_rd_addr_reg[4]),
        .I5(bram_rd_addr_reg[5]),
        .O(p_0_in[5]));
  LUT3 #(
    .INIT(8'h78)) 
    \bram_rd_addr[6]_i_1 
       (.I0(\bram_rd_addr[6]_i_2_n_0 ),
        .I1(bram_rd_addr_reg[5]),
        .I2(bram_rd_addr_reg[6]),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \bram_rd_addr[6]_i_2 
       (.I0(bram_rd_addr_reg[4]),
        .I1(bram_rd_addr_reg[2]),
        .I2(bram_rd_addr_reg[0]),
        .I3(bram_rd_addr_reg[1]),
        .I4(bram_rd_addr_reg[3]),
        .O(\bram_rd_addr[6]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[0] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[0]),
        .Q(bram_rd_addr_reg[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[1] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[1]),
        .Q(bram_rd_addr_reg[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[2] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[2]),
        .Q(bram_rd_addr_reg[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[3] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[3]),
        .Q(bram_rd_addr_reg[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[4] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[4]),
        .Q(bram_rd_addr_reg[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[5] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[5]),
        .Q(bram_rd_addr_reg[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bram_rd_addr_reg[6] 
       (.C(out),
        .CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
        .D(p_0_in[6]),
        .Q(bram_rd_addr_reg[6]),
        .R(1'b0));
  FDRE bram_rd_en_reg
       (.C(out),
        .CE(1'b1),
        .D(bram_rd_en),
        .Q(bram_rd_en_0),
        .R(1'b0));
  FDRE bram_rd_we_reg
       (.C(out),
        .CE(1'b1),
        .D(toggle_rd),
        .Q(bram_rd_we),
        .R(1'b0));
  FDRE bram_we_reg
       (.C(out),
        .CE(1'b1),
        .D(E),
        .Q(bram_we),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hA808)) 
    \cntcmpsel[0]_i_1 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_12_14_n_0),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_12_14_n_0),
        .O(douta[12]));
  LUT4 #(
    .INIT(16'hA808)) 
    \cntcmpsel[1]_i_3 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_12_14_n_1),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_12_14_n_1),
        .O(douta[13]));
  FDRE \cntcmpsel_reg[0] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(douta[12]),
        .Q(cntcmpsel[0]),
        .R(\current_state_reg[0]_1 ));
  FDRE \cntcmpsel_reg[1] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(douta[13]),
        .Q(cntcmpsel[1]),
        .R(\current_state_reg[0]_1 ));
  LUT4 #(
    .INIT(16'hA808)) 
    \current_state[0]_i_1__49 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_n_0),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_0_2_n_0),
        .O(douta[0]));
  LUT4 #(
    .INIT(16'hA808)) 
    \current_state[1]_i_1__49 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_n_1),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_0_2_n_1),
        .O(douta[1]));
  LUT4 #(
    .INIT(16'hA808)) 
    \current_state[2]_i_1__49 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_n_2),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_0_2_n_2),
        .O(douta[2]));
  LUT4 #(
    .INIT(16'hA808)) 
    \current_state[3]_i_1__49 
       (.I0(\current_state_reg[0]_0 ),
        .I1(fsm_mem_data_reg_r1_0_63_3_5_n_0),
        .I2(current_state[3]),
        .I3(fsm_mem_data_reg_r1_64_127_3_5_n_0),
        .O(douta[3]));
  FDRE \current_state_reg[0] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(douta[0]),
        .Q(current_state[0]),
        .R(\current_state_reg[0]_1 ));
  FDRE \current_state_reg[1] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(douta[1]),
        .Q(current_state[1]),
        .R(\current_state_reg[0]_1 ));
  FDRE \current_state_reg[2] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(douta[2]),
        .Q(current_state[2]),
        .R(\current_state_reg[0]_1 ));
  FDRE \current_state_reg[3] 
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(\cntcmpsel_reg[1]_0 ),
        .D(douta[3]),
        .Q(current_state[3]),
        .R(\current_state_reg[0]_1 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "2" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_0_2
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_0_2_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_0_2_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_0_2_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  LUT3 #(
    .INIT(8'h08)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_1
       (.I0(bram_we),
        .I1(bram_en_1),
        .I2(bram_addr_reg[6]),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "14" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_12_14
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_12_14_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_12_14_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_12_14_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "15" *) 
  (* ram_slice_end = "17" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_15_17
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_15_17_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_15_17_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_15_17_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "20" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_18_20
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_18_20_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_18_20_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_18_20_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "21" *) 
  (* ram_slice_end = "23" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_21_23
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_21_23_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_21_23_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_21_23_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "3" *) 
  (* ram_slice_end = "5" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_3_5
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_3_5_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_3_5_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_3_5_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "8" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_6_8
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_6_8_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_6_8_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_6_8_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "9" *) 
  (* ram_slice_end = "11" *) 
  RAM64M fsm_mem_data_reg_r1_0_63_9_11
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_0_63_9_11_n_0),
        .DOB(fsm_mem_data_reg_r1_0_63_9_11_n_1),
        .DOC(fsm_mem_data_reg_r1_0_63_9_11_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "2" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_0_2
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_0_2_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_0_2_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_0_2_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    fsm_mem_data_reg_r1_64_127_0_2_i_1
       (.I0(bram_we),
        .I1(bram_en_1),
        .I2(bram_addr_reg[6]),
        .O(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "14" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_12_14
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_12_14_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_12_14_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_12_14_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "15" *) 
  (* ram_slice_end = "17" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_15_17
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_15_17_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_15_17_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_15_17_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "20" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_18_20
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_18_20_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_18_20_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_18_20_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "21" *) 
  (* ram_slice_end = "23" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_21_23
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_21_23_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_21_23_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_21_23_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "3" *) 
  (* ram_slice_end = "5" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_3_5
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_3_5_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_3_5_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_3_5_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "8" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_6_8
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_6_8_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_6_8_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_6_8_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "9" *) 
  (* ram_slice_end = "11" *) 
  RAM64M fsm_mem_data_reg_r1_64_127_9_11
       (.ADDRA({current_state[2:0],ADDRA,addra__0}),
        .ADDRB({current_state[2:0],ADDRA,addra__0}),
        .ADDRC({current_state[2:0],ADDRA,addra__0}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r1_64_127_9_11_n_0),
        .DOB(fsm_mem_data_reg_r1_64_127_9_11_n_1),
        .DOC(fsm_mem_data_reg_r1_64_127_9_11_n_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "2" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_0_2
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_0_2_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_0_2_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_0_2_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "14" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_12_14
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_12_14_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_12_14_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_12_14_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "15" *) 
  (* ram_slice_end = "17" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_15_17
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_15_17_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_15_17_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_15_17_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "20" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_18_20
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_18_20_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_18_20_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_18_20_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "21" *) 
  (* ram_slice_end = "23" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_21_23
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_21_23_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_21_23_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_21_23_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "3" *) 
  (* ram_slice_end = "5" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_3_5
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_3_5_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_3_5_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_3_5_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "8" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_6_8
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_6_8_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_6_8_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_6_8_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "63" *) 
  (* ram_slice_begin = "9" *) 
  (* ram_slice_end = "11" *) 
  RAM64M fsm_mem_data_reg_r2_0_63_9_11
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_0_63_9_11_n_0),
        .DOB(fsm_mem_data_reg_r2_0_63_9_11_n_1),
        .DOC(fsm_mem_data_reg_r2_0_63_9_11_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "2" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_0_2
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_0_2_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_0_2_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_0_2_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "14" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_12_14
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_12_14_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_12_14_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_12_14_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "15" *) 
  (* ram_slice_end = "17" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_15_17
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_15_17_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_15_17_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_15_17_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "20" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_18_20
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_18_20_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_18_20_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_18_20_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "21" *) 
  (* ram_slice_end = "23" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_21_23
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_21_23_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_21_23_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_21_23_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "3" *) 
  (* ram_slice_end = "5" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_3_5
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_3_5_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_3_5_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_3_5_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "8" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_6_8
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_6_8_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_6_8_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_6_8_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* ram_addr_begin = "64" *) 
  (* ram_addr_end = "127" *) 
  (* ram_slice_begin = "9" *) 
  (* ram_slice_end = "11" *) 
  RAM64M fsm_mem_data_reg_r2_64_127_9_11
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(fsm_mem_data_reg_r2_64_127_9_11_n_0),
        .DOB(fsm_mem_data_reg_r2_64_127_9_11_n_1),
        .DOC(fsm_mem_data_reg_r2_64_127_9_11_n_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED),
        .WCLK(out),
        .WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    trigger_i_2
       (.I0(fsm_mem_data_reg_r1_64_127_18_20_n_1),
        .I1(current_state[3]),
        .I2(fsm_mem_data_reg_r1_0_63_18_20_n_1),
        .O(douta0[1]));
  FDRE trigger_reg
       (.C(\SEQUENCER_STATE_O_reg[0]_0 ),
        .CE(1'b1),
        .D(trigger_reg_0),
        .Q(trig_out_fsm),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_addrgen
   (u_wcnt_lcmp_q,
    u_scnt_cmp_q,
    wcnt_hcmp,
    \i_intcap.CAP_ADDR_O_reg[9]_0 ,
    CAP_WR_EN_O_reg_0,
    SR,
    DOUT_O,
    shift_en_reg,
    shift_en_reg_0,
    SRL_Q_O,
    \captured_samples_reg[9]_0 ,
    E,
    A,
    out,
    scnt_cmp_temp,
    \probeDelay1_reg[0] ,
    wcnt_lcmp_temp,
    wcnt_hcmp_temp,
    in0,
    Q,
    \captured_samples_reg[0]_0 );
  output [0:0]u_wcnt_lcmp_q;
  output [0:0]u_scnt_cmp_q;
  output wcnt_hcmp;
  output [9:0]\i_intcap.CAP_ADDR_O_reg[9]_0 ;
  output CAP_WR_EN_O_reg_0;
  output [0:0]SR;
  output DOUT_O;
  output shift_en_reg;
  output shift_en_reg_0;
  output SRL_Q_O;
  output [9:0]\captured_samples_reg[9]_0 ;
  input [0:0]E;
  input [3:0]A;
  input [0:0]out;
  input scnt_cmp_temp;
  input \probeDelay1_reg[0] ;
  input wcnt_lcmp_temp;
  input wcnt_hcmp_temp;
  input [0:0]in0;
  input [0:0]Q;
  input [0:0]\captured_samples_reg[0]_0 ;

  wire [3:0]A;
  (* async_reg = "true" *) wire CAP_WR_EN_O_reg_0;
  wire DOUT_O;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire SRL_Q_O;
  wire [9:0]cap_addr_next;
  wire [0:0]\captured_samples_reg[0]_0 ;
  wire [9:0]\captured_samples_reg[9]_0 ;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [16:1]cfg_data_vec;
  (* async_reg = "true" *) wire [32:0]cfg_data_vec_sync1;
  (* async_reg = "true" *) wire [32:0]cfg_data_vec_sync2;
  wire cmp_reset;
  (* async_reg = "true" *) wire [9:0]\i_intcap.CAP_ADDR_O_reg[9]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [9:0]icap_addr;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire icap_wr_en;
  wire [0:0]in0;
  wire n_0_0;
  wire n_0_1;
  wire n_0_10;
  wire n_0_11;
  wire n_0_12;
  wire n_0_13;
  wire n_0_14;
  wire n_0_15;
  wire n_0_2;
  wire n_0_3;
  wire n_0_4;
  wire n_0_5;
  wire n_0_6;
  wire n_0_7;
  wire n_0_8;
  wire n_0_9;
  wire [0:0]out;
  wire \probeDelay1_reg[0] ;
  wire scnt_ce;
  wire scnt_cmp_temp;
  wire shift_en_reg;
  wire shift_en_reg_0;
  wire [0:0]u_scnt_cmp_q;
  wire [0:0]u_wcnt_lcmp_q;
  wire [9:0]wcnt;
  wire wcnt_hcmp;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp_temp;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE CAP_WR_EN_O_reg
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_wr_en),
        .Q(CAP_WR_EN_O_reg_0),
        .R(Q));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6 U_CMPRESET
       (.A({u_wcnt_lcmp_q,A}),
        .E(E),
        .cfg_data_0(cfg_data_0),
        .cfg_data_1(cfg_data_1),
        .cmp_reset(cmp_reset),
        .out(out),
        .u_wcnt_hcmp_q(u_scnt_cmp_q));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[0] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[0]),
        .Q(\captured_samples_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[1] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[1]),
        .Q(\captured_samples_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[2] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[2]),
        .Q(\captured_samples_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[3] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[3]),
        .Q(\captured_samples_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[4] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[4]),
        .Q(\captured_samples_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[5] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[5]),
        .Q(\captured_samples_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[6] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[6]),
        .Q(\captured_samples_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[7] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[7]),
        .Q(\captured_samples_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[8] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[8]),
        .Q(\captured_samples_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \captured_samples_reg[9] 
       (.C(\probeDelay1_reg[0] ),
        .CE(\captured_samples_reg[0]_0 ),
        .D(wcnt[9]),
        .Q(\captured_samples_reg[9]_0 [9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[0] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(in0),
        .Q(cfg_data_vec_sync1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[10] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[10]),
        .Q(cfg_data_vec_sync1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[11] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[11]),
        .Q(cfg_data_vec_sync1[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[12] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[12]),
        .Q(cfg_data_vec_sync1[12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[13] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[13]),
        .Q(cfg_data_vec_sync1[13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[14] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[14]),
        .Q(cfg_data_vec_sync1[14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[15] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[15]),
        .Q(cfg_data_vec_sync1[15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[16] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[16]),
        .Q(cfg_data_vec_sync1[16]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[17] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_15),
        .Q(cfg_data_vec_sync1[17]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[18] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_14),
        .Q(cfg_data_vec_sync1[18]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[19] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_13),
        .Q(cfg_data_vec_sync1[19]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[1] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[1]),
        .Q(cfg_data_vec_sync1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[20] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_12),
        .Q(cfg_data_vec_sync1[20]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[21] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_11),
        .Q(cfg_data_vec_sync1[21]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[22] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_10),
        .Q(cfg_data_vec_sync1[22]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[23] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_9),
        .Q(cfg_data_vec_sync1[23]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[24] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_8),
        .Q(cfg_data_vec_sync1[24]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[25] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_7),
        .Q(cfg_data_vec_sync1[25]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[26] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_6),
        .Q(cfg_data_vec_sync1[26]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[27] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_5),
        .Q(cfg_data_vec_sync1[27]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[28] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_4),
        .Q(cfg_data_vec_sync1[28]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[29] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_3),
        .Q(cfg_data_vec_sync1[29]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[2] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[2]),
        .Q(cfg_data_vec_sync1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[30] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_2),
        .Q(cfg_data_vec_sync1[30]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[31] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_1),
        .Q(cfg_data_vec_sync1[31]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[32] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_0),
        .Q(cfg_data_vec_sync1[32]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[3] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[3]),
        .Q(cfg_data_vec_sync1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[4] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[4]),
        .Q(cfg_data_vec_sync1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[5] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[5]),
        .Q(cfg_data_vec_sync1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[6] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[6]),
        .Q(cfg_data_vec_sync1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[7] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[7]),
        .Q(cfg_data_vec_sync1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[8] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[8]),
        .Q(cfg_data_vec_sync1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync1_reg[9] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec[9]),
        .Q(cfg_data_vec_sync1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[0] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[0]),
        .Q(cfg_data_vec_sync2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[10] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[10]),
        .Q(cfg_data_vec_sync2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[11] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[11]),
        .Q(cfg_data_vec_sync2[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[12] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[12]),
        .Q(cfg_data_vec_sync2[12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[13] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[13]),
        .Q(cfg_data_vec_sync2[13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[14] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[14]),
        .Q(cfg_data_vec_sync2[14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[15] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[15]),
        .Q(cfg_data_vec_sync2[15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[16] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[16]),
        .Q(cfg_data_vec_sync2[16]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[17] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[17]),
        .Q(cfg_data_vec_sync2[17]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[18] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[18]),
        .Q(cfg_data_vec_sync2[18]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[19] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[19]),
        .Q(cfg_data_vec_sync2[19]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[1] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[1]),
        .Q(cfg_data_vec_sync2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[20] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[20]),
        .Q(cfg_data_vec_sync2[20]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[21] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[21]),
        .Q(cfg_data_vec_sync2[21]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[22] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[22]),
        .Q(cfg_data_vec_sync2[22]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[23] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[23]),
        .Q(cfg_data_vec_sync2[23]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[24] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[24]),
        .Q(cfg_data_vec_sync2[24]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[25] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[25]),
        .Q(cfg_data_vec_sync2[25]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[26] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[26]),
        .Q(cfg_data_vec_sync2[26]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[27] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[27]),
        .Q(cfg_data_vec_sync2[27]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[28] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[28]),
        .Q(cfg_data_vec_sync2[28]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[29] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[29]),
        .Q(cfg_data_vec_sync2[29]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[2] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[2]),
        .Q(cfg_data_vec_sync2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[30] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[30]),
        .Q(cfg_data_vec_sync2[30]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[31] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[31]),
        .Q(cfg_data_vec_sync2[31]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[32] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[32]),
        .Q(cfg_data_vec_sync2[32]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[3] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[3]),
        .Q(cfg_data_vec_sync2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[4] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[4]),
        .Q(cfg_data_vec_sync2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[5] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[5]),
        .Q(cfg_data_vec_sync2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[6] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[6]),
        .Q(cfg_data_vec_sync2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[7] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[7]),
        .Q(cfg_data_vec_sync2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[8] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[8]),
        .Q(cfg_data_vec_sync2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \cfg_data_vec_sync2_reg[9] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cfg_data_vec_sync1[9]),
        .Q(cfg_data_vec_sync2[9]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(n_0_0));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(n_0_1));
  LUT1 #(
    .INIT(2'h2)) 
    i_10
       (.I0(1'b0),
        .O(n_0_10));
  LUT1 #(
    .INIT(2'h2)) 
    i_11
       (.I0(1'b0),
        .O(n_0_11));
  LUT1 #(
    .INIT(2'h2)) 
    i_12
       (.I0(1'b0),
        .O(n_0_12));
  LUT1 #(
    .INIT(2'h2)) 
    i_13
       (.I0(1'b0),
        .O(n_0_13));
  LUT1 #(
    .INIT(2'h2)) 
    i_14
       (.I0(1'b0),
        .O(n_0_14));
  LUT1 #(
    .INIT(2'h2)) 
    i_15
       (.I0(1'b0),
        .O(n_0_15));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(n_0_2));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(n_0_3));
  LUT1 #(
    .INIT(2'h2)) 
    i_4
       (.I0(1'b0),
        .O(n_0_4));
  LUT1 #(
    .INIT(2'h2)) 
    i_5
       (.I0(1'b0),
        .O(n_0_5));
  LUT1 #(
    .INIT(2'h2)) 
    i_6
       (.I0(1'b0),
        .O(n_0_6));
  LUT1 #(
    .INIT(2'h2)) 
    i_7
       (.I0(1'b0),
        .O(n_0_7));
  LUT1 #(
    .INIT(2'h2)) 
    i_8
       (.I0(1'b0),
        .O(n_0_8));
  LUT1 #(
    .INIT(2'h2)) 
    i_9
       (.I0(1'b0),
        .O(n_0_9));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[0] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[0]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [0]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[1] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[1]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [1]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[2] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[2]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [2]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[3] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[3]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [3]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[4] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[4]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [4]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[5] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[5]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [5]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[6] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[6]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [6]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[7] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[7]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [7]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[8] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[8]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [8]),
        .R(Q));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.CAP_ADDR_O_reg[9] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(icap_addr[9]),
        .Q(\i_intcap.CAP_ADDR_O_reg[9]_0 [9]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[0] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[0]),
        .Q(icap_addr[0]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[1] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[1]),
        .Q(icap_addr[1]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[2] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[2]),
        .Q(icap_addr[2]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[3] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[3]),
        .Q(icap_addr[3]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[4] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[4]),
        .Q(icap_addr[4]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[5] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[5]),
        .Q(icap_addr[5]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[6] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[6]),
        .Q(icap_addr[6]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[7] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[7]),
        .Q(icap_addr[7]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[8] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[8]),
        .Q(icap_addr[8]),
        .R(Q));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \i_intcap.icap_addr_reg[9] 
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(cap_addr_next[9]),
        .Q(icap_addr[9]),
        .R(Q));
  FDRE \i_o_to_64k.cfg_data_vec_reg[10] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[9]),
        .Q(cfg_data_vec[10]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[11] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[10]),
        .Q(cfg_data_vec[11]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[12] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[11]),
        .Q(cfg_data_vec[12]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[13] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[12]),
        .Q(cfg_data_vec[13]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[14] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[13]),
        .Q(cfg_data_vec[14]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[15] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[14]),
        .Q(cfg_data_vec[15]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[16] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[15]),
        .Q(cfg_data_vec[16]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[1] 
       (.C(out),
        .CE(E),
        .D(in0),
        .Q(cfg_data_vec[1]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[2] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[1]),
        .Q(cfg_data_vec[2]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[3] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[2]),
        .Q(cfg_data_vec[3]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[4] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[3]),
        .Q(cfg_data_vec[4]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[5] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[4]),
        .Q(cfg_data_vec[5]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[6] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[5]),
        .Q(cfg_data_vec[6]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[7] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[6]),
        .Q(cfg_data_vec[7]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[8] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[7]),
        .Q(cfg_data_vec[8]),
        .R(1'b0));
  FDRE \i_o_to_64k.cfg_data_vec_reg[9] 
       (.C(out),
        .CE(E),
        .D(cfg_data_vec[8]),
        .Q(cfg_data_vec[9]),
        .R(1'b0));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.u_selx " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \i_o_to_64k.u_selx 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(E),
        .CLK(out),
        .D(cfg_data_vec[16]),
        .Q(cfg_data_0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE icap_wr_en_reg
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(scnt_ce),
        .Q(icap_wr_en),
        .R(Q));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_sample_counter u_cap_sample_counter
       (.A({u_wcnt_lcmp_q,A}),
        .D(cap_addr_next),
        .DOUT_O(DOUT_O),
        .E(scnt_ce),
        .Q(wcnt),
        .SR(SR),
        .SRL_Q_O(cfg_data_2),
        .cfg_data_1(cfg_data_1),
        .cmp_reset(cmp_reset),
        .\i_intcap.icap_addr_reg[9] (cfg_data_vec_sync2[10:1]),
        .out(out),
        .\probeDelay1_reg[9] (\probeDelay1_reg[0] ),
        .scnt_cmp_temp(scnt_cmp_temp),
        .u_scnt_cmp_q_0(u_scnt_cmp_q),
        .u_scnt_cmp_q_1(E));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_window_counter u_cap_window_counter
       (.A(A),
        .E(E),
        .Q(wcnt),
        .SRL_Q_O(cfg_data_2),
        .cmp_reset(cmp_reset),
        .\iwcnt_reg[0]_0 (Q),
        .out(out),
        .\probeDelay1_reg[0] (\probeDelay1_reg[0] ),
        .shift_en_reg(shift_en_reg),
        .shift_en_reg_0(shift_en_reg_0),
        .shift_en_reg_1(SRL_Q_O),
        .u_wcnt_lcmp_q_0(u_wcnt_lcmp_q),
        .wcnt_hcmp(wcnt_hcmp),
        .wcnt_hcmp_temp(wcnt_hcmp_temp),
        .wcnt_lcmp_temp(wcnt_lcmp_temp));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_ctrl_legacy
   (O_reg,
    \I_YESLUT6.I_YES_OREG.O_reg_reg ,
    \i_intcap.CAP_ADDR_O_reg[9] ,
    CAP_WR_EN_O_reg,
    D,
    TRIGGERED_SL_I,
    cap_done,
    dout_reg1_reg,
    CAP_DONE_O_reg_0,
    CAP_DONE_O_reg_1,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
    SR,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ,
    DOUT_O,
    shift_en_reg,
    shift_en_reg_0,
    \captured_samples_reg[9] ,
    E,
    capture_ctrl_config_serial_output,
    A,
    out,
    scnt_cmp_temp,
    \probeDelay1_reg[0] ,
    wcnt_lcmp_temp,
    wcnt_hcmp_temp,
    capture_strg_qual,
    capture_fsm,
    u_wcnt_lcmp_q,
    Q,
    douta0,
    \current_state_reg[0] ,
    trig_out_fsm,
    itrigger_out_reg_0,
    basic_trigger,
    \captured_samples_reg[0] );
  output O_reg;
  output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
  output [9:0]\i_intcap.CAP_ADDR_O_reg[9] ;
  output CAP_WR_EN_O_reg;
  output [0:0]D;
  output TRIGGERED_SL_I;
  output cap_done;
  output dout_reg1_reg;
  output CAP_DONE_O_reg_0;
  output CAP_DONE_O_reg_1;
  output \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  output [0:0]SR;
  output \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
  output DOUT_O;
  output shift_en_reg;
  output shift_en_reg_0;
  output [9:0]\captured_samples_reg[9] ;
  input [0:0]E;
  input capture_ctrl_config_serial_output;
  input [0:0]A;
  input [0:0]out;
  input scnt_cmp_temp;
  input \probeDelay1_reg[0] ;
  input wcnt_lcmp_temp;
  input wcnt_hcmp_temp;
  input capture_strg_qual;
  input capture_fsm;
  input [1:0]u_wcnt_lcmp_q;
  input [1:0]Q;
  input [1:0]douta0;
  input \current_state_reg[0] ;
  input trig_out_fsm;
  input itrigger_out_reg_0;
  input basic_trigger;
  input [0:0]\captured_samples_reg[0] ;

  wire [0:0]A;
  wire CAP_DONE_O_reg_0;
  wire CAP_DONE_O_reg_1;
  wire CAP_WR_EN_O_reg;
  wire [0:0]D;
  wire DOUT_O;
  wire [0:0]E;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
  wire O_reg;
  wire [1:0]Q;
  wire [0:0]SR;
  wire TRIGGERED_SL_I;
  wire U_CDONE_n_1;
  wire basic_trigger;
  wire cap_done;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm;
  wire capture_i;
  wire capture_strg_qual;
  wire [0:0]\captured_samples_reg[0] ;
  wire [9:0]\captured_samples_reg[9] ;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire \current_state_reg[0] ;
  wire dout_reg1_reg;
  wire [1:0]douta0;
  wire [9:0]\i_intcap.CAP_ADDR_O_reg[9] ;
  wire itrigger_in;
  (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire itrigger_out;
  wire itrigger_out_reg_0;
  (* async_reg = "true" *) wire n_0_0;
  wire [0:0]out;
  wire \probeDelay1_reg[0] ;
  wire scnt_cmp;
  wire scnt_cmp_temp;
  wire shift_en_reg;
  wire shift_en_reg_0;
  wire trig_out_fsm;
  wire [1:0]u_wcnt_lcmp_q;
  wire wcnt_hcmp;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp;
  wire wcnt_lcmp_temp;

  LUT4 #(
    .INIT(16'hFACF)) 
    A0
       (.I0(capture_strg_qual),
        .I1(capture_fsm),
        .I2(u_wcnt_lcmp_q[1]),
        .I3(u_wcnt_lcmp_q[0]),
        .O(capture_i));
  FDRE #(
    .INIT(1'b0)) 
    CAP_DONE_O_reg
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(U_CDONE_n_1),
        .Q(cap_done),
        .R(1'b0));
  FDRE CAP_TRIGGER_O_reg
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(n_0_0),
        .Q(TRIGGERED_SL_I),
        .R(Q[0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6__parameterized0 U_CDONE
       (.A({wcnt_lcmp,capture_i,A,O_reg,\I_YESLUT6.I_YES_OREG.O_reg_reg }),
        .CAP_DONE_O_reg(U_CDONE_n_1),
        .CAP_DONE_O_reg_0(cap_done),
        .D(D),
        .E(E),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (\probeDelay1_reg[0] ),
        .Q(Q),
        .SRL_Q_O(cfg_data_2),
        .out(out),
        .wcnt_hcmp(wcnt_hcmp));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7 U_NS0
       (.A({scnt_cmp,capture_i,A,O_reg}),
        .CAP_DONE_O_reg(CAP_DONE_O_reg_1),
        .E(E),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_1 (\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_2 (\probeDelay1_reg[0] ),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_3 (wcnt_lcmp),
        .Q(Q[0]),
        .cfg_data_0(cfg_data_0),
        .\cntcmpsel_reg[1] (\current_state_reg[0] ),
        .douta0(douta0[1]),
        .in0(cfg_data_1),
        .out(out),
        .trig_out_fsm(trig_out_fsm),
        .trigger_reg(cap_done),
        .wcnt_hcmp(wcnt_hcmp));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7_251 U_NS1
       (.A({scnt_cmp,capture_i,A}),
        .CAPTURE_O_reg(cap_done),
        .CAP_DONE_O_reg(CAP_DONE_O_reg_0),
        .E(E),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (O_reg),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_1 (\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_2 ({wcnt_lcmp,\I_YESLUT6.I_YES_OREG.O_reg_reg }),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_3 (\probeDelay1_reg[0] ),
        .Q(Q[0]),
        .basic_trigger(basic_trigger),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .capture_fsm(capture_fsm),
        .cfg_data_0(cfg_data_0),
        .\current_state_reg[0] (\current_state_reg[0] ),
        .dout_reg1_reg(dout_reg1_reg),
        .douta0(douta0[0]),
        .itrigger_in(itrigger_in),
        .itrigger_out_reg(itrigger_out_reg_0),
        .out(out),
        .trig_out_fsm(trig_out_fsm),
        .wcnt_hcmp(wcnt_hcmp));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(itrigger_out),
        .O(n_0_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    itrigger_out_reg
       (.C(\probeDelay1_reg[0] ),
        .CE(1'b1),
        .D(itrigger_in),
        .Q(itrigger_out),
        .R(Q[0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_addrgen u_cap_addrgen
       (.A({capture_i,A,O_reg,\I_YESLUT6.I_YES_OREG.O_reg_reg }),
        .CAP_WR_EN_O_reg_0(CAP_WR_EN_O_reg),
        .DOUT_O(DOUT_O),
        .E(E),
        .Q(Q[0]),
        .SR(SR),
        .SRL_Q_O(cfg_data_2),
        .\captured_samples_reg[0]_0 (\captured_samples_reg[0] ),
        .\captured_samples_reg[9]_0 (\captured_samples_reg[9] ),
        .\i_intcap.CAP_ADDR_O_reg[9]_0 (\i_intcap.CAP_ADDR_O_reg[9] ),
        .in0(cfg_data_1),
        .out(out),
        .\probeDelay1_reg[0] (\probeDelay1_reg[0] ),
        .scnt_cmp_temp(scnt_cmp_temp),
        .shift_en_reg(shift_en_reg),
        .shift_en_reg_0(shift_en_reg_0),
        .u_scnt_cmp_q(scnt_cmp),
        .u_wcnt_lcmp_q(wcnt_lcmp),
        .wcnt_hcmp(wcnt_hcmp),
        .wcnt_hcmp_temp(wcnt_hcmp_temp),
        .wcnt_lcmp_temp(wcnt_lcmp_temp));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_sample_counter
   (E,
    u_scnt_cmp_q_0,
    SR,
    D,
    DOUT_O,
    SRL_Q_O,
    u_scnt_cmp_q_1,
    cfg_data_1,
    A,
    out,
    cmp_reset,
    scnt_cmp_temp,
    \probeDelay1_reg[9] ,
    \i_intcap.icap_addr_reg[9] ,
    Q);
  output [0:0]E;
  output [0:0]u_scnt_cmp_q_0;
  output [0:0]SR;
  output [9:0]D;
  output DOUT_O;
  output SRL_Q_O;
  input [0:0]u_scnt_cmp_q_1;
  input cfg_data_1;
  input [4:0]A;
  input [0:0]out;
  input cmp_reset;
  input scnt_cmp_temp;
  input \probeDelay1_reg[9] ;
  input [9:0]\i_intcap.icap_addr_reg[9] ;
  input [9:0]Q;

  wire [4:0]A;
  wire [9:0]D;
  wire DOUT_O;
  wire [0:0]E;
  wire [9:0]Q;
  wire [0:0]SR;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_1_0;
  wire cfg_data_2;
  wire cmp_reset;
  wire [9:0]\i_intcap.icap_addr_reg[9] ;
  wire \iscnt[9]_i_2_n_0 ;
  wire [0:0]out;
  wire [9:0]p_0_in__1;
  wire \probeDelay1_reg[9] ;
  wire [9:0]scnt;
  wire scnt_cmp_ce;
  wire scnt_cmp_temp;
  wire [0:0]u_scnt_cmp_q_0;
  wire [0:0]u_scnt_cmp_q_1;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4_258 U_SCE
       (.A(A[3:0]),
        .E(E),
        .cfg_data_0(cfg_data_0),
        .cfg_data_1(cfg_data_1),
        .\iscnt_reg[9] (u_scnt_cmp_q_1),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_259 U_SCMPCE
       (.A({u_scnt_cmp_q_0,A[3:0]}),
        .cfg_data_0(cfg_data_0),
        .cfg_data_1_0(cfg_data_1_0),
        .out(out),
        .scnt_cmp_ce(scnt_cmp_ce),
        .u_scnt_cmp_q(u_scnt_cmp_q_1));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6_260 U_SCRST
       (.A(A),
        .SR(SR),
        .SRL_D_I(cfg_data_2),
        .cfg_data_1_0(cfg_data_1_0),
        .\iscnt_reg[0] (u_scnt_cmp_q_1),
        .\iscnt_reg[0]_0 (u_scnt_cmp_q_0),
        .out(out));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[0]_i_1 
       (.I0(scnt[0]),
        .I1(\i_intcap.icap_addr_reg[9] [0]),
        .I2(Q[0]),
        .O(D[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[1]_i_1 
       (.I0(scnt[1]),
        .I1(\i_intcap.icap_addr_reg[9] [1]),
        .I2(Q[1]),
        .O(D[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[2]_i_1 
       (.I0(scnt[2]),
        .I1(\i_intcap.icap_addr_reg[9] [2]),
        .I2(Q[2]),
        .O(D[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[3]_i_1 
       (.I0(scnt[3]),
        .I1(\i_intcap.icap_addr_reg[9] [3]),
        .I2(Q[3]),
        .O(D[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[4]_i_1 
       (.I0(scnt[4]),
        .I1(\i_intcap.icap_addr_reg[9] [4]),
        .I2(Q[4]),
        .O(D[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[5]_i_1 
       (.I0(scnt[5]),
        .I1(\i_intcap.icap_addr_reg[9] [5]),
        .I2(Q[5]),
        .O(D[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[6]_i_1 
       (.I0(scnt[6]),
        .I1(\i_intcap.icap_addr_reg[9] [6]),
        .I2(Q[6]),
        .O(D[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[7]_i_1 
       (.I0(scnt[7]),
        .I1(\i_intcap.icap_addr_reg[9] [7]),
        .I2(Q[7]),
        .O(D[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[8]_i_1 
       (.I0(scnt[8]),
        .I1(\i_intcap.icap_addr_reg[9] [8]),
        .I2(Q[8]),
        .O(D[8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_intcap.icap_addr[9]_i_1 
       (.I0(scnt[9]),
        .I1(\i_intcap.icap_addr_reg[9] [9]),
        .I2(Q[9]),
        .O(D[9]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \iscnt[0]_i_1 
       (.I0(scnt[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \iscnt[1]_i_1 
       (.I0(scnt[0]),
        .I1(scnt[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \iscnt[2]_i_1 
       (.I0(scnt[0]),
        .I1(scnt[1]),
        .I2(scnt[2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \iscnt[3]_i_1 
       (.I0(scnt[1]),
        .I1(scnt[0]),
        .I2(scnt[2]),
        .I3(scnt[3]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \iscnt[4]_i_1 
       (.I0(scnt[2]),
        .I1(scnt[0]),
        .I2(scnt[1]),
        .I3(scnt[3]),
        .I4(scnt[4]),
        .O(p_0_in__1[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \iscnt[5]_i_1 
       (.I0(scnt[3]),
        .I1(scnt[1]),
        .I2(scnt[0]),
        .I3(scnt[2]),
        .I4(scnt[4]),
        .I5(scnt[5]),
        .O(p_0_in__1[5]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \iscnt[6]_i_1 
       (.I0(\iscnt[9]_i_2_n_0 ),
        .I1(scnt[6]),
        .O(p_0_in__1[6]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \iscnt[7]_i_1 
       (.I0(\iscnt[9]_i_2_n_0 ),
        .I1(scnt[6]),
        .I2(scnt[7]),
        .O(p_0_in__1[7]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \iscnt[8]_i_1 
       (.I0(scnt[6]),
        .I1(\iscnt[9]_i_2_n_0 ),
        .I2(scnt[7]),
        .I3(scnt[8]),
        .O(p_0_in__1[8]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \iscnt[9]_i_1 
       (.I0(scnt[7]),
        .I1(\iscnt[9]_i_2_n_0 ),
        .I2(scnt[6]),
        .I3(scnt[8]),
        .I4(scnt[9]),
        .O(p_0_in__1[9]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \iscnt[9]_i_2 
       (.I0(scnt[5]),
        .I1(scnt[3]),
        .I2(scnt[1]),
        .I3(scnt[0]),
        .I4(scnt[2]),
        .I5(scnt[4]),
        .O(\iscnt[9]_i_2_n_0 ));
  FDRE \iscnt_reg[0] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[0]),
        .Q(scnt[0]),
        .R(SR));
  FDRE \iscnt_reg[1] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[1]),
        .Q(scnt[1]),
        .R(SR));
  FDRE \iscnt_reg[2] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[2]),
        .Q(scnt[2]),
        .R(SR));
  FDRE \iscnt_reg[3] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[3]),
        .Q(scnt[3]),
        .R(SR));
  FDRE \iscnt_reg[4] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[4]),
        .Q(scnt[4]),
        .R(SR));
  FDRE \iscnt_reg[5] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[5]),
        .Q(scnt[5]),
        .R(SR));
  FDRE \iscnt_reg[6] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[6]),
        .Q(scnt[6]),
        .R(SR));
  FDRE \iscnt_reg[7] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[7]),
        .Q(scnt[7]),
        .R(SR));
  FDRE \iscnt_reg[8] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[8]),
        .Q(scnt[8]),
        .R(SR));
  FDRE \iscnt_reg[9] 
       (.C(\probeDelay1_reg[9] ),
        .CE(E),
        .D(p_0_in__1[9]),
        .Q(scnt[9]),
        .R(SR));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_261 u_scnt_cmp
       (.DOUT_O(DOUT_O),
        .Q(scnt),
        .SRL_D_I(cfg_data_2),
        .SRL_Q_O(SRL_Q_O),
        .\iwcnt_reg[0] (u_scnt_cmp_q_1),
        .out(out),
        .\probeDelay1_reg[9] (\probeDelay1_reg[9] ));
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    u_scnt_cmp_q
       (.C(\probeDelay1_reg[9] ),
        .CE(scnt_cmp_ce),
        .D(scnt_cmp_temp),
        .Q(u_scnt_cmp_q_0),
        .R(cmp_reset));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_window_counter
   (u_wcnt_lcmp_q_0,
    wcnt_hcmp,
    Q,
    shift_en_reg,
    shift_en_reg_0,
    shift_en_reg_1,
    E,
    SRL_Q_O,
    A,
    out,
    cmp_reset,
    wcnt_lcmp_temp,
    \probeDelay1_reg[0] ,
    wcnt_hcmp_temp,
    \iwcnt_reg[0]_0 );
  output [0:0]u_wcnt_lcmp_q_0;
  output wcnt_hcmp;
  output [9:0]Q;
  output shift_en_reg;
  output shift_en_reg_0;
  output shift_en_reg_1;
  input [0:0]E;
  input SRL_Q_O;
  input [3:0]A;
  input [0:0]out;
  input cmp_reset;
  input wcnt_lcmp_temp;
  input \probeDelay1_reg[0] ;
  input wcnt_hcmp_temp;
  input [0:0]\iwcnt_reg[0]_0 ;

  wire [3:0]A;
  wire [0:0]E;
  wire [9:0]Q;
  wire SRL_Q_O;
  wire [9:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire cfg_data_3;
  wire cmp_reset;
  wire \iwcnt[9]_i_2_n_0 ;
  wire [0:0]\iwcnt_reg[0]_0 ;
  wire [0:0]out;
  wire [9:0]p_0_in__0__0;
  wire \probeDelay1_reg[0] ;
  wire shift_en_reg;
  wire shift_en_reg_0;
  wire shift_en_reg_1;
  wire [0:0]u_wcnt_lcmp_q_0;
  wire wcnt_ce;
  wire wcnt_hcmp;
  wire wcnt_hcmp_ce;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp_ce;
  wire wcnt_lcmp_temp;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4 U_WCE
       (.A(A),
        .E(wcnt_ce),
        .SRL_Q_O(SRL_Q_O),
        .cfg_data_0(cfg_data_0),
        .\iwcnt_reg[0] (E),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5 U_WHCMPCE
       (.A({wcnt_hcmp,A}),
        .E(E),
        .SRL_D_I(cfg_data_3),
        .SRL_Q_O(cfg_data_2),
        .out(out),
        .wcnt_hcmp_ce(wcnt_hcmp_ce));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_252 U_WLCMPCE
       (.A({u_wcnt_lcmp_q_0,A}),
        .E(E),
        .SRL_D_I(cfg_data_1),
        .cfg_data_0(cfg_data_0),
        .out(out),
        .wcnt_lcmp_ce(wcnt_lcmp_ce));
  LUT1 #(
    .INIT(2'h1)) 
    \iwcnt[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \iwcnt[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \iwcnt[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(p_0_in__0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \iwcnt[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(p_0_in__0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \iwcnt[4]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(p_0_in__0__0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \iwcnt[5]_i_1 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(p_0_in__0__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \iwcnt[6]_i_1 
       (.I0(\iwcnt[9]_i_2_n_0 ),
        .I1(Q[6]),
        .O(p_0_in__0__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \iwcnt[7]_i_1 
       (.I0(\iwcnt[9]_i_2_n_0 ),
        .I1(Q[6]),
        .I2(Q[7]),
        .O(p_0_in__0__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \iwcnt[8]_i_1 
       (.I0(Q[6]),
        .I1(\iwcnt[9]_i_2_n_0 ),
        .I2(Q[7]),
        .I3(Q[8]),
        .O(p_0_in__0__0[8]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \iwcnt[9]_i_1 
       (.I0(Q[7]),
        .I1(\iwcnt[9]_i_2_n_0 ),
        .I2(Q[6]),
        .I3(Q[8]),
        .I4(Q[9]),
        .O(p_0_in__0__0[9]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \iwcnt[9]_i_2 
       (.I0(Q[5]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[4]),
        .O(\iwcnt[9]_i_2_n_0 ));
  FDRE \iwcnt_reg[0] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[0]),
        .Q(Q[0]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[1] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[1]),
        .Q(Q[1]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[2] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[2]),
        .Q(Q[2]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[3] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[3]),
        .Q(Q[3]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[4] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[4]),
        .Q(Q[4]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[5] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[5]),
        .Q(Q[5]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[6] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[6]),
        .Q(Q[6]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[7] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[7]),
        .Q(Q[7]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[8] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[8]),
        .Q(Q[8]),
        .R(\iwcnt_reg[0]_0 ));
  FDRE \iwcnt_reg[9] 
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_ce),
        .D(p_0_in__0__0[9]),
        .Q(Q[9]),
        .R(\iwcnt_reg[0]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay u_wcnt_hcmp
       (.E(E),
        .PROBES_I({\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [9],Q[9],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [8],Q[8],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [7],Q[7],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [6],Q[6],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [5],Q[5],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [4],Q[4],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [3],Q[3],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [2],Q[2],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [1],Q[1],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 [0],Q[0]}),
        .SRL_D_I(cfg_data_3),
        .out(out),
        .shift_en_reg(shift_en_reg_0),
        .shift_en_reg_0(shift_en_reg_1));
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    u_wcnt_hcmp_q
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_hcmp_ce),
        .D(wcnt_hcmp_temp),
        .Q(wcnt_hcmp),
        .R(cmp_reset));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_253 u_wcnt_lcmp
       (.E(E),
        .Q(Q),
        .SRL_D_I(cfg_data_1),
        .SRL_Q_O(cfg_data_2),
        .out(out),
        .\probeDelay1_reg[0] (\probeDelay1_reg[0] ),
        .\probeDelay1_reg[9] (\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .shift_en_reg(shift_en_reg));
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    u_wcnt_lcmp_q
       (.C(\probeDelay1_reg[0] ),
        .CE(wcnt_lcmp_ce),
        .D(wcnt_lcmp_temp),
        .Q(u_wcnt_lcmp_q_0),
        .R(cmp_reset));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_core
   (SL_OPORT_O,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    probe2,
    probe1,
    probe0,
    DUMMY_I);
  output [16:0]SL_OPORT_O;
  input [36:0]out;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input [21:0]probe2;
  input [21:0]probe1;
  input [20:0]probe0;
  input DUMMY_I;

  wire [23:0]CFG_BRAM_DATA;
  wire [23:0]CFG_BRAM_RD_DATA;
  wire DUMMY_I;
  wire \I_EN_CTL_EQ1.temp_en_i_3_n_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire O_reg;
  wire [15:0]SEQUENCER_STATE_O;
  wire [16:0]SL_OPORT_O;
  wire address;
  wire adv_drdy;
  wire adv_drdy_i_1_n_0;
  wire arm_ctrl;
  wire arm_status;
  wire basic_trigger;
  wire bram_en;
  wire bram_rd_en;
  wire cap_done;
  wire cap_trigger_out;
  wire [9:0]cap_wr_addr;
  wire cap_wr_en;
  wire [9:0]capture_cnt;
  wire capture_ctrl_config_cs_serial_input;
  wire capture_ctrl_config_en;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm;
  (* async_reg = "true" *) wire [1:0]capture_qual_ctrl;
  wire [1:0]capture_qual_ctrl_1;
  (* async_reg = "true" *) wire [1:0]capture_qual_ctrl_2;
  wire capture_strg_qual;
  wire [3:0]cnt_config_cs_serial_input;
  wire [3:0]cnt_config_cs_serial_output;
  wire [3:0]cnt_config_cs_shift_en;
  wire [15:0]config_fsm_data;
  wire [15:0]config_fsm_data_rd;
  wire count_tt;
  wire count_tt_i_1_n_0;
  wire [7:0]counter_ctrl;
  wire [3:0]counter_out;
  wire [3:0]current_state;
  wire \current_state[1]_i_2__0__0_n_0 ;
  wire \current_state[1]_i_2__0_n_0 ;
  wire \current_state[1]_i_2__10_n_0 ;
  wire \current_state[1]_i_2__11_n_0 ;
  wire \current_state[1]_i_2__1_n_0 ;
  wire \current_state[1]_i_2__2_n_0 ;
  wire \current_state[1]_i_2__3_n_0 ;
  wire \current_state[1]_i_2__4_n_0 ;
  wire \current_state[1]_i_2__5_n_0 ;
  wire \current_state[1]_i_2__6_n_0 ;
  wire \current_state[1]_i_2__7_n_0 ;
  wire \current_state[1]_i_2__8_n_0 ;
  wire \current_state[1]_i_2__9_n_0 ;
  wire \current_state[1]_i_3_n_0 ;
  wire \current_state[1]_i_4_n_0 ;
  wire \current_state[3]_i_5__0__0_n_0 ;
  wire \current_state[3]_i_5__0_n_0 ;
  wire data_out_en;
  wire [15:0]debug_data_in;
  (* async_reg = "true" *) wire [15:0]debug_data_in_sync1;
  (* async_reg = "true" *) wire [15:0]debug_data_in_sync2;
  wire [19:18]douta0;
  wire drdy_ff9;
  wire drdy_ffa;
  (* async_reg = "true" *) wire en_adv_trigger;
  wire en_adv_trigger_1;
  (* async_reg = "true" *) wire en_adv_trigger_2;
  wire flag0_temp;
  wire flag1_temp;
  wire flag2_temp;
  wire flag3_temp;
  wire halt_ctrl;
  wire halt_status;
  wire ila_clk_flag_i_1_n_0;
  wire [65:0]mem_data_out;
  wire [11:0]mu_config_cs_serial_input;
  wire [11:0]mu_config_cs_serial_output;
  wire [11:0]mu_config_cs_shift_en;
  wire next_state_ila;
  wire [36:0]out;
  wire p_1_in_0;
  wire [20:0]probe0;
  wire [21:0]probe1;
  wire [21:0]probe2;
  wire [15:0]probe_data;
  wire qual_strg_config_cs_serial_input;
  wire qual_strg_config_cs_serial_output;
  wire qual_strg_config_cs_shift_en;
  wire read_addr_reset;
  wire read_data_en;
  wire [9:0]read_reset_addr;
  wire [3:0]reset;
  wire [12:0]s_daddr;
  wire s_den;
  wire s_dwe;
  wire s_rst;
  wire scnt_reset;
  wire \shift_reg0[2]_i_1_n_0 ;
  wire \shift_reg1[11]_i_1_n_0 ;
  wire \shifted_data_in_reg[7][0]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][10]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][11]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][12]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][13]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][14]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][15]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][16]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][17]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][18]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][19]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][1]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][20]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][21]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][22]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][23]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][24]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][25]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][26]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][27]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][28]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][29]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][2]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][30]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][31]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][32]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][33]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][34]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][35]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][36]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][37]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][38]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][39]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][3]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][40]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][41]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][42]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][43]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][44]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][45]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][46]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][47]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][48]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][49]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][4]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][50]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][51]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][52]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][53]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][54]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][55]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][56]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][57]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][58]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][59]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][5]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][60]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][61]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][62]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][63]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][64]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][6]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][7]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][8]_srl8_n_0 ;
  wire \shifted_data_in_reg[7][9]_srl8_n_0 ;
  wire \shifted_data_in_reg_n_0_[8][0] ;
  wire \shifted_data_in_reg_n_0_[8][10] ;
  wire \shifted_data_in_reg_n_0_[8][11] ;
  wire \shifted_data_in_reg_n_0_[8][12] ;
  wire \shifted_data_in_reg_n_0_[8][13] ;
  wire \shifted_data_in_reg_n_0_[8][14] ;
  wire \shifted_data_in_reg_n_0_[8][15] ;
  wire \shifted_data_in_reg_n_0_[8][16] ;
  wire \shifted_data_in_reg_n_0_[8][17] ;
  wire \shifted_data_in_reg_n_0_[8][18] ;
  wire \shifted_data_in_reg_n_0_[8][19] ;
  wire \shifted_data_in_reg_n_0_[8][1] ;
  wire \shifted_data_in_reg_n_0_[8][20] ;
  wire \shifted_data_in_reg_n_0_[8][21] ;
  wire \shifted_data_in_reg_n_0_[8][22] ;
  wire \shifted_data_in_reg_n_0_[8][23] ;
  wire \shifted_data_in_reg_n_0_[8][24] ;
  wire \shifted_data_in_reg_n_0_[8][25] ;
  wire \shifted_data_in_reg_n_0_[8][26] ;
  wire \shifted_data_in_reg_n_0_[8][27] ;
  wire \shifted_data_in_reg_n_0_[8][28] ;
  wire \shifted_data_in_reg_n_0_[8][29] ;
  wire \shifted_data_in_reg_n_0_[8][2] ;
  wire \shifted_data_in_reg_n_0_[8][30] ;
  wire \shifted_data_in_reg_n_0_[8][31] ;
  wire \shifted_data_in_reg_n_0_[8][32] ;
  wire \shifted_data_in_reg_n_0_[8][33] ;
  wire \shifted_data_in_reg_n_0_[8][34] ;
  wire \shifted_data_in_reg_n_0_[8][35] ;
  wire \shifted_data_in_reg_n_0_[8][36] ;
  wire \shifted_data_in_reg_n_0_[8][37] ;
  wire \shifted_data_in_reg_n_0_[8][38] ;
  wire \shifted_data_in_reg_n_0_[8][39] ;
  wire \shifted_data_in_reg_n_0_[8][3] ;
  wire \shifted_data_in_reg_n_0_[8][40] ;
  wire \shifted_data_in_reg_n_0_[8][41] ;
  wire \shifted_data_in_reg_n_0_[8][42] ;
  wire \shifted_data_in_reg_n_0_[8][43] ;
  wire \shifted_data_in_reg_n_0_[8][44] ;
  wire \shifted_data_in_reg_n_0_[8][45] ;
  wire \shifted_data_in_reg_n_0_[8][46] ;
  wire \shifted_data_in_reg_n_0_[8][47] ;
  wire \shifted_data_in_reg_n_0_[8][48] ;
  wire \shifted_data_in_reg_n_0_[8][49] ;
  wire \shifted_data_in_reg_n_0_[8][4] ;
  wire \shifted_data_in_reg_n_0_[8][50] ;
  wire \shifted_data_in_reg_n_0_[8][51] ;
  wire \shifted_data_in_reg_n_0_[8][52] ;
  wire \shifted_data_in_reg_n_0_[8][53] ;
  wire \shifted_data_in_reg_n_0_[8][54] ;
  wire \shifted_data_in_reg_n_0_[8][55] ;
  wire \shifted_data_in_reg_n_0_[8][56] ;
  wire \shifted_data_in_reg_n_0_[8][57] ;
  wire \shifted_data_in_reg_n_0_[8][58] ;
  wire \shifted_data_in_reg_n_0_[8][59] ;
  wire \shifted_data_in_reg_n_0_[8][5] ;
  wire \shifted_data_in_reg_n_0_[8][60] ;
  wire \shifted_data_in_reg_n_0_[8][61] ;
  wire \shifted_data_in_reg_n_0_[8][62] ;
  wire \shifted_data_in_reg_n_0_[8][63] ;
  wire \shifted_data_in_reg_n_0_[8][64] ;
  wire \shifted_data_in_reg_n_0_[8][6] ;
  wire \shifted_data_in_reg_n_0_[8][7] ;
  wire \shifted_data_in_reg_n_0_[8][8] ;
  wire \shifted_data_in_reg_n_0_[8][9] ;
  wire \slaveRegDo_mux_0[4]_i_13_n_0 ;
  wire \slaveRegDo_mux_6[15]_i_6_n_0 ;
  wire [31:0]tc_config_cs_serial_input;
  wire [31:0]tc_config_cs_serial_output;
  wire [31:0]tc_config_cs_shift_en;
  wire toggle;
  wire toggle_rd;
  wire [1:1]trace_data_ack;
  wire \trace_data_ack_reg_n_0_[0] ;
  wire [9:0]trace_read_addr;
  wire trace_read_en;
  wire trig_out_fsm;
  wire trigger_i__0;
  wire \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ;
  wire \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ;
  wire \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ;
  wire \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ;
  wire \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ;
  wire \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ;
  wire u_ila_cap_ctrl_n_1;
  wire u_ila_cap_ctrl_n_16;
  wire u_ila_cap_ctrl_n_17;
  wire u_ila_cap_ctrl_n_18;
  wire u_ila_cap_ctrl_n_19;
  wire u_ila_cap_ctrl_n_21;
  wire u_ila_regs_n_106;
  wire u_ila_regs_n_107;
  wire u_ila_regs_n_33;
  wire u_ila_regs_n_36;
  wire u_ila_regs_n_38;
  wire u_ila_regs_n_39;
  wire u_ila_regs_n_40;
  wire u_ila_regs_n_45;
  wire u_ila_regs_n_46;
  wire u_ila_regs_n_47;
  wire u_ila_regs_n_48;
  wire u_ila_regs_n_59;
  wire u_ila_regs_n_61;
  wire u_ila_reset_ctrl_n_2;
  wire u_ila_reset_ctrl_n_6;
  wire u_ila_reset_ctrl_n_7;
  wire u_trig_n_47;
  wire u_trig_n_48;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire use_probe_debug_circuit;
  wire use_probe_debug_circuit_1;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire use_probe_debug_circuit_2;
  wire xsdb_memory_read_inst_n_15;
  wire xsdb_memory_read_inst_n_16;
  wire xsdb_memory_read_inst_n_17;
  wire xsdb_memory_read_inst_n_18;
  wire xsdb_memory_read_inst_n_19;
  wire xsdb_memory_read_inst_n_2;
  wire xsdb_memory_read_inst_n_20;
  wire xsdb_memory_read_inst_n_21;
  wire xsdb_memory_read_inst_n_22;
  wire xsdb_memory_read_inst_n_23;
  wire xsdb_memory_read_inst_n_24;
  wire xsdb_memory_read_inst_n_25;
  wire xsdb_memory_read_inst_n_26;
  wire xsdb_memory_read_inst_n_27;
  wire xsdb_memory_read_inst_n_28;
  wire xsdb_memory_read_inst_n_3;
  wire xsdb_memory_read_inst_n_4;
  wire xsdb_rden_ff8;
  wire \xsdb_reg[15]_i_2__0__0_n_0 ;
  wire \xsdb_reg[15]_i_2__1__0_n_0 ;
  wire \xsdb_reg[15]_i_2__2__0_n_0 ;
  wire \xsdb_reg[15]_i_2__3__0_n_0 ;
  wire \xsdb_reg[15]_i_2__6_n_0 ;
  wire \xsdb_reg[15]_i_3__3_n_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_adv_trigger_sequencer \ADV_TRIG.u_adv_trig 
       (.A(trigger_i__0),
        .ADDRA({address,u_trig_n_47}),
        .CAPTURE_O_reg_0(u_ila_cap_ctrl_n_16),
        .CFG_BRAM_DATA(CFG_BRAM_DATA),
        .\CFG_BRAM_RD_DATA_reg[23]_0 (CFG_BRAM_RD_DATA),
        .CNT_CTRL(counter_ctrl),
        .COUNTER_EQ(counter_out),
        .E(toggle),
        .O_reg(O_reg),
        .Q(reset[1:0]),
        .SEQUENCER_STATE_O(SEQUENCER_STATE_O),
        .\SEQUENCER_STATE_O_reg[0]_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\SEQUENCER_STATE_O_reg[0]_1 (u_ila_cap_ctrl_n_1),
        .\SEQUENCER_STATE_O_reg[0]_2 (arm_status),
        .\SEQUENCER_STATE_O_reg[8]_0 (u_ila_reset_ctrl_n_6),
        .basic_trigger(basic_trigger),
        .bram_en(bram_en),
        .bram_rd_en(bram_rd_en),
        .capture_fsm(capture_fsm),
        .\cntcmpsel_reg[1]_0 (u_ila_cap_ctrl_n_21),
        .current_state(current_state),
        .\current_state_reg[0]_0 (u_ila_cap_ctrl_n_17),
        .\current_state_reg[0]_1 (u_ila_cap_ctrl_n_19),
        .douta0(douta0),
        .flag0_temp(flag0_temp),
        .flag1_temp(flag1_temp),
        .flag2_temp(flag2_temp),
        .flag3_temp(flag3_temp),
        .out(out[1]),
        .toggle_rd(toggle_rd),
        .trig_out_fsm(trig_out_fsm),
        .trigger_reg_0(u_ila_cap_ctrl_n_18),
        .u_wcnt_lcmp_q(en_adv_trigger));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_fsm_memory_read \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst 
       (.CFG_BRAM_DATA(CFG_BRAM_DATA),
        .\CFG_DATA_O_reg[7]_0 (CFG_BRAM_RD_DATA),
        .D(config_fsm_data),
        .E(toggle),
        .FSM_BRAM_CONFIG_DATA_I(config_fsm_data_rd),
        .out(out[1]),
        .toggle_rd(toggle_rd),
        .toggle_rd_reg_0(u_ila_regs_n_59),
        .toggle_reg_0(u_ila_regs_n_61));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_counter \COUNTER.u_count 
       (.CFG_CNT_DIN(cnt_config_cs_serial_output),
        .CFG_CNT_DOUT(cnt_config_cs_serial_input),
        .CNT_CTRL(counter_ctrl),
        .COUNTER_EQ(counter_out),
        .Q(reset[1:0]),
        .SR(scnt_reset),
        .cnt_config_cs_shift_en(cnt_config_cs_shift_en),
        .\counter_reg[0] (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .out(out[1]));
  LUT2 #(
    .INIT(4'h7)) 
    \I_EN_CTL_EQ1.temp_en_i_3 
       (.I0(s_daddr[2]),
        .I1(s_daddr[3]),
        .O(\I_EN_CTL_EQ1.temp_en_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEF00000020)) 
    adv_drdy_i_1
       (.I0(s_den),
        .I1(s_daddr[12]),
        .I2(u_ila_regs_n_45),
        .I3(u_ila_regs_n_46),
        .I4(\I_EN_CTL_EQ1.temp_en_i_3_n_0 ),
        .I5(adv_drdy),
        .O(adv_drdy_i_1_n_0));
  FDRE basic_trigger_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(u_trig_n_48),
        .Q(basic_trigger),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \capture_qual_ctrl_2_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(capture_qual_ctrl_1[0]),
        .Q(capture_qual_ctrl_2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \capture_qual_ctrl_2_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(capture_qual_ctrl_1[1]),
        .Q(capture_qual_ctrl_2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \capture_qual_ctrl_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(capture_qual_ctrl_2[0]),
        .Q(capture_qual_ctrl[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \capture_qual_ctrl_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(capture_qual_ctrl_2[1]),
        .Q(capture_qual_ctrl[1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h6)) 
    count_tt_i_1
       (.I0(xsdb_rden_ff8),
        .I1(count_tt),
        .O(count_tt_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFF7FFFFFFFFFFFF)) 
    \current_state[1]_i_2__0 
       (.I0(s_daddr[12]),
        .I1(s_den),
        .I2(s_daddr[11]),
        .I3(s_daddr[10]),
        .I4(s_daddr[1]),
        .I5(s_daddr[0]),
        .O(\current_state[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    \current_state[1]_i_2__0__0 
       (.I0(s_daddr[12]),
        .I1(s_den),
        .I2(s_daddr[11]),
        .I3(s_daddr[10]),
        .I4(s_daddr[1]),
        .I5(s_daddr[0]),
        .O(\current_state[1]_i_2__0__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \current_state[1]_i_2__1 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[3]),
        .I3(s_daddr[2]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \current_state[1]_i_2__10 
       (.I0(s_daddr[12]),
        .I1(s_den),
        .I2(s_daddr[11]),
        .I3(s_daddr[10]),
        .I4(s_daddr[1]),
        .I5(s_daddr[0]),
        .O(\current_state[1]_i_2__10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF7FF)) 
    \current_state[1]_i_2__11 
       (.I0(s_daddr[12]),
        .I1(s_den),
        .I2(s_daddr[11]),
        .I3(s_daddr[10]),
        .I4(s_daddr[1]),
        .I5(s_daddr[0]),
        .O(\current_state[1]_i_2__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \current_state[1]_i_2__2 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[2]),
        .I3(s_daddr[3]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \current_state[1]_i_2__3 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[2]),
        .I3(s_daddr[3]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFB)) 
    \current_state[1]_i_2__4 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[2]),
        .I3(s_daddr[3]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \current_state[1]_i_2__5 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[3]),
        .I3(s_daddr[2]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \current_state[1]_i_2__6 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[2]),
        .I3(s_daddr[3]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT5 #(
    .INIT(32'hFFFFBFFF)) 
    \current_state[1]_i_2__7 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[2]),
        .I3(s_daddr[3]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_2__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF7FFFFFF)) 
    \current_state[1]_i_2__8 
       (.I0(s_daddr[12]),
        .I1(s_den),
        .I2(s_daddr[11]),
        .I3(s_daddr[10]),
        .I4(s_daddr[1]),
        .I5(s_daddr[0]),
        .O(\current_state[1]_i_2__8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF7FFFFFF)) 
    \current_state[1]_i_2__9 
       (.I0(s_daddr[12]),
        .I1(s_den),
        .I2(s_daddr[11]),
        .I3(s_daddr[10]),
        .I4(s_daddr[0]),
        .I5(s_daddr[1]),
        .O(\current_state[1]_i_2__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \current_state[1]_i_3 
       (.I0(s_daddr[5]),
        .I1(s_daddr[4]),
        .I2(s_daddr[2]),
        .I3(s_daddr[3]),
        .I4(\current_state[1]_i_4_n_0 ),
        .O(\current_state[1]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[1]_i_4 
       (.I0(s_daddr[7]),
        .I1(s_daddr[6]),
        .I2(s_daddr[8]),
        .I3(s_daddr[9]),
        .O(\current_state[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT4 #(
    .INIT(16'hEFFF)) 
    \current_state[3]_i_5__0 
       (.I0(s_daddr[10]),
        .I1(s_daddr[11]),
        .I2(s_den),
        .I3(s_daddr[12]),
        .O(\current_state[3]_i_5__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT4 #(
    .INIT(16'hDFFF)) 
    \current_state[3]_i_5__0__0 
       (.I0(s_daddr[11]),
        .I1(s_daddr[10]),
        .I2(s_den),
        .I3(s_daddr[12]),
        .O(\current_state[3]_i_5__0__0_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[0]),
        .Q(debug_data_in_sync1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[10]),
        .Q(debug_data_in_sync1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[11]),
        .Q(debug_data_in_sync1[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[12]),
        .Q(debug_data_in_sync1[12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[13]),
        .Q(debug_data_in_sync1[13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[14]),
        .Q(debug_data_in_sync1[14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[15]),
        .Q(debug_data_in_sync1[15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[1]),
        .Q(debug_data_in_sync1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[2]),
        .Q(debug_data_in_sync1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[3]),
        .Q(debug_data_in_sync1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[4]),
        .Q(debug_data_in_sync1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[5]),
        .Q(debug_data_in_sync1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[6]),
        .Q(debug_data_in_sync1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[7]),
        .Q(debug_data_in_sync1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[8]),
        .Q(debug_data_in_sync1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync1_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in[9]),
        .Q(debug_data_in_sync1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[0]),
        .Q(debug_data_in_sync2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[10]),
        .Q(debug_data_in_sync2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[11]),
        .Q(debug_data_in_sync2[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[12]),
        .Q(debug_data_in_sync2[12]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[13]),
        .Q(debug_data_in_sync2[13]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[14]),
        .Q(debug_data_in_sync2[14]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[15]),
        .Q(debug_data_in_sync2[15]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[1]),
        .Q(debug_data_in_sync2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[2]),
        .Q(debug_data_in_sync2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[3]),
        .Q(debug_data_in_sync2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[4]),
        .Q(debug_data_in_sync2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[5]),
        .Q(debug_data_in_sync2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[6]),
        .Q(debug_data_in_sync2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[7]),
        .Q(debug_data_in_sync2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[8]),
        .Q(debug_data_in_sync2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \debug_data_in_sync2_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(debug_data_in_sync1[9]),
        .Q(debug_data_in_sync2[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE en_adv_trigger_2_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(en_adv_trigger_1),
        .Q(en_adv_trigger_2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE en_adv_trigger_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(en_adv_trigger_2),
        .Q(en_adv_trigger),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h8E)) 
    ila_clk_flag_i_1
       (.I0(p_1_in_0),
        .I1(next_state_ila),
        .I2(u_ila_regs_n_33),
        .O(ila_clk_flag_i_1_n_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_trace_memory ila_trace_memory_inst
       (.D(mem_data_out),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (cap_wr_en),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (trace_read_en),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (cap_wr_addr),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ({cap_trigger_out,\shifted_data_in_reg_n_0_[8][64] ,\shifted_data_in_reg_n_0_[8][63] ,\shifted_data_in_reg_n_0_[8][62] ,\shifted_data_in_reg_n_0_[8][61] ,\shifted_data_in_reg_n_0_[8][60] ,\shifted_data_in_reg_n_0_[8][59] ,\shifted_data_in_reg_n_0_[8][58] ,\shifted_data_in_reg_n_0_[8][57] ,\shifted_data_in_reg_n_0_[8][56] ,\shifted_data_in_reg_n_0_[8][55] ,\shifted_data_in_reg_n_0_[8][54] ,\shifted_data_in_reg_n_0_[8][53] ,\shifted_data_in_reg_n_0_[8][52] ,\shifted_data_in_reg_n_0_[8][51] ,\shifted_data_in_reg_n_0_[8][50] ,\shifted_data_in_reg_n_0_[8][49] ,\shifted_data_in_reg_n_0_[8][48] ,\shifted_data_in_reg_n_0_[8][47] ,\shifted_data_in_reg_n_0_[8][46] ,\shifted_data_in_reg_n_0_[8][45] ,\shifted_data_in_reg_n_0_[8][44] ,\shifted_data_in_reg_n_0_[8][43] ,\shifted_data_in_reg_n_0_[8][42] ,\shifted_data_in_reg_n_0_[8][41] ,\shifted_data_in_reg_n_0_[8][40] ,\shifted_data_in_reg_n_0_[8][39] ,\shifted_data_in_reg_n_0_[8][38] ,\shifted_data_in_reg_n_0_[8][37] ,\shifted_data_in_reg_n_0_[8][36] }),
        .DIADI({\shifted_data_in_reg_n_0_[8][34] ,\shifted_data_in_reg_n_0_[8][33] ,\shifted_data_in_reg_n_0_[8][32] ,\shifted_data_in_reg_n_0_[8][31] ,\shifted_data_in_reg_n_0_[8][30] ,\shifted_data_in_reg_n_0_[8][29] ,\shifted_data_in_reg_n_0_[8][28] ,\shifted_data_in_reg_n_0_[8][27] ,\shifted_data_in_reg_n_0_[8][25] ,\shifted_data_in_reg_n_0_[8][24] ,\shifted_data_in_reg_n_0_[8][23] ,\shifted_data_in_reg_n_0_[8][22] ,\shifted_data_in_reg_n_0_[8][21] ,\shifted_data_in_reg_n_0_[8][20] ,\shifted_data_in_reg_n_0_[8][19] ,\shifted_data_in_reg_n_0_[8][18] ,\shifted_data_in_reg_n_0_[8][16] ,\shifted_data_in_reg_n_0_[8][15] ,\shifted_data_in_reg_n_0_[8][14] ,\shifted_data_in_reg_n_0_[8][13] ,\shifted_data_in_reg_n_0_[8][12] ,\shifted_data_in_reg_n_0_[8][11] ,\shifted_data_in_reg_n_0_[8][10] ,\shifted_data_in_reg_n_0_[8][9] ,\shifted_data_in_reg_n_0_[8][7] ,\shifted_data_in_reg_n_0_[8][6] ,\shifted_data_in_reg_n_0_[8][5] ,\shifted_data_in_reg_n_0_[8][4] ,\shifted_data_in_reg_n_0_[8][3] ,\shifted_data_in_reg_n_0_[8][2] ,\shifted_data_in_reg_n_0_[8][1] ,\shifted_data_in_reg_n_0_[8][0] }),
        .DIPADIP({\shifted_data_in_reg_n_0_[8][35] ,\shifted_data_in_reg_n_0_[8][26] ,\shifted_data_in_reg_n_0_[8][17] ,\shifted_data_in_reg_n_0_[8][8] }),
        .Q(trace_read_addr),
        .out(out[1]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[0]_i_1 
       (.I0(debug_data_in_sync2[0]),
        .I1(probe0[0]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[0]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[10]_i_1 
       (.I0(debug_data_in_sync2[10]),
        .I1(probe0[10]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[10]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[11]_i_1 
       (.I0(debug_data_in_sync2[11]),
        .I1(probe0[11]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[11]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[12]_i_1 
       (.I0(debug_data_in_sync2[12]),
        .I1(probe0[12]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[12]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[13]_i_1 
       (.I0(debug_data_in_sync2[13]),
        .I1(probe0[13]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[13]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[14]_i_1 
       (.I0(debug_data_in_sync2[14]),
        .I1(probe0[14]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[14]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[15]_i_1 
       (.I0(debug_data_in_sync2[15]),
        .I1(probe0[15]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[15]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[1]_i_1 
       (.I0(debug_data_in_sync2[1]),
        .I1(probe0[1]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[1]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[2]_i_1 
       (.I0(debug_data_in_sync2[2]),
        .I1(probe0[2]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[2]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[3]_i_1 
       (.I0(debug_data_in_sync2[3]),
        .I1(probe0[3]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[3]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[4]_i_1 
       (.I0(debug_data_in_sync2[4]),
        .I1(probe0[4]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[4]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[5]_i_1 
       (.I0(debug_data_in_sync2[5]),
        .I1(probe0[5]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[5]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[6]_i_1 
       (.I0(debug_data_in_sync2[6]),
        .I1(probe0[6]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[6]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[7]_i_1 
       (.I0(debug_data_in_sync2[7]),
        .I1(probe0[7]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[7]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[8]_i_1 
       (.I0(debug_data_in_sync2[8]),
        .I1(probe0[8]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[8]));
  LUT3 #(
    .INIT(8'hAC)) 
    \probeDelay1[9]_i_1 
       (.I0(debug_data_in_sync2[9]),
        .I1(probe0[9]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[9]));
  LUT5 #(
    .INIT(32'hFFFF22F2)) 
    \shift_reg0[2]_i_1 
       (.I0(u_ila_regs_n_36),
        .I1(drdy_ff9),
        .I2(u_ila_regs_n_47),
        .I3(u_ila_regs_n_106),
        .I4(s_rst),
        .O(\shift_reg0[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF22F2)) 
    \shift_reg1[11]_i_1 
       (.I0(u_ila_regs_n_38),
        .I1(drdy_ffa),
        .I2(u_ila_regs_n_48),
        .I3(u_ila_regs_n_107),
        .I4(s_rst),
        .O(\shift_reg1[11]_i_1_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][0]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][0]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[0]),
        .Q(\shifted_data_in_reg[7][0]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][10]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][10]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[10]),
        .Q(\shifted_data_in_reg[7][10]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][11]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][11]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[11]),
        .Q(\shifted_data_in_reg[7][11]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][12]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][12]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[12]),
        .Q(\shifted_data_in_reg[7][12]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][13]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][13]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[13]),
        .Q(\shifted_data_in_reg[7][13]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][14]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][14]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[14]),
        .Q(\shifted_data_in_reg[7][14]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][15]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][15]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[15]),
        .Q(\shifted_data_in_reg[7][15]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][16]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][16]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[16]),
        .Q(\shifted_data_in_reg[7][16]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][17]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][17]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[17]),
        .Q(\shifted_data_in_reg[7][17]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][18]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][18]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[18]),
        .Q(\shifted_data_in_reg[7][18]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][19]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][19]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[19]),
        .Q(\shifted_data_in_reg[7][19]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][1]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][1]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[1]),
        .Q(\shifted_data_in_reg[7][1]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][20]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][20]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[20]),
        .Q(\shifted_data_in_reg[7][20]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][21]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][21]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[0]),
        .Q(\shifted_data_in_reg[7][21]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][22]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][22]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[1]),
        .Q(\shifted_data_in_reg[7][22]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][23]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][23]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[2]),
        .Q(\shifted_data_in_reg[7][23]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][24]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][24]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[3]),
        .Q(\shifted_data_in_reg[7][24]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][25]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][25]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[4]),
        .Q(\shifted_data_in_reg[7][25]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][26]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][26]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[5]),
        .Q(\shifted_data_in_reg[7][26]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][27]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][27]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[6]),
        .Q(\shifted_data_in_reg[7][27]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][28]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][28]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[7]),
        .Q(\shifted_data_in_reg[7][28]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][29]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][29]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[8]),
        .Q(\shifted_data_in_reg[7][29]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][2]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][2]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[2]),
        .Q(\shifted_data_in_reg[7][2]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][30]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][30]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[9]),
        .Q(\shifted_data_in_reg[7][30]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][31]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][31]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[10]),
        .Q(\shifted_data_in_reg[7][31]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][32]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][32]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[11]),
        .Q(\shifted_data_in_reg[7][32]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][33]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][33]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[12]),
        .Q(\shifted_data_in_reg[7][33]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][34]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][34]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[13]),
        .Q(\shifted_data_in_reg[7][34]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][35]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][35]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[14]),
        .Q(\shifted_data_in_reg[7][35]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][36]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][36]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[15]),
        .Q(\shifted_data_in_reg[7][36]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][37]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][37]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[16]),
        .Q(\shifted_data_in_reg[7][37]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][38]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][38]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[17]),
        .Q(\shifted_data_in_reg[7][38]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][39]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][39]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[18]),
        .Q(\shifted_data_in_reg[7][39]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][3]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][3]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[3]),
        .Q(\shifted_data_in_reg[7][3]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][40]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][40]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[19]),
        .Q(\shifted_data_in_reg[7][40]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][41]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][41]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[20]),
        .Q(\shifted_data_in_reg[7][41]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][42]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][42]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe1[21]),
        .Q(\shifted_data_in_reg[7][42]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][43]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][43]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[0]),
        .Q(\shifted_data_in_reg[7][43]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][44]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][44]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[1]),
        .Q(\shifted_data_in_reg[7][44]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][45]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][45]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[2]),
        .Q(\shifted_data_in_reg[7][45]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][46]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][46]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[3]),
        .Q(\shifted_data_in_reg[7][46]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][47]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][47]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[4]),
        .Q(\shifted_data_in_reg[7][47]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][48]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][48]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[5]),
        .Q(\shifted_data_in_reg[7][48]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][49]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][49]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[6]),
        .Q(\shifted_data_in_reg[7][49]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][4]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][4]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[4]),
        .Q(\shifted_data_in_reg[7][4]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][50]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][50]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[7]),
        .Q(\shifted_data_in_reg[7][50]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][51]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][51]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[8]),
        .Q(\shifted_data_in_reg[7][51]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][52]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][52]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[9]),
        .Q(\shifted_data_in_reg[7][52]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][53]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][53]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[10]),
        .Q(\shifted_data_in_reg[7][53]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][54]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][54]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[11]),
        .Q(\shifted_data_in_reg[7][54]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][55]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][55]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[12]),
        .Q(\shifted_data_in_reg[7][55]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][56]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][56]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[13]),
        .Q(\shifted_data_in_reg[7][56]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][57]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][57]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[14]),
        .Q(\shifted_data_in_reg[7][57]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][58]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][58]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[15]),
        .Q(\shifted_data_in_reg[7][58]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][59]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][59]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[16]),
        .Q(\shifted_data_in_reg[7][59]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][5]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][5]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[5]),
        .Q(\shifted_data_in_reg[7][5]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][60]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][60]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[17]),
        .Q(\shifted_data_in_reg[7][60]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][61]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][61]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[18]),
        .Q(\shifted_data_in_reg[7][61]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][62]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][62]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[19]),
        .Q(\shifted_data_in_reg[7][62]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][63]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][63]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[20]),
        .Q(\shifted_data_in_reg[7][63]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][64]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][64]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe2[21]),
        .Q(\shifted_data_in_reg[7][64]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][6]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][6]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[6]),
        .Q(\shifted_data_in_reg[7][6]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][7]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][7]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[7]),
        .Q(\shifted_data_in_reg[7][7]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][8]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][8]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[8]),
        .Q(\shifted_data_in_reg[7][8]_srl8_n_0 ));
  (* srl_bus_name = "inst/\ila_core_inst/shifted_data_in_reg[7] " *) 
  (* srl_name = "inst/\ila_core_inst/shifted_data_in_reg[7][9]_srl8 " *) 
  SRL16E \shifted_data_in_reg[7][9]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .D(probe0[9]),
        .Q(\shifted_data_in_reg[7][9]_srl8_n_0 ));
  FDRE \shifted_data_in_reg[8][0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][0]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][0] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][10]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][10] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][11]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][11] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][12]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][12] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][13]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][13] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][14]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][14] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][15]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][15] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][16]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][16] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][17]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][17] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][18]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][18] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][19]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][19] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][1]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][1] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][20]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][20] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][21] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][21]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][21] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][22] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][22]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][22] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][23] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][23]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][23] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][24] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][24]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][24] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][25] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][25]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][25] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][26] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][26]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][26] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][27] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][27]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][27] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][28] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][28]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][28] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][29] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][29]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][29] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][2]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][2] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][30] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][30]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][30] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][31] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][31]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][31] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][32] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][32]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][32] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][33] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][33]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][33] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][34] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][34]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][34] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][35] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][35]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][35] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][36] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][36]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][36] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][37] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][37]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][37] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][38] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][38]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][38] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][39] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][39]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][39] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][3]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][3] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][40] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][40]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][40] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][41] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][41]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][41] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][42] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][42]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][42] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][43] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][43]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][43] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][44] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][44]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][44] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][45] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][45]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][45] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][46] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][46]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][46] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][47] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][47]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][47] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][48] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][48]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][48] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][49] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][49]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][49] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][4]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][4] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][50] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][50]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][50] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][51] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][51]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][51] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][52] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][52]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][52] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][53] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][53]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][53] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][54] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][54]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][54] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][55] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][55]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][55] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][56] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][56]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][56] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][57] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][57]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][57] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][58] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][58]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][58] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][59] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][59]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][59] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][5]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][5] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][60] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][60]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][60] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][61] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][61]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][61] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][62] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][62]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][62] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][63] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][63]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][63] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][64] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][64]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][64] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][6]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][6] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][7]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][7] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][8]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][8] ),
        .R(1'b0));
  FDRE \shifted_data_in_reg[8][9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(\shifted_data_in_reg[7][9]_srl8_n_0 ),
        .Q(\shifted_data_in_reg_n_0_[8][9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \slaveRegDo_mux_0[4]_i_13 
       (.I0(s_daddr[2]),
        .I1(s_daddr[3]),
        .O(\slaveRegDo_mux_0[4]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \slaveRegDo_mux_6[15]_i_6 
       (.I0(s_daddr[3]),
        .I1(s_daddr[2]),
        .O(\slaveRegDo_mux_6[15]_i_6_n_0 ));
  FDRE \trace_data_ack_reg[0] 
       (.C(out[1]),
        .CE(1'b1),
        .D(trace_read_en),
        .Q(\trace_data_ack_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \trace_data_ack_reg[1] 
       (.C(out[1]),
        .CE(1'b1),
        .D(\trace_data_ack_reg_n_0_[0] ),
        .Q(trace_data_ack),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_cap_ctrl_legacy u_ila_cap_ctrl
       (.A(trigger_i__0),
        .CAP_DONE_O_reg_0(u_ila_cap_ctrl_n_17),
        .CAP_DONE_O_reg_1(u_ila_cap_ctrl_n_18),
        .CAP_WR_EN_O_reg(cap_wr_en),
        .D(capture_ctrl_config_cs_serial_input),
        .DOUT_O(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ),
        .E(capture_ctrl_config_en),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg (u_ila_cap_ctrl_n_1),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (u_ila_cap_ctrl_n_19),
        .\I_YESLUT6.I_YES_OREG.O_reg_reg_1 (u_ila_cap_ctrl_n_21),
        .O_reg(O_reg),
        .Q(reset[1:0]),
        .SR(scnt_reset),
        .TRIGGERED_SL_I(cap_trigger_out),
        .basic_trigger(basic_trigger),
        .cap_done(cap_done),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .capture_fsm(capture_fsm),
        .capture_strg_qual(capture_strg_qual),
        .\captured_samples_reg[0] (u_ila_reset_ctrl_n_7),
        .\captured_samples_reg[9] (capture_cnt),
        .\current_state_reg[0] (arm_status),
        .dout_reg1_reg(u_ila_cap_ctrl_n_16),
        .douta0(douta0),
        .\i_intcap.CAP_ADDR_O_reg[9] (cap_wr_addr),
        .itrigger_out_reg_0(en_adv_trigger),
        .out(out[1]),
        .\probeDelay1_reg[0] (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .scnt_cmp_temp(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ),
        .shift_en_reg(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ),
        .shift_en_reg_0(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ),
        .trig_out_fsm(trig_out_fsm),
        .u_wcnt_lcmp_q(capture_qual_ctrl),
        .wcnt_hcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ),
        .wcnt_lcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_register u_ila_regs
       (.CFG_CNT_DIN(cnt_config_cs_serial_output),
        .CFG_CNT_DOUT(cnt_config_cs_serial_input),
        .D(config_fsm_data),
        .DOUT_O(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ),
        .DUMMY_I(DUMMY_I),
        .E(toggle),
        .\G_1PIPE_IFACE.s_daddr_r_reg[11] (u_ila_regs_n_45),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (u_ila_regs_n_46),
        .SEQUENCER_STATE_O(SEQUENCER_STATE_O),
        .SL_OPORT_O(SL_OPORT_O),
        .SR(read_addr_reset),
        .adv_drdy(adv_drdy),
        .adv_drdy_reg_0(adv_drdy_i_1_n_0),
        .arm_ctrl(arm_ctrl),
        .bram_en(bram_en),
        .bram_rd_en(bram_rd_en),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .capture_qual_ctrl_1(capture_qual_ctrl_1),
        .cnt_config_cs_shift_en(cnt_config_cs_shift_en),
        .\count0_reg[1]_0 (u_ila_regs_n_106),
        .\count0_reg[5]_0 (u_ila_regs_n_47),
        .\count1_reg[1]_0 (u_ila_regs_n_107),
        .\count1_reg[2]_0 (u_ila_regs_n_48),
        .count_tt(count_tt),
        .count_tt_reg_0(count_tt_i_1_n_0),
        .\current_state_reg[1] (\current_state[1]_i_2__1_n_0 ),
        .\current_state_reg[1]_0 (\current_state[1]_i_2__0__0_n_0 ),
        .\current_state_reg[1]_1 (\current_state[1]_i_3_n_0 ),
        .\current_state_reg[1]_10 (\current_state[1]_i_2__5_n_0 ),
        .\current_state_reg[1]_11 (\current_state[1]_i_2__6_n_0 ),
        .\current_state_reg[1]_12 (\current_state[1]_i_2__7_n_0 ),
        .\current_state_reg[1]_2 (\current_state[1]_i_2__0_n_0 ),
        .\current_state_reg[1]_3 (\current_state[1]_i_2__2_n_0 ),
        .\current_state_reg[1]_4 (\current_state[1]_i_2__11_n_0 ),
        .\current_state_reg[1]_5 (\current_state[1]_i_2__9_n_0 ),
        .\current_state_reg[1]_6 (\current_state[1]_i_2__8_n_0 ),
        .\current_state_reg[1]_7 (\current_state[1]_i_2__10_n_0 ),
        .\current_state_reg[1]_8 (\current_state[1]_i_2__3_n_0 ),
        .\current_state_reg[1]_9 (\current_state[1]_i_2__4_n_0 ),
        .\current_state_reg[3] (\current_state[3]_i_5__0__0_n_0 ),
        .\current_state_reg[3]_0 (\current_state[3]_i_5__0_n_0 ),
        .\current_state_reg[3]_1 (\current_state[1]_i_4_n_0 ),
        .data_out_en(data_out_en),
        .debug_data_in(debug_data_in),
        .drdy_ff9(drdy_ff9),
        .drdy_ffa(drdy_ffa),
        .en_adv_trigger_1(en_adv_trigger_1),
        .flag0_temp(flag0_temp),
        .flag1_temp(flag1_temp),
        .flag2_temp(flag2_temp),
        .flag3_temp(flag3_temp),
        .halt_ctrl(halt_ctrl),
        .ila_clk_flag_reg_0(p_1_in_0),
        .ila_clk_flag_reg_1(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .ila_clk_flag_reg_2(ila_clk_flag_i_1_n_0),
        .in0(use_probe_debug_circuit_1),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .next_state_ila(next_state_ila),
        .out(out),
        .\parallel_dout_reg[15] (qual_strg_config_cs_serial_input),
        .\parallel_dout_reg[15]_0 (capture_ctrl_config_cs_serial_input),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
        .read_data_en(read_data_en),
        .read_reset_addr(read_reset_addr),
        .s_daddr_o(s_daddr),
        .s_dclk_flag_sync2_reg_0(u_ila_regs_n_33),
        .s_den_o(s_den),
        .s_dwe_o(s_dwe),
        .s_rst_o(s_rst),
        .scnt_cmp_temp(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ),
        .shift_en_reg(qual_strg_config_cs_shift_en),
        .shift_en_reg_0(capture_ctrl_config_en),
        .\shift_reg0_reg[2]_0 (u_ila_regs_n_36),
        .\shift_reg0_reg[2]_1 (\shift_reg0[2]_i_1_n_0 ),
        .\shift_reg1_reg[11]_0 (u_ila_regs_n_38),
        .\shift_reg1_reg[11]_1 (\shift_reg1[11]_i_1_n_0 ),
        .\slaveRegDo_mux_0[4]_i_2 (\slaveRegDo_mux_0[4]_i_13_n_0 ),
        .\slaveRegDo_mux_2_reg[5]_0 (\I_EN_CTL_EQ1.temp_en_i_3_n_0 ),
        .\slaveRegDo_mux_6_reg[0]_0 (\slaveRegDo_mux_6[15]_i_6_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en),
        .toggle_rd(toggle_rd),
        .toggle_rd_reg(u_ila_regs_n_59),
        .toggle_reg(u_ila_regs_n_61),
        .u_wcnt_hcmp_q(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ),
        .u_wcnt_lcmp_q(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ),
        .wcnt_hcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ),
        .wcnt_lcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ),
        .xsdb_rden_ff8(xsdb_rden_ff8),
        .\xsdb_reg_reg[0] (u_ila_regs_n_40),
        .\xsdb_reg_reg[0]_0 (xsdb_memory_read_inst_n_4),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg[15]_i_2__2__0_n_0 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg[15]_i_2__3__0_n_0 ),
        .\xsdb_reg_reg[0]_3 (\xsdb_reg[15]_i_2__6_n_0 ),
        .\xsdb_reg_reg[0]_4 (\xsdb_reg[15]_i_2__1__0_n_0 ),
        .\xsdb_reg_reg[0]_5 (\xsdb_reg[15]_i_3__3_n_0 ),
        .\xsdb_reg_reg[0]_6 (\xsdb_reg[15]_i_2__0__0_n_0 ),
        .\xsdb_reg_reg[10] (xsdb_memory_read_inst_n_20),
        .\xsdb_reg_reg[11] (xsdb_memory_read_inst_n_19),
        .\xsdb_reg_reg[12] (xsdb_memory_read_inst_n_18),
        .\xsdb_reg_reg[13] (xsdb_memory_read_inst_n_17),
        .\xsdb_reg_reg[14] (xsdb_memory_read_inst_n_16),
        .\xsdb_reg_reg[15] (xsdb_memory_read_inst_n_2),
        .\xsdb_reg_reg[15]_0 (xsdb_memory_read_inst_n_15),
        .\xsdb_reg_reg[15]_1 (en_adv_trigger),
        .\xsdb_reg_reg[15]_2 (config_fsm_data_rd),
        .\xsdb_reg_reg[1] (u_ila_regs_n_39),
        .\xsdb_reg_reg[1]_0 (xsdb_memory_read_inst_n_3),
        .\xsdb_reg_reg[1]_1 ({O_reg,u_ila_cap_ctrl_n_1}),
        .\xsdb_reg_reg[2] (xsdb_memory_read_inst_n_28),
        .\xsdb_reg_reg[3] (xsdb_memory_read_inst_n_27),
        .\xsdb_reg_reg[3]_0 ({cap_done,cap_trigger_out,halt_status,arm_status}),
        .\xsdb_reg_reg[4] (xsdb_memory_read_inst_n_26),
        .\xsdb_reg_reg[5] (xsdb_memory_read_inst_n_25),
        .\xsdb_reg_reg[6] (xsdb_memory_read_inst_n_24),
        .\xsdb_reg_reg[7] (xsdb_memory_read_inst_n_23),
        .\xsdb_reg_reg[8] (xsdb_memory_read_inst_n_22),
        .\xsdb_reg_reg[9] (xsdb_memory_read_inst_n_21),
        .\xsdb_reg_reg[9]_0 (capture_cnt));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_reset_ctrl u_ila_reset_ctrl
       (.Q({u_ila_reset_ctrl_n_2,reset[3],reset[1:0]}),
        .\SEQUENCER_STATE_O_reg[8] (u_ila_cap_ctrl_n_1),
        .arm_ctrl(arm_ctrl),
        .cap_done(cap_done),
        .current_state(current_state[3]),
        .dout_reg1_reg({halt_status,arm_status}),
        .dout_reg1_reg_0(u_ila_reset_ctrl_n_6),
        .halt_ctrl(halt_ctrl),
        .last_din_reg(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .out(out[1]),
        .\reset_out_reg[0]_0 (u_ila_reset_ctrl_n_7));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_trigger u_trig
       (.ADDRA({address,u_trig_n_47}),
        .D(probe_data),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q({u_ila_reset_ctrl_n_2,reset[3],reset[0]}),
        .\TRIGGER_EQ_reg[0]_0 (u_trig_n_48),
        .capture_strg_qual(capture_strg_qual),
        .current_state(current_state),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out[1]),
        .\parallel_dout_reg[15] (qual_strg_config_cs_shift_en),
        .probe0(probe0[20:16]),
        .probe1(probe1),
        .probe2(probe2),
        .\probeDelay1_reg[0] (use_probe_debug_circuit),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
        .shift_en_reg(qual_strg_config_cs_serial_input),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE use_probe_debug_circuit_2_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(use_probe_debug_circuit_1),
        .Q(use_probe_debug_circuit_2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE use_probe_debug_circuit_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(use_probe_debug_circuit_2),
        .Q(use_probe_debug_circuit),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_generic_memrd xsdb_memory_read_inst
       (.D(trace_read_en),
        .Q(trace_read_addr),
        .SR(read_addr_reset),
        .\curr_read_block_reg[2]_0 (xsdb_memory_read_inst_n_2),
        .\current_state_reg[3]_0 (trace_data_ack),
        .data_out_en(data_out_en),
        .\input_data_reg[50]_0 (xsdb_memory_read_inst_n_28),
        .\input_data_reg[51]_0 (xsdb_memory_read_inst_n_27),
        .\input_data_reg[52]_0 (xsdb_memory_read_inst_n_26),
        .\input_data_reg[53]_0 (xsdb_memory_read_inst_n_25),
        .\input_data_reg[54]_0 (xsdb_memory_read_inst_n_24),
        .\input_data_reg[55]_0 (xsdb_memory_read_inst_n_23),
        .\input_data_reg[56]_0 (xsdb_memory_read_inst_n_22),
        .\input_data_reg[57]_0 (xsdb_memory_read_inst_n_21),
        .\input_data_reg[58]_0 (xsdb_memory_read_inst_n_20),
        .\input_data_reg[59]_0 (xsdb_memory_read_inst_n_19),
        .\input_data_reg[60]_0 (xsdb_memory_read_inst_n_18),
        .\input_data_reg[61]_0 (xsdb_memory_read_inst_n_17),
        .\input_data_reg[62]_0 (xsdb_memory_read_inst_n_16),
        .\input_data_reg[63]_0 (xsdb_memory_read_inst_n_15),
        .\input_data_reg[64]_0 (xsdb_memory_read_inst_n_4),
        .\input_data_reg[65]_0 (xsdb_memory_read_inst_n_3),
        .\input_data_reg[65]_1 (mem_data_out),
        .out(out[1]),
        .read_data_en(read_data_en),
        .read_reset_addr(read_reset_addr),
        .\xsdb_reg_reg[0] (u_ila_regs_n_40),
        .\xsdb_reg_reg[1] (u_ila_regs_n_39));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \xsdb_reg[15]_i_2__0__0 
       (.I0(s_daddr[0]),
        .I1(s_daddr[1]),
        .O(\xsdb_reg[15]_i_2__0__0_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \xsdb_reg[15]_i_2__1__0 
       (.I0(s_daddr[1]),
        .I1(s_daddr[0]),
        .O(\xsdb_reg[15]_i_2__1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \xsdb_reg[15]_i_2__2__0 
       (.I0(s_daddr[0]),
        .I1(s_daddr[1]),
        .I2(s_daddr[2]),
        .I3(\xsdb_reg[15]_i_2__3__0_n_0 ),
        .O(\xsdb_reg[15]_i_2__2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \xsdb_reg[15]_i_2__3__0 
       (.I0(s_daddr[11]),
        .I1(s_daddr[12]),
        .I2(s_daddr[9]),
        .I3(s_daddr[10]),
        .I4(s_dwe),
        .I5(s_den),
        .O(\xsdb_reg[15]_i_2__3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \xsdb_reg[15]_i_2__6 
       (.I0(s_daddr[5]),
        .I1(s_daddr[6]),
        .I2(s_daddr[3]),
        .I3(s_daddr[4]),
        .I4(s_daddr[8]),
        .I5(s_daddr[7]),
        .O(\xsdb_reg[15]_i_2__6_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \xsdb_reg[15]_i_3__3 
       (.I0(s_dwe),
        .I1(s_den),
        .O(\xsdb_reg[15]_i_3__3_n_0 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_counter
   (CFG_CNT_DOUT,
    COUNTER_EQ,
    \counter_reg[0] ,
    out,
    Q,
    SR,
    CNT_CTRL,
    CFG_CNT_DIN,
    cnt_config_cs_shift_en);
  output [3:0]CFG_CNT_DOUT;
  output [3:0]COUNTER_EQ;
  input \counter_reg[0] ;
  input [0:0]out;
  input [1:0]Q;
  input [0:0]SR;
  input [7:0]CNT_CTRL;
  input [3:0]CFG_CNT_DIN;
  input [3:0]cnt_config_cs_shift_en;

  wire [3:0]CFG_CNT_DIN;
  wire [3:0]CFG_CNT_DOUT;
  wire [7:0]CNT_CTRL;
  wire [3:0]COUNTER_EQ;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [3:0]cnt_config_cs_shift_en;
  wire \counter_reg[0] ;
  wire [0:0]out;

  (* CNT_MAX = "17'b10000000000000000" *) 
  (* C_COUNTER_WIDTH = "17" *) 
  (* DONT_TOUCH *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter__1 \G_COUNTER[0].U_COUNTER 
       (.CFG_CLK(out),
        .CLK(\counter_reg[0] ),
        .CNT_CTRL(CNT_CTRL[1:0]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[0]),
        .CNT_LOAD_EN(cnt_config_cs_shift_en[0]),
        .CNT_LOAD_IN(CFG_CNT_DIN[0]),
        .COUNTER_MATCH(COUNTER_EQ[0]),
        .RESET(Q),
        .SCNT_RESET(SR));
  (* CNT_MAX = "17'b10000000000000000" *) 
  (* C_COUNTER_WIDTH = "17" *) 
  (* DONT_TOUCH *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter__2 \G_COUNTER[1].U_COUNTER 
       (.CFG_CLK(out),
        .CLK(\counter_reg[0] ),
        .CNT_CTRL(CNT_CTRL[3:2]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[1]),
        .CNT_LOAD_EN(cnt_config_cs_shift_en[1]),
        .CNT_LOAD_IN(CFG_CNT_DIN[1]),
        .COUNTER_MATCH(COUNTER_EQ[1]),
        .RESET(Q),
        .SCNT_RESET(SR));
  (* CNT_MAX = "17'b10000000000000000" *) 
  (* C_COUNTER_WIDTH = "17" *) 
  (* DONT_TOUCH *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter__3 \G_COUNTER[2].U_COUNTER 
       (.CFG_CLK(out),
        .CLK(\counter_reg[0] ),
        .CNT_CTRL(CNT_CTRL[5:4]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[2]),
        .CNT_LOAD_EN(cnt_config_cs_shift_en[2]),
        .CNT_LOAD_IN(CFG_CNT_DIN[2]),
        .COUNTER_MATCH(COUNTER_EQ[2]),
        .RESET(Q),
        .SCNT_RESET(SR));
  (* CNT_MAX = "17'b10000000000000000" *) 
  (* C_COUNTER_WIDTH = "17" *) 
  (* DONT_TOUCH *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_generic_counter \G_COUNTER[3].U_COUNTER 
       (.CFG_CLK(out),
        .CLK(\counter_reg[0] ),
        .CNT_CTRL(CNT_CTRL[7:6]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[3]),
        .CNT_LOAD_EN(cnt_config_cs_shift_en[3]),
        .CNT_LOAD_IN(CFG_CNT_DIN[3]),
        .COUNTER_MATCH(COUNTER_EQ[3]),
        .RESET(Q),
        .SCNT_RESET(SR));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_fsm_memory_read
   (toggle_rd,
    E,
    CFG_BRAM_DATA,
    FSM_BRAM_CONFIG_DATA_I,
    toggle_rd_reg_0,
    out,
    toggle_reg_0,
    D,
    \CFG_DATA_O_reg[7]_0 );
  output toggle_rd;
  output [0:0]E;
  output [23:0]CFG_BRAM_DATA;
  output [15:0]FSM_BRAM_CONFIG_DATA_I;
  input toggle_rd_reg_0;
  input [0:0]out;
  input toggle_reg_0;
  input [15:0]D;
  input [23:0]\CFG_DATA_O_reg[7]_0 ;

  wire \BRAM_DATA[15]_i_1_n_0 ;
  wire [23:0]CFG_BRAM_DATA;
  wire \CFG_DATA_O[0]_i_1_n_0 ;
  wire \CFG_DATA_O[15]_i_1_n_0 ;
  wire \CFG_DATA_O[1]_i_1_n_0 ;
  wire \CFG_DATA_O[2]_i_1_n_0 ;
  wire \CFG_DATA_O[3]_i_1_n_0 ;
  wire \CFG_DATA_O[4]_i_1_n_0 ;
  wire \CFG_DATA_O[5]_i_1_n_0 ;
  wire \CFG_DATA_O[6]_i_1_n_0 ;
  wire \CFG_DATA_O[7]_i_1_n_0 ;
  wire [23:0]\CFG_DATA_O_reg[7]_0 ;
  wire [15:0]D;
  wire [0:0]E;
  wire [15:0]FSM_BRAM_CONFIG_DATA_I;
  wire [0:0]out;
  wire toggle_rd;
  wire toggle_rd_reg_0;
  wire toggle_reg_0;

  LUT1 #(
    .INIT(2'h1)) 
    \BRAM_DATA[15]_i_1 
       (.I0(E),
        .O(\BRAM_DATA[15]_i_1_n_0 ));
  FDRE \BRAM_DATA_reg[0] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[0]),
        .Q(CFG_BRAM_DATA[0]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[10] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[10]),
        .Q(CFG_BRAM_DATA[10]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[11] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[11]),
        .Q(CFG_BRAM_DATA[11]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[12] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[12]),
        .Q(CFG_BRAM_DATA[12]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[13] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[13]),
        .Q(CFG_BRAM_DATA[13]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[14] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[14]),
        .Q(CFG_BRAM_DATA[14]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[15] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[15]),
        .Q(CFG_BRAM_DATA[15]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[16] 
       (.C(out),
        .CE(E),
        .D(D[0]),
        .Q(CFG_BRAM_DATA[16]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[17] 
       (.C(out),
        .CE(E),
        .D(D[1]),
        .Q(CFG_BRAM_DATA[17]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[18] 
       (.C(out),
        .CE(E),
        .D(D[2]),
        .Q(CFG_BRAM_DATA[18]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[19] 
       (.C(out),
        .CE(E),
        .D(D[3]),
        .Q(CFG_BRAM_DATA[19]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[1] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[1]),
        .Q(CFG_BRAM_DATA[1]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[20] 
       (.C(out),
        .CE(E),
        .D(D[4]),
        .Q(CFG_BRAM_DATA[20]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[21] 
       (.C(out),
        .CE(E),
        .D(D[5]),
        .Q(CFG_BRAM_DATA[21]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[22] 
       (.C(out),
        .CE(E),
        .D(D[6]),
        .Q(CFG_BRAM_DATA[22]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[23] 
       (.C(out),
        .CE(E),
        .D(D[7]),
        .Q(CFG_BRAM_DATA[23]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[2] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[2]),
        .Q(CFG_BRAM_DATA[2]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[3] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[3]),
        .Q(CFG_BRAM_DATA[3]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[4] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[4]),
        .Q(CFG_BRAM_DATA[4]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[5] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[5]),
        .Q(CFG_BRAM_DATA[5]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[6] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[6]),
        .Q(CFG_BRAM_DATA[6]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[7] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[7]),
        .Q(CFG_BRAM_DATA[7]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[8] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[8]),
        .Q(CFG_BRAM_DATA[8]),
        .R(1'b0));
  FDRE \BRAM_DATA_reg[9] 
       (.C(out),
        .CE(\BRAM_DATA[15]_i_1_n_0 ),
        .D(D[9]),
        .Q(CFG_BRAM_DATA[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[0]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [0]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [16]),
        .O(\CFG_DATA_O[0]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \CFG_DATA_O[15]_i_1 
       (.I0(toggle_rd),
        .O(\CFG_DATA_O[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[1]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [1]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [17]),
        .O(\CFG_DATA_O[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[2]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [2]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [18]),
        .O(\CFG_DATA_O[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[3]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [3]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [19]),
        .O(\CFG_DATA_O[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[4]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [4]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [20]),
        .O(\CFG_DATA_O[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[5]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [5]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [21]),
        .O(\CFG_DATA_O[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[6]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [6]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [22]),
        .O(\CFG_DATA_O[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \CFG_DATA_O[7]_i_1 
       (.I0(\CFG_DATA_O_reg[7]_0 [7]),
        .I1(toggle_rd),
        .I2(\CFG_DATA_O_reg[7]_0 [23]),
        .O(\CFG_DATA_O[7]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[0] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[0]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[0]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[10] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [10]),
        .Q(FSM_BRAM_CONFIG_DATA_I[10]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[11] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [11]),
        .Q(FSM_BRAM_CONFIG_DATA_I[11]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[12] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [12]),
        .Q(FSM_BRAM_CONFIG_DATA_I[12]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[13] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [13]),
        .Q(FSM_BRAM_CONFIG_DATA_I[13]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[14] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [14]),
        .Q(FSM_BRAM_CONFIG_DATA_I[14]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[15] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [15]),
        .Q(FSM_BRAM_CONFIG_DATA_I[15]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[1] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[1]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[1]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[2] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[2]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[2]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[3] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[3]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[3]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[4] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[4]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[4]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[5] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[5]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[5]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[6] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[6]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[6]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[7] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O[7]_i_1_n_0 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[7]),
        .R(1'b0));
  FDRE \CFG_DATA_O_reg[8] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [8]),
        .Q(FSM_BRAM_CONFIG_DATA_I[8]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE \CFG_DATA_O_reg[9] 
       (.C(out),
        .CE(1'b1),
        .D(\CFG_DATA_O_reg[7]_0 [9]),
        .Q(FSM_BRAM_CONFIG_DATA_I[9]),
        .R(\CFG_DATA_O[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    toggle_rd_reg
       (.C(out),
        .CE(1'b1),
        .D(toggle_rd_reg_0),
        .Q(toggle_rd),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    toggle_reg
       (.C(out),
        .CE(1'b1),
        .D(toggle_reg_0),
        .Q(E),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_register
   (s_rst_o,
    s_den_o,
    s_dwe_o,
    s_daddr_o,
    SL_OPORT_O,
    s_dclk_flag_sync2_reg_0,
    ila_clk_flag_reg_0,
    drdy_ff9,
    \shift_reg0_reg[2]_0 ,
    drdy_ffa,
    \shift_reg1_reg[11]_0 ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    xsdb_rden_ff8,
    next_state_ila,
    count_tt,
    adv_drdy,
    \G_1PIPE_IFACE.s_daddr_r_reg[11] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \count0_reg[5]_0 ,
    \count1_reg[2]_0 ,
    read_reset_addr,
    toggle_rd_reg,
    bram_rd_en,
    toggle_reg,
    bram_en,
    D,
    halt_ctrl,
    arm_ctrl,
    in0,
    SR,
    en_adv_trigger_1,
    capture_qual_ctrl_1,
    debug_data_in,
    scnt_cmp_temp,
    wcnt_lcmp_temp,
    wcnt_hcmp_temp,
    read_data_en,
    \count0_reg[1]_0 ,
    \count1_reg[1]_0 ,
    shift_en_reg,
    qual_strg_config_cs_serial_output,
    shift_en_reg_0,
    capture_ctrl_config_serial_output,
    mu_config_cs_shift_en,
    mu_config_cs_serial_output,
    tc_config_cs_shift_en,
    tc_config_cs_serial_output,
    cnt_config_cs_shift_en,
    CFG_CNT_DIN,
    out,
    \xsdb_reg_reg[15] ,
    data_out_en,
    \xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    ila_clk_flag_reg_1,
    DUMMY_I,
    count_tt_reg_0,
    \shift_reg0_reg[2]_1 ,
    \shift_reg1_reg[11]_1 ,
    adv_drdy_reg_0,
    ila_clk_flag_reg_2,
    \slaveRegDo_mux_2_reg[5]_0 ,
    \slaveRegDo_mux_6_reg[0]_0 ,
    \slaveRegDo_mux_0[4]_i_2 ,
    toggle_rd,
    E,
    \xsdb_reg_reg[15]_1 ,
    \xsdb_reg_reg[15]_2 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[1]_1 ,
    flag3_temp,
    flag2_temp,
    flag1_temp,
    flag0_temp,
    SEQUENCER_STATE_O,
    DOUT_O,
    u_wcnt_lcmp_q,
    u_wcnt_hcmp_q,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 ,
    \xsdb_reg_reg[0]_3 ,
    \xsdb_reg_reg[0]_4 ,
    \xsdb_reg_reg[0]_5 ,
    \xsdb_reg_reg[0]_6 ,
    \parallel_dout_reg[15] ,
    \current_state_reg[1] ,
    \current_state_reg[3] ,
    \parallel_dout_reg[15]_0 ,
    mu_config_cs_serial_input,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    \current_state_reg[1]_2 ,
    \current_state_reg[1]_3 ,
    tc_config_cs_serial_input,
    \current_state_reg[1]_4 ,
    \current_state_reg[1]_5 ,
    \current_state_reg[1]_6 ,
    \current_state_reg[1]_7 ,
    \current_state_reg[3]_1 ,
    \current_state_reg[1]_8 ,
    \current_state_reg[1]_9 ,
    \current_state_reg[1]_10 ,
    \current_state_reg[1]_11 ,
    \current_state_reg[1]_12 ,
    CFG_CNT_DOUT);
  output s_rst_o;
  output s_den_o;
  output s_dwe_o;
  output [12:0]s_daddr_o;
  output [16:0]SL_OPORT_O;
  output s_dclk_flag_sync2_reg_0;
  output ila_clk_flag_reg_0;
  output drdy_ff9;
  output \shift_reg0_reg[2]_0 ;
  output drdy_ffa;
  output \shift_reg1_reg[11]_0 ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  output xsdb_rden_ff8;
  output next_state_ila;
  output count_tt;
  output adv_drdy;
  output \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \count0_reg[5]_0 ;
  output \count1_reg[2]_0 ;
  output [9:0]read_reset_addr;
  output toggle_rd_reg;
  output bram_rd_en;
  output toggle_reg;
  output bram_en;
  output [15:0]D;
  output halt_ctrl;
  output arm_ctrl;
  output in0;
  output [0:0]SR;
  output en_adv_trigger_1;
  output [1:0]capture_qual_ctrl_1;
  output [15:0]debug_data_in;
  output scnt_cmp_temp;
  output wcnt_lcmp_temp;
  output wcnt_hcmp_temp;
  output read_data_en;
  output \count0_reg[1]_0 ;
  output \count1_reg[1]_0 ;
  output [0:0]shift_en_reg;
  output qual_strg_config_cs_serial_output;
  output [0:0]shift_en_reg_0;
  output capture_ctrl_config_serial_output;
  output [11:0]mu_config_cs_shift_en;
  output [11:0]mu_config_cs_serial_output;
  output [31:0]tc_config_cs_shift_en;
  output [31:0]tc_config_cs_serial_output;
  output [3:0]cnt_config_cs_shift_en;
  output [3:0]CFG_CNT_DIN;
  input [36:0]out;
  input \xsdb_reg_reg[15] ;
  input data_out_en;
  input \xsdb_reg_reg[15]_0 ;
  input \xsdb_reg_reg[14] ;
  input \xsdb_reg_reg[13] ;
  input \xsdb_reg_reg[12] ;
  input \xsdb_reg_reg[11] ;
  input \xsdb_reg_reg[10] ;
  input \xsdb_reg_reg[9] ;
  input \xsdb_reg_reg[8] ;
  input \xsdb_reg_reg[7] ;
  input \xsdb_reg_reg[6] ;
  input \xsdb_reg_reg[5] ;
  input \xsdb_reg_reg[4] ;
  input \xsdb_reg_reg[3] ;
  input \xsdb_reg_reg[2] ;
  input \xsdb_reg_reg[1]_0 ;
  input \xsdb_reg_reg[0]_0 ;
  input ila_clk_flag_reg_1;
  input DUMMY_I;
  input count_tt_reg_0;
  input \shift_reg0_reg[2]_1 ;
  input \shift_reg1_reg[11]_1 ;
  input adv_drdy_reg_0;
  input ila_clk_flag_reg_2;
  input \slaveRegDo_mux_2_reg[5]_0 ;
  input \slaveRegDo_mux_6_reg[0]_0 ;
  input \slaveRegDo_mux_0[4]_i_2 ;
  input toggle_rd;
  input [0:0]E;
  input \xsdb_reg_reg[15]_1 ;
  input [15:0]\xsdb_reg_reg[15]_2 ;
  input [3:0]\xsdb_reg_reg[3]_0 ;
  input [9:0]\xsdb_reg_reg[9]_0 ;
  input [1:0]\xsdb_reg_reg[1]_1 ;
  input flag3_temp;
  input flag2_temp;
  input flag1_temp;
  input flag0_temp;
  input [15:0]SEQUENCER_STATE_O;
  input DOUT_O;
  input u_wcnt_lcmp_q;
  input u_wcnt_hcmp_q;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;
  input \xsdb_reg_reg[0]_3 ;
  input \xsdb_reg_reg[0]_4 ;
  input \xsdb_reg_reg[0]_5 ;
  input \xsdb_reg_reg[0]_6 ;
  input [0:0]\parallel_dout_reg[15] ;
  input \current_state_reg[1] ;
  input \current_state_reg[3] ;
  input [0:0]\parallel_dout_reg[15]_0 ;
  input [11:0]mu_config_cs_serial_input;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[1]_2 ;
  input \current_state_reg[1]_3 ;
  input [31:0]tc_config_cs_serial_input;
  input \current_state_reg[1]_4 ;
  input \current_state_reg[1]_5 ;
  input \current_state_reg[1]_6 ;
  input \current_state_reg[1]_7 ;
  input \current_state_reg[3]_1 ;
  input \current_state_reg[1]_8 ;
  input \current_state_reg[1]_9 ;
  input \current_state_reg[1]_10 ;
  input \current_state_reg[1]_11 ;
  input \current_state_reg[1]_12 ;
  input [3:0]CFG_CNT_DOUT;

  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ;
  wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ;
  wire [3:0]CFG_CNT_DIN;
  wire [3:0]CFG_CNT_DOUT;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_0 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_1 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_10 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_11 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_12 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_13 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_14 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_15 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_2 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_3 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_4 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_5 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_6 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_7 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_8 ;
  wire \CNT.CNT_SRL[2].cnt_srl_reg_n_9 ;
  wire \CNT.CNT_SRL[3].cnt_srl_reg_n_0 ;
  wire [15:0]D;
  wire DOUT_O;
  wire DUMMY_I;
  wire [0:0]E;
  wire FSM_BRAM_EN_RB_O_i_2_n_0;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \MU_SRL[11].mu_srl_reg_n_0 ;
  wire \MU_SRL[11].mu_srl_reg_n_1 ;
  wire \MU_SRL[11].mu_srl_reg_n_10 ;
  wire \MU_SRL[11].mu_srl_reg_n_11 ;
  wire \MU_SRL[11].mu_srl_reg_n_12 ;
  wire \MU_SRL[11].mu_srl_reg_n_13 ;
  wire \MU_SRL[11].mu_srl_reg_n_14 ;
  wire \MU_SRL[11].mu_srl_reg_n_15 ;
  wire \MU_SRL[11].mu_srl_reg_n_2 ;
  wire \MU_SRL[11].mu_srl_reg_n_3 ;
  wire \MU_SRL[11].mu_srl_reg_n_4 ;
  wire \MU_SRL[11].mu_srl_reg_n_5 ;
  wire \MU_SRL[11].mu_srl_reg_n_6 ;
  wire \MU_SRL[11].mu_srl_reg_n_7 ;
  wire \MU_SRL[11].mu_srl_reg_n_8 ;
  wire \MU_SRL[11].mu_srl_reg_n_9 ;
  wire \MU_SRL[3].mu_srl_reg_n_0 ;
  wire \MU_SRL[3].mu_srl_reg_n_1 ;
  wire \MU_SRL[3].mu_srl_reg_n_10 ;
  wire \MU_SRL[3].mu_srl_reg_n_11 ;
  wire \MU_SRL[3].mu_srl_reg_n_12 ;
  wire \MU_SRL[3].mu_srl_reg_n_13 ;
  wire \MU_SRL[3].mu_srl_reg_n_14 ;
  wire \MU_SRL[3].mu_srl_reg_n_15 ;
  wire \MU_SRL[3].mu_srl_reg_n_2 ;
  wire \MU_SRL[3].mu_srl_reg_n_3 ;
  wire \MU_SRL[3].mu_srl_reg_n_4 ;
  wire \MU_SRL[3].mu_srl_reg_n_5 ;
  wire \MU_SRL[3].mu_srl_reg_n_6 ;
  wire \MU_SRL[3].mu_srl_reg_n_7 ;
  wire \MU_SRL[3].mu_srl_reg_n_8 ;
  wire \MU_SRL[3].mu_srl_reg_n_9 ;
  wire \MU_SRL[7].mu_srl_reg_n_0 ;
  wire \MU_SRL[7].mu_srl_reg_n_1 ;
  wire \MU_SRL[7].mu_srl_reg_n_10 ;
  wire \MU_SRL[7].mu_srl_reg_n_11 ;
  wire \MU_SRL[7].mu_srl_reg_n_12 ;
  wire \MU_SRL[7].mu_srl_reg_n_13 ;
  wire \MU_SRL[7].mu_srl_reg_n_14 ;
  wire \MU_SRL[7].mu_srl_reg_n_15 ;
  wire \MU_SRL[7].mu_srl_reg_n_2 ;
  wire \MU_SRL[7].mu_srl_reg_n_3 ;
  wire \MU_SRL[7].mu_srl_reg_n_4 ;
  wire \MU_SRL[7].mu_srl_reg_n_5 ;
  wire \MU_SRL[7].mu_srl_reg_n_6 ;
  wire \MU_SRL[7].mu_srl_reg_n_7 ;
  wire \MU_SRL[7].mu_srl_reg_n_8 ;
  wire \MU_SRL[7].mu_srl_reg_n_9 ;
  wire [15:0]SEQUENCER_STATE_O;
  wire [16:0]SL_OPORT_O;
  wire [0:0]SR;
  wire \TC_SRL[11].tc_srl_reg_n_0 ;
  wire \TC_SRL[11].tc_srl_reg_n_1 ;
  wire \TC_SRL[11].tc_srl_reg_n_10 ;
  wire \TC_SRL[11].tc_srl_reg_n_11 ;
  wire \TC_SRL[11].tc_srl_reg_n_12 ;
  wire \TC_SRL[11].tc_srl_reg_n_13 ;
  wire \TC_SRL[11].tc_srl_reg_n_14 ;
  wire \TC_SRL[11].tc_srl_reg_n_15 ;
  wire \TC_SRL[11].tc_srl_reg_n_2 ;
  wire \TC_SRL[11].tc_srl_reg_n_3 ;
  wire \TC_SRL[11].tc_srl_reg_n_4 ;
  wire \TC_SRL[11].tc_srl_reg_n_5 ;
  wire \TC_SRL[11].tc_srl_reg_n_6 ;
  wire \TC_SRL[11].tc_srl_reg_n_7 ;
  wire \TC_SRL[11].tc_srl_reg_n_8 ;
  wire \TC_SRL[11].tc_srl_reg_n_9 ;
  wire \TC_SRL[15].tc_srl_reg_n_0 ;
  wire \TC_SRL[15].tc_srl_reg_n_1 ;
  wire \TC_SRL[15].tc_srl_reg_n_10 ;
  wire \TC_SRL[15].tc_srl_reg_n_11 ;
  wire \TC_SRL[15].tc_srl_reg_n_12 ;
  wire \TC_SRL[15].tc_srl_reg_n_13 ;
  wire \TC_SRL[15].tc_srl_reg_n_14 ;
  wire \TC_SRL[15].tc_srl_reg_n_15 ;
  wire \TC_SRL[15].tc_srl_reg_n_2 ;
  wire \TC_SRL[15].tc_srl_reg_n_3 ;
  wire \TC_SRL[15].tc_srl_reg_n_4 ;
  wire \TC_SRL[15].tc_srl_reg_n_5 ;
  wire \TC_SRL[15].tc_srl_reg_n_6 ;
  wire \TC_SRL[15].tc_srl_reg_n_7 ;
  wire \TC_SRL[15].tc_srl_reg_n_8 ;
  wire \TC_SRL[15].tc_srl_reg_n_9 ;
  wire \TC_SRL[19].tc_srl_reg_n_0 ;
  wire \TC_SRL[19].tc_srl_reg_n_1 ;
  wire \TC_SRL[19].tc_srl_reg_n_10 ;
  wire \TC_SRL[19].tc_srl_reg_n_11 ;
  wire \TC_SRL[19].tc_srl_reg_n_12 ;
  wire \TC_SRL[19].tc_srl_reg_n_13 ;
  wire \TC_SRL[19].tc_srl_reg_n_14 ;
  wire \TC_SRL[19].tc_srl_reg_n_15 ;
  wire \TC_SRL[19].tc_srl_reg_n_2 ;
  wire \TC_SRL[19].tc_srl_reg_n_3 ;
  wire \TC_SRL[19].tc_srl_reg_n_4 ;
  wire \TC_SRL[19].tc_srl_reg_n_5 ;
  wire \TC_SRL[19].tc_srl_reg_n_6 ;
  wire \TC_SRL[19].tc_srl_reg_n_7 ;
  wire \TC_SRL[19].tc_srl_reg_n_8 ;
  wire \TC_SRL[19].tc_srl_reg_n_9 ;
  wire \TC_SRL[23].tc_srl_reg_n_0 ;
  wire \TC_SRL[23].tc_srl_reg_n_1 ;
  wire \TC_SRL[23].tc_srl_reg_n_10 ;
  wire \TC_SRL[23].tc_srl_reg_n_11 ;
  wire \TC_SRL[23].tc_srl_reg_n_12 ;
  wire \TC_SRL[23].tc_srl_reg_n_13 ;
  wire \TC_SRL[23].tc_srl_reg_n_14 ;
  wire \TC_SRL[23].tc_srl_reg_n_15 ;
  wire \TC_SRL[23].tc_srl_reg_n_2 ;
  wire \TC_SRL[23].tc_srl_reg_n_3 ;
  wire \TC_SRL[23].tc_srl_reg_n_4 ;
  wire \TC_SRL[23].tc_srl_reg_n_5 ;
  wire \TC_SRL[23].tc_srl_reg_n_6 ;
  wire \TC_SRL[23].tc_srl_reg_n_7 ;
  wire \TC_SRL[23].tc_srl_reg_n_8 ;
  wire \TC_SRL[23].tc_srl_reg_n_9 ;
  wire \TC_SRL[27].tc_srl_reg_n_0 ;
  wire \TC_SRL[27].tc_srl_reg_n_1 ;
  wire \TC_SRL[27].tc_srl_reg_n_10 ;
  wire \TC_SRL[27].tc_srl_reg_n_11 ;
  wire \TC_SRL[27].tc_srl_reg_n_12 ;
  wire \TC_SRL[27].tc_srl_reg_n_13 ;
  wire \TC_SRL[27].tc_srl_reg_n_14 ;
  wire \TC_SRL[27].tc_srl_reg_n_15 ;
  wire \TC_SRL[27].tc_srl_reg_n_2 ;
  wire \TC_SRL[27].tc_srl_reg_n_3 ;
  wire \TC_SRL[27].tc_srl_reg_n_4 ;
  wire \TC_SRL[27].tc_srl_reg_n_5 ;
  wire \TC_SRL[27].tc_srl_reg_n_6 ;
  wire \TC_SRL[27].tc_srl_reg_n_7 ;
  wire \TC_SRL[27].tc_srl_reg_n_8 ;
  wire \TC_SRL[27].tc_srl_reg_n_9 ;
  wire \TC_SRL[31].tc_srl_reg_n_0 ;
  wire \TC_SRL[31].tc_srl_reg_n_1 ;
  wire \TC_SRL[31].tc_srl_reg_n_10 ;
  wire \TC_SRL[31].tc_srl_reg_n_11 ;
  wire \TC_SRL[31].tc_srl_reg_n_12 ;
  wire \TC_SRL[31].tc_srl_reg_n_13 ;
  wire \TC_SRL[31].tc_srl_reg_n_14 ;
  wire \TC_SRL[31].tc_srl_reg_n_15 ;
  wire \TC_SRL[31].tc_srl_reg_n_2 ;
  wire \TC_SRL[31].tc_srl_reg_n_3 ;
  wire \TC_SRL[31].tc_srl_reg_n_4 ;
  wire \TC_SRL[31].tc_srl_reg_n_5 ;
  wire \TC_SRL[31].tc_srl_reg_n_6 ;
  wire \TC_SRL[31].tc_srl_reg_n_7 ;
  wire \TC_SRL[31].tc_srl_reg_n_8 ;
  wire \TC_SRL[31].tc_srl_reg_n_9 ;
  wire \TC_SRL[3].tc_srl_reg_n_0 ;
  wire \TC_SRL[3].tc_srl_reg_n_1 ;
  wire \TC_SRL[3].tc_srl_reg_n_10 ;
  wire \TC_SRL[3].tc_srl_reg_n_11 ;
  wire \TC_SRL[3].tc_srl_reg_n_12 ;
  wire \TC_SRL[3].tc_srl_reg_n_13 ;
  wire \TC_SRL[3].tc_srl_reg_n_14 ;
  wire \TC_SRL[3].tc_srl_reg_n_15 ;
  wire \TC_SRL[3].tc_srl_reg_n_2 ;
  wire \TC_SRL[3].tc_srl_reg_n_3 ;
  wire \TC_SRL[3].tc_srl_reg_n_4 ;
  wire \TC_SRL[3].tc_srl_reg_n_5 ;
  wire \TC_SRL[3].tc_srl_reg_n_6 ;
  wire \TC_SRL[3].tc_srl_reg_n_7 ;
  wire \TC_SRL[3].tc_srl_reg_n_8 ;
  wire \TC_SRL[3].tc_srl_reg_n_9 ;
  wire \TC_SRL[7].tc_srl_reg_n_0 ;
  wire \TC_SRL[7].tc_srl_reg_n_1 ;
  wire \TC_SRL[7].tc_srl_reg_n_10 ;
  wire \TC_SRL[7].tc_srl_reg_n_11 ;
  wire \TC_SRL[7].tc_srl_reg_n_12 ;
  wire \TC_SRL[7].tc_srl_reg_n_13 ;
  wire \TC_SRL[7].tc_srl_reg_n_14 ;
  wire \TC_SRL[7].tc_srl_reg_n_15 ;
  wire \TC_SRL[7].tc_srl_reg_n_2 ;
  wire \TC_SRL[7].tc_srl_reg_n_3 ;
  wire \TC_SRL[7].tc_srl_reg_n_4 ;
  wire \TC_SRL[7].tc_srl_reg_n_5 ;
  wire \TC_SRL[7].tc_srl_reg_n_6 ;
  wire \TC_SRL[7].tc_srl_reg_n_7 ;
  wire \TC_SRL[7].tc_srl_reg_n_8 ;
  wire \TC_SRL[7].tc_srl_reg_n_9 ;
  wire U_XSDB_SLAVE_n_1;
  wire adv_drdy;
  wire adv_drdy_reg_0;
  wire adv_rb_drdy;
  wire adv_rb_drdy1;
  wire adv_rb_drdy3_reg_srl2_n_0;
  wire adv_rb_drdy4;
  wire arm_ctrl;
  wire bram_en;
  wire bram_en_i_2_n_0;
  wire bram_rd_en;
  wire bram_rd_en_i_2_n_0;
  wire bram_rd_en_i_3_n_0;
  wire bram_rd_en_i_4_n_0;
  wire capture_ctrl_config_serial_output;
  wire [1:0]capture_qual_ctrl_1;
  wire clk_lost;
  wire \clk_lost_cnt[8]_i_1_n_0 ;
  wire \clk_lost_cnt[8]_i_4_n_0 ;
  wire [8:8]clk_lost_cnt_reg__0;
  wire \clk_lost_cnt_reg_n_0_[0] ;
  wire \clk_lost_cnt_reg_n_0_[1] ;
  wire \clk_lost_cnt_reg_n_0_[2] ;
  wire \clk_lost_cnt_reg_n_0_[3] ;
  wire \clk_lost_cnt_reg_n_0_[4] ;
  wire \clk_lost_cnt_reg_n_0_[5] ;
  wire \clk_lost_cnt_reg_n_0_[6] ;
  wire \clk_lost_cnt_reg_n_0_[7] ;
  wire clk_lost_i_1_n_0;
  wire [3:0]cnt_config_cs_shift_en;
  wire [16:0]config_fsm_addr;
  wire config_fsm_en_rb;
  wire config_fsm_we;
  wire count00;
  wire \count0_reg[1]_0 ;
  wire \count0_reg[5]_0 ;
  wire [6:0]count0_reg__0;
  wire count10;
  wire \count1_reg[1]_0 ;
  wire \count1_reg[2]_0 ;
  wire [6:0]count1_reg__0;
  wire count_tt;
  wire count_tt_reg_0;
  wire \current_state[4]_i_4_n_0 ;
  wire \current_state_reg[1] ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[1]_10 ;
  wire \current_state_reg[1]_11 ;
  wire \current_state_reg[1]_12 ;
  wire \current_state_reg[1]_2 ;
  wire \current_state_reg[1]_3 ;
  wire \current_state_reg[1]_4 ;
  wire \current_state_reg[1]_5 ;
  wire \current_state_reg[1]_6 ;
  wire \current_state_reg[1]_7 ;
  wire \current_state_reg[1]_8 ;
  wire \current_state_reg[1]_9 ;
  wire \current_state_reg[3] ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_en;
  wire [15:0]debug_data_in;
  wire [5:0]drdyCount;
  wire \drdyCount[0]_i_1_n_0 ;
  wire \drdyCount[1]_i_1_n_0 ;
  wire \drdyCount[2]_i_1_n_0 ;
  wire \drdyCount[3]_i_1_n_0 ;
  wire \drdyCount[4]_i_1_n_0 ;
  wire \drdyCount[4]_i_2_n_0 ;
  wire \drdyCount[5]_i_1_n_0 ;
  wire \drdyCount[5]_i_2_n_0 ;
  wire \drdyCount[5]_i_3_n_0 ;
  wire \drdyCount[5]_i_4_n_0 ;
  wire \drdyCount[5]_i_5_n_0 ;
  wire \drdyCount[5]_i_6_n_0 ;
  wire drdy_ff7;
  wire drdy_ff7_i_2_n_0;
  wire drdy_ff8;
  wire drdy_ff9;
  wire drdy_ff9_i_3_n_0;
  wire drdy_ffa;
  wire drdy_ffa_i_2_n_0;
  wire drdy_mux_ff;
  wire drdy_mux_ff1;
  wire drdy_mux_ff_i_1_n_0;
  (* DONT_TOUCH *) wire dummy_temp;
  (* DONT_TOUCH *) wire dummy_temp1;
  wire en_adv_trigger_1;
  wire flag0_temp;
  wire flag1_temp;
  wire flag2_temp;
  wire flag3_temp;
  wire halt_ctrl;
  wire ila_clk_flag;
  wire ila_clk_flag_reg_1;
  wire ila_clk_flag_reg_2;
  (* async_reg = "true" *) wire ila_clk_flag_sync1;
  (* async_reg = "true" *) wire ila_clk_flag_sync2;
  wire in0;
  wire [11:0]mu_config_cs_serial_input;
  wire [11:0]mu_config_cs_serial_output;
  wire [11:0]mu_config_cs_shift_en;
  wire next_state_ila;
  wire next_state_xsdb;
  wire [36:0]out;
  wire [6:0]p_0_in;
  wire [6:0]p_0_in__0;
  wire [8:0]p_0_in__1__0;
  wire [0:0]\parallel_dout_reg[15] ;
  wire [0:0]\parallel_dout_reg[15]_0 ;
  wire qual_strg_config_cs_serial_output;
  wire read_data_en;
  wire [9:0]read_reset_addr;
  wire regAck_reg;
  wire \regAck_reg_n_0_[1] ;
  wire regAck_temp;
  wire regAck_temp_reg;
  wire regDrdy_i_1_n_0;
  wire regDrdy_i_2_n_0;
  wire regDrdy_i_3_n_0;
  wire regDrdy_i_4_n_0;
  wire regDrdy_i_5_n_0;
  wire regDrdy_i_6_n_0;
  wire regDrdy_reg_n_0;
  wire reg_15_n_0;
  wire reg_15_n_1;
  wire reg_15_n_10;
  wire reg_15_n_11;
  wire reg_15_n_12;
  wire reg_15_n_14;
  wire reg_15_n_2;
  wire reg_15_n_3;
  wire reg_15_n_4;
  wire reg_15_n_5;
  wire reg_15_n_6;
  wire reg_15_n_7;
  wire reg_15_n_8;
  wire reg_15_n_9;
  wire reg_16_n_0;
  wire reg_16_n_1;
  wire reg_16_n_2;
  wire reg_16_n_3;
  wire reg_16_n_4;
  wire reg_16_n_5;
  wire reg_16_n_6;
  wire reg_16_n_7;
  wire reg_16_n_8;
  wire reg_17_n_0;
  wire reg_17_n_1;
  wire reg_17_n_10;
  wire reg_17_n_11;
  wire reg_17_n_12;
  wire reg_17_n_13;
  wire reg_17_n_14;
  wire reg_17_n_15;
  wire reg_17_n_2;
  wire reg_17_n_3;
  wire reg_17_n_4;
  wire reg_17_n_5;
  wire reg_17_n_6;
  wire reg_17_n_7;
  wire reg_17_n_8;
  wire reg_17_n_9;
  wire reg_18_n_11;
  wire reg_18_n_12;
  wire reg_18_n_13;
  wire reg_18_n_14;
  wire reg_18_n_15;
  wire reg_18_n_16;
  wire reg_19_n_0;
  wire reg_19_n_1;
  wire reg_19_n_10;
  wire reg_19_n_11;
  wire reg_19_n_12;
  wire reg_19_n_13;
  wire reg_19_n_14;
  wire reg_19_n_15;
  wire reg_19_n_2;
  wire reg_19_n_3;
  wire reg_19_n_4;
  wire reg_19_n_5;
  wire reg_19_n_6;
  wire reg_19_n_7;
  wire reg_19_n_8;
  wire reg_19_n_9;
  wire reg_1a_n_0;
  wire reg_1a_n_1;
  wire reg_1a_n_12;
  wire reg_1a_n_13;
  wire reg_1a_n_14;
  wire reg_1a_n_15;
  wire reg_1a_n_16;
  wire reg_1a_n_17;
  wire reg_1a_n_18;
  wire reg_1a_n_2;
  wire reg_1a_n_3;
  wire reg_1a_n_4;
  wire reg_1a_n_5;
  wire reg_1a_n_6;
  wire reg_1a_n_7;
  wire reg_1a_n_9;
  wire reg_6_n_0;
  wire reg_6_n_10;
  wire reg_6_n_11;
  wire reg_6_n_12;
  wire reg_6_n_13;
  wire reg_6_n_14;
  wire reg_6_n_15;
  wire reg_6_n_6;
  wire reg_6_n_7;
  wire reg_6_n_8;
  wire reg_6_n_9;
  wire reg_7_n_0;
  wire reg_7_n_1;
  wire reg_7_n_10;
  wire reg_7_n_11;
  wire reg_7_n_12;
  wire reg_7_n_13;
  wire reg_7_n_14;
  wire reg_7_n_15;
  wire reg_7_n_2;
  wire reg_7_n_3;
  wire reg_7_n_4;
  wire reg_7_n_6;
  wire reg_7_n_7;
  wire reg_7_n_8;
  wire reg_7_n_9;
  wire reg_83_n_0;
  wire reg_83_n_1;
  wire reg_83_n_10;
  wire reg_83_n_11;
  wire reg_83_n_12;
  wire reg_83_n_13;
  wire reg_83_n_14;
  wire reg_83_n_15;
  wire reg_83_n_16;
  wire reg_83_n_17;
  wire reg_83_n_2;
  wire reg_83_n_3;
  wire reg_83_n_4;
  wire reg_83_n_5;
  wire reg_83_n_6;
  wire reg_83_n_7;
  wire reg_83_n_8;
  wire reg_83_n_9;
  wire reg_84_n_0;
  wire reg_84_n_13;
  wire reg_84_n_14;
  wire reg_84_n_15;
  wire reg_85_n_0;
  wire reg_85_n_1;
  wire reg_85_n_10;
  wire reg_85_n_11;
  wire reg_85_n_12;
  wire reg_85_n_13;
  wire reg_85_n_14;
  wire reg_85_n_15;
  wire reg_85_n_16;
  wire reg_85_n_17;
  wire reg_85_n_2;
  wire reg_85_n_3;
  wire reg_85_n_4;
  wire reg_85_n_5;
  wire reg_85_n_6;
  wire reg_85_n_7;
  wire reg_85_n_8;
  wire reg_85_n_9;
  wire reg_887_n_0;
  wire reg_88d_n_0;
  wire reg_88d_n_1;
  wire reg_88f_n_0;
  wire reg_88f_n_1;
  wire reg_88f_n_10;
  wire reg_88f_n_11;
  wire reg_88f_n_12;
  wire reg_88f_n_13;
  wire reg_88f_n_14;
  wire reg_88f_n_15;
  wire reg_88f_n_16;
  wire reg_88f_n_2;
  wire reg_88f_n_3;
  wire reg_88f_n_4;
  wire reg_88f_n_5;
  wire reg_88f_n_6;
  wire reg_88f_n_7;
  wire reg_88f_n_8;
  wire reg_88f_n_9;
  wire reg_892_n_0;
  wire reg_892_n_1;
  wire reg_892_n_2;
  wire reg_892_n_3;
  wire reg_8_n_0;
  wire reg_8_n_1;
  wire reg_8_n_2;
  wire reg_8_n_3;
  wire reg_8_n_4;
  wire reg_9_n_0;
  wire reg_9_n_1;
  wire reg_9_n_2;
  wire reg_9_n_3;
  wire reg_9_n_4;
  wire reg_9_n_5;
  wire reg_9_n_6;
  wire reg_9_n_7;
  wire reg_9_n_8;
  wire reg_9_n_9;
  wire reg_ce;
  wire reg_srl_fff_n_0;
  wire reg_srl_fff_n_1;
  wire reg_srl_fff_n_10;
  wire reg_srl_fff_n_11;
  wire reg_srl_fff_n_12;
  wire reg_srl_fff_n_13;
  wire reg_srl_fff_n_14;
  wire reg_srl_fff_n_15;
  wire reg_srl_fff_n_2;
  wire reg_srl_fff_n_3;
  wire reg_srl_fff_n_4;
  wire reg_srl_fff_n_5;
  wire reg_srl_fff_n_6;
  wire reg_srl_fff_n_7;
  wire reg_srl_fff_n_8;
  wire reg_srl_fff_n_9;
  wire reg_stream_ffd_n_0;
  wire reg_stream_ffd_n_1;
  wire reg_stream_ffe_n_0;
  wire reg_stream_ffe_n_1;
  wire reg_stream_ffe_n_10;
  wire reg_stream_ffe_n_11;
  wire reg_stream_ffe_n_12;
  wire reg_stream_ffe_n_13;
  wire reg_stream_ffe_n_2;
  wire reg_stream_ffe_n_3;
  wire reg_stream_ffe_n_4;
  wire reg_stream_ffe_n_5;
  wire reg_stream_ffe_n_6;
  wire reg_stream_ffe_n_7;
  wire reg_stream_ffe_n_8;
  wire reg_stream_ffe_n_9;
  wire [16:13]s_daddr;
  wire [12:0]s_daddr_o;
  wire s_dclk_flag;
  wire s_dclk_flag_i_1_n_0;
  (* async_reg = "true" *) wire s_dclk_flag_sync1;
  (* async_reg = "true" *) wire s_dclk_flag_sync2;
  wire s_den_o;
  wire [15:0]s_di;
  wire s_dwe_o;
  wire s_rst_o;
  wire scnt_cmp_temp;
  wire sel;
  wire [0:0]shift_en_reg;
  wire [0:0]shift_en_reg_0;
  wire \shift_reg0_reg[2]_0 ;
  wire \shift_reg0_reg[2]_1 ;
  wire \shift_reg1_reg[11]_0 ;
  wire \shift_reg1_reg[11]_1 ;
  wire [15:0]slaveRegDo_18;
  wire [10:1]slaveRegDo_6;
  wire [15:0]slaveRegDo_80;
  wire [15:0]slaveRegDo_81;
  wire [15:0]slaveRegDo_82;
  wire [15:3]slaveRegDo_84;
  wire [15:0]slaveRegDo_890;
  wire [15:0]\slaveRegDo_cntConfig[6144]_45 ;
  wire [15:0]\slaveRegDo_cntConfig[6145]_46 ;
  wire [15:0]\slaveRegDo_cntConfig[6147]_48 ;
  wire \slaveRegDo_ff8[15]_i_1_n_0 ;
  wire \slaveRegDo_ff8[4]_i_1_n_0 ;
  wire \slaveRegDo_ff8_reg_n_0_[15] ;
  wire \slaveRegDo_ff8_reg_n_0_[4] ;
  wire [2:2]slaveRegDo_ff9;
  wire [11:11]slaveRegDo_ffa;
  wire [15:0]\slaveRegDo_muConfig[4096]_1 ;
  wire [15:0]\slaveRegDo_muConfig[4097]_2 ;
  wire [15:0]\slaveRegDo_muConfig[4098]_3 ;
  wire [15:0]\slaveRegDo_muConfig[4100]_5 ;
  wire [15:0]\slaveRegDo_muConfig[4101]_6 ;
  wire [15:0]\slaveRegDo_muConfig[4102]_7 ;
  wire [15:0]\slaveRegDo_muConfig[4104]_9 ;
  wire [15:0]\slaveRegDo_muConfig[4105]_10 ;
  wire [15:0]\slaveRegDo_muConfig[4106]_11 ;
  wire [15:0]slaveRegDo_mux;
  wire \slaveRegDo_mux[0]_i_2_n_0 ;
  wire \slaveRegDo_mux[0]_i_3_n_0 ;
  wire \slaveRegDo_mux[10]_i_2_n_0 ;
  wire \slaveRegDo_mux[10]_i_3_n_0 ;
  wire \slaveRegDo_mux[11]_i_2_n_0 ;
  wire \slaveRegDo_mux[11]_i_3_n_0 ;
  wire \slaveRegDo_mux[12]_i_2_n_0 ;
  wire \slaveRegDo_mux[12]_i_3_n_0 ;
  wire \slaveRegDo_mux[13]_i_2_n_0 ;
  wire \slaveRegDo_mux[13]_i_3_n_0 ;
  wire \slaveRegDo_mux[14]_i_2_n_0 ;
  wire \slaveRegDo_mux[14]_i_3_n_0 ;
  wire \slaveRegDo_mux[15]_i_2_n_0 ;
  wire \slaveRegDo_mux[15]_i_3_n_0 ;
  wire \slaveRegDo_mux[1]_i_2_n_0 ;
  wire \slaveRegDo_mux[1]_i_3_n_0 ;
  wire \slaveRegDo_mux[2]_i_2_n_0 ;
  wire \slaveRegDo_mux[2]_i_3_n_0 ;
  wire \slaveRegDo_mux[3]_i_2_n_0 ;
  wire \slaveRegDo_mux[3]_i_3_n_0 ;
  wire \slaveRegDo_mux[4]_i_2_n_0 ;
  wire \slaveRegDo_mux[4]_i_3_n_0 ;
  wire \slaveRegDo_mux[5]_i_2_n_0 ;
  wire \slaveRegDo_mux[5]_i_3_n_0 ;
  wire \slaveRegDo_mux[6]_i_2_n_0 ;
  wire \slaveRegDo_mux[6]_i_3_n_0 ;
  wire \slaveRegDo_mux[7]_i_2_n_0 ;
  wire \slaveRegDo_mux[7]_i_3_n_0 ;
  wire \slaveRegDo_mux[8]_i_2_n_0 ;
  wire \slaveRegDo_mux[8]_i_3_n_0 ;
  wire \slaveRegDo_mux[9]_i_2_n_0 ;
  wire \slaveRegDo_mux[9]_i_3_n_0 ;
  wire [15:0]slaveRegDo_mux_0;
  wire \slaveRegDo_mux_0[15]_i_1_n_0 ;
  wire \slaveRegDo_mux_0[15]_i_9_n_0 ;
  wire \slaveRegDo_mux_0[4]_i_10_n_0 ;
  wire \slaveRegDo_mux_0[4]_i_2 ;
  wire \slaveRegDo_mux_0[4]_i_3_n_0 ;
  wire \slaveRegDo_mux_0[4]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[4]_i_8_n_0 ;
  wire [4:0]slaveRegDo_mux_1;
  wire \slaveRegDo_mux_1[0]_i_1_n_0 ;
  wire \slaveRegDo_mux_1[1]_i_1_n_0 ;
  wire \slaveRegDo_mux_1[4]_i_1_n_0 ;
  wire [15:0]slaveRegDo_mux_2;
  wire \slaveRegDo_mux_2[0]_i_2_n_0 ;
  wire \slaveRegDo_mux_2[15]_i_1_n_0 ;
  wire \slaveRegDo_mux_2[1]_i_3_n_0 ;
  wire \slaveRegDo_mux_2[2]_i_2_n_0 ;
  wire \slaveRegDo_mux_2[2]_i_4_n_0 ;
  wire \slaveRegDo_mux_2[2]_i_5_n_0 ;
  wire \slaveRegDo_mux_2[4]_i_2_n_0 ;
  wire \slaveRegDo_mux_2[4]_i_4_n_0 ;
  wire \slaveRegDo_mux_2[4]_i_5_n_0 ;
  wire \slaveRegDo_mux_2_reg[5]_0 ;
  wire [15:0]slaveRegDo_mux_3;
  wire \slaveRegDo_mux_3[10]_i_3_n_0 ;
  wire \slaveRegDo_mux_3[11]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[15]_i_1_n_0 ;
  wire \slaveRegDo_mux_3[15]_i_4_n_0 ;
  wire [15:0]slaveRegDo_mux_4;
  wire [15:0]slaveRegDo_mux_5;
  wire \slaveRegDo_mux_6[15]_i_3_n_0 ;
  wire \slaveRegDo_mux_6[15]_i_4_n_0 ;
  wire \slaveRegDo_mux_6[15]_i_5_n_0 ;
  wire \slaveRegDo_mux_6_reg[0]_0 ;
  wire \slaveRegDo_mux_6_reg_n_0_[0] ;
  wire \slaveRegDo_mux_6_reg_n_0_[10] ;
  wire \slaveRegDo_mux_6_reg_n_0_[11] ;
  wire \slaveRegDo_mux_6_reg_n_0_[12] ;
  wire \slaveRegDo_mux_6_reg_n_0_[13] ;
  wire \slaveRegDo_mux_6_reg_n_0_[14] ;
  wire \slaveRegDo_mux_6_reg_n_0_[15] ;
  wire \slaveRegDo_mux_6_reg_n_0_[1] ;
  wire \slaveRegDo_mux_6_reg_n_0_[2] ;
  wire \slaveRegDo_mux_6_reg_n_0_[3] ;
  wire \slaveRegDo_mux_6_reg_n_0_[4] ;
  wire \slaveRegDo_mux_6_reg_n_0_[5] ;
  wire \slaveRegDo_mux_6_reg_n_0_[6] ;
  wire \slaveRegDo_mux_6_reg_n_0_[7] ;
  wire \slaveRegDo_mux_6_reg_n_0_[8] ;
  wire \slaveRegDo_mux_6_reg_n_0_[9] ;
  wire \slaveRegDo_mux_reg_n_0_[0] ;
  wire \slaveRegDo_mux_reg_n_0_[10] ;
  wire \slaveRegDo_mux_reg_n_0_[11] ;
  wire \slaveRegDo_mux_reg_n_0_[12] ;
  wire \slaveRegDo_mux_reg_n_0_[13] ;
  wire \slaveRegDo_mux_reg_n_0_[14] ;
  wire \slaveRegDo_mux_reg_n_0_[15] ;
  wire \slaveRegDo_mux_reg_n_0_[1] ;
  wire \slaveRegDo_mux_reg_n_0_[2] ;
  wire \slaveRegDo_mux_reg_n_0_[3] ;
  wire \slaveRegDo_mux_reg_n_0_[4] ;
  wire \slaveRegDo_mux_reg_n_0_[5] ;
  wire \slaveRegDo_mux_reg_n_0_[6] ;
  wire \slaveRegDo_mux_reg_n_0_[7] ;
  wire \slaveRegDo_mux_reg_n_0_[8] ;
  wire \slaveRegDo_mux_reg_n_0_[9] ;
  wire [15:0]slaveRegDo_qualStrgConfig;
  wire [15:0]\slaveRegDo_tcConfig[5120]_13 ;
  wire [15:0]\slaveRegDo_tcConfig[5121]_14 ;
  wire [15:0]\slaveRegDo_tcConfig[5122]_15 ;
  wire [15:0]\slaveRegDo_tcConfig[5124]_17 ;
  wire [15:0]\slaveRegDo_tcConfig[5125]_18 ;
  wire [15:0]\slaveRegDo_tcConfig[5126]_19 ;
  wire [15:0]\slaveRegDo_tcConfig[5128]_21 ;
  wire [15:0]\slaveRegDo_tcConfig[5129]_22 ;
  wire [15:0]\slaveRegDo_tcConfig[5130]_23 ;
  wire [15:0]\slaveRegDo_tcConfig[5132]_25 ;
  wire [15:0]\slaveRegDo_tcConfig[5133]_26 ;
  wire [15:0]\slaveRegDo_tcConfig[5134]_27 ;
  wire [15:0]\slaveRegDo_tcConfig[5136]_29 ;
  wire [15:0]\slaveRegDo_tcConfig[5137]_30 ;
  wire [15:0]\slaveRegDo_tcConfig[5138]_31 ;
  wire [15:0]\slaveRegDo_tcConfig[5140]_33 ;
  wire [15:0]\slaveRegDo_tcConfig[5141]_34 ;
  wire [15:0]\slaveRegDo_tcConfig[5142]_35 ;
  wire [15:0]\slaveRegDo_tcConfig[5144]_37 ;
  wire [15:0]\slaveRegDo_tcConfig[5145]_38 ;
  wire [15:0]\slaveRegDo_tcConfig[5146]_39 ;
  wire [15:0]\slaveRegDo_tcConfig[5148]_41 ;
  wire [15:0]\slaveRegDo_tcConfig[5149]_42 ;
  wire [15:0]\slaveRegDo_tcConfig[5150]_43 ;
  wire [31:0]tc_config_cs_serial_input;
  wire [31:0]tc_config_cs_serial_output;
  wire [31:0]tc_config_cs_shift_en;
  wire toggle_rd;
  wire toggle_rd_reg;
  wire toggle_reg;
  wire u_wcnt_hcmp_q;
  wire u_wcnt_lcmp_q;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp_temp;
  wire xsdb_rden_ff7;
  wire xsdb_rden_ff8;
  wire xsdb_rden_ff9;
  wire xsdb_rden_ffa;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[0]_3 ;
  wire \xsdb_reg_reg[0]_4 ;
  wire \xsdb_reg_reg[0]_5 ;
  wire \xsdb_reg_reg[0]_6 ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[15]_1 ;
  wire [15:0]\xsdb_reg_reg[15]_2 ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[1]_0 ;
  wire [1:0]\xsdb_reg_reg[1]_1 ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[3] ;
  wire [3:0]\xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;
  wire [9:0]\xsdb_reg_reg[9]_0 ;
  wire [15:0]NLW_reg_890_dout_o_UNCONNECTED;

  assign ila_clk_flag_reg_0 = ila_clk_flag;
  assign s_dclk_flag_sync2_reg_0 = s_dclk_flag_sync2;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized0 \ADV_TRIG_STREAM.reg_stream_ffc 
       (.D({s_daddr_o[12:10],s_daddr_o[8],s_daddr_o[1:0]}),
        .E(E),
        .\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
        .\I_EN_CTL_EQ1.temp_en_reg_0 (\slaveRegDo_mux_2_reg[5]_0 ),
        .\I_EN_CTL_EQ1.temp_en_reg_1 (s_den_o),
        .\I_EN_CTL_EQ1.temp_en_reg_2 (reg_stream_ffd_n_1),
        .Q(config_fsm_addr[0]),
        .bram_en(bram_en),
        .bram_en_reg(bram_rd_en_i_2_n_0),
        .bram_en_reg_0(bram_en_i_2_n_0),
        .bram_en_reg_1(bram_rd_en_i_4_n_0),
        .config_fsm_we(config_fsm_we),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .s_dwe_o(s_dwe_o),
        .toggle_reg(toggle_reg),
        .\xsdb_reg_reg[15] (D));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream \ADV_TRIG_STREAM_READBACK.reg_stream_ffb 
       (.D(s_daddr_o[3:0]),
        .E(adv_rb_drdy1),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ),
        .Q({\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 }),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .slaveRegDo_ff9(slaveRegDo_ff9),
        .\slaveRegDo_ff9_reg[2] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ),
        .\slaveRegDo_ff9_reg[2]_0 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ),
        .slaveRegDo_ffa(slaveRegDo_ffa),
        .\slaveRegDo_ffa_reg[11] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ),
        .\slaveRegDo_ffa_reg[11]_0 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ),
        .\slaveRegDo_mux_3_reg[11] (\slaveRegDo_mux_3[11]_i_2_n_0 ),
        .\slaveRegDo_mux_3_reg[11]_0 (reg_83_n_15),
        .\slaveRegDo_mux_3_reg[11]_1 (reg_srl_fff_n_11),
        .\slaveRegDo_mux_3_reg[12] (reg_srl_fff_n_10),
        .\slaveRegDo_mux_3_reg[13] (reg_srl_fff_n_9),
        .\slaveRegDo_mux_3_reg[14] (reg_srl_fff_n_8),
        .\slaveRegDo_mux_3_reg[4] (\slaveRegDo_ff8_reg_n_0_[4] ),
        .\slaveRegDo_mux_3_reg[5] (reg_srl_fff_n_15),
        .\slaveRegDo_mux_3_reg[6] (reg_srl_fff_n_14),
        .\slaveRegDo_mux_3_reg[8] (reg_srl_fff_n_13),
        .\slaveRegDo_mux_3_reg[9] (reg_srl_fff_n_12),
        .\xsdb_reg_reg[0] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ),
        .\xsdb_reg_reg[11] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ),
        .\xsdb_reg_reg[15] (\xsdb_reg_reg[15]_2 ),
        .\xsdb_reg_reg[5] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ),
        .\xsdb_reg_reg[6] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ),
        .\xsdb_reg_reg[8] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ),
        .\xsdb_reg_reg[9] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized43 \CNT.CNT_SRL[0].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[0]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[0]),
        .E(cnt_config_cs_shift_en[0]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_1 (\current_state_reg[3] ),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_cntConfig[6144]_45 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized44 \CNT.CNT_SRL[1].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[1]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[1]),
        .D(s_daddr_o[12:10]),
        .E(cnt_config_cs_shift_en[1]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_4 ),
        .\current_state_reg[3]_2 (s_den_o),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_cntConfig[6145]_46 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized45 \CNT.CNT_SRL[2].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[2]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[2]),
        .D({\CNT.CNT_SRL[2].cnt_srl_reg_n_0 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_1 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_2 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_3 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_4 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_5 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_6 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_7 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_8 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_9 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_10 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_11 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_12 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_13 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_14 ,\CNT.CNT_SRL[2].cnt_srl_reg_n_15 }),
        .E(cnt_config_cs_shift_en[2]),
        .Q(slaveRegDo_qualStrgConfig),
        .\current_state_reg[3]_0 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_6 ),
        .s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_cntConfig[6144]_45 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_6_reg[0] (\slaveRegDo_mux_6[15]_i_3_n_0 ),
        .\slaveRegDo_mux_6_reg[0]_0 (\slaveRegDo_mux_6[15]_i_4_n_0 ),
        .\slaveRegDo_mux_6_reg[15] (\slaveRegDo_cntConfig[6147]_48 ),
        .\slaveRegDo_mux_6_reg[15]_0 (\slaveRegDo_cntConfig[6145]_46 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized46 \CNT.CNT_SRL[3].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[3]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[3]),
        .E(cnt_config_cs_shift_en[3]),
        .\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\current_state_reg[3]_0 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_1 (\current_state_reg[3] ),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_cntConfig[6147]_48 ),
        .s_dwe_o(s_dwe_o));
  FDRE \FSM_BRAM_ADDR_O_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[0]),
        .Q(config_fsm_addr[0]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[10]),
        .Q(config_fsm_addr[10]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[11]),
        .Q(config_fsm_addr[11]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[12]),
        .Q(config_fsm_addr[12]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr[13]),
        .Q(config_fsm_addr[13]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr[14]),
        .Q(config_fsm_addr[14]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr[15]),
        .Q(config_fsm_addr[15]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[16] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr[16]),
        .Q(config_fsm_addr[16]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[1]),
        .Q(config_fsm_addr[1]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[2]),
        .Q(config_fsm_addr[2]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[3]),
        .Q(config_fsm_addr[3]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[4]),
        .Q(config_fsm_addr[4]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[5]),
        .Q(config_fsm_addr[5]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[6]),
        .Q(config_fsm_addr[6]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[7]),
        .Q(config_fsm_addr[7]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[8]),
        .Q(config_fsm_addr[8]),
        .R(1'b0));
  FDRE \FSM_BRAM_ADDR_O_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_daddr_o[9]),
        .Q(config_fsm_addr[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000004000000)) 
    FSM_BRAM_EN_RB_O_i_1
       (.I0(reg_stream_ffd_n_0),
        .I1(s_den_o),
        .I2(s_daddr_o[12]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[11]),
        .I5(FSM_BRAM_EN_RB_O_i_2_n_0),
        .O(reg_ce));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    FSM_BRAM_EN_RB_O_i_2
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .O(FSM_BRAM_EN_RB_O_i_2_n_0));
  FDRE FSM_BRAM_EN_RB_O_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_ce),
        .Q(config_fsm_en_rb),
        .R(1'b0));
  FDRE FSM_BRAM_WE_O_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_dwe_o),
        .Q(config_fsm_we),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s \MU_SRL[0].mu_srl_reg 
       (.E(mu_config_cs_shift_en[0]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_0 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4096]_1 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized9 \MU_SRL[10].mu_srl_reg 
       (.E(mu_config_cs_shift_en[10]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_6 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[10]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[10]),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4106]_11 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized10 \MU_SRL[11].mu_srl_reg 
       (.D({\MU_SRL[11].mu_srl_reg_n_0 ,\MU_SRL[11].mu_srl_reg_n_1 ,\MU_SRL[11].mu_srl_reg_n_2 ,\MU_SRL[11].mu_srl_reg_n_3 ,\MU_SRL[11].mu_srl_reg_n_4 ,\MU_SRL[11].mu_srl_reg_n_5 ,\MU_SRL[11].mu_srl_reg_n_6 ,\MU_SRL[11].mu_srl_reg_n_7 ,\MU_SRL[11].mu_srl_reg_n_8 ,\MU_SRL[11].mu_srl_reg_n_9 ,\MU_SRL[11].mu_srl_reg_n_10 ,\MU_SRL[11].mu_srl_reg_n_11 ,\MU_SRL[11].mu_srl_reg_n_12 ,\MU_SRL[11].mu_srl_reg_n_13 ,\MU_SRL[11].mu_srl_reg_n_14 ,\MU_SRL[11].mu_srl_reg_n_15 }),
        .E(mu_config_cs_shift_en[11]),
        .Q(\slaveRegDo_muConfig[4105]_10 ),
        .\current_state_reg[3]_0 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_1 (\current_state_reg[3]_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[11]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[11]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4106]_11 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_4_reg[0] (s_daddr_o[3:0]),
        .\slaveRegDo_mux_4_reg[0]_0 (\MU_SRL[7].mu_srl_reg_n_15 ),
        .\slaveRegDo_mux_4_reg[0]_1 (\MU_SRL[3].mu_srl_reg_n_15 ),
        .\slaveRegDo_mux_4_reg[10] (\MU_SRL[7].mu_srl_reg_n_5 ),
        .\slaveRegDo_mux_4_reg[10]_0 (\MU_SRL[3].mu_srl_reg_n_5 ),
        .\slaveRegDo_mux_4_reg[11] (\MU_SRL[7].mu_srl_reg_n_4 ),
        .\slaveRegDo_mux_4_reg[11]_0 (\MU_SRL[3].mu_srl_reg_n_4 ),
        .\slaveRegDo_mux_4_reg[12] (\MU_SRL[7].mu_srl_reg_n_3 ),
        .\slaveRegDo_mux_4_reg[12]_0 (\MU_SRL[3].mu_srl_reg_n_3 ),
        .\slaveRegDo_mux_4_reg[13] (\MU_SRL[7].mu_srl_reg_n_2 ),
        .\slaveRegDo_mux_4_reg[13]_0 (\MU_SRL[3].mu_srl_reg_n_2 ),
        .\slaveRegDo_mux_4_reg[14] (\MU_SRL[7].mu_srl_reg_n_1 ),
        .\slaveRegDo_mux_4_reg[14]_0 (\MU_SRL[3].mu_srl_reg_n_1 ),
        .\slaveRegDo_mux_4_reg[15] (\MU_SRL[7].mu_srl_reg_n_0 ),
        .\slaveRegDo_mux_4_reg[15]_0 (\MU_SRL[3].mu_srl_reg_n_0 ),
        .\slaveRegDo_mux_4_reg[15]_1 (\slaveRegDo_muConfig[4104]_9 ),
        .\slaveRegDo_mux_4_reg[1] (\MU_SRL[7].mu_srl_reg_n_14 ),
        .\slaveRegDo_mux_4_reg[1]_0 (\MU_SRL[3].mu_srl_reg_n_14 ),
        .\slaveRegDo_mux_4_reg[2] (\MU_SRL[7].mu_srl_reg_n_13 ),
        .\slaveRegDo_mux_4_reg[2]_0 (\MU_SRL[3].mu_srl_reg_n_13 ),
        .\slaveRegDo_mux_4_reg[3] (\MU_SRL[7].mu_srl_reg_n_12 ),
        .\slaveRegDo_mux_4_reg[3]_0 (\MU_SRL[3].mu_srl_reg_n_12 ),
        .\slaveRegDo_mux_4_reg[4] (\MU_SRL[7].mu_srl_reg_n_11 ),
        .\slaveRegDo_mux_4_reg[4]_0 (\MU_SRL[3].mu_srl_reg_n_11 ),
        .\slaveRegDo_mux_4_reg[5] (\MU_SRL[7].mu_srl_reg_n_10 ),
        .\slaveRegDo_mux_4_reg[5]_0 (\MU_SRL[3].mu_srl_reg_n_10 ),
        .\slaveRegDo_mux_4_reg[6] (\MU_SRL[7].mu_srl_reg_n_9 ),
        .\slaveRegDo_mux_4_reg[6]_0 (\MU_SRL[3].mu_srl_reg_n_9 ),
        .\slaveRegDo_mux_4_reg[7] (\MU_SRL[7].mu_srl_reg_n_8 ),
        .\slaveRegDo_mux_4_reg[7]_0 (\MU_SRL[3].mu_srl_reg_n_8 ),
        .\slaveRegDo_mux_4_reg[8] (\MU_SRL[7].mu_srl_reg_n_7 ),
        .\slaveRegDo_mux_4_reg[8]_0 (\MU_SRL[3].mu_srl_reg_n_7 ),
        .\slaveRegDo_mux_4_reg[9] (\MU_SRL[7].mu_srl_reg_n_6 ),
        .\slaveRegDo_mux_4_reg[9]_0 (\MU_SRL[3].mu_srl_reg_n_6 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized0 \MU_SRL[1].mu_srl_reg 
       (.E(mu_config_cs_shift_en[1]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_4 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4097]_2 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized1 \MU_SRL[2].mu_srl_reg 
       (.E(mu_config_cs_shift_en[2]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_6 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4098]_3 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized2 \MU_SRL[3].mu_srl_reg 
       (.E(mu_config_cs_shift_en[3]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_2 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
        .\parallel_dout_reg[0]_0 (\MU_SRL[3].mu_srl_reg_n_15 ),
        .\parallel_dout_reg[10]_0 (\MU_SRL[3].mu_srl_reg_n_5 ),
        .\parallel_dout_reg[11]_0 (\MU_SRL[3].mu_srl_reg_n_4 ),
        .\parallel_dout_reg[12]_0 (\MU_SRL[3].mu_srl_reg_n_3 ),
        .\parallel_dout_reg[13]_0 (\MU_SRL[3].mu_srl_reg_n_2 ),
        .\parallel_dout_reg[14]_0 (\MU_SRL[3].mu_srl_reg_n_1 ),
        .\parallel_dout_reg[15]_0 (\MU_SRL[3].mu_srl_reg_n_0 ),
        .\parallel_dout_reg[1]_0 (\MU_SRL[3].mu_srl_reg_n_14 ),
        .\parallel_dout_reg[2]_0 (\MU_SRL[3].mu_srl_reg_n_13 ),
        .\parallel_dout_reg[3]_0 (\MU_SRL[3].mu_srl_reg_n_12 ),
        .\parallel_dout_reg[4]_0 (\MU_SRL[3].mu_srl_reg_n_11 ),
        .\parallel_dout_reg[5]_0 (\MU_SRL[3].mu_srl_reg_n_10 ),
        .\parallel_dout_reg[6]_0 (\MU_SRL[3].mu_srl_reg_n_9 ),
        .\parallel_dout_reg[7]_0 (\MU_SRL[3].mu_srl_reg_n_8 ),
        .\parallel_dout_reg[8]_0 (\MU_SRL[3].mu_srl_reg_n_7 ),
        .\parallel_dout_reg[9]_0 (\MU_SRL[3].mu_srl_reg_n_6 ),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4098]_3 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_4_reg[15] (\slaveRegDo_muConfig[4097]_2 ),
        .\slaveRegDo_mux_4_reg[15]_0 (\slaveRegDo_muConfig[4096]_1 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized3 \MU_SRL[4].mu_srl_reg 
       (.E(mu_config_cs_shift_en[4]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_0 ),
        .\current_state_reg[1]_1 (\current_state_reg[1] ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4100]_5 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized4 \MU_SRL[5].mu_srl_reg 
       (.E(mu_config_cs_shift_en[5]),
        .\current_state_reg[3]_0 (\current_state_reg[1] ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_4 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4101]_6 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized5 \MU_SRL[6].mu_srl_reg 
       (.E(mu_config_cs_shift_en[6]),
        .\current_state_reg[3]_0 (\current_state_reg[1] ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_6 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4102]_7 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized6 \MU_SRL[7].mu_srl_reg 
       (.E(mu_config_cs_shift_en[7]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_2 ),
        .\current_state_reg[1]_1 (\current_state_reg[1] ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
        .\parallel_dout_reg[0]_0 (\MU_SRL[7].mu_srl_reg_n_15 ),
        .\parallel_dout_reg[10]_0 (\MU_SRL[7].mu_srl_reg_n_5 ),
        .\parallel_dout_reg[11]_0 (\MU_SRL[7].mu_srl_reg_n_4 ),
        .\parallel_dout_reg[12]_0 (\MU_SRL[7].mu_srl_reg_n_3 ),
        .\parallel_dout_reg[13]_0 (\MU_SRL[7].mu_srl_reg_n_2 ),
        .\parallel_dout_reg[14]_0 (\MU_SRL[7].mu_srl_reg_n_1 ),
        .\parallel_dout_reg[15]_0 (\MU_SRL[7].mu_srl_reg_n_0 ),
        .\parallel_dout_reg[1]_0 (\MU_SRL[7].mu_srl_reg_n_14 ),
        .\parallel_dout_reg[2]_0 (\MU_SRL[7].mu_srl_reg_n_13 ),
        .\parallel_dout_reg[3]_0 (\MU_SRL[7].mu_srl_reg_n_12 ),
        .\parallel_dout_reg[4]_0 (\MU_SRL[7].mu_srl_reg_n_11 ),
        .\parallel_dout_reg[5]_0 (\MU_SRL[7].mu_srl_reg_n_10 ),
        .\parallel_dout_reg[6]_0 (\MU_SRL[7].mu_srl_reg_n_9 ),
        .\parallel_dout_reg[7]_0 (\MU_SRL[7].mu_srl_reg_n_8 ),
        .\parallel_dout_reg[8]_0 (\MU_SRL[7].mu_srl_reg_n_7 ),
        .\parallel_dout_reg[9]_0 (\MU_SRL[7].mu_srl_reg_n_6 ),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4102]_7 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_4_reg[15] (\slaveRegDo_muConfig[4101]_6 ),
        .\slaveRegDo_mux_4_reg[15]_0 (\slaveRegDo_muConfig[4100]_5 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized7 \MU_SRL[8].mu_srl_reg 
       (.E(mu_config_cs_shift_en[8]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_1 (\current_state_reg[3]_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4104]_9 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized8 \MU_SRL[9].mu_srl_reg 
       (.E(mu_config_cs_shift_en[9]),
        .\current_state_reg[3]_0 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_1 (\xsdb_reg_reg[0]_4 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_muConfig[4105]_10 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized47 \STRG_QUAL.qual_strg_srl_reg 
       (.E(shift_en_reg),
        .Q(slaveRegDo_qualStrgConfig),
        .\current_state_reg[3]_0 (\current_state_reg[1] ),
        .\current_state_reg[3]_1 (\current_state_reg[3] ),
        .\parallel_dout_reg[15]_0 (\parallel_dout_reg[15] ),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized11 \TC_SRL[0].tc_srl_reg 
       (.E(tc_config_cs_shift_en[0]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_1 ),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5120]_13 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized21 \TC_SRL[10].tc_srl_reg 
       (.E(tc_config_cs_shift_en[10]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_0 (\xsdb_reg_reg[0]_6 ),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5130]_23 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[10]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized22 \TC_SRL[11].tc_srl_reg 
       (.E(tc_config_cs_shift_en[11]),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\TC_SRL[11].tc_srl_reg_n_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\TC_SRL[11].tc_srl_reg_n_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\TC_SRL[11].tc_srl_reg_n_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 (\TC_SRL[11].tc_srl_reg_n_11 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 (\TC_SRL[11].tc_srl_reg_n_12 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 (\TC_SRL[11].tc_srl_reg_n_13 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 (\TC_SRL[11].tc_srl_reg_n_14 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 (\TC_SRL[11].tc_srl_reg_n_15 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\TC_SRL[11].tc_srl_reg_n_3 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (\TC_SRL[11].tc_srl_reg_n_4 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 (\TC_SRL[11].tc_srl_reg_n_5 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 (\TC_SRL[11].tc_srl_reg_n_6 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 (\TC_SRL[11].tc_srl_reg_n_7 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 (\TC_SRL[11].tc_srl_reg_n_8 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 (\TC_SRL[11].tc_srl_reg_n_9 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 (\TC_SRL[11].tc_srl_reg_n_10 ),
        .Q(\slaveRegDo_tcConfig[5129]_22 ),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5130]_23 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[0] (\TC_SRL[15].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[10] (\TC_SRL[15].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[11] (\TC_SRL[15].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[12] (\TC_SRL[15].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[13] (\TC_SRL[15].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[14] (\TC_SRL[15].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[15] (\TC_SRL[15].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_4_0 (\slaveRegDo_tcConfig[5128]_21 ),
        .\slaveRegDo_mux_5_reg[1] (\TC_SRL[15].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[2] (\TC_SRL[15].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[3] (\TC_SRL[15].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[4] (\TC_SRL[15].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[5] (\TC_SRL[15].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[6] (\TC_SRL[15].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[7] (\TC_SRL[15].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[8] (\TC_SRL[15].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[9] (\TC_SRL[15].tc_srl_reg_n_6 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[11]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized23 \TC_SRL[12].tc_srl_reg 
       (.E(tc_config_cs_shift_en[12]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_8 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5132]_25 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[12]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized24 \TC_SRL[13].tc_srl_reg 
       (.E(tc_config_cs_shift_en[13]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_8 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5133]_26 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[13]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized25 \TC_SRL[14].tc_srl_reg 
       (.E(tc_config_cs_shift_en[14]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_8 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5134]_27 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[14]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized26 \TC_SRL[15].tc_srl_reg 
       (.E(tc_config_cs_shift_en[15]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_8 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .\parallel_dout_reg[0]_0 (\TC_SRL[15].tc_srl_reg_n_15 ),
        .\parallel_dout_reg[10]_0 (\TC_SRL[15].tc_srl_reg_n_5 ),
        .\parallel_dout_reg[11]_0 (\TC_SRL[15].tc_srl_reg_n_4 ),
        .\parallel_dout_reg[12]_0 (\TC_SRL[15].tc_srl_reg_n_3 ),
        .\parallel_dout_reg[13]_0 (\TC_SRL[15].tc_srl_reg_n_2 ),
        .\parallel_dout_reg[14]_0 (\TC_SRL[15].tc_srl_reg_n_1 ),
        .\parallel_dout_reg[15]_0 (\TC_SRL[15].tc_srl_reg_n_0 ),
        .\parallel_dout_reg[1]_0 (\TC_SRL[15].tc_srl_reg_n_14 ),
        .\parallel_dout_reg[2]_0 (\TC_SRL[15].tc_srl_reg_n_13 ),
        .\parallel_dout_reg[3]_0 (\TC_SRL[15].tc_srl_reg_n_12 ),
        .\parallel_dout_reg[4]_0 (\TC_SRL[15].tc_srl_reg_n_11 ),
        .\parallel_dout_reg[5]_0 (\TC_SRL[15].tc_srl_reg_n_10 ),
        .\parallel_dout_reg[6]_0 (\TC_SRL[15].tc_srl_reg_n_9 ),
        .\parallel_dout_reg[7]_0 (\TC_SRL[15].tc_srl_reg_n_8 ),
        .\parallel_dout_reg[8]_0 (\TC_SRL[15].tc_srl_reg_n_7 ),
        .\parallel_dout_reg[9]_0 (\TC_SRL[15].tc_srl_reg_n_6 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5134]_27 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_4 (\slaveRegDo_tcConfig[5133]_26 ),
        .\slaveRegDo_mux_5_reg[15]_i_4_0 (\slaveRegDo_tcConfig[5132]_25 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[15]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized27 \TC_SRL[16].tc_srl_reg 
       (.E(tc_config_cs_shift_en[16]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_9 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5136]_29 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[16]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized28 \TC_SRL[17].tc_srl_reg 
       (.E(tc_config_cs_shift_en[17]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_9 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5137]_30 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[17]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized29 \TC_SRL[18].tc_srl_reg 
       (.E(tc_config_cs_shift_en[18]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_9 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5138]_31 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[18]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized30 \TC_SRL[19].tc_srl_reg 
       (.E(tc_config_cs_shift_en[19]),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\TC_SRL[19].tc_srl_reg_n_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\TC_SRL[19].tc_srl_reg_n_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\TC_SRL[19].tc_srl_reg_n_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 (\TC_SRL[19].tc_srl_reg_n_11 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 (\TC_SRL[19].tc_srl_reg_n_12 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 (\TC_SRL[19].tc_srl_reg_n_13 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 (\TC_SRL[19].tc_srl_reg_n_14 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 (\TC_SRL[19].tc_srl_reg_n_15 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\TC_SRL[19].tc_srl_reg_n_3 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (\TC_SRL[19].tc_srl_reg_n_4 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 (\TC_SRL[19].tc_srl_reg_n_5 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 (\TC_SRL[19].tc_srl_reg_n_6 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 (\TC_SRL[19].tc_srl_reg_n_7 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 (\TC_SRL[19].tc_srl_reg_n_8 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 (\TC_SRL[19].tc_srl_reg_n_9 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 (\TC_SRL[19].tc_srl_reg_n_10 ),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_9 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5138]_31 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[0] (\TC_SRL[23].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[10] (\TC_SRL[23].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[11] (\TC_SRL[23].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[12] (\TC_SRL[23].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[13] (\TC_SRL[23].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[14] (\TC_SRL[23].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[15] (\TC_SRL[23].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_3_0 (\slaveRegDo_tcConfig[5137]_30 ),
        .\slaveRegDo_mux_5_reg[15]_i_3_1 (\slaveRegDo_tcConfig[5136]_29 ),
        .\slaveRegDo_mux_5_reg[1] (\TC_SRL[23].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[2] (\TC_SRL[23].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[3] (\TC_SRL[23].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[4] (\TC_SRL[23].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[5] (\TC_SRL[23].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[6] (\TC_SRL[23].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[7] (\TC_SRL[23].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[8] (\TC_SRL[23].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[9] (\TC_SRL[23].tc_srl_reg_n_6 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[19]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized12 \TC_SRL[1].tc_srl_reg 
       (.E(tc_config_cs_shift_en[1]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_0 (\xsdb_reg_reg[0]_4 ),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5121]_14 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[1]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized31 \TC_SRL[20].tc_srl_reg 
       (.E(tc_config_cs_shift_en[20]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_10 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5140]_33 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[20]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized32 \TC_SRL[21].tc_srl_reg 
       (.E(tc_config_cs_shift_en[21]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_10 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5141]_34 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[21]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized33 \TC_SRL[22].tc_srl_reg 
       (.E(tc_config_cs_shift_en[22]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_10 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5142]_35 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[22]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34 \TC_SRL[23].tc_srl_reg 
       (.E(tc_config_cs_shift_en[23]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_10 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .\parallel_dout_reg[0]_0 (\TC_SRL[23].tc_srl_reg_n_15 ),
        .\parallel_dout_reg[10]_0 (\TC_SRL[23].tc_srl_reg_n_5 ),
        .\parallel_dout_reg[11]_0 (\TC_SRL[23].tc_srl_reg_n_4 ),
        .\parallel_dout_reg[12]_0 (\TC_SRL[23].tc_srl_reg_n_3 ),
        .\parallel_dout_reg[13]_0 (\TC_SRL[23].tc_srl_reg_n_2 ),
        .\parallel_dout_reg[14]_0 (\TC_SRL[23].tc_srl_reg_n_1 ),
        .\parallel_dout_reg[15]_0 (\TC_SRL[23].tc_srl_reg_n_0 ),
        .\parallel_dout_reg[1]_0 (\TC_SRL[23].tc_srl_reg_n_14 ),
        .\parallel_dout_reg[2]_0 (\TC_SRL[23].tc_srl_reg_n_13 ),
        .\parallel_dout_reg[3]_0 (\TC_SRL[23].tc_srl_reg_n_12 ),
        .\parallel_dout_reg[4]_0 (\TC_SRL[23].tc_srl_reg_n_11 ),
        .\parallel_dout_reg[5]_0 (\TC_SRL[23].tc_srl_reg_n_10 ),
        .\parallel_dout_reg[6]_0 (\TC_SRL[23].tc_srl_reg_n_9 ),
        .\parallel_dout_reg[7]_0 (\TC_SRL[23].tc_srl_reg_n_8 ),
        .\parallel_dout_reg[8]_0 (\TC_SRL[23].tc_srl_reg_n_7 ),
        .\parallel_dout_reg[9]_0 (\TC_SRL[23].tc_srl_reg_n_6 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5142]_35 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_3 (\slaveRegDo_tcConfig[5141]_34 ),
        .\slaveRegDo_mux_5_reg[15]_i_3_0 (\slaveRegDo_tcConfig[5140]_33 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[23]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized35 \TC_SRL[24].tc_srl_reg 
       (.E(tc_config_cs_shift_en[24]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_11 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5144]_37 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[24]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized36 \TC_SRL[25].tc_srl_reg 
       (.E(tc_config_cs_shift_en[25]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_11 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5145]_38 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[25]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized37 \TC_SRL[26].tc_srl_reg 
       (.E(tc_config_cs_shift_en[26]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_11 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5146]_39 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[26]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized38 \TC_SRL[27].tc_srl_reg 
       (.D({\TC_SRL[27].tc_srl_reg_n_0 ,\TC_SRL[27].tc_srl_reg_n_1 ,\TC_SRL[27].tc_srl_reg_n_2 ,\TC_SRL[27].tc_srl_reg_n_3 ,\TC_SRL[27].tc_srl_reg_n_4 ,\TC_SRL[27].tc_srl_reg_n_5 ,\TC_SRL[27].tc_srl_reg_n_6 ,\TC_SRL[27].tc_srl_reg_n_7 ,\TC_SRL[27].tc_srl_reg_n_8 ,\TC_SRL[27].tc_srl_reg_n_9 ,\TC_SRL[27].tc_srl_reg_n_10 ,\TC_SRL[27].tc_srl_reg_n_11 ,\TC_SRL[27].tc_srl_reg_n_12 ,\TC_SRL[27].tc_srl_reg_n_13 ,\TC_SRL[27].tc_srl_reg_n_14 ,\TC_SRL[27].tc_srl_reg_n_15 }),
        .E(tc_config_cs_shift_en[27]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_11 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5146]_39 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[0] (\TC_SRL[19].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[0]_0 (\TC_SRL[11].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[0]_1 (\TC_SRL[3].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[0]_2 (\TC_SRL[31].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[10] (\TC_SRL[19].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[10]_0 (\TC_SRL[11].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[10]_1 (\TC_SRL[3].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[10]_2 (\TC_SRL[31].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[11] (\TC_SRL[19].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[11]_0 (\TC_SRL[11].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[11]_1 (\TC_SRL[3].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[11]_2 (\TC_SRL[31].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[12] (\TC_SRL[19].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[12]_0 (\TC_SRL[11].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[12]_1 (\TC_SRL[3].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[12]_2 (\TC_SRL[31].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[13] (\TC_SRL[19].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[13]_0 (\TC_SRL[11].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[13]_1 (\TC_SRL[3].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[13]_2 (\TC_SRL[31].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[14] (\TC_SRL[19].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[14]_0 (\TC_SRL[11].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[14]_1 (\TC_SRL[3].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[14]_2 (\TC_SRL[31].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[15] (\TC_SRL[19].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_0 (\TC_SRL[11].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_1 (\TC_SRL[3].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_2 (\TC_SRL[31].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_2_0 (\slaveRegDo_tcConfig[5145]_38 ),
        .\slaveRegDo_mux_5_reg[15]_i_2_1 (\slaveRegDo_tcConfig[5144]_37 ),
        .\slaveRegDo_mux_5_reg[1] (\TC_SRL[19].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[1]_0 (\TC_SRL[11].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[1]_1 (\TC_SRL[3].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[1]_2 (\TC_SRL[31].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[2] (\TC_SRL[19].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[2]_0 (\TC_SRL[11].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[2]_1 (\TC_SRL[3].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[2]_2 (\TC_SRL[31].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[3] (\TC_SRL[19].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[3]_0 (\TC_SRL[11].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[3]_1 (\TC_SRL[3].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[3]_2 (\TC_SRL[31].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[4] (\TC_SRL[19].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[4]_0 (\TC_SRL[11].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[4]_1 (\TC_SRL[3].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[4]_2 (\TC_SRL[31].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[5] (\TC_SRL[19].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[5]_0 (\TC_SRL[11].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[5]_1 (\TC_SRL[3].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[5]_2 (\TC_SRL[31].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[6] (\TC_SRL[19].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[6]_0 (\TC_SRL[11].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[6]_1 (\TC_SRL[3].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[6]_2 (\TC_SRL[31].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[7] (\TC_SRL[19].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[7]_0 (\TC_SRL[11].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[7]_1 (\TC_SRL[3].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[7]_2 (\TC_SRL[31].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[8] (\TC_SRL[19].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[8]_0 (\TC_SRL[11].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[8]_1 (\TC_SRL[3].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[8]_2 (\TC_SRL[31].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[9] (\TC_SRL[19].tc_srl_reg_n_6 ),
        .\slaveRegDo_mux_5_reg[9]_0 (\TC_SRL[11].tc_srl_reg_n_6 ),
        .\slaveRegDo_mux_5_reg[9]_1 (\TC_SRL[3].tc_srl_reg_n_6 ),
        .\slaveRegDo_mux_5_reg[9]_2 (\TC_SRL[31].tc_srl_reg_n_6 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[27]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized39 \TC_SRL[28].tc_srl_reg 
       (.E(tc_config_cs_shift_en[28]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_12 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5148]_41 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[28]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized40 \TC_SRL[29].tc_srl_reg 
       (.E(tc_config_cs_shift_en[29]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_12 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5149]_42 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[29]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized13 \TC_SRL[2].tc_srl_reg 
       (.E(tc_config_cs_shift_en[2]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_1 ),
        .\current_state_reg[3]_0 (\xsdb_reg_reg[0]_6 ),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5122]_15 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[2]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized41 \TC_SRL[30].tc_srl_reg 
       (.E(tc_config_cs_shift_en[30]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_12 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5150]_43 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[30]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized42 \TC_SRL[31].tc_srl_reg 
       (.E(tc_config_cs_shift_en[31]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_12 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .\parallel_dout_reg[0]_0 (\TC_SRL[31].tc_srl_reg_n_15 ),
        .\parallel_dout_reg[10]_0 (\TC_SRL[31].tc_srl_reg_n_5 ),
        .\parallel_dout_reg[11]_0 (\TC_SRL[31].tc_srl_reg_n_4 ),
        .\parallel_dout_reg[12]_0 (\TC_SRL[31].tc_srl_reg_n_3 ),
        .\parallel_dout_reg[13]_0 (\TC_SRL[31].tc_srl_reg_n_2 ),
        .\parallel_dout_reg[14]_0 (\TC_SRL[31].tc_srl_reg_n_1 ),
        .\parallel_dout_reg[15]_0 (\TC_SRL[31].tc_srl_reg_n_0 ),
        .\parallel_dout_reg[1]_0 (\TC_SRL[31].tc_srl_reg_n_14 ),
        .\parallel_dout_reg[2]_0 (\TC_SRL[31].tc_srl_reg_n_13 ),
        .\parallel_dout_reg[3]_0 (\TC_SRL[31].tc_srl_reg_n_12 ),
        .\parallel_dout_reg[4]_0 (\TC_SRL[31].tc_srl_reg_n_11 ),
        .\parallel_dout_reg[5]_0 (\TC_SRL[31].tc_srl_reg_n_10 ),
        .\parallel_dout_reg[6]_0 (\TC_SRL[31].tc_srl_reg_n_9 ),
        .\parallel_dout_reg[7]_0 (\TC_SRL[31].tc_srl_reg_n_8 ),
        .\parallel_dout_reg[8]_0 (\TC_SRL[31].tc_srl_reg_n_7 ),
        .\parallel_dout_reg[9]_0 (\TC_SRL[31].tc_srl_reg_n_6 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5150]_43 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_2 (\slaveRegDo_tcConfig[5149]_42 ),
        .\slaveRegDo_mux_5_reg[15]_i_2_0 (\slaveRegDo_tcConfig[5148]_41 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[31]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized14 \TC_SRL[3].tc_srl_reg 
       (.E(tc_config_cs_shift_en[3]),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\TC_SRL[3].tc_srl_reg_n_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\TC_SRL[3].tc_srl_reg_n_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\TC_SRL[3].tc_srl_reg_n_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 (\TC_SRL[3].tc_srl_reg_n_11 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 (\TC_SRL[3].tc_srl_reg_n_12 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 (\TC_SRL[3].tc_srl_reg_n_13 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 (\TC_SRL[3].tc_srl_reg_n_14 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 (\TC_SRL[3].tc_srl_reg_n_15 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\TC_SRL[3].tc_srl_reg_n_3 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (\TC_SRL[3].tc_srl_reg_n_4 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 (\TC_SRL[3].tc_srl_reg_n_5 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 (\TC_SRL[3].tc_srl_reg_n_6 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 (\TC_SRL[3].tc_srl_reg_n_7 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 (\TC_SRL[3].tc_srl_reg_n_8 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 (\TC_SRL[3].tc_srl_reg_n_9 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 (\TC_SRL[3].tc_srl_reg_n_10 ),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_1 ),
        .s_daddr_o(s_daddr_o[2:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5122]_15 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[0] (\TC_SRL[7].tc_srl_reg_n_15 ),
        .\slaveRegDo_mux_5_reg[10] (\TC_SRL[7].tc_srl_reg_n_5 ),
        .\slaveRegDo_mux_5_reg[11] (\TC_SRL[7].tc_srl_reg_n_4 ),
        .\slaveRegDo_mux_5_reg[12] (\TC_SRL[7].tc_srl_reg_n_3 ),
        .\slaveRegDo_mux_5_reg[13] (\TC_SRL[7].tc_srl_reg_n_2 ),
        .\slaveRegDo_mux_5_reg[14] (\TC_SRL[7].tc_srl_reg_n_1 ),
        .\slaveRegDo_mux_5_reg[15] (\TC_SRL[7].tc_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_5_0 (\slaveRegDo_tcConfig[5121]_14 ),
        .\slaveRegDo_mux_5_reg[15]_i_5_1 (\slaveRegDo_tcConfig[5120]_13 ),
        .\slaveRegDo_mux_5_reg[1] (\TC_SRL[7].tc_srl_reg_n_14 ),
        .\slaveRegDo_mux_5_reg[2] (\TC_SRL[7].tc_srl_reg_n_13 ),
        .\slaveRegDo_mux_5_reg[3] (\TC_SRL[7].tc_srl_reg_n_12 ),
        .\slaveRegDo_mux_5_reg[4] (\TC_SRL[7].tc_srl_reg_n_11 ),
        .\slaveRegDo_mux_5_reg[5] (\TC_SRL[7].tc_srl_reg_n_10 ),
        .\slaveRegDo_mux_5_reg[6] (\TC_SRL[7].tc_srl_reg_n_9 ),
        .\slaveRegDo_mux_5_reg[7] (\TC_SRL[7].tc_srl_reg_n_8 ),
        .\slaveRegDo_mux_5_reg[8] (\TC_SRL[7].tc_srl_reg_n_7 ),
        .\slaveRegDo_mux_5_reg[9] (\TC_SRL[7].tc_srl_reg_n_6 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[3]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized15 \TC_SRL[4].tc_srl_reg 
       (.E(tc_config_cs_shift_en[4]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1] ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5124]_17 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[4]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized16 \TC_SRL[5].tc_srl_reg 
       (.E(tc_config_cs_shift_en[5]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1] ),
        .\current_state_reg[3]_0 (\xsdb_reg_reg[0]_4 ),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5125]_18 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[5]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized17 \TC_SRL[6].tc_srl_reg 
       (.E(tc_config_cs_shift_en[6]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_6 ),
        .\current_state_reg[1]_1 (\current_state_reg[1] ),
        .\current_state_reg[3]_0 (\xsdb_reg_reg[0]_6 ),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5126]_19 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[6]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized18 \TC_SRL[7].tc_srl_reg 
       (.E(tc_config_cs_shift_en[7]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_7 ),
        .\current_state_reg[1]_1 (\current_state_reg[1] ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .\parallel_dout_reg[0]_0 (\TC_SRL[7].tc_srl_reg_n_15 ),
        .\parallel_dout_reg[10]_0 (\TC_SRL[7].tc_srl_reg_n_5 ),
        .\parallel_dout_reg[11]_0 (\TC_SRL[7].tc_srl_reg_n_4 ),
        .\parallel_dout_reg[12]_0 (\TC_SRL[7].tc_srl_reg_n_3 ),
        .\parallel_dout_reg[13]_0 (\TC_SRL[7].tc_srl_reg_n_2 ),
        .\parallel_dout_reg[14]_0 (\TC_SRL[7].tc_srl_reg_n_1 ),
        .\parallel_dout_reg[15]_0 (\TC_SRL[7].tc_srl_reg_n_0 ),
        .\parallel_dout_reg[1]_0 (\TC_SRL[7].tc_srl_reg_n_14 ),
        .\parallel_dout_reg[2]_0 (\TC_SRL[7].tc_srl_reg_n_13 ),
        .\parallel_dout_reg[3]_0 (\TC_SRL[7].tc_srl_reg_n_12 ),
        .\parallel_dout_reg[4]_0 (\TC_SRL[7].tc_srl_reg_n_11 ),
        .\parallel_dout_reg[5]_0 (\TC_SRL[7].tc_srl_reg_n_10 ),
        .\parallel_dout_reg[6]_0 (\TC_SRL[7].tc_srl_reg_n_9 ),
        .\parallel_dout_reg[7]_0 (\TC_SRL[7].tc_srl_reg_n_8 ),
        .\parallel_dout_reg[8]_0 (\TC_SRL[7].tc_srl_reg_n_7 ),
        .\parallel_dout_reg[9]_0 (\TC_SRL[7].tc_srl_reg_n_6 ),
        .s_daddr_o(s_daddr_o[5:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5126]_19 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_5_reg[15]_i_5 (\slaveRegDo_tcConfig[5125]_18 ),
        .\slaveRegDo_mux_5_reg[15]_i_5_0 (\slaveRegDo_tcConfig[5124]_17 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[7]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized19 \TC_SRL[8].tc_srl_reg 
       (.E(tc_config_cs_shift_en[8]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_4 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_0 (\current_state_reg[3]_1 ),
        .s_daddr_o(s_daddr_o[5:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5128]_21 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[8]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized20 \TC_SRL[9].tc_srl_reg 
       (.E(tc_config_cs_shift_en[9]),
        .\current_state_reg[1]_0 (\current_state_reg[1]_5 ),
        .\current_state_reg[1]_1 (\current_state_reg[1]_3 ),
        .\current_state_reg[3]_0 (\xsdb_reg_reg[0]_4 ),
        .s_daddr_o(s_daddr_o[12:10]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_do_o(\slaveRegDo_tcConfig[5129]_22 ),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[9]));
  (* C_BUILD_REVISION = "0" *) 
  (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_CORE_MAJOR_VER = "6" *) 
  (* C_CORE_MINOR_VER = "2" *) 
  (* C_CORE_TYPE = "1" *) 
  (* C_CSE_DRV_VER = "2" *) 
  (* C_MAJOR_VERSION = "2018" *) 
  (* C_MINOR_VERSION = "3" *) 
  (* C_NEXT_SLAVE = "0" *) 
  (* C_PIPE_IFACE = "1" *) 
  (* C_USE_TEST_REG = "1" *) 
  (* C_XDEVICEFAMILY = "zynq" *) 
  (* C_XSDB_SLAVE_TYPE = "17" *) 
  (* DONT_TOUCH *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
       (.s_daddr_o({s_daddr,s_daddr_o}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di),
        .s_do_i({\slaveRegDo_mux_reg_n_0_[15] ,\slaveRegDo_mux_reg_n_0_[14] ,\slaveRegDo_mux_reg_n_0_[13] ,\slaveRegDo_mux_reg_n_0_[12] ,\slaveRegDo_mux_reg_n_0_[11] ,\slaveRegDo_mux_reg_n_0_[10] ,\slaveRegDo_mux_reg_n_0_[9] ,\slaveRegDo_mux_reg_n_0_[8] ,\slaveRegDo_mux_reg_n_0_[7] ,\slaveRegDo_mux_reg_n_0_[6] ,\slaveRegDo_mux_reg_n_0_[5] ,\slaveRegDo_mux_reg_n_0_[4] ,\slaveRegDo_mux_reg_n_0_[3] ,\slaveRegDo_mux_reg_n_0_[2] ,\slaveRegDo_mux_reg_n_0_[1] ,\slaveRegDo_mux_reg_n_0_[0] }),
        .s_drdy_i(regDrdy_reg_n_0),
        .s_dwe_o(s_dwe_o),
        .s_rst_o(s_rst_o),
        .sl_iport_i(out),
        .sl_oport_o(SL_OPORT_O));
  FDRE adv_drdy_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(adv_drdy_reg_0),
        .Q(adv_drdy),
        .R(1'b0));
  FDRE adv_rb_drdy1_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(adv_rb_drdy),
        .Q(adv_rb_drdy1),
        .R(1'b0));
  (* srl_name = "inst/\ila_core_inst/u_ila_regs/adv_rb_drdy3_reg_srl2 " *) 
  SRL16E adv_rb_drdy3_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(U_XSDB_SLAVE_n_1),
        .D(adv_rb_drdy1),
        .Q(adv_rb_drdy3_reg_srl2_n_0));
  FDRE adv_rb_drdy4_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(adv_rb_drdy3_reg_srl2_n_0),
        .Q(adv_rb_drdy4),
        .R(1'b0));
  FDRE adv_rb_drdy_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(drdy_mux_ff1),
        .Q(adv_rb_drdy),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0080000000000000)) 
    bram_en_i_2
       (.I0(config_fsm_addr[3]),
        .I1(config_fsm_addr[4]),
        .I2(config_fsm_addr[2]),
        .I3(config_fsm_addr[1]),
        .I4(config_fsm_addr[6]),
        .I5(config_fsm_addr[5]),
        .O(bram_en_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    bram_rd_en_i_1
       (.I0(bram_rd_en_i_2_n_0),
        .I1(bram_rd_en_i_3_n_0),
        .I2(config_fsm_addr[0]),
        .I3(bram_rd_en_i_4_n_0),
        .I4(config_fsm_we),
        .I5(config_fsm_en_rb),
        .O(bram_rd_en));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    bram_rd_en_i_2
       (.I0(config_fsm_addr[9]),
        .I1(config_fsm_addr[10]),
        .I2(config_fsm_addr[7]),
        .I3(config_fsm_addr[8]),
        .I4(config_fsm_addr[12]),
        .I5(config_fsm_addr[11]),
        .O(bram_rd_en_i_2_n_0));
  LUT6 #(
    .INIT(64'h0080000000000000)) 
    bram_rd_en_i_3
       (.I0(config_fsm_addr[3]),
        .I1(config_fsm_addr[4]),
        .I2(config_fsm_addr[1]),
        .I3(config_fsm_addr[2]),
        .I4(config_fsm_addr[6]),
        .I5(config_fsm_addr[5]),
        .O(bram_rd_en_i_3_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    bram_rd_en_i_4
       (.I0(config_fsm_addr[14]),
        .I1(config_fsm_addr[13]),
        .I2(config_fsm_addr[16]),
        .I3(config_fsm_addr[15]),
        .O(bram_rd_en_i_4_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \clk_lost_cnt[0]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[0] ),
        .O(p_0_in__1__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \clk_lost_cnt[1]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[0] ),
        .I1(\clk_lost_cnt_reg_n_0_[1] ),
        .O(p_0_in__1__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \clk_lost_cnt[2]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[2] ),
        .I1(\clk_lost_cnt_reg_n_0_[0] ),
        .I2(\clk_lost_cnt_reg_n_0_[1] ),
        .O(p_0_in__1__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \clk_lost_cnt[3]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[3] ),
        .I1(\clk_lost_cnt_reg_n_0_[1] ),
        .I2(\clk_lost_cnt_reg_n_0_[0] ),
        .I3(\clk_lost_cnt_reg_n_0_[2] ),
        .O(p_0_in__1__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \clk_lost_cnt[4]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[4] ),
        .I1(\clk_lost_cnt_reg_n_0_[2] ),
        .I2(\clk_lost_cnt_reg_n_0_[0] ),
        .I3(\clk_lost_cnt_reg_n_0_[1] ),
        .I4(\clk_lost_cnt_reg_n_0_[3] ),
        .O(p_0_in__1__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \clk_lost_cnt[5]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[5] ),
        .I1(\clk_lost_cnt_reg_n_0_[3] ),
        .I2(\clk_lost_cnt_reg_n_0_[1] ),
        .I3(\clk_lost_cnt_reg_n_0_[0] ),
        .I4(\clk_lost_cnt_reg_n_0_[2] ),
        .I5(\clk_lost_cnt_reg_n_0_[4] ),
        .O(p_0_in__1__0[5]));
  LUT2 #(
    .INIT(4'h9)) 
    \clk_lost_cnt[6]_i_1 
       (.I0(\clk_lost_cnt[8]_i_4_n_0 ),
        .I1(\clk_lost_cnt_reg_n_0_[6] ),
        .O(p_0_in__1__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \clk_lost_cnt[7]_i_1 
       (.I0(\clk_lost_cnt_reg_n_0_[7] ),
        .I1(\clk_lost_cnt[8]_i_4_n_0 ),
        .I2(\clk_lost_cnt_reg_n_0_[6] ),
        .O(p_0_in__1__0[7]));
  LUT3 #(
    .INIT(8'hBE)) 
    \clk_lost_cnt[8]_i_1 
       (.I0(s_rst_o),
        .I1(next_state_xsdb),
        .I2(ila_clk_flag_sync2),
        .O(\clk_lost_cnt[8]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \clk_lost_cnt[8]_i_2 
       (.I0(clk_lost_cnt_reg__0),
        .O(sel));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \clk_lost_cnt[8]_i_3 
       (.I0(\clk_lost_cnt_reg_n_0_[6] ),
        .I1(\clk_lost_cnt[8]_i_4_n_0 ),
        .I2(\clk_lost_cnt_reg_n_0_[7] ),
        .O(p_0_in__1__0[8]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \clk_lost_cnt[8]_i_4 
       (.I0(\clk_lost_cnt_reg_n_0_[4] ),
        .I1(\clk_lost_cnt_reg_n_0_[2] ),
        .I2(\clk_lost_cnt_reg_n_0_[0] ),
        .I3(\clk_lost_cnt_reg_n_0_[1] ),
        .I4(\clk_lost_cnt_reg_n_0_[3] ),
        .I5(\clk_lost_cnt_reg_n_0_[5] ),
        .O(\clk_lost_cnt[8]_i_4_n_0 ));
  FDRE \clk_lost_cnt_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[0]),
        .Q(\clk_lost_cnt_reg_n_0_[0] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[1]),
        .Q(\clk_lost_cnt_reg_n_0_[1] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[2]),
        .Q(\clk_lost_cnt_reg_n_0_[2] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[3]),
        .Q(\clk_lost_cnt_reg_n_0_[3] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[4]),
        .Q(\clk_lost_cnt_reg_n_0_[4] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[5]),
        .Q(\clk_lost_cnt_reg_n_0_[5] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[6]),
        .Q(\clk_lost_cnt_reg_n_0_[6] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[7]),
        .Q(\clk_lost_cnt_reg_n_0_[7] ),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  FDRE \clk_lost_cnt_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(sel),
        .D(p_0_in__1__0[8]),
        .Q(clk_lost_cnt_reg__0),
        .R(\clk_lost_cnt[8]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0082)) 
    clk_lost_i_1
       (.I0(clk_lost_cnt_reg__0),
        .I1(ila_clk_flag_sync2),
        .I2(next_state_xsdb),
        .I3(s_rst_o),
        .O(clk_lost_i_1_n_0));
  FDRE clk_lost_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(clk_lost_i_1_n_0),
        .Q(clk_lost),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \count0[0]_i_1 
       (.I0(count0_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \count0[1]_i_1 
       (.I0(count0_reg__0[0]),
        .I1(count0_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \count0[2]_i_1 
       (.I0(count0_reg__0[2]),
        .I1(count0_reg__0[1]),
        .I2(count0_reg__0[0]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \count0[3]_i_1 
       (.I0(count0_reg__0[3]),
        .I1(count0_reg__0[0]),
        .I2(count0_reg__0[1]),
        .I3(count0_reg__0[2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \count0[4]_i_1 
       (.I0(count0_reg__0[4]),
        .I1(count0_reg__0[2]),
        .I2(count0_reg__0[1]),
        .I3(count0_reg__0[0]),
        .I4(count0_reg__0[3]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \count0[5]_i_1 
       (.I0(count0_reg__0[5]),
        .I1(count0_reg__0[3]),
        .I2(count0_reg__0[0]),
        .I3(count0_reg__0[1]),
        .I4(count0_reg__0[2]),
        .I5(count0_reg__0[4]),
        .O(p_0_in[5]));
  LUT2 #(
    .INIT(4'hE)) 
    \count0[6]_i_1 
       (.I0(count0_reg__0[6]),
        .I1(s_rst_o),
        .O(count00));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \count0[6]_i_2 
       (.I0(count0_reg__0[4]),
        .I1(count0_reg__0[2]),
        .I2(count0_reg__0[1]),
        .I3(count0_reg__0[0]),
        .I4(count0_reg__0[3]),
        .I5(count0_reg__0[5]),
        .O(p_0_in[6]));
  FDRE \count0_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[0]),
        .Q(count0_reg__0[0]),
        .R(count00));
  FDRE \count0_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[1]),
        .Q(count0_reg__0[1]),
        .R(count00));
  FDRE \count0_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[2]),
        .Q(count0_reg__0[2]),
        .R(count00));
  FDRE \count0_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[3]),
        .Q(count0_reg__0[3]),
        .R(count00));
  FDRE \count0_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[4]),
        .Q(count0_reg__0[4]),
        .R(count00));
  FDRE \count0_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[5]),
        .Q(count0_reg__0[5]),
        .R(count00));
  FDRE \count0_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ff9),
        .D(p_0_in[6]),
        .Q(count0_reg__0[6]),
        .R(count00));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \count1[0]_i_1 
       (.I0(count1_reg__0[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \count1[1]_i_1 
       (.I0(count1_reg__0[0]),
        .I1(count1_reg__0[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \count1[2]_i_1 
       (.I0(count1_reg__0[2]),
        .I1(count1_reg__0[1]),
        .I2(count1_reg__0[0]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \count1[3]_i_1 
       (.I0(count1_reg__0[3]),
        .I1(count1_reg__0[2]),
        .I2(count1_reg__0[0]),
        .I3(count1_reg__0[1]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \count1[4]_i_1 
       (.I0(count1_reg__0[4]),
        .I1(count1_reg__0[1]),
        .I2(count1_reg__0[0]),
        .I3(count1_reg__0[2]),
        .I4(count1_reg__0[3]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \count1[5]_i_1 
       (.I0(count1_reg__0[5]),
        .I1(count1_reg__0[3]),
        .I2(count1_reg__0[2]),
        .I3(count1_reg__0[0]),
        .I4(count1_reg__0[1]),
        .I5(count1_reg__0[4]),
        .O(p_0_in__0[5]));
  LUT2 #(
    .INIT(4'hE)) 
    \count1[6]_i_1 
       (.I0(s_rst_o),
        .I1(count1_reg__0[6]),
        .O(count10));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \count1[6]_i_2 
       (.I0(count1_reg__0[4]),
        .I1(count1_reg__0[1]),
        .I2(count1_reg__0[0]),
        .I3(count1_reg__0[2]),
        .I4(count1_reg__0[3]),
        .I5(count1_reg__0[5]),
        .O(p_0_in__0[6]));
  FDRE \count1_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[0]),
        .Q(count1_reg__0[0]),
        .R(count10));
  FDRE \count1_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[1]),
        .Q(count1_reg__0[1]),
        .R(count10));
  FDRE \count1_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[2]),
        .Q(count1_reg__0[2]),
        .R(count10));
  FDRE \count1_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[3]),
        .Q(count1_reg__0[3]),
        .R(count10));
  FDRE \count1_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[4]),
        .Q(count1_reg__0[4]),
        .R(count10));
  FDRE \count1_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[5]),
        .Q(count1_reg__0[5]),
        .R(count10));
  FDRE \count1_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(xsdb_rden_ffa),
        .D(p_0_in__0[6]),
        .Q(count1_reg__0[6]),
        .R(count10));
  FDSE count_tt_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(count_tt_reg_0),
        .Q(count_tt),
        .S(s_rst_o));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \current_state[4]_i_3 
       (.I0(reg_stream_ffd_n_1),
        .I1(s_daddr_o[10]),
        .I2(s_daddr_o[8]),
        .I3(s_den_o),
        .I4(s_daddr_o[12]),
        .I5(\current_state[4]_i_4_n_0 ),
        .O(read_data_en));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \current_state[4]_i_4 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[11]),
        .I4(s_daddr_o[1]),
        .O(\current_state[4]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h00DE)) 
    \drdyCount[0]_i_1 
       (.I0(drdyCount[0]),
        .I1(s_den_o),
        .I2(\drdyCount[5]_i_2_n_0 ),
        .I3(\drdyCount[5]_i_4_n_0 ),
        .O(\drdyCount[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \drdyCount[1]_i_1 
       (.I0(drdyCount[1]),
        .I1(drdyCount[0]),
        .O(\drdyCount[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \drdyCount[2]_i_1 
       (.I0(drdyCount[2]),
        .I1(drdyCount[0]),
        .I2(drdyCount[1]),
        .O(\drdyCount[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \drdyCount[3]_i_1 
       (.I0(drdyCount[3]),
        .I1(drdyCount[1]),
        .I2(drdyCount[0]),
        .I3(drdyCount[2]),
        .O(\drdyCount[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F707F808)) 
    \drdyCount[4]_i_1 
       (.I0(\drdyCount[5]_i_6_n_0 ),
        .I1(\drdyCount[5]_i_2_n_0 ),
        .I2(s_den_o),
        .I3(\drdyCount[4]_i_2_n_0 ),
        .I4(drdyCount[4]),
        .I5(\drdyCount[5]_i_4_n_0 ),
        .O(\drdyCount[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1555555555555555)) 
    \drdyCount[4]_i_2 
       (.I0(s_daddr_o[12]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
        .O(\drdyCount[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \drdyCount[5]_i_1 
       (.I0(s_den_o),
        .I1(\drdyCount[5]_i_4_n_0 ),
        .O(\drdyCount[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \drdyCount[5]_i_2 
       (.I0(drdyCount[1]),
        .I1(drdyCount[0]),
        .I2(drdyCount[3]),
        .I3(s_den_o),
        .I4(drdyCount[2]),
        .I5(\drdyCount[5]_i_5_n_0 ),
        .O(\drdyCount[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \drdyCount[5]_i_3 
       (.I0(drdyCount[4]),
        .I1(\drdyCount[5]_i_6_n_0 ),
        .I2(drdyCount[5]),
        .O(\drdyCount[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEEEEEEEEE)) 
    \drdyCount[5]_i_4 
       (.I0(s_rst_o),
        .I1(drdyCount[5]),
        .I2(drdyCount[1]),
        .I3(drdyCount[2]),
        .I4(drdyCount[3]),
        .I5(drdyCount[4]),
        .O(\drdyCount[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \drdyCount[5]_i_5 
       (.I0(drdyCount[4]),
        .I1(drdyCount[5]),
        .O(\drdyCount[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \drdyCount[5]_i_6 
       (.I0(drdyCount[3]),
        .I1(drdyCount[1]),
        .I2(drdyCount[0]),
        .I3(drdyCount[2]),
        .O(\drdyCount[5]_i_6_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \drdyCount_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\drdyCount[0]_i_1_n_0 ),
        .Q(drdyCount[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \drdyCount_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(\drdyCount[5]_i_2_n_0 ),
        .D(\drdyCount[1]_i_1_n_0 ),
        .Q(drdyCount[1]),
        .R(\drdyCount[5]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \drdyCount_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(\drdyCount[5]_i_2_n_0 ),
        .D(\drdyCount[2]_i_1_n_0 ),
        .Q(drdyCount[2]),
        .R(\drdyCount[5]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \drdyCount_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(\drdyCount[5]_i_2_n_0 ),
        .D(\drdyCount[3]_i_1_n_0 ),
        .Q(drdyCount[3]),
        .R(\drdyCount[5]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \drdyCount_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\drdyCount[4]_i_1_n_0 ),
        .Q(drdyCount[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \drdyCount_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(\drdyCount[5]_i_2_n_0 ),
        .D(\drdyCount[5]_i_3_n_0 ),
        .Q(drdyCount[5]),
        .R(\drdyCount[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0200)) 
    drdy_ff7_i_1
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
        .I1(drdy_ff7_i_2_n_0),
        .I2(s_dwe_o),
        .I3(s_den_o),
        .O(xsdb_rden_ff7));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT4 #(
    .INIT(16'hFF7F)) 
    drdy_ff7_i_2
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .O(drdy_ff7_i_2_n_0));
  FDRE drdy_ff7_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(xsdb_rden_ff7),
        .Q(drdy_ff7),
        .R(s_rst_o));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    drdy_ff8_i_1
       (.I0(reg_stream_ffd_n_1),
        .I1(s_daddr_o[11]),
        .I2(s_daddr_o[3]),
        .I3(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .I4(s_daddr_o[2]),
        .I5(drdy_ff9_i_3_n_0),
        .O(xsdb_rden_ff8));
  FDRE drdy_ff8_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(xsdb_rden_ff8),
        .Q(drdy_ff8),
        .R(s_rst_o));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    drdy_ff9_i_1
       (.I0(reg_stream_ffd_n_1),
        .I1(s_daddr_o[3]),
        .I2(\xsdb_reg_reg[0]_4 ),
        .I3(s_daddr_o[11]),
        .I4(s_daddr_o[2]),
        .I5(drdy_ff9_i_3_n_0),
        .O(xsdb_rden_ff9));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT4 #(
    .INIT(16'hFF7F)) 
    drdy_ff9_i_3
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[8]),
        .I2(s_den_o),
        .I3(s_dwe_o),
        .O(drdy_ff9_i_3_n_0));
  FDRE drdy_ff9_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(xsdb_rden_ff9),
        .Q(drdy_ff9),
        .R(s_rst_o));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    drdy_ffa_i_1
       (.I0(drdy_ffa_i_2_n_0),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[11]),
        .I4(s_daddr_o[1]),
        .I5(drdy_ff9_i_3_n_0),
        .O(xsdb_rden_ffa));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    drdy_ffa_i_2
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[9]),
        .I3(s_daddr_o[7]),
        .I4(s_daddr_o[4]),
        .I5(s_daddr_o[6]),
        .O(drdy_ffa_i_2_n_0));
  FDRE drdy_ffa_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(xsdb_rden_ffa),
        .Q(drdy_ffa),
        .R(s_rst_o));
  FDRE drdy_mux_ff1_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(drdy_mux_ff),
        .Q(drdy_mux_ff1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    drdy_mux_ff_i_1
       (.I0(drdyCount[3]),
        .I1(drdyCount[2]),
        .I2(drdyCount[1]),
        .I3(drdyCount[5]),
        .I4(drdyCount[0]),
        .I5(drdyCount[4]),
        .O(drdy_mux_ff_i_1_n_0));
  FDRE drdy_mux_ff_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(drdy_mux_ff_i_1_n_0),
        .Q(drdy_mux_ff),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE dummy_temp1_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(DUMMY_I),
        .Q(dummy_temp1),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE dummy_temp_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(dummy_temp1),
        .Q(dummy_temp),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    ila_clk_flag_reg
       (.C(ila_clk_flag_reg_1),
        .CE(1'b1),
        .D(ila_clk_flag_reg_2),
        .Q(ila_clk_flag),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE ila_clk_flag_sync1_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(ila_clk_flag),
        .Q(ila_clk_flag_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE ila_clk_flag_sync2_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(ila_clk_flag_sync1),
        .Q(ila_clk_flag_sync2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    next_state_ila_reg
       (.C(ila_clk_flag_reg_1),
        .CE(1'b1),
        .D(s_dclk_flag_sync2),
        .Q(next_state_ila),
        .R(1'b0));
  FDRE next_state_xsdb_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(ila_clk_flag_sync2),
        .Q(next_state_xsdb),
        .R(s_rst_o));
  FDRE \regAck_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(regAck_temp),
        .Q(regAck_reg),
        .R(1'b0));
  FDRE \regAck_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(regAck_temp_reg),
        .Q(\regAck_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \regAck_temp_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_den_o),
        .Q(regAck_temp),
        .R(1'b0));
  FDRE \regAck_temp_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(data_out_en),
        .Q(regAck_temp_reg),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF54FFFFFF100000)) 
    regDrdy_i_1
       (.I0(s_daddr_o[3]),
        .I1(regDrdy_i_2_n_0),
        .I2(drdy_ff7),
        .I3(regDrdy_i_3_n_0),
        .I4(regDrdy_i_4_n_0),
        .I5(drdy_mux_ff1),
        .O(regDrdy_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    regDrdy_i_2
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .O(regDrdy_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT4 #(
    .INIT(16'hB080)) 
    regDrdy_i_3
       (.I0(regDrdy_i_5_n_0),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(regDrdy_i_6_n_0),
        .O(regDrdy_i_3_n_0));
  LUT5 #(
    .INIT(32'h00004000)) 
    regDrdy_i_4
       (.I0(reg_stream_ffd_n_1),
        .I1(s_daddr_o[10]),
        .I2(s_daddr_o[8]),
        .I3(s_daddr_o[11]),
        .I4(s_daddr_o[12]),
        .O(regDrdy_i_4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    regDrdy_i_5
       (.I0(drdy_mux_ff1),
        .I1(\regAck_reg_n_0_[1] ),
        .I2(s_daddr_o[1]),
        .I3(regAck_reg),
        .I4(s_daddr_o[0]),
        .I5(adv_drdy),
        .O(regDrdy_i_5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    regDrdy_i_6
       (.I0(adv_rb_drdy4),
        .I1(drdy_ffa),
        .I2(s_daddr_o[1]),
        .I3(drdy_ff9),
        .I4(s_daddr_o[0]),
        .I5(drdy_ff8),
        .O(regDrdy_i_6_n_0));
  FDRE regDrdy_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(regDrdy_i_1_n_0),
        .Q(regDrdy_reg_n_0),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized39 reg_15
       (.Q(reg_9_n_0),
        .SR(SR),
        .in0(in0),
        .read_reset_addr({read_reset_addr[9:7],read_reset_addr[5:4]}),
        .s_daddr_o(s_daddr_o[4:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\slaveRegDo_mux_0[4]_i_2 (\slaveRegDo_mux_6_reg[0]_0 ),
        .\slaveRegDo_mux_0[4]_i_2_0 (reg_17_n_15),
        .\slaveRegDo_mux_0[5]_i_3 (reg_17_n_14),
        .\slaveRegDo_mux_0[7]_i_3 (reg_17_n_13),
        .\slaveRegDo_mux_0[8]_i_3 (reg_17_n_12),
        .\slaveRegDo_mux_0[9]_i_3 (reg_17_n_11),
        .\slaveRegDo_mux_0_reg[9] (reg_18_n_16),
        .\slaveRegDo_mux_0_reg[9]_0 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
        .\slaveRegDo_mux_0_reg[9]_1 (reg_6_n_6),
        .\slaveRegDo_mux_0_reg[9]_2 (\slaveRegDo_mux_0[4]_i_10_n_0 ),
        .\xsdb_reg_reg[0] (reg_16_n_1),
        .\xsdb_reg_reg[0]_0 (reg_85_n_1),
        .\xsdb_reg_reg[10] (reg_15_n_10),
        .\xsdb_reg_reg[11] (reg_15_n_9),
        .\xsdb_reg_reg[12] (reg_15_n_8),
        .\xsdb_reg_reg[13] (reg_15_n_7),
        .\xsdb_reg_reg[14] (reg_15_n_6),
        .\xsdb_reg_reg[15] (reg_15_n_5),
        .\xsdb_reg_reg[1] (reg_15_n_14),
        .\xsdb_reg_reg[3] (reg_15_n_12),
        .\xsdb_reg_reg[4] (reg_15_n_4),
        .\xsdb_reg_reg[5] (reg_15_n_3),
        .\xsdb_reg_reg[6] (reg_15_n_11),
        .\xsdb_reg_reg[7] (reg_15_n_2),
        .\xsdb_reg_reg[8] (reg_15_n_1),
        .\xsdb_reg_reg[9] (reg_15_n_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized40 reg_16
       (.\G_1PIPE_IFACE.s_daddr_r_reg[12] (reg_16_n_1),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_16_n_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[6] (reg_16_n_2),
        .read_reset_addr(read_reset_addr),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di),
        .s_dwe_o(s_dwe_o),
        .\xsdb_reg_reg[10] (reg_16_n_8),
        .\xsdb_reg_reg[11] (reg_16_n_7),
        .\xsdb_reg_reg[12] (reg_16_n_6),
        .\xsdb_reg_reg[13] (reg_16_n_5),
        .\xsdb_reg_reg[14] (reg_16_n_4),
        .\xsdb_reg_reg[15] (reg_16_n_3));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized41 reg_17
       (.D({reg_17_n_0,reg_17_n_1,reg_17_n_2}),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (reg_17_n_4),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (reg_17_n_5),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (reg_17_n_6),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (reg_17_n_7),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (reg_17_n_8),
        .\G_1PIPE_IFACE.s_daddr_r_reg[7] (reg_17_n_3),
        .SR(SR),
        .in0(in0),
        .read_reset_addr({read_reset_addr[6],read_reset_addr[3:0]}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di),
        .s_dwe_o(s_dwe_o),
        .\slaveRegDo_mux_0[10]_i_3 (reg_16_n_8),
        .\slaveRegDo_mux_0[10]_i_3_0 (reg_15_n_10),
        .\slaveRegDo_mux_0[11]_i_3 (reg_16_n_7),
        .\slaveRegDo_mux_0[11]_i_3_0 (reg_15_n_9),
        .\slaveRegDo_mux_0[12]_i_3 (reg_16_n_6),
        .\slaveRegDo_mux_0[12]_i_3_0 (reg_15_n_8),
        .\slaveRegDo_mux_0[13]_i_3 (reg_16_n_5),
        .\slaveRegDo_mux_0[13]_i_3_0 (reg_15_n_7),
        .\slaveRegDo_mux_0[14]_i_3 (reg_16_n_4),
        .\slaveRegDo_mux_0[14]_i_3_0 (reg_15_n_6),
        .\slaveRegDo_mux_0[15]_i_3 (reg_16_n_3),
        .\slaveRegDo_mux_0[15]_i_3_0 (reg_15_n_5),
        .\slaveRegDo_mux_0[1]_i_2 (reg_15_n_14),
        .\slaveRegDo_mux_0[3]_i_3 (reg_15_n_12),
        .\slaveRegDo_mux_0[6]_i_3 (reg_15_n_11),
        .\slaveRegDo_mux_0_reg[0] (reg_83_n_3),
        .\slaveRegDo_mux_0_reg[0]_0 (reg_1a_n_13),
        .\slaveRegDo_mux_0_reg[0]_1 (reg_8_n_3),
        .\slaveRegDo_mux_0_reg[11] (reg_1a_n_6),
        .\slaveRegDo_mux_0_reg[11]_0 (reg_6_n_14),
        .\slaveRegDo_mux_0_reg[12] (reg_1a_n_5),
        .\slaveRegDo_mux_0_reg[12]_0 (reg_6_n_13),
        .\slaveRegDo_mux_0_reg[13] (reg_1a_n_4),
        .\slaveRegDo_mux_0_reg[13]_0 (reg_6_n_12),
        .\slaveRegDo_mux_0_reg[14] (reg_1a_n_3),
        .\slaveRegDo_mux_0_reg[14]_0 (reg_6_n_11),
        .\slaveRegDo_mux_0_reg[15] (s_daddr_o[7:0]),
        .\slaveRegDo_mux_0_reg[15]_0 (reg_83_n_17),
        .\slaveRegDo_mux_0_reg[15]_1 (reg_1a_n_2),
        .\slaveRegDo_mux_0_reg[15]_2 (reg_6_n_0),
        .\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
        .\slaveRegDo_mux_0_reg[1]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .\slaveRegDo_mux_0_reg[1]_1 ({\slaveRegDo_mux_1[1]_i_1_n_0 ,\slaveRegDo_mux_1[0]_i_1_n_0 }),
        .\slaveRegDo_mux_0_reg[1]_2 (reg_83_n_4),
        .\slaveRegDo_mux_0_reg[1]_3 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
        .\slaveRegDo_mux_0_reg[1]_4 (reg_1a_n_12),
        .\slaveRegDo_mux_0_reg[1]_5 (reg_7_n_4),
        .\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_1[4]_i_1_n_0 ),
        .\slaveRegDo_mux_0_reg[2]_0 (reg_83_n_5),
        .\slaveRegDo_mux_0_reg[2]_1 (reg_1a_n_9),
        .\slaveRegDo_mux_0_reg[2]_2 (reg_8_n_1),
        .\slaveRegDo_mux_0_reg[3] (reg_1a_n_7),
        .\slaveRegDo_mux_0_reg[3]_0 (reg_8_n_0),
        .\xsdb_reg_reg[0] (reg_16_n_0),
        .\xsdb_reg_reg[10] (reg_17_n_9),
        .\xsdb_reg_reg[4] (reg_17_n_15),
        .\xsdb_reg_reg[5] (reg_17_n_14),
        .\xsdb_reg_reg[6] (reg_17_n_10),
        .\xsdb_reg_reg[7] (reg_17_n_13),
        .\xsdb_reg_reg[8] (reg_17_n_12),
        .\xsdb_reg_reg[9] (reg_17_n_11));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized42 reg_18
       (.D(reg_18_n_11),
        .\G_1PIPE_IFACE.s_daddr_r_reg[6] (reg_18_n_15),
        .Q({reg_9_n_1,reg_9_n_2,reg_9_n_4,reg_9_n_5}),
        .s_daddr_o({s_daddr_o[8:3],s_daddr_o[1:0]}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\slaveRegDo_mux_0[4]_i_2 (\slaveRegDo_mux_0[4]_i_2 ),
        .\slaveRegDo_mux_0[4]_i_2_0 (reg_19_n_11),
        .\slaveRegDo_mux_0[4]_i_2_1 (reg_1a_n_18),
        .\slaveRegDo_mux_0[5]_i_3 (reg_19_n_10),
        .\slaveRegDo_mux_0[5]_i_3_0 (reg_1a_n_17),
        .\slaveRegDo_mux_0[7]_i_3 (reg_19_n_8),
        .\slaveRegDo_mux_0[7]_i_3_0 (reg_1a_n_16),
        .\slaveRegDo_mux_0[8]_i_3 (reg_19_n_7),
        .\slaveRegDo_mux_0[8]_i_3_0 (reg_1a_n_15),
        .\slaveRegDo_mux_0[9]_i_3 (reg_19_n_6),
        .\slaveRegDo_mux_0[9]_i_3_0 (reg_1a_n_14),
        .\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
        .\slaveRegDo_mux_0_reg[4]_0 (reg_83_n_7),
        .\slaveRegDo_mux_0_reg[4]_1 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .\slaveRegDo_mux_0_reg[4]_2 (\slaveRegDo_mux_1[4]_i_1_n_0 ),
        .\slaveRegDo_mux_0_reg[4]_3 (reg_15_n_4),
        .\slaveRegDo_mux_0_reg[4]_4 (reg_7_n_0),
        .\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
        .\slaveRegDo_mux_0_reg[5]_0 (\slaveRegDo_mux_0[4]_i_10_n_0 ),
        .\slaveRegDo_mux_0_reg[5]_1 (reg_15_n_3),
        .\slaveRegDo_mux_0_reg[5]_2 (reg_6_n_15),
        .\slaveRegDo_mux_0_reg[7] (reg_15_n_2),
        .\slaveRegDo_mux_0_reg[7]_0 (reg_7_n_1),
        .\slaveRegDo_mux_0_reg[8] (reg_15_n_1),
        .\slaveRegDo_mux_0_reg[8]_0 (reg_7_n_2),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0]_1 ),
        .\xsdb_reg_reg[15] ({slaveRegDo_18[15:10],slaveRegDo_18[6],slaveRegDo_18[3:0]}),
        .\xsdb_reg_reg[5] (reg_18_n_14),
        .\xsdb_reg_reg[7] (reg_18_n_12),
        .\xsdb_reg_reg[8] (reg_18_n_13),
        .\xsdb_reg_reg[9] (reg_18_n_16));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized43 reg_19
       (.s_daddr_o(s_daddr_o[4:2]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\xsdb_reg_reg[0] (reg_19_n_15),
        .\xsdb_reg_reg[0]_0 (reg_16_n_1),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_4 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_5 ),
        .\xsdb_reg_reg[10] (reg_19_n_5),
        .\xsdb_reg_reg[11] (reg_19_n_4),
        .\xsdb_reg_reg[12] (reg_19_n_3),
        .\xsdb_reg_reg[13] (reg_19_n_2),
        .\xsdb_reg_reg[14] (reg_19_n_1),
        .\xsdb_reg_reg[15] (reg_19_n_0),
        .\xsdb_reg_reg[1] (reg_19_n_14),
        .\xsdb_reg_reg[2] (reg_19_n_13),
        .\xsdb_reg_reg[3] (reg_19_n_12),
        .\xsdb_reg_reg[4] (reg_19_n_11),
        .\xsdb_reg_reg[5] (reg_19_n_10),
        .\xsdb_reg_reg[6] (reg_19_n_9),
        .\xsdb_reg_reg[7] (reg_19_n_8),
        .\xsdb_reg_reg[8] (reg_19_n_7),
        .\xsdb_reg_reg[9] (reg_19_n_6));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized44 reg_1a
       (.\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_1a_n_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_1a_n_1),
        .s_daddr_o(s_daddr_o[4:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\slaveRegDo_mux_0[0]_i_2 (reg_19_n_15),
        .\slaveRegDo_mux_0[10]_i_3 (reg_19_n_5),
        .\slaveRegDo_mux_0[11]_i_3 (reg_19_n_4),
        .\slaveRegDo_mux_0[12]_i_3 (reg_19_n_3),
        .\slaveRegDo_mux_0[13]_i_3 (reg_19_n_2),
        .\slaveRegDo_mux_0[14]_i_3 (reg_19_n_1),
        .\slaveRegDo_mux_0[15]_i_3 (reg_19_n_0),
        .\slaveRegDo_mux_0[15]_i_3_0 ({slaveRegDo_18[15:10],slaveRegDo_18[6],slaveRegDo_18[3:0]}),
        .\slaveRegDo_mux_0[1]_i_2 (reg_19_n_14),
        .\slaveRegDo_mux_0[2]_i_2 (reg_19_n_13),
        .\slaveRegDo_mux_0[3]_i_3 (reg_19_n_12),
        .\slaveRegDo_mux_0[6]_i_3 (reg_19_n_9),
        .\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
        .\slaveRegDo_mux_0_reg[10]_0 (reg_17_n_9),
        .\slaveRegDo_mux_0_reg[10]_1 (reg_7_n_3),
        .\slaveRegDo_mux_0_reg[6] (reg_17_n_10),
        .\slaveRegDo_mux_0_reg[6]_0 (reg_8_n_2),
        .\xsdb_reg_reg[0] (reg_1a_n_13),
        .\xsdb_reg_reg[0]_0 (reg_16_n_1),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_6 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_5 ),
        .\xsdb_reg_reg[11] (reg_1a_n_6),
        .\xsdb_reg_reg[12] (reg_1a_n_5),
        .\xsdb_reg_reg[13] (reg_1a_n_4),
        .\xsdb_reg_reg[14] (reg_1a_n_3),
        .\xsdb_reg_reg[15] (reg_1a_n_2),
        .\xsdb_reg_reg[1] (reg_1a_n_12),
        .\xsdb_reg_reg[2] (reg_1a_n_9),
        .\xsdb_reg_reg[2]_0 (capture_qual_ctrl_1),
        .\xsdb_reg_reg[3] (reg_1a_n_7),
        .\xsdb_reg_reg[3]_0 (en_adv_trigger_1),
        .\xsdb_reg_reg[4] (reg_1a_n_18),
        .\xsdb_reg_reg[5] (reg_1a_n_17),
        .\xsdb_reg_reg[7] (reg_1a_n_16),
        .\xsdb_reg_reg[8] (reg_1a_n_15),
        .\xsdb_reg_reg[9] (reg_1a_n_14));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized24 reg_6
       (.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_6_n_7),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (reg_6_n_8),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 (reg_6_n_9),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_2 (reg_6_n_10),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_6_n_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_6_n_11),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_6_n_12),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (reg_6_n_13),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (reg_6_n_14),
        .s_daddr_o(s_daddr_o[8:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\slaveRegDo_mux_0[0]_i_6 (arm_ctrl),
        .\slaveRegDo_mux_0[11]_i_3 (reg_7_n_10),
        .\slaveRegDo_mux_0[12]_i_3 (reg_7_n_9),
        .\slaveRegDo_mux_0[13]_i_3 (reg_7_n_8),
        .\slaveRegDo_mux_0[14]_i_3 (reg_7_n_7),
        .\slaveRegDo_mux_0[15]_i_3 (reg_7_n_6),
        .\slaveRegDo_mux_0[2]_i_6 (reg_7_n_15),
        .\slaveRegDo_mux_0[3]_i_7 (reg_7_n_14),
        .\slaveRegDo_mux_0[5]_i_3 (reg_7_n_13),
        .\slaveRegDo_mux_0[6]_i_7 (reg_7_n_12),
        .\slaveRegDo_mux_0[9]_i_3 (reg_7_n_11),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[10] ({slaveRegDo_6[10],slaveRegDo_6[8:7],slaveRegDo_6[4],slaveRegDo_6[1]}),
        .\xsdb_reg_reg[5] (reg_6_n_15),
        .\xsdb_reg_reg[9] (reg_6_n_6));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized25 reg_7
       (.DOUT_O(DOUT_O),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_7_n_4),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_7_n_3),
        .Q(reg_8_n_4),
        .halt_ctrl(halt_ctrl),
        .s_daddr_o(s_daddr_o[3:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .scnt_cmp_temp(scnt_cmp_temp),
        .\slaveRegDo_mux_0[10]_i_3 ({slaveRegDo_6[10],slaveRegDo_6[8:7],slaveRegDo_6[4],slaveRegDo_6[1]}),
        .\slaveRegDo_mux_0[1]_i_2 (reg_9_n_8),
        .\slaveRegDo_mux_0[1]_i_2_0 (\slaveRegDo_mux_0[4]_i_2 ),
        .u_wcnt_hcmp_q(u_wcnt_hcmp_q),
        .u_wcnt_lcmp_q(u_wcnt_lcmp_q),
        .wcnt_hcmp_temp(wcnt_hcmp_temp),
        .wcnt_lcmp_temp(wcnt_lcmp_temp),
        .\xsdb_reg_reg[0] (arm_ctrl),
        .\xsdb_reg_reg[0]_0 (reg_16_n_1),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_5 ),
        .\xsdb_reg_reg[0]_2 (reg_83_n_16),
        .\xsdb_reg_reg[11] (reg_7_n_10),
        .\xsdb_reg_reg[12] (reg_7_n_9),
        .\xsdb_reg_reg[13] (reg_7_n_8),
        .\xsdb_reg_reg[14] (reg_7_n_7),
        .\xsdb_reg_reg[15] (reg_7_n_6),
        .\xsdb_reg_reg[2] (reg_7_n_15),
        .\xsdb_reg_reg[3] (reg_7_n_14),
        .\xsdb_reg_reg[4] (reg_7_n_0),
        .\xsdb_reg_reg[5] (reg_7_n_13),
        .\xsdb_reg_reg[6] (reg_7_n_12),
        .\xsdb_reg_reg[7] (reg_7_n_1),
        .\xsdb_reg_reg[8] (reg_7_n_2),
        .\xsdb_reg_reg[9] (reg_7_n_11));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized26 reg_8
       (.D({clk_lost,\xsdb_reg_reg[3]_0 }),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_8_n_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (reg_8_n_2),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 (reg_8_n_3),
        .Q({reg_9_n_3,reg_9_n_6,reg_9_n_7,reg_9_n_9}),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .\slaveRegDo_mux_0[0]_i_2 (\slaveRegDo_mux_0[4]_i_2 ),
        .\slaveRegDo_mux_0[0]_i_2_0 (reg_6_n_10),
        .\slaveRegDo_mux_0[2]_i_2 (reg_6_n_8),
        .\slaveRegDo_mux_0[3]_i_3 (reg_6_n_7),
        .\slaveRegDo_mux_0[6]_i_3 (reg_6_n_9),
        .\xsdb_reg_reg[1] (reg_8_n_4),
        .\xsdb_reg_reg[2] (reg_8_n_1));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized45 reg_80
       (.s_daddr_o(s_daddr_o[2:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .slaveRegDo_80(slaveRegDo_80),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0]_3 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized46 reg_81
       (.s_daddr_o(s_daddr_o[2:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .slaveRegDo_81(slaveRegDo_81),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0]_3 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized47 reg_82
       (.s_daddr_o(s_daddr_o[2:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .slaveRegDo_82(slaveRegDo_82),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0]_3 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized48 reg_83
       (.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_15),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (reg_83_n_3),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (reg_83_n_4),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (reg_83_n_5),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (reg_83_n_7),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_83_n_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_83_n_1),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_83_n_2),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (reg_83_n_6),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (reg_83_n_8),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (reg_83_n_9),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (reg_83_n_10),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (reg_83_n_11),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (reg_83_n_12),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 (reg_83_n_13),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 (reg_83_n_14),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_83_n_16),
        .s_daddr_o({s_daddr_o[7],s_daddr_o[5:0]}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di),
        .s_dwe_o(s_dwe_o),
        .slaveRegDo_80(slaveRegDo_80),
        .slaveRegDo_81(slaveRegDo_81),
        .slaveRegDo_82(slaveRegDo_82),
        .slaveRegDo_84({slaveRegDo_84[15:5],slaveRegDo_84[3]}),
        .\slaveRegDo_mux_0_reg[0] (reg_84_n_15),
        .\slaveRegDo_mux_0_reg[10] (reg_1a_n_1),
        .\slaveRegDo_mux_0_reg[10]_0 (reg_85_n_7),
        .\slaveRegDo_mux_0_reg[11] (reg_17_n_8),
        .\slaveRegDo_mux_0_reg[11]_0 (reg_85_n_6),
        .\slaveRegDo_mux_0_reg[12] (reg_17_n_7),
        .\slaveRegDo_mux_0_reg[12]_0 (reg_85_n_5),
        .\slaveRegDo_mux_0_reg[13] (reg_17_n_6),
        .\slaveRegDo_mux_0_reg[13]_0 (reg_85_n_4),
        .\slaveRegDo_mux_0_reg[14] (reg_17_n_5),
        .\slaveRegDo_mux_0_reg[14]_0 (reg_85_n_3),
        .\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0[15]_i_9_n_0 ),
        .\slaveRegDo_mux_0_reg[15]_0 (reg_85_n_2),
        .\slaveRegDo_mux_0_reg[1] (reg_84_n_14),
        .\slaveRegDo_mux_0_reg[2] (reg_84_n_13),
        .\slaveRegDo_mux_0_reg[3] (reg_17_n_4),
        .\slaveRegDo_mux_0_reg[3]_0 (reg_85_n_14),
        .\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
        .\slaveRegDo_mux_0_reg[4]_0 (reg_84_n_0),
        .\slaveRegDo_mux_0_reg[5] (reg_18_n_14),
        .\slaveRegDo_mux_0_reg[5]_0 (reg_85_n_12),
        .\slaveRegDo_mux_0_reg[6] (reg_1a_n_0),
        .\slaveRegDo_mux_0_reg[6]_0 (reg_85_n_11),
        .\slaveRegDo_mux_0_reg[7] (reg_18_n_12),
        .\slaveRegDo_mux_0_reg[7]_0 (reg_85_n_10),
        .\slaveRegDo_mux_0_reg[8] (reg_18_n_13),
        .\slaveRegDo_mux_0_reg[8]_0 (reg_85_n_9),
        .\slaveRegDo_mux_0_reg[9] (reg_15_n_0),
        .\slaveRegDo_mux_0_reg[9]_0 (reg_85_n_8),
        .\xsdb_reg_reg[0] (reg_85_n_0),
        .\xsdb_reg_reg[15] (reg_83_n_17));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized49 reg_84
       (.s_daddr_o(s_daddr_o[2:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\slaveRegDo_mux_0[0]_i_3 (reg_85_n_17),
        .\slaveRegDo_mux_0[1]_i_3 (reg_85_n_16),
        .\slaveRegDo_mux_0[2]_i_3 (reg_85_n_15),
        .\slaveRegDo_mux_0[4]_i_4 (reg_85_n_13),
        .\xsdb_reg_reg[0] (reg_84_n_15),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_3 ),
        .\xsdb_reg_reg[15] ({slaveRegDo_84[15:5],slaveRegDo_84[3]}),
        .\xsdb_reg_reg[1] (reg_84_n_14),
        .\xsdb_reg_reg[2] (reg_84_n_13),
        .\xsdb_reg_reg[4] (reg_84_n_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized50 reg_85
       (.\G_1PIPE_IFACE.s_daddr_r_reg[0] (reg_85_n_1),
        .\G_1PIPE_IFACE.s_daddr_r_reg[12] (reg_85_n_0),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di),
        .s_dwe_o(s_dwe_o),
        .\xsdb_reg_reg[0] (reg_85_n_17),
        .\xsdb_reg_reg[10] (reg_85_n_7),
        .\xsdb_reg_reg[11] (reg_85_n_6),
        .\xsdb_reg_reg[12] (reg_85_n_5),
        .\xsdb_reg_reg[13] (reg_85_n_4),
        .\xsdb_reg_reg[14] (reg_85_n_3),
        .\xsdb_reg_reg[15] (reg_85_n_2),
        .\xsdb_reg_reg[1] (reg_85_n_16),
        .\xsdb_reg_reg[2] (reg_85_n_15),
        .\xsdb_reg_reg[3] (reg_85_n_14),
        .\xsdb_reg_reg[4] (reg_85_n_13),
        .\xsdb_reg_reg[5] (reg_85_n_12),
        .\xsdb_reg_reg[6] (reg_85_n_11),
        .\xsdb_reg_reg[7] (reg_85_n_10),
        .\xsdb_reg_reg[8] (reg_85_n_9),
        .\xsdb_reg_reg[9] (reg_85_n_8));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized52 reg_887
       (.\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_887_n_0),
        .out(dummy_temp),
        .s_daddr_o(s_daddr_o[4:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_do_o(slaveRegDo_890[3]),
        .\slaveRegDo_mux_2_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .\slaveRegDo_mux_2_reg[3]_0 (reg_892_n_0),
        .\slaveRegDo_mux_2_reg[3]_1 (reg_88f_n_14));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized54 reg_88d
       (.D({reg_88d_n_0,reg_88d_n_1}),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_do_o(slaveRegDo_890[1:0]),
        .\slaveRegDo_mux_2_reg[0] (\slaveRegDo_mux_2[2]_i_2_n_0 ),
        .\slaveRegDo_mux_2_reg[0]_0 (\slaveRegDo_mux_2[4]_i_2_n_0 ),
        .\slaveRegDo_mux_2_reg[0]_1 (\slaveRegDo_mux_2[0]_i_2_n_0 ),
        .\slaveRegDo_mux_2_reg[0]_2 (\slaveRegDo_mux_2[4]_i_4_n_0 ),
        .\slaveRegDo_mux_2_reg[0]_3 (reg_892_n_3),
        .\slaveRegDo_mux_2_reg[0]_4 (reg_88f_n_16),
        .\slaveRegDo_mux_2_reg[1] (\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .\slaveRegDo_mux_2_reg[1]_0 (\slaveRegDo_mux_1[1]_i_1_n_0 ),
        .\slaveRegDo_mux_2_reg[1]_1 (\slaveRegDo_mux_2[1]_i_3_n_0 ),
        .\slaveRegDo_mux_2_reg[1]_2 (reg_892_n_2),
        .\slaveRegDo_mux_2_reg[1]_3 (reg_88f_n_15),
        .\xsdb_reg_reg[1] (\xsdb_reg_reg[1]_1 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized56 reg_88f
       (.D({reg_88f_n_11,reg_88f_n_12}),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_88f_n_9),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (reg_88f_n_13),
        .\G_1PIPE_IFACE.s_den_r_reg (reg_88f_n_10),
        .SEQUENCER_STATE_O(SEQUENCER_STATE_O),
        .s_daddr_o({s_daddr_o[4:3],s_daddr_o[1:0]}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_do_o({slaveRegDo_890[15:4],slaveRegDo_890[2]}),
        .\slaveRegDo_mux_2_reg[15] (\slaveRegDo_mux_2[2]_i_2_n_0 ),
        .\slaveRegDo_mux_2_reg[15]_0 (reg_83_n_15),
        .\slaveRegDo_mux_2_reg[2] (\slaveRegDo_mux_2[2]_i_4_n_0 ),
        .\slaveRegDo_mux_2_reg[2]_0 (reg_892_n_1),
        .\slaveRegDo_mux_2_reg[2]_1 (\slaveRegDo_mux_2[2]_i_5_n_0 ),
        .\slaveRegDo_mux_2_reg[4] (\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .\slaveRegDo_mux_2_reg[4]_0 (\slaveRegDo_mux_1[4]_i_1_n_0 ),
        .\slaveRegDo_mux_2_reg[4]_1 (\slaveRegDo_mux_2[4]_i_2_n_0 ),
        .\slaveRegDo_mux_2_reg[4]_2 (\slaveRegDo_mux_2[4]_i_4_n_0 ),
        .\slaveRegDo_mux_2_reg[5] (\slaveRegDo_mux_2_reg[5]_0 ),
        .\xsdb_reg_reg[0] (reg_88f_n_16),
        .\xsdb_reg_reg[10] (reg_88f_n_5),
        .\xsdb_reg_reg[11] (reg_88f_n_6),
        .\xsdb_reg_reg[12] (reg_88f_n_7),
        .\xsdb_reg_reg[13] (reg_88f_n_8),
        .\xsdb_reg_reg[15] (\xsdb_reg_reg[15]_1 ),
        .\xsdb_reg_reg[1] (reg_88f_n_15),
        .\xsdb_reg_reg[3] (reg_88f_n_14),
        .\xsdb_reg_reg[5] (reg_88f_n_0),
        .\xsdb_reg_reg[6] (reg_88f_n_1),
        .\xsdb_reg_reg[7] (reg_88f_n_2),
        .\xsdb_reg_reg[8] (reg_88f_n_3),
        .\xsdb_reg_reg[9] (reg_88f_n_4));
  (* C_ADDR_W = "13" *) 
  (* C_CTLRST_VAL = "47'b00000000000000000000000000000000000000000000000" *) 
  (* C_DATA_W = "16" *) 
  (* C_EN_CTL = "0" *) 
  (* C_EN_STAT = "1" *) 
  (* C_REG_ADDR = "13'b0100010010000" *) 
  (* DONT_TOUCH *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized57 reg_890
       (.din_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .dout_o(NLW_reg_890_dout_o_UNCONNECTED[15:0]),
        .rst_reg_i(1'b0),
        .s_daddr_i(s_daddr_o),
        .s_dclk_i(U_XSDB_SLAVE_n_1),
        .s_den_i(s_den_o),
        .s_di_i(s_di),
        .s_do_o(slaveRegDo_890),
        .s_dwe_i(s_dwe_o));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized55 reg_892
       (.flag0_temp(flag0_temp),
        .flag1_temp(flag1_temp),
        .flag2_temp(flag2_temp),
        .flag3_temp(flag3_temp),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .\xsdb_reg_reg[0] (reg_892_n_3),
        .\xsdb_reg_reg[1] (reg_892_n_2),
        .\xsdb_reg_reg[2] (reg_892_n_1),
        .\xsdb_reg_reg[3] (reg_892_n_0),
        .\xsdb_reg_reg[3]_0 (reg_88f_n_10));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized27 reg_9
       (.Q({reg_9_n_0,reg_9_n_1,reg_9_n_2,reg_9_n_3,reg_9_n_4,reg_9_n_5,reg_9_n_6,reg_9_n_7,reg_9_n_8,reg_9_n_9}),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .\xsdb_reg_reg[9] (\xsdb_reg_reg[9]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized48 reg_srl_fff
       (.D(D),
        .E(shift_en_reg_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (reg_srl_fff_n_1),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (reg_srl_fff_n_2),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (reg_srl_fff_n_3),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (reg_srl_fff_n_4),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (reg_srl_fff_n_5),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 (reg_srl_fff_n_6),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_srl_fff_n_0),
        .Q({\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 }),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .\parallel_dout_reg[11]_0 (reg_srl_fff_n_11),
        .\parallel_dout_reg[12]_0 (reg_srl_fff_n_10),
        .\parallel_dout_reg[13]_0 (reg_srl_fff_n_9),
        .\parallel_dout_reg[14]_0 (reg_srl_fff_n_8),
        .\parallel_dout_reg[15]_0 (\parallel_dout_reg[15]_0 ),
        .\parallel_dout_reg[5]_0 (reg_srl_fff_n_15),
        .\parallel_dout_reg[6]_0 (reg_srl_fff_n_14),
        .\parallel_dout_reg[8]_0 (reg_srl_fff_n_13),
        .\parallel_dout_reg[9]_0 (reg_srl_fff_n_12),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_den_o(s_den_o),
        .s_di_o(s_di[14:0]),
        .s_dwe_o(s_dwe_o),
        .\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
        .\slaveRegDo_mux_3_reg[0] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ),
        .\slaveRegDo_mux_3_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\slaveRegDo_mux_3_reg[10] (reg_stream_ffe_n_5),
        .\slaveRegDo_mux_3_reg[11] (reg_stream_ffe_n_4),
        .\slaveRegDo_mux_3_reg[12] (reg_stream_ffe_n_3),
        .\slaveRegDo_mux_3_reg[13] (reg_stream_ffe_n_2),
        .\slaveRegDo_mux_3_reg[14] (reg_stream_ffe_n_1),
        .\slaveRegDo_mux_3_reg[15] (\slaveRegDo_mux_3[15]_i_4_n_0 ),
        .\slaveRegDo_mux_3_reg[15]_0 (reg_stream_ffe_n_0),
        .\slaveRegDo_mux_3_reg[15]_1 (debug_data_in),
        .\slaveRegDo_mux_3_reg[1] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ),
        .\slaveRegDo_mux_3_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\slaveRegDo_mux_3_reg[2] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ),
        .\slaveRegDo_mux_3_reg[2]_0 (reg_stream_ffe_n_13),
        .\slaveRegDo_mux_3_reg[3] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ),
        .\slaveRegDo_mux_3_reg[3]_0 (reg_stream_ffe_n_12),
        .\slaveRegDo_mux_3_reg[4] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ),
        .\slaveRegDo_mux_3_reg[4]_0 (reg_stream_ffe_n_11),
        .\slaveRegDo_mux_3_reg[5] (reg_stream_ffe_n_10),
        .\slaveRegDo_mux_3_reg[6] (reg_stream_ffe_n_9),
        .\slaveRegDo_mux_3_reg[7] (\slaveRegDo_mux_3[10]_i_3_n_0 ),
        .\slaveRegDo_mux_3_reg[7]_0 (reg_83_n_15),
        .\slaveRegDo_mux_3_reg[7]_1 (reg_stream_ffe_n_8),
        .\slaveRegDo_mux_3_reg[8] (reg_stream_ffe_n_7),
        .\slaveRegDo_mux_3_reg[9] (reg_stream_ffe_n_6),
        .\xsdb_reg_reg[15] (reg_srl_fff_n_7));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized1 reg_stream_ffd
       (.\G_1PIPE_IFACE.s_daddr_r_reg[10] (reg_stream_ffd_n_0),
        .\G_1PIPE_IFACE.s_daddr_r_reg[6] (reg_stream_ffd_n_1),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .s_di_o(s_di),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0]_5 ),
        .\xsdb_reg_reg[15] (debug_data_in));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized2 reg_stream_ffe
       (.data_out_en(data_out_en),
        .s_dclk_o(U_XSDB_SLAVE_n_1),
        .\xsdb_reg_reg[0] (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[10] (reg_stream_ffe_n_5),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[11] (reg_stream_ffe_n_4),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12] (reg_stream_ffe_n_3),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13] (reg_stream_ffe_n_2),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14] (reg_stream_ffe_n_1),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15] (reg_stream_ffe_n_0),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[15]_1 (\xsdb_reg_reg[15]_0 ),
        .\xsdb_reg_reg[1] (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1]_0 ),
        .\xsdb_reg_reg[2] (reg_stream_ffe_n_13),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[3] (reg_stream_ffe_n_12),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[4] (reg_stream_ffe_n_11),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5] (reg_stream_ffe_n_10),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6] (reg_stream_ffe_n_9),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7] (reg_stream_ffe_n_8),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8] (reg_stream_ffe_n_7),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9] (reg_stream_ffe_n_6),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
  LUT3 #(
    .INIT(8'hB2)) 
    s_dclk_flag_i_1
       (.I0(s_dclk_flag),
        .I1(next_state_xsdb),
        .I2(ila_clk_flag_sync2),
        .O(s_dclk_flag_i_1_n_0));
  FDRE s_dclk_flag_reg
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(s_dclk_flag_i_1_n_0),
        .Q(s_dclk_flag),
        .R(s_rst_o));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE s_dclk_flag_sync1_reg
       (.C(ila_clk_flag_reg_1),
        .CE(1'b1),
        .D(s_dclk_flag),
        .Q(s_dclk_flag_sync1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE s_dclk_flag_sync2_reg
       (.C(ila_clk_flag_reg_1),
        .CE(1'b1),
        .D(s_dclk_flag_sync1),
        .Q(s_dclk_flag_sync2),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h01)) 
    \shift_reg0[2]_i_2 
       (.I0(count0_reg__0[5]),
        .I1(count0_reg__0[4]),
        .I2(count0_reg__0[6]),
        .O(\count0_reg[5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \shift_reg0[2]_i_3 
       (.I0(count0_reg__0[1]),
        .I1(count0_reg__0[0]),
        .I2(count0_reg__0[3]),
        .I3(count0_reg__0[2]),
        .O(\count0_reg[1]_0 ));
  FDRE \shift_reg0_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\shift_reg0_reg[2]_1 ),
        .Q(\shift_reg0_reg[2]_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h01)) 
    \shift_reg1[11]_i_2 
       (.I0(count1_reg__0[2]),
        .I1(count1_reg__0[5]),
        .I2(count1_reg__0[3]),
        .O(\count1_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \shift_reg1[11]_i_3 
       (.I0(count1_reg__0[1]),
        .I1(count1_reg__0[0]),
        .I2(count1_reg__0[4]),
        .I3(count1_reg__0[6]),
        .O(\count1_reg[1]_0 ));
  FDRE \shift_reg1_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\shift_reg1_reg[11]_1 ),
        .Q(\shift_reg1_reg[11]_0 ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h74)) 
    \slaveRegDo_ff8[15]_i_1 
       (.I0(count_tt),
        .I1(xsdb_rden_ff8),
        .I2(\slaveRegDo_ff8_reg_n_0_[15] ),
        .O(\slaveRegDo_ff8[15]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \slaveRegDo_ff8[4]_i_1 
       (.I0(count_tt),
        .I1(xsdb_rden_ff8),
        .I2(\slaveRegDo_ff8_reg_n_0_[4] ),
        .O(\slaveRegDo_ff8[4]_i_1_n_0 ));
  FDSE \slaveRegDo_ff8_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\slaveRegDo_ff8[15]_i_1_n_0 ),
        .Q(\slaveRegDo_ff8_reg_n_0_[15] ),
        .S(s_rst_o));
  FDRE \slaveRegDo_ff8_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\slaveRegDo_ff8[4]_i_1_n_0 ),
        .Q(\slaveRegDo_ff8_reg_n_0_[4] ),
        .R(s_rst_o));
  FDRE \slaveRegDo_ff9_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\shift_reg0_reg[2]_0 ),
        .Q(slaveRegDo_ff9),
        .R(s_rst_o));
  FDRE \slaveRegDo_ffa_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\shift_reg1_reg[11]_0 ),
        .Q(slaveRegDo_ffa),
        .R(s_rst_o));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux[0]_i_2 
       (.I0(slaveRegDo_mux_3[0]),
        .I1(slaveRegDo_mux_2[0]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_1[0]),
        .I4(s_daddr_o[10]),
        .I5(slaveRegDo_mux_0[0]),
        .O(\slaveRegDo_mux[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[0]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[0] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[0]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[0]),
        .O(\slaveRegDo_mux[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[10]_i_2 
       (.I0(slaveRegDo_mux_3[10]),
        .I1(slaveRegDo_mux_2[10]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[10]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[10]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[10]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[10] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[10]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[10]),
        .O(\slaveRegDo_mux[10]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[11]_i_2 
       (.I0(slaveRegDo_mux_3[11]),
        .I1(slaveRegDo_mux_2[11]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[11]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[11]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[11] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[11]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[11]),
        .O(\slaveRegDo_mux[11]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[12]_i_2 
       (.I0(slaveRegDo_mux_3[12]),
        .I1(slaveRegDo_mux_2[12]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[12]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[12]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[12] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[12]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[12]),
        .O(\slaveRegDo_mux[12]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[13]_i_2 
       (.I0(slaveRegDo_mux_3[13]),
        .I1(slaveRegDo_mux_2[13]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[13]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[13]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[13] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[13]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[13]),
        .O(\slaveRegDo_mux[13]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[14]_i_2 
       (.I0(slaveRegDo_mux_3[14]),
        .I1(slaveRegDo_mux_2[14]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[14]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[14]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[14] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[14]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[14]),
        .O(\slaveRegDo_mux[14]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[15]_i_2 
       (.I0(slaveRegDo_mux_3[15]),
        .I1(slaveRegDo_mux_2[15]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[15]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[15]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[15] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[15]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[15]),
        .O(\slaveRegDo_mux[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux[1]_i_2 
       (.I0(slaveRegDo_mux_3[1]),
        .I1(slaveRegDo_mux_2[1]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_1[1]),
        .I4(s_daddr_o[10]),
        .I5(slaveRegDo_mux_0[1]),
        .O(\slaveRegDo_mux[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[1]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[1] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[1]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[1]),
        .O(\slaveRegDo_mux[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux[2]_i_2 
       (.I0(slaveRegDo_mux_3[2]),
        .I1(slaveRegDo_mux_2[2]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_1[4]),
        .I4(s_daddr_o[10]),
        .I5(slaveRegDo_mux_0[2]),
        .O(\slaveRegDo_mux[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[2]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[2] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[2]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[2]),
        .O(\slaveRegDo_mux[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[3]_i_2 
       (.I0(slaveRegDo_mux_3[3]),
        .I1(slaveRegDo_mux_2[3]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[3]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[3]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[3] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[3]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[3]),
        .O(\slaveRegDo_mux[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux[4]_i_2 
       (.I0(slaveRegDo_mux_3[4]),
        .I1(slaveRegDo_mux_2[4]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_1[4]),
        .I4(s_daddr_o[10]),
        .I5(slaveRegDo_mux_0[4]),
        .O(\slaveRegDo_mux[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[4]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[4] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[4]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[4]),
        .O(\slaveRegDo_mux[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[5]_i_2 
       (.I0(slaveRegDo_mux_3[5]),
        .I1(slaveRegDo_mux_2[5]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[5]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[5]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[5] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[5]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[5]),
        .O(\slaveRegDo_mux[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[6]_i_2 
       (.I0(slaveRegDo_mux_3[6]),
        .I1(slaveRegDo_mux_2[6]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[6]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[6]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[6] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[6]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[6]),
        .O(\slaveRegDo_mux[6]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[7]_i_2 
       (.I0(slaveRegDo_mux_3[7]),
        .I1(slaveRegDo_mux_2[7]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[7]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[7]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[7] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[7]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[7]),
        .O(\slaveRegDo_mux[7]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[8]_i_2 
       (.I0(slaveRegDo_mux_3[8]),
        .I1(slaveRegDo_mux_2[8]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[8]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[8]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[8] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[8]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[8]),
        .O(\slaveRegDo_mux[8]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \slaveRegDo_mux[9]_i_2 
       (.I0(slaveRegDo_mux_3[9]),
        .I1(slaveRegDo_mux_2[9]),
        .I2(s_daddr_o[11]),
        .I3(slaveRegDo_mux_0[9]),
        .I4(s_daddr_o[10]),
        .O(\slaveRegDo_mux[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux[9]_i_3 
       (.I0(\slaveRegDo_mux_6_reg_n_0_[9] ),
        .I1(s_daddr_o[11]),
        .I2(slaveRegDo_mux_5[9]),
        .I3(s_daddr_o[10]),
        .I4(slaveRegDo_mux_4[9]),
        .O(\slaveRegDo_mux[9]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \slaveRegDo_mux_0[15]_i_1 
       (.I0(s_daddr_o[6]),
        .I1(\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .O(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    \slaveRegDo_mux_0[15]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[4]),
        .O(\slaveRegDo_mux_0[15]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \slaveRegDo_mux_0[4]_i_10 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .O(\slaveRegDo_mux_0[4]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \slaveRegDo_mux_0[4]_i_3 
       (.I0(s_daddr_o[7]),
        .I1(s_daddr_o[5]),
        .O(\slaveRegDo_mux_0[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000100011111111)) 
    \slaveRegDo_mux_0[4]_i_5 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[8]),
        .I2(regDrdy_i_2_n_0),
        .I3(reg_83_n_16),
        .I4(reg_18_n_15),
        .I5(s_daddr_o[7]),
        .O(\slaveRegDo_mux_0[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT3 #(
    .INIT(8'hDC)) 
    \slaveRegDo_mux_0[4]_i_8 
       (.I0(s_daddr_o[7]),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[4]),
        .O(\slaveRegDo_mux_0[4]_i_8_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_17_n_2),
        .Q(slaveRegDo_mux_0[0]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_0_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_10),
        .Q(slaveRegDo_mux_0[10]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_11),
        .Q(slaveRegDo_mux_0[11]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_12),
        .Q(slaveRegDo_mux_0[12]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_13),
        .Q(slaveRegDo_mux_0[13]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_14),
        .Q(slaveRegDo_mux_0[14]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_17_n_3),
        .Q(slaveRegDo_mux_0[15]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_17_n_1),
        .Q(slaveRegDo_mux_0[1]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_0_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_17_n_0),
        .Q(slaveRegDo_mux_0[2]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_0_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_6),
        .Q(slaveRegDo_mux_0[3]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_18_n_11),
        .Q(slaveRegDo_mux_0[4]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_0_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_8),
        .Q(slaveRegDo_mux_0[5]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_9),
        .Q(slaveRegDo_mux_0[6]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_0),
        .Q(slaveRegDo_mux_0[7]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_1),
        .Q(slaveRegDo_mux_0[8]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_0_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_83_n_2),
        .Q(slaveRegDo_mux_0[9]),
        .R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT5 #(
    .INIT(32'h80005F5F)) 
    \slaveRegDo_mux_1[0]_i_1 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .O(\slaveRegDo_mux_1[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT4 #(
    .INIT(16'h0488)) 
    \slaveRegDo_mux_1[1]_i_1 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[0]),
        .O(\slaveRegDo_mux_1[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT5 #(
    .INIT(32'h80000AFF)) 
    \slaveRegDo_mux_1[4]_i_1 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .O(\slaveRegDo_mux_1[4]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_1_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\slaveRegDo_mux_1[0]_i_1_n_0 ),
        .Q(slaveRegDo_mux_1[0]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_1_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\slaveRegDo_mux_1[1]_i_1_n_0 ),
        .Q(slaveRegDo_mux_1[1]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_1_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\slaveRegDo_mux_1[4]_i_1_n_0 ),
        .Q(slaveRegDo_mux_1[4]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8505555500000000)) 
    \slaveRegDo_mux_2[0]_i_2 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .O(\slaveRegDo_mux_2[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \slaveRegDo_mux_2[15]_i_1 
       (.I0(\slaveRegDo_mux_2[2]_i_4_n_0 ),
        .O(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \slaveRegDo_mux_2[1]_i_3 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .O(\slaveRegDo_mux_2[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \slaveRegDo_mux_2[2]_i_2 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[3]),
        .O(\slaveRegDo_mux_2[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \slaveRegDo_mux_2[2]_i_4 
       (.I0(\slaveRegDo_mux_0[4]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_2[4]_i_2_n_0 ),
        .I2(\slaveRegDo_mux_2[4]_i_4_n_0 ),
        .O(\slaveRegDo_mux_2[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \slaveRegDo_mux_2[2]_i_5 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[2]),
        .O(\slaveRegDo_mux_2[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \slaveRegDo_mux_2[3]_i_2 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT5 #(
    .INIT(32'hFFFFFFEF)) 
    \slaveRegDo_mux_2[4]_i_2 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[6]),
        .O(\slaveRegDo_mux_2[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000002000000000)) 
    \slaveRegDo_mux_2[4]_i_4 
       (.I0(\slaveRegDo_mux_2[4]_i_5_n_0 ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(reg_18_n_15),
        .I5(s_daddr_o[7]),
        .O(\slaveRegDo_mux_2[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \slaveRegDo_mux_2[4]_i_5 
       (.I0(s_daddr_o[8]),
        .I1(s_daddr_o[9]),
        .O(\slaveRegDo_mux_2[4]_i_5_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88d_n_1),
        .Q(slaveRegDo_mux_2[0]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_2_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_5),
        .Q(slaveRegDo_mux_2[10]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_6),
        .Q(slaveRegDo_mux_2[11]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_7),
        .Q(slaveRegDo_mux_2[12]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_8),
        .Q(slaveRegDo_mux_2[13]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_9),
        .Q(slaveRegDo_mux_2[14]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_13),
        .Q(slaveRegDo_mux_2[15]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88d_n_0),
        .Q(slaveRegDo_mux_2[1]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_2_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_12),
        .Q(slaveRegDo_mux_2[2]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_2_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_887_n_0),
        .Q(slaveRegDo_mux_2[3]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_11),
        .Q(slaveRegDo_mux_2[4]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_2_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_0),
        .Q(slaveRegDo_mux_2[5]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_1),
        .Q(slaveRegDo_mux_2[6]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_2),
        .Q(slaveRegDo_mux_2[7]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_3),
        .Q(slaveRegDo_mux_2[8]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_2_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_88f_n_4),
        .Q(slaveRegDo_mux_2[9]),
        .R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT4 #(
    .INIT(16'h3202)) 
    \slaveRegDo_mux_3[10]_i_3 
       (.I0(\slaveRegDo_ff8_reg_n_0_[15] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_ffa),
        .O(\slaveRegDo_mux_3[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \slaveRegDo_mux_3[11]_i_2 
       (.I0(slaveRegDo_ffa),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .O(\slaveRegDo_mux_3[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \slaveRegDo_mux_3[15]_i_1 
       (.I0(s_daddr_o[5]),
        .I1(s_daddr_o[9]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[6]),
        .I5(s_daddr_o[8]),
        .O(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \slaveRegDo_mux_3[15]_i_4 
       (.I0(\slaveRegDo_ff8_reg_n_0_[15] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .O(\slaveRegDo_mux_3[15]_i_4_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_0),
        .Q(slaveRegDo_mux_3[0]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_6),
        .Q(slaveRegDo_mux_3[10]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ),
        .Q(slaveRegDo_mux_3[11]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ),
        .Q(slaveRegDo_mux_3[12]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ),
        .Q(slaveRegDo_mux_3[13]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ),
        .Q(slaveRegDo_mux_3[14]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_7),
        .Q(slaveRegDo_mux_3[15]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_1),
        .Q(slaveRegDo_mux_3[1]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_2),
        .Q(slaveRegDo_mux_3[2]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_3),
        .Q(slaveRegDo_mux_3[3]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_4),
        .Q(slaveRegDo_mux_3[4]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ),
        .Q(slaveRegDo_mux_3[5]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ),
        .Q(slaveRegDo_mux_3[6]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(reg_srl_fff_n_5),
        .Q(slaveRegDo_mux_3[7]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ),
        .Q(slaveRegDo_mux_3[8]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_3_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ),
        .Q(slaveRegDo_mux_3[9]),
        .R(\slaveRegDo_mux_3[15]_i_1_n_0 ));
  FDRE \slaveRegDo_mux_4_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_15 ),
        .Q(slaveRegDo_mux_4[0]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_5 ),
        .Q(slaveRegDo_mux_4[10]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_4 ),
        .Q(slaveRegDo_mux_4[11]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_3 ),
        .Q(slaveRegDo_mux_4[12]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_2 ),
        .Q(slaveRegDo_mux_4[13]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_1 ),
        .Q(slaveRegDo_mux_4[14]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_0 ),
        .Q(slaveRegDo_mux_4[15]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_14 ),
        .Q(slaveRegDo_mux_4[1]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_13 ),
        .Q(slaveRegDo_mux_4[2]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_12 ),
        .Q(slaveRegDo_mux_4[3]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_11 ),
        .Q(slaveRegDo_mux_4[4]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_10 ),
        .Q(slaveRegDo_mux_4[5]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_9 ),
        .Q(slaveRegDo_mux_4[6]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_8 ),
        .Q(slaveRegDo_mux_4[7]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_7 ),
        .Q(slaveRegDo_mux_4[8]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_4_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\MU_SRL[11].mu_srl_reg_n_6 ),
        .Q(slaveRegDo_mux_4[9]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_15 ),
        .Q(slaveRegDo_mux_5[0]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_5 ),
        .Q(slaveRegDo_mux_5[10]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_4 ),
        .Q(slaveRegDo_mux_5[11]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_3 ),
        .Q(slaveRegDo_mux_5[12]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_2 ),
        .Q(slaveRegDo_mux_5[13]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_1 ),
        .Q(slaveRegDo_mux_5[14]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_0 ),
        .Q(slaveRegDo_mux_5[15]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_14 ),
        .Q(slaveRegDo_mux_5[1]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_13 ),
        .Q(slaveRegDo_mux_5[2]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_12 ),
        .Q(slaveRegDo_mux_5[3]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_11 ),
        .Q(slaveRegDo_mux_5[4]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_10 ),
        .Q(slaveRegDo_mux_5[5]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_9 ),
        .Q(slaveRegDo_mux_5[6]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_8 ),
        .Q(slaveRegDo_mux_5[7]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_7 ),
        .Q(slaveRegDo_mux_5[8]),
        .R(1'b0));
  FDRE \slaveRegDo_mux_5_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\TC_SRL[27].tc_srl_reg_n_6 ),
        .Q(slaveRegDo_mux_5[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \slaveRegDo_mux_6[15]_i_3 
       (.I0(\slaveRegDo_mux_6[15]_i_5_n_0 ),
        .I1(s_daddr_o[7]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[6]),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\slaveRegDo_mux_6[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \slaveRegDo_mux_6[15]_i_4 
       (.I0(reg_16_n_2),
        .I1(\slaveRegDo_mux_6_reg[0]_0 ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[9]),
        .I4(s_daddr_o[1]),
        .I5(s_daddr_o[0]),
        .O(\slaveRegDo_mux_6[15]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \slaveRegDo_mux_6[15]_i_5 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[8]),
        .I2(s_daddr_o[4]),
        .O(\slaveRegDo_mux_6[15]_i_5_n_0 ));
  FDRE \slaveRegDo_mux_6_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_15 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_5 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_4 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_3 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_2 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_1 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_0 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_14 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_13 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_12 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_11 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_10 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_9 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_8 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_7 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_6_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(\CNT.CNT_SRL[2].cnt_srl_reg_n_6 ),
        .Q(\slaveRegDo_mux_6_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \slaveRegDo_mux_reg[0] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[0]),
        .Q(\slaveRegDo_mux_reg_n_0_[0] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[0]_i_1 
       (.I0(\slaveRegDo_mux[0]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[0]_i_3_n_0 ),
        .O(slaveRegDo_mux[0]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[10] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[10]),
        .Q(\slaveRegDo_mux_reg_n_0_[10] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[10]_i_1 
       (.I0(\slaveRegDo_mux[10]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[10]_i_3_n_0 ),
        .O(slaveRegDo_mux[10]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[11] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[11]),
        .Q(\slaveRegDo_mux_reg_n_0_[11] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[11]_i_1 
       (.I0(\slaveRegDo_mux[11]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[11]_i_3_n_0 ),
        .O(slaveRegDo_mux[11]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[12] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[12]),
        .Q(\slaveRegDo_mux_reg_n_0_[12] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[12]_i_1 
       (.I0(\slaveRegDo_mux[12]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[12]_i_3_n_0 ),
        .O(slaveRegDo_mux[12]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[13] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[13]),
        .Q(\slaveRegDo_mux_reg_n_0_[13] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[13]_i_1 
       (.I0(\slaveRegDo_mux[13]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[13]_i_3_n_0 ),
        .O(slaveRegDo_mux[13]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[14] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[14]),
        .Q(\slaveRegDo_mux_reg_n_0_[14] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[14]_i_1 
       (.I0(\slaveRegDo_mux[14]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[14]_i_3_n_0 ),
        .O(slaveRegDo_mux[14]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[15] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[15]),
        .Q(\slaveRegDo_mux_reg_n_0_[15] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[15]_i_1 
       (.I0(\slaveRegDo_mux[15]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[15]_i_3_n_0 ),
        .O(slaveRegDo_mux[15]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[1] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[1]),
        .Q(\slaveRegDo_mux_reg_n_0_[1] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[1]_i_1 
       (.I0(\slaveRegDo_mux[1]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[1]_i_3_n_0 ),
        .O(slaveRegDo_mux[1]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[2] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[2]),
        .Q(\slaveRegDo_mux_reg_n_0_[2] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[2]_i_1 
       (.I0(\slaveRegDo_mux[2]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[2]_i_3_n_0 ),
        .O(slaveRegDo_mux[2]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[3] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[3]),
        .Q(\slaveRegDo_mux_reg_n_0_[3] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[3]_i_1 
       (.I0(\slaveRegDo_mux[3]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[3]_i_3_n_0 ),
        .O(slaveRegDo_mux[3]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[4] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[4]),
        .Q(\slaveRegDo_mux_reg_n_0_[4] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[4]_i_1 
       (.I0(\slaveRegDo_mux[4]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[4]_i_3_n_0 ),
        .O(slaveRegDo_mux[4]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[5] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[5]),
        .Q(\slaveRegDo_mux_reg_n_0_[5] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[5]_i_1 
       (.I0(\slaveRegDo_mux[5]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[5]_i_3_n_0 ),
        .O(slaveRegDo_mux[5]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[6] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[6]),
        .Q(\slaveRegDo_mux_reg_n_0_[6] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[6]_i_1 
       (.I0(\slaveRegDo_mux[6]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[6]_i_3_n_0 ),
        .O(slaveRegDo_mux[6]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[7] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[7]),
        .Q(\slaveRegDo_mux_reg_n_0_[7] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[7]_i_1 
       (.I0(\slaveRegDo_mux[7]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[7]_i_3_n_0 ),
        .O(slaveRegDo_mux[7]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[8] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[8]),
        .Q(\slaveRegDo_mux_reg_n_0_[8] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[8]_i_1 
       (.I0(\slaveRegDo_mux[8]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[8]_i_3_n_0 ),
        .O(slaveRegDo_mux[8]),
        .S(s_daddr_o[12]));
  FDRE \slaveRegDo_mux_reg[9] 
       (.C(U_XSDB_SLAVE_n_1),
        .CE(1'b1),
        .D(slaveRegDo_mux[9]),
        .Q(\slaveRegDo_mux_reg_n_0_[9] ),
        .R(1'b0));
  MUXF7 \slaveRegDo_mux_reg[9]_i_1 
       (.I0(\slaveRegDo_mux[9]_i_2_n_0 ),
        .I1(\slaveRegDo_mux[9]_i_3_n_0 ),
        .O(slaveRegDo_mux[9]),
        .S(s_daddr_o[12]));
  LUT2 #(
    .INIT(4'h6)) 
    toggle_rd_i_1
       (.I0(bram_rd_en),
        .I1(toggle_rd),
        .O(toggle_rd_reg));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_reset_ctrl
   (dout_reg1_reg,
    Q,
    dout_reg1_reg_0,
    \reset_out_reg[0]_0 ,
    last_din_reg,
    out,
    cap_done,
    halt_ctrl,
    arm_ctrl,
    \SEQUENCER_STATE_O_reg[8] ,
    current_state);
  output [1:0]dout_reg1_reg;
  output [3:0]Q;
  output dout_reg1_reg_0;
  output [0:0]\reset_out_reg[0]_0 ;
  input last_din_reg;
  input [0:0]out;
  input cap_done;
  input halt_ctrl;
  input arm_ctrl;
  input \SEQUENCER_STATE_O_reg[8] ;
  input [0:0]current_state;

  wire [3:0]Q;
  wire \SEQUENCER_STATE_O_reg[8] ;
  wire arm_ctrl;
  wire arm_in_detection;
  wire arm_in_transferred;
  wire \asyncrounous_transfer.arm_in_transfer_inst_n_1 ;
  wire \asyncrounous_transfer.halt_in_transfer_inst_n_1 ;
  wire cap_done;
  wire [0:0]current_state;
  wire [1:0]dout_reg1_reg;
  wire dout_reg1_reg_0;
  wire halt_ctrl;
  wire halt_detection_inst_n_1;
  wire halt_detection_inst_n_2;
  wire halt_in_transferred;
  wire halt_out;
  wire last_din;
  wire last_din_0;
  wire last_din_reg;
  wire [0:0]out;
  wire [0:0]p_0_out;
  wire prev_cap_done;
  wire [4:2]reset;
  wire [0:0]\reset_out_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection arm_detection_inst
       (.D(p_0_out),
        .Q(Q[1]),
        .\dout_pulse_reg[0]_0 (\asyncrounous_transfer.arm_in_transfer_inst_n_1 ),
        .\dout_pulse_reg[1]_0 (arm_in_detection),
        .last_din(last_din),
        .last_din_reg_0(last_din_reg),
        .out(arm_in_transferred));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer \asyncrounous_transfer.arm_in_transfer_inst 
       (.arm_ctrl(arm_ctrl),
        .din_reg_reg_0(out),
        .dout_reg0_reg_0(last_din_reg),
        .dout_reg1_reg_0(\asyncrounous_transfer.arm_in_transfer_inst_n_1 ),
        .last_din(last_din),
        .out(arm_in_transferred));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_227 \asyncrounous_transfer.arm_out_transfer_inst 
       (.Q(Q[0]),
        .\SEQUENCER_STATE_O_reg[8] (\SEQUENCER_STATE_O_reg[8] ),
        .current_state(current_state),
        .dout_reg1_reg_0(dout_reg1_reg[0]),
        .dout_reg1_reg_1(dout_reg1_reg_0),
        .out(out),
        .temp_reg1_reg_0(last_din_reg));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_228 \asyncrounous_transfer.halt_in_transfer_inst 
       (.D(\asyncrounous_transfer.halt_in_transfer_inst_n_1 ),
        .din_reg_reg_0(out),
        .dout_reg0_reg_0(last_din_reg),
        .halt_ctrl(halt_ctrl),
        .last_din(last_din_0),
        .out(halt_in_transferred));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_229 \asyncrounous_transfer.halt_out_transfer_inst 
       (.dout_reg1_reg_0(dout_reg1_reg[1]),
        .halt_out(halt_out),
        .out(out),
        .temp_reg0_reg_0(last_din_reg));
  LUT1 #(
    .INIT(2'h1)) 
    \captured_samples[9]_i_1 
       (.I0(Q[0]),
        .O(\reset_out_reg[0]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection_230 halt_detection_inst
       (.D(\asyncrounous_transfer.halt_in_transfer_inst_n_1 ),
        .Q(Q[0]),
        .SS(halt_detection_inst_n_2),
        .cap_done(cap_done),
        .halt_out(halt_out),
        .halt_out_reg(halt_detection_inst_n_1),
        .halt_out_reg_0(arm_in_detection),
        .last_din(last_din_0),
        .last_din_reg_0(last_din_reg),
        .out(halt_in_transferred),
        .prev_cap_done(prev_cap_done));
  FDRE #(
    .INIT(1'b0)) 
    halt_out_reg
       (.C(last_din_reg),
        .CE(1'b1),
        .D(halt_detection_inst_n_1),
        .Q(halt_out),
        .R(1'b0));
  FDRE prev_cap_done_reg
       (.C(last_din_reg),
        .CE(1'b1),
        .D(cap_done),
        .Q(prev_cap_done),
        .R(1'b0));
  FDSE #(
    .INIT(1'b1)) 
    \reset_out_reg[0] 
       (.C(last_din_reg),
        .CE(1'b1),
        .D(p_0_out),
        .Q(Q[0]),
        .S(halt_detection_inst_n_2));
  FDSE #(
    .INIT(1'b1)) 
    \reset_out_reg[1] 
       (.C(last_din_reg),
        .CE(1'b1),
        .D(Q[0]),
        .Q(Q[1]),
        .S(halt_detection_inst_n_2));
  FDSE #(
    .INIT(1'b1)) 
    \reset_out_reg[2] 
       (.C(last_din_reg),
        .CE(1'b1),
        .D(Q[1]),
        .Q(reset[2]),
        .S(halt_detection_inst_n_2));
  FDSE #(
    .INIT(1'b1)) 
    \reset_out_reg[3] 
       (.C(last_din_reg),
        .CE(1'b1),
        .D(reset[2]),
        .Q(Q[2]),
        .S(halt_detection_inst_n_2));
  FDSE #(
    .INIT(1'b1)) 
    \reset_out_reg[4] 
       (.C(last_din_reg),
        .CE(1'b1),
        .D(Q[2]),
        .Q(reset[4]),
        .S(halt_detection_inst_n_2));
  FDSE #(
    .INIT(1'b1)) 
    \reset_out_reg[5] 
       (.C(last_din_reg),
        .CE(1'b1),
        .D(reset[4]),
        .Q(Q[3]),
        .S(halt_detection_inst_n_2));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_trace_memory
   (D,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
    out,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ,
    Q,
    DIADI,
    DIPADIP,
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 );
  output [65:0]D;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  input [0:0]out;
  input \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  input [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  input [9:0]Q;
  input [31:0]DIADI;
  input [3:0]DIPADIP;
  input [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;

  wire [65:0]D;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
  wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ;
  wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ;
  wire [29:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ;
  wire [31:0]DIADI;
  wire [3:0]DIPADIP;
  wire [9:0]Q;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 \SUBCORE_RAM_BLK_MEM_1.trace_block_memory 
       (.D(D),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2 ),
        .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3 ),
        .DIADI(DIADI),
        .DIPADIP(DIPADIP),
        .Q(Q),
        .out(out));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_trig_match
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \probeDelay1_reg[15] ,
    \probeDelay1_reg[0] ,
    probe0,
    probe1,
    probe2);
  output [11:0]mu_config_cs_serial_input;
  output [11:0]D;
  input [11:0]mu_config_cs_serial_output;
  input [11:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]Q;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input [15:0]\probeDelay1_reg[15] ;
  input \probeDelay1_reg[0] ;
  input [4:0]probe0;
  input [21:0]probe1;
  input [21:0]probe2;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]Q;
  wire [20:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ;
  wire [21:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ;
  wire [21:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ;
  wire [20:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
  wire [21:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ;
  wire [21:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ;
  wire [11:0]mu_config_cs_serial_input;
  wire [11:0]mu_config_cs_serial_output;
  wire [11:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [4:0]probe0;
  wire [21:0]probe1;
  wire [21:0]probe2;
  wire \probeDelay1_reg[0] ;
  wire [15:0]\probeDelay1_reg[15] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0 \N_DDR_MODE.G_NMU[0].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[0]),
        .out(out),
        .probe0(probe0),
        .\probeDelay1_reg[15] (\probeDelay1_reg[15] ),
        .\probeDelay1_reg[16] (\probeDelay1_reg[0] ),
        .\yes_output_reg.dout_reg_reg_0 (D[0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1 \N_DDR_MODE.G_NMU[10].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[10]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[10]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[10]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[10]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_32 \N_DDR_MODE.G_NMU[11].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[11]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[11]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[11]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[11]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0_33 \N_DDR_MODE.G_NMU[1].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[1]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[1]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0_34 \N_DDR_MODE.G_NMU[2].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[2]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[2]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0_35 \N_DDR_MODE.G_NMU[3].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[3]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[3]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_36 \N_DDR_MODE.G_NMU[4].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[4]),
        .out(out),
        .probe1(probe1),
        .\probeDelay1_reg[0] (\probeDelay1_reg[0] ),
        .\yes_output_reg.dout_reg_reg_0 (D[4]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_37 \N_DDR_MODE.G_NMU[5].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[5]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[5]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_38 \N_DDR_MODE.G_NMU[6].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[6]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[6]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_39 \N_DDR_MODE.G_NMU[7].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[7]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[7]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_40 \N_DDR_MODE.G_NMU[8].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[8]),
        .out(out),
        .probe2(probe2),
        .\probeDelay1_reg[0] (\probeDelay1_reg[0] ),
        .\yes_output_reg.dout_reg_reg_0 (D[8]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_41 \N_DDR_MODE.G_NMU[9].U_M 
       (.D(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[9]),
        .out(out),
        .\yes_output_reg.dout_reg_reg_0 (D[9]));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_trigger
   (shift_en_reg,
    mu_config_cs_serial_input,
    tc_config_cs_serial_input,
    capture_strg_qual,
    ADDRA,
    \TRIGGER_EQ_reg[0]_0 ,
    qual_strg_config_cs_serial_output,
    \parallel_dout_reg[15] ,
    out,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    Q,
    current_state,
    D,
    \probeDelay1_reg[0] ,
    probe0,
    probe1,
    probe2);
  output [0:0]shift_en_reg;
  output [11:0]mu_config_cs_serial_input;
  output [31:0]tc_config_cs_serial_input;
  output capture_strg_qual;
  output [1:0]ADDRA;
  output [0:0]\TRIGGER_EQ_reg[0]_0 ;
  input qual_strg_config_cs_serial_output;
  input [0:0]\parallel_dout_reg[15] ;
  input [0:0]out;
  input [11:0]mu_config_cs_serial_output;
  input [11:0]mu_config_cs_shift_en;
  input [31:0]tc_config_cs_serial_output;
  input [31:0]tc_config_cs_shift_en;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input [2:0]Q;
  input [3:0]current_state;
  input [15:0]D;
  input \probeDelay1_reg[0] ;
  input [4:0]probe0;
  input [21:0]probe1;
  input [21:0]probe2;

  wire [1:0]ADDRA;
  wire [15:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [2:0]Q;
  wire [0:0]\TRIGGER_EQ_reg[0]_0 ;
  wire \TRIGGER_EQ_reg_n_0_[10] ;
  wire \TRIGGER_EQ_reg_n_0_[11] ;
  wire \TRIGGER_EQ_reg_n_0_[12] ;
  wire \TRIGGER_EQ_reg_n_0_[13] ;
  wire \TRIGGER_EQ_reg_n_0_[14] ;
  wire \TRIGGER_EQ_reg_n_0_[15] ;
  wire \TRIGGER_EQ_reg_n_0_[1] ;
  wire \TRIGGER_EQ_reg_n_0_[2] ;
  wire \TRIGGER_EQ_reg_n_0_[3] ;
  wire \TRIGGER_EQ_reg_n_0_[4] ;
  wire \TRIGGER_EQ_reg_n_0_[5] ;
  wire \TRIGGER_EQ_reg_n_0_[6] ;
  wire \TRIGGER_EQ_reg_n_0_[7] ;
  wire \TRIGGER_EQ_reg_n_0_[8] ;
  wire \TRIGGER_EQ_reg_n_0_[9] ;
  wire [11:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
  wire cap_strg_qual;
  wire capture_strg_qual;
  wire [3:0]current_state;
  wire data0;
  wire data1;
  wire data10;
  wire data11;
  wire data12;
  wire data13;
  wire data14;
  wire data15;
  wire data2;
  wire data3;
  wire data4;
  wire data5;
  wire data6;
  wire data7;
  wire data8;
  wire data9;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0;
  wire fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0;
  wire [11:0]mu_config_cs_serial_input;
  wire [11:0]mu_config_cs_serial_output;
  wire [11:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [0:0]\parallel_dout_reg[15] ;
  wire [4:0]probe0;
  wire [21:0]probe1;
  wire [21:0]probe2;
  wire \probeDelay1_reg[0] ;
  wire qual_strg_config_cs_serial_output;
  wire shift_cap_strg_qual;
  wire [0:0]shift_en_reg;
  wire [31:0]tc_config_cs_serial_input;
  wire [31:0]tc_config_cs_serial_output;
  wire [31:0]tc_config_cs_shift_en;
  wire [11:0]trigCondIn_temp;
  wire [31:0]trigEqOut;

  FDRE CAP_QUAL_STRG_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(shift_cap_strg_qual),
        .Q(capture_strg_qual),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match \N_DDR_TC.N_DDR_TC_INST[0].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[0]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[0]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_0 \N_DDR_TC.N_DDR_TC_INST[10].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[10]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[10]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[10]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_1 \N_DDR_TC.N_DDR_TC_INST[11].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[11]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[11]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[11]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_2 \N_DDR_TC.N_DDR_TC_INST[12].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[12]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[12]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[12]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_3 \N_DDR_TC.N_DDR_TC_INST[13].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[13]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[13]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[13]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_4 \N_DDR_TC.N_DDR_TC_INST[14].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[14]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[14]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[14]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_5 \N_DDR_TC.N_DDR_TC_INST[15].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[15]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[15]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[15]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_6 \N_DDR_TC.N_DDR_TC_INST[16].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[16]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[16]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[16]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_7 \N_DDR_TC.N_DDR_TC_INST[17].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[17]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[17]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[17]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_8 \N_DDR_TC.N_DDR_TC_INST[18].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[18]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[18]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[18]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_9 \N_DDR_TC.N_DDR_TC_INST[19].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[19]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[19]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[19]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_10 \N_DDR_TC.N_DDR_TC_INST[1].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[1]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[1]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[1]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_11 \N_DDR_TC.N_DDR_TC_INST[20].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[20]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[20]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[20]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_12 \N_DDR_TC.N_DDR_TC_INST[21].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[21]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[21]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[21]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_13 \N_DDR_TC.N_DDR_TC_INST[22].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[22]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[22]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[22]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_14 \N_DDR_TC.N_DDR_TC_INST[23].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[23]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[23]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[23]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_15 \N_DDR_TC.N_DDR_TC_INST[24].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[24]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[24]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[24]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_16 \N_DDR_TC.N_DDR_TC_INST[25].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[25]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[25]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[25]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_17 \N_DDR_TC.N_DDR_TC_INST[26].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[26]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[26]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[26]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_18 \N_DDR_TC.N_DDR_TC_INST[27].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[27]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[27]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[27]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_19 \N_DDR_TC.N_DDR_TC_INST[28].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[28]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[28]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[28]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_20 \N_DDR_TC.N_DDR_TC_INST[29].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[29]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[29]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[29]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_21 \N_DDR_TC.N_DDR_TC_INST[2].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[2]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[2]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[2]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_22 \N_DDR_TC.N_DDR_TC_INST[30].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[30]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[30]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[30]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_23 \N_DDR_TC.N_DDR_TC_INST[31].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[31]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[31]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[31]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_24 \N_DDR_TC.N_DDR_TC_INST[3].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[3]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[3]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[3]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_25 \N_DDR_TC.N_DDR_TC_INST[4].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[4]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[4]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[4]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_26 \N_DDR_TC.N_DDR_TC_INST[5].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[5]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[5]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[5]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_27 \N_DDR_TC.N_DDR_TC_INST[6].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[6]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[6]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[6]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_28 \N_DDR_TC.N_DDR_TC_INST[7].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[7]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[7]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[7]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_29 \N_DDR_TC.N_DDR_TC_INST[8].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[8]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[8]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[8]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_30 \N_DDR_TC.N_DDR_TC_INST[9].U_TC 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[9]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[9]),
        .\yes_output_reg.dout_reg_reg_0 (trigEqOut[9]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_31 \STRG_QUAL.U_STRG_QUAL 
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (Q[1]),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
        .out(out),
        .\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
        .shift_en_reg(shift_en_reg),
        .\yes_output_reg.dout_reg_reg_0 (cap_strg_qual));
  FDRE \TRIGGER_EQ_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[0]),
        .Q(\TRIGGER_EQ_reg[0]_0 ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[10]),
        .Q(\TRIGGER_EQ_reg_n_0_[10] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[11]),
        .Q(\TRIGGER_EQ_reg_n_0_[11] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[12]),
        .Q(\TRIGGER_EQ_reg_n_0_[12] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[13]),
        .Q(\TRIGGER_EQ_reg_n_0_[13] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[14]),
        .Q(\TRIGGER_EQ_reg_n_0_[14] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[15]),
        .Q(\TRIGGER_EQ_reg_n_0_[15] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[16]),
        .Q(data0),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[17]),
        .Q(data1),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[18]),
        .Q(data2),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[19]),
        .Q(data3),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[1]),
        .Q(\TRIGGER_EQ_reg_n_0_[1] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[20]),
        .Q(data4),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[21] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[21]),
        .Q(data5),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[22] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[22]),
        .Q(data6),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[23] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[23]),
        .Q(data7),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[24] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[24]),
        .Q(data8),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[25] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[25]),
        .Q(data9),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[26] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[26]),
        .Q(data10),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[27] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[27]),
        .Q(data11),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[28] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[28]),
        .Q(data12),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[29] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[29]),
        .Q(data13),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[2]),
        .Q(\TRIGGER_EQ_reg_n_0_[2] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[30] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[30]),
        .Q(data14),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[31] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[31]),
        .Q(data15),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[3]),
        .Q(\TRIGGER_EQ_reg_n_0_[3] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[4]),
        .Q(\TRIGGER_EQ_reg_n_0_[4] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[5]),
        .Q(\TRIGGER_EQ_reg_n_0_[5] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[6]),
        .Q(\TRIGGER_EQ_reg_n_0_[6] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[7]),
        .Q(\TRIGGER_EQ_reg_n_0_[7] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[8]),
        .Q(\TRIGGER_EQ_reg_n_0_[8] ),
        .R(Q[2]));
  FDRE \TRIGGER_EQ_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(trigEqOut[9]),
        .Q(\TRIGGER_EQ_reg_n_0_[9] ),
        .R(Q[2]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_8_ila_trig_match U_TM
       (.D(trigCondIn_temp),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .Q(Q[0]),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .probe0(probe0),
        .probe1(probe1),
        .probe2(probe2),
        .\probeDelay1_reg[0] (\probeDelay1_reg[0] ),
        .\probeDelay1_reg[15] (D));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_10
       (.I0(\TRIGGER_EQ_reg_n_0_[11] ),
        .I1(\TRIGGER_EQ_reg_n_0_[10] ),
        .I2(current_state[1]),
        .I3(\TRIGGER_EQ_reg_n_0_[9] ),
        .I4(current_state[0]),
        .I5(\TRIGGER_EQ_reg_n_0_[8] ),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_11
       (.I0(\TRIGGER_EQ_reg_n_0_[15] ),
        .I1(\TRIGGER_EQ_reg_n_0_[14] ),
        .I2(current_state[1]),
        .I3(\TRIGGER_EQ_reg_n_0_[13] ),
        .I4(current_state[0]),
        .I5(\TRIGGER_EQ_reg_n_0_[12] ),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_12
       (.I0(data3),
        .I1(data2),
        .I2(current_state[1]),
        .I3(data1),
        .I4(current_state[0]),
        .I5(data0),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_13
       (.I0(data7),
        .I1(data6),
        .I2(current_state[1]),
        .I3(data5),
        .I4(current_state[0]),
        .I5(data4),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_14
       (.I0(data11),
        .I1(data10),
        .I2(current_state[1]),
        .I3(data9),
        .I4(current_state[0]),
        .I5(data8),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_15
       (.I0(data15),
        .I1(data14),
        .I2(current_state[1]),
        .I3(data13),
        .I4(current_state[0]),
        .I5(data12),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0));
  MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_2
       (.I0(fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0),
        .O(ADDRA[1]),
        .S(current_state[3]));
  MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_3
       (.I0(fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0),
        .O(ADDRA[0]),
        .S(current_state[3]));
  MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_4
       (.I0(fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0),
        .S(current_state[2]));
  MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_5
       (.I0(fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0),
        .S(current_state[2]));
  MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_6
       (.I0(fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0),
        .S(current_state[2]));
  MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_7
       (.I0(fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0),
        .I1(fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0),
        .S(current_state[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_8
       (.I0(\TRIGGER_EQ_reg_n_0_[3] ),
        .I1(\TRIGGER_EQ_reg_n_0_[2] ),
        .I2(current_state[1]),
        .I3(\TRIGGER_EQ_reg_n_0_[1] ),
        .I4(current_state[0]),
        .I5(\TRIGGER_EQ_reg[0]_0 ),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    fsm_mem_data_reg_r1_0_63_0_2_i_9
       (.I0(\TRIGGER_EQ_reg_n_0_[7] ),
        .I1(\TRIGGER_EQ_reg_n_0_[6] ),
        .I2(current_state[1]),
        .I3(\TRIGGER_EQ_reg_n_0_[5] ),
        .I4(current_state[0]),
        .I5(\TRIGGER_EQ_reg_n_0_[4] ),
        .O(fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0));
  FDRE shift_cap_strg_qual_reg
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .CE(1'b1),
        .D(cap_strg_qual),
        .Q(shift_cap_strg_qual),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    shift_en_reg,
    qual_strg_config_cs_serial_output,
    \parallel_dout_reg[15] ,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]shift_en_reg;
  input qual_strg_config_cs_serial_output;
  input [0:0]\parallel_dout_reg[15] ;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire [0:0]\parallel_dout_reg[15] ;
  wire qual_strg_config_cs_serial_output;
  wire [0:0]shift_en_reg;
  wire srl_q_0;
  wire srl_q_1;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_97 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .\parallel_dout_reg[15] (\parallel_dout_reg[15] ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_98 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\parallel_dout_reg[15] ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_3 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(\parallel_dout_reg[15] ),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(shift_en_reg));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_100
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_101 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_102 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_104
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_105 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_106 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_108
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_109 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_110 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_112
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_113 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_114 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_116
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_117 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_118 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_120
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_121 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_122 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_124
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_125 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_126 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_128
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_129 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_130 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_132
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_133 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_134 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_136
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_137 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_138 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_140
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_141 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_142 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_144
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_145 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_146 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_148
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_149 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_150 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_152
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_153 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_154 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_156
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_157 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_158 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_160
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_161 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_162 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_164
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_165 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_166 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_168
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_169 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_170 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_172
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_173 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_174 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_176
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_177 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_178 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_180
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_181 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_182 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_184
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_185 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_186 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_188
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_189 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_190 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_192
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_193 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_194 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_196
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_197 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_198 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_200
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_201 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_202 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_204
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_205 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_206 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_208
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_209 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_210 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_212
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_213 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_214 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_216
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_217 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_218 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_220
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_221 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_222 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_224
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_225 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(srl_q_1),
        .SRL_Q_O(srl_q_0),
        .out(out),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_226 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[11:8]),
        .DOUT_O(all_carry_1),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[11:8]),
        .SRL_D_I(srl_q_1),
        .out(out),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_42 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_44
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_45 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_46 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_49
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_50 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_51 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_52 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_54
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_55 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_56 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_57 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_59
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_60 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_61 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_62 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_64
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_65 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_66 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_67 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_68
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_69 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_70 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_71 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[20:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[20:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_73
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_74 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_75 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_76 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[20:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[20:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_78
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_79 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_80 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_81 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[20:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[20:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_83
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_84 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_85 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_86 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_88
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_89 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_90 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_91 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[21:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[21:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_93
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire all_carry_0;
  wire all_carry_1;
  wire all_carry_2;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire srl_q_2;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_94 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_95 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(all_carry_2),
        .SRL_A_I({Q[15],D[15],Q[14],D[14],Q[13],D[13],Q[12],D[12],Q[11],D[11],Q[10],D[10],Q[9],D[9],Q[8],D[8]}),
        .SRL_D_I(srl_q_2),
        .SRL_Q_O(srl_q_1),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_96 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.D(D[20:16]),
        .DOUT_O(all_carry_2),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q[20:16]),
        .SRL_D_I(srl_q_2),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1
   (shift_en_reg,
    SRL_Q_O,
    E,
    out,
    PROBES_I,
    SRL_D_I);
  output shift_en_reg;
  output SRL_Q_O;
  input [0:0]E;
  input [0:0]out;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire [0:0]E;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire shift_en_reg;
  wire srl_q_0;
  wire srl_q_1;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .E(E),
        .PROBES_I(PROBES_I[15:0]),
        .SRL_Q_O(srl_q_1),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .E(E),
        .PROBES_I(PROBES_I[19:16]),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(srl_q_1),
        .out(out),
        .shift_en_reg(shift_en_reg));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(E),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(SRL_Q_O));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1_255
   (shift_en_reg,
    shift_en_reg_0,
    E,
    out,
    PROBES_I,
    SRL_D_I);
  output shift_en_reg;
  output shift_en_reg_0;
  input [0:0]E;
  input [0:0]out;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire [0:0]E;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]out;
  wire shift_en_reg;
  wire shift_en_reg_0;
  wire srl_q_0;
  wire srl_q_1;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1_256 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .E(E),
        .PROBES_I(PROBES_I[15:0]),
        .SRL_Q_O(srl_q_1),
        .out(out),
        .shift_en_reg(srl_q_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2_257 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .E(E),
        .PROBES_I(PROBES_I[19:16]),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(srl_q_1),
        .out(out),
        .shift_en_reg(shift_en_reg));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(E),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(shift_en_reg_0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1_263
   (DOUT_O,
    SRL_Q_O,
    \iwcnt_reg[0] ,
    out,
    PROBES_I,
    SRL_D_I);
  output DOUT_O;
  output SRL_Q_O;
  input [0:0]\iwcnt_reg[0] ;
  input [0:0]out;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire DOUT_O;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire all_carry_0;
  wire all_carry_1;
  wire drive_ci;
  wire [0:0]\iwcnt_reg[0] ;
  wire [0:0]out;
  wire srl_q_0;
  wire srl_q_1;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1_264 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_0),
        .DOUT_O(all_carry_1),
        .PROBES_I(PROBES_I[15:0]),
        .SRL_Q_O(srl_q_1),
        .out(out),
        .shift_en_reg(srl_q_0),
        .u_carry4_inst_0(\iwcnt_reg[0] ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2_265 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(all_carry_1),
        .DOUT_O(DOUT_O),
        .PROBES_I(PROBES_I[19:16]),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(srl_q_1),
        .out(out),
        .u_carry4_inst_0(\iwcnt_reg[0] ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
  (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
  (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
  (* box_type = "PRIMITIVE" *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(\iwcnt_reg[0] ),
        .CLK(out),
        .D(srl_q_0),
        .Q(drive_ci),
        .Q31(SRL_Q_O));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_101
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_105
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_109
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_113
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_117
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_121
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_125
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_129
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_133
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_137
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_141
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_145
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_149
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_153
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_157
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_161
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_165
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_169
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_173
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_177
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_181
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_185
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_189
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_193
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_197
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_201
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_205
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_209
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_213
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_217
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_221
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_225
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_42
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_45
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_46
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_50
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_51
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_55
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_56
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_60
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_61
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_65
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_66
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_69
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_70
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_74
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_75
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_79
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_80
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_84
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_85
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_89
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_90
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_94
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_95
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_97
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    \parallel_dout_reg[15] ,
    out,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]\parallel_dout_reg[15] ;
  input [0:0]out;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [0:0]\parallel_dout_reg[15] ;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(\parallel_dout_reg[15] ),
        .CLK(out),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(\parallel_dout_reg[15] ),
        .CLK(out),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(\parallel_dout_reg[15] ),
        .CLK(out),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(\parallel_dout_reg[15] ),
        .CLK(out),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_102
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_106
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_110
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_114
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_118
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_122
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_126
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_130
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_134
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_138
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_142
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_146
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_150
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_154
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_158
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_162
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_166
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_170
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_174
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_178
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_182
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_186
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_190
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_194
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_198
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_202
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_206
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_210
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_214
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_218
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_222
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_226
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(tc_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_47
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_52
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_57
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_62
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_67
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_71
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [4:0]D;
  input [4:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [4:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [4:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_76
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [4:0]D;
  input [4:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [4:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [4:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_81
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [4:0]D;
  input [4:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [4:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [4:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_86
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_91
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [5:0]D;
  input [5:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [5:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [5:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(D[5]),
        .I3(Q[5]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_96
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [4:0]D;
  input [4:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;

  wire [4:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire [4:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(mu_config_cs_shift_en),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_98
   (SRL_D_I,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    qual_strg_config_cs_serial_output,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    out,
    D,
    Q,
    DOUT_O,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_3 );
  output SRL_D_I;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input qual_strg_config_cs_serial_output;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input [0:0]out;
  input [3:0]D;
  input [3:0]Q;
  input DOUT_O;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_3 ;

  wire [3:0]D;
  wire DOUT_O;
  (* async_reg = "true" *) wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_3 ;
  wire [3:0]Q;
  wire SRL_D_I;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [3:3]muxcy_lo;
  wire [0:0]out;
  wire qual_strg_config_cs_serial_output;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_3 ),
        .CE(1'b1),
        .D(muxcy_lo),
        .Q(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_2 ));
  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(DOUT_O),
        .CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_D_I),
        .CE(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CLK(out),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CLK(out),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(qual_strg_config_cs_serial_output),
        .CDO(cfg_data_2),
        .CE(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    E,
    out,
    PROBES_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]E;
  input [0:0]out;
  input [15:0]PROBES_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [0:0]E;
  wire [15:0]PROBES_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[4]),
        .I1(PROBES_I[5]),
        .I2(PROBES_I[6]),
        .I3(PROBES_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[8]),
        .I1(PROBES_I[9]),
        .I2(PROBES_I[10]),
        .I3(PROBES_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[12]),
        .I1(PROBES_I[13]),
        .I2(PROBES_I[14]),
        .I3(PROBES_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1_256
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    E,
    out,
    PROBES_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]E;
  input [0:0]out;
  input [15:0]PROBES_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [0:0]E;
  wire [15:0]PROBES_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[4]),
        .I1(PROBES_I[5]),
        .I2(PROBES_I[6]),
        .I3(PROBES_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[8]),
        .I1(PROBES_I[9]),
        .I2(PROBES_I[10]),
        .I3(PROBES_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[12]),
        .I1(PROBES_I[13]),
        .I2(PROBES_I[14]),
        .I3(PROBES_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1_264
   (shift_en_reg,
    DOUT_O,
    SRL_Q_O,
    u_carry4_inst_0,
    out,
    PROBES_I,
    CI_I);
  output shift_en_reg;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]u_carry4_inst_0;
  input [0:0]out;
  input [15:0]PROBES_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [15:0]PROBES_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire shift_en_reg;
  wire [0:0]u_carry4_inst_0;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(shift_en_reg),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(PROBES_I[4]),
        .I1(PROBES_I[5]),
        .I2(PROBES_I[6]),
        .I3(PROBES_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(PROBES_I[8]),
        .I1(PROBES_I[9]),
        .I2(PROBES_I[10]),
        .I3(PROBES_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_Q_O),
        .CDO(cfg_data_2),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(PROBES_I[12]),
        .I1(PROBES_I[13]),
        .I2(PROBES_I[14]),
        .I3(PROBES_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2
   (SRL_Q_O,
    shift_en_reg,
    SRL_D_I,
    E,
    out,
    PROBES_I,
    CI_I);
  output SRL_Q_O;
  output shift_en_reg;
  input SRL_D_I;
  input [0:0]E;
  input [0:0]out;
  input [3:0]PROBES_I;
  input CI_I;

  wire CI_I;
  wire [0:0]E;
  wire [3:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  (* async_reg = "true" *) wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({shift_en_reg,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(E),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(E),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(E),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2_257
   (SRL_Q_O,
    shift_en_reg,
    SRL_D_I,
    E,
    out,
    PROBES_I,
    CI_I);
  output SRL_Q_O;
  output shift_en_reg;
  input SRL_D_I;
  input [0:0]E;
  input [0:0]out;
  input [3:0]PROBES_I;
  input CI_I;

  wire CI_I;
  wire [0:0]E;
  wire [3:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  (* async_reg = "true" *) wire shift_en_reg;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({shift_en_reg,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(E),
        .CLK(out),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(E),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(E),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(E),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_all_typeA_slice" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2_265
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    u_carry4_inst_0,
    out,
    PROBES_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]u_carry4_inst_0;
  input [0:0]out;
  input [3:0]PROBES_I;
  input CI_I;

  wire CI_I;
  (* async_reg = "true" *) wire DOUT_O;
  wire [3:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cfg_data_2;
  wire [3:0]mux_di;
  wire [0:0]out;
  wire [3:0]sel;
  wire [0:0]u_carry4_inst_0;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

  (* box_type = "PRIMITIVE" *) 
  CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlA
       (.CDI(cfg_data_0),
        .CDO(SRL_Q_O),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlB
       (.CDI(cfg_data_1),
        .CDO(cfg_data_0),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlC
       (.CDI(cfg_data_2),
        .CDO(cfg_data_1),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
  (* box_type = "PRIMITIVE" *) 
  CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    u_srlD
       (.CDI(SRL_D_I),
        .CDO(cfg_data_2),
        .CE(u_carry4_inst_0),
        .CLK(out),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA
   (Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    shift_en_reg,
    qual_strg_config_cs_serial_output,
    \parallel_dout_reg[15] ,
    out,
    D,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output [11:0]Q;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]shift_en_reg;
  input qual_strg_config_cs_serial_output;
  input [0:0]\parallel_dout_reg[15] ;
  input [0:0]out;
  input [11:0]D;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]\parallel_dout_reg[15] ;
  wire qual_strg_config_cs_serial_output;
  wire [0:0]shift_en_reg;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
        .shift_en_reg(shift_en_reg));
  FDRE \probeDelay1_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \probeDelay1_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \probeDelay1_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \probeDelay1_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \probeDelay1_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \probeDelay1_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \probeDelay1_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \probeDelay1_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \probeDelay1_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \probeDelay1_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \probeDelay1_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \probeDelay1_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_103
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_104 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_107
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_108 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_111
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_112 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_115
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_116 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_119
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_120 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_123
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_124 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_127
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_128 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_131
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_132 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_135
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_136 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_139
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_140 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_143
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_144 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_147
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_148 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_151
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_152 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_155
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_156 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_159
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_160 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_163
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_164 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_167
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_168 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_171
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_172 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_175
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_176 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_179
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_180 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_183
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_184 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_187
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_188 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_191
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_192 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_195
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_196 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_199
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_200 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_203
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_204 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_207
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_208 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_211
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_212 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_215
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_216 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_219
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_220 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_223
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_224 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_99
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    tc_config_cs_serial_input,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]tc_config_cs_serial_input;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [11:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [11:0]Q;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_100 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_68 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0_72
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_73 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0_77
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_78 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0_92
   (D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \probeDelay1_reg[15]_0 ,
    \probeDelay1_reg[16]_0 ,
    probe0);
  output [20:0]D;
  output [20:0]Q;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input [15:0]\probeDelay1_reg[15]_0 ;
  input \probeDelay1_reg[16]_0 ;
  input [4:0]probe0;

  wire [20:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [20:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [4:0]probe0;
  wire [15:0]\probeDelay1_reg[15]_0 ;
  wire \probeDelay1_reg[16]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_93 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[12]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[13]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[14]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[15]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[16]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[17]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[18]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[19]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[20]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \probeDelay1_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [0]),
        .Q(D[0]),
        .R(1'b0));
  FDRE \probeDelay1_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [10]),
        .Q(D[10]),
        .R(1'b0));
  FDRE \probeDelay1_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [11]),
        .Q(D[11]),
        .R(1'b0));
  FDRE \probeDelay1_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [12]),
        .Q(D[12]),
        .R(1'b0));
  FDRE \probeDelay1_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [13]),
        .Q(D[13]),
        .R(1'b0));
  FDRE \probeDelay1_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [14]),
        .Q(D[14]),
        .R(1'b0));
  FDRE \probeDelay1_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [15]),
        .Q(D[15]),
        .R(1'b0));
  FDRE \probeDelay1_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe0[0]),
        .Q(D[16]),
        .R(\probeDelay1_reg[16]_0 ));
  FDRE \probeDelay1_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe0[1]),
        .Q(D[17]),
        .R(\probeDelay1_reg[16]_0 ));
  FDRE \probeDelay1_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe0[2]),
        .Q(D[18]),
        .R(\probeDelay1_reg[16]_0 ));
  FDRE \probeDelay1_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe0[3]),
        .Q(D[19]),
        .R(\probeDelay1_reg[16]_0 ));
  FDRE \probeDelay1_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [1]),
        .Q(D[1]),
        .R(1'b0));
  FDRE \probeDelay1_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe0[4]),
        .Q(D[20]),
        .R(\probeDelay1_reg[16]_0 ));
  FDRE \probeDelay1_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [2]),
        .Q(D[2]),
        .R(1'b0));
  FDRE \probeDelay1_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [3]),
        .Q(D[3]),
        .R(1'b0));
  FDRE \probeDelay1_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [4]),
        .Q(D[4]),
        .R(1'b0));
  FDRE \probeDelay1_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [5]),
        .Q(D[5]),
        .R(1'b0));
  FDRE \probeDelay1_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [6]),
        .Q(D[6]),
        .R(1'b0));
  FDRE \probeDelay1_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [7]),
        .Q(D[7]),
        .R(1'b0));
  FDRE \probeDelay1_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [8]),
        .Q(D[8]),
        .R(1'b0));
  FDRE \probeDelay1_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(\probeDelay1_reg[15]_0 [9]),
        .Q(D[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_43
   (D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \probeDelay1_reg[0]_0 ,
    probe2);
  output [21:0]D;
  output [21:0]Q;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \probeDelay1_reg[0]_0 ;
  input [21:0]probe2;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [21:0]probe2;
  wire \probeDelay1_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_44 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[12]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[13]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[14]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[15]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[16]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[17]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[18]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[19]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[20]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[21] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[21]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \probeDelay1_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[0]),
        .Q(D[0]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[10]),
        .Q(D[10]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[11]),
        .Q(D[11]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[12]),
        .Q(D[12]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[13]),
        .Q(D[13]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[14]),
        .Q(D[14]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[15]),
        .Q(D[15]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[16]),
        .Q(D[16]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[17]),
        .Q(D[17]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[18]),
        .Q(D[18]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[19]),
        .Q(D[19]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[1]),
        .Q(D[1]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[20]),
        .Q(D[20]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[21] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[21]),
        .Q(D[21]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[2]),
        .Q(D[2]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[3]),
        .Q(D[3]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[4]),
        .Q(D[4]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[5]),
        .Q(D[5]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[6]),
        .Q(D[6]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[7]),
        .Q(D[7]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[8]),
        .Q(D[8]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe2[9]),
        .Q(D[9]),
        .R(\probeDelay1_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_48
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_49 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_53
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_54 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_58
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_59 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_63
   (D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ,
    \probeDelay1_reg[0]_0 ,
    probe1);
  output [21:0]D;
  output [21:0]Q;
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  input \probeDelay1_reg[0]_0 ;
  input [21:0]probe1;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [21:0]probe1;
  wire \probeDelay1_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_64 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[12]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[13]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[14]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[15]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[16]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[17]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[18]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[19]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[20]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[21] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[21]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \probeDelay1_reg[0] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[0]),
        .Q(D[0]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[10] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[10]),
        .Q(D[10]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[11] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[11]),
        .Q(D[11]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[12] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[12]),
        .Q(D[12]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[13] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[13]),
        .Q(D[13]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[14] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[14]),
        .Q(D[14]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[15] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[15]),
        .Q(D[15]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[16] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[16]),
        .Q(D[16]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[17] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[17]),
        .Q(D[17]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[18] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[18]),
        .Q(D[18]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[19] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[19]),
        .Q(D[19]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[1] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[1]),
        .Q(D[1]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[20] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[20]),
        .Q(D[20]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[21] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[21]),
        .Q(D[21]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[2] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[2]),
        .Q(D[2]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[3] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[3]),
        .Q(D[3]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[4] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[4]),
        .Q(D[4]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[5] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[5]),
        .Q(D[5]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[6] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[6]),
        .Q(D[6]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[7] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[7]),
        .Q(D[7]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[8] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[8]),
        .Q(D[8]),
        .R(\probeDelay1_reg[0]_0 ));
  FDRE \probeDelay1_reg[9] 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .CE(1'b1),
        .D(probe1[9]),
        .Q(D[9]),
        .R(\probeDelay1_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_82
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_83 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_87
   (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    mu_config_cs_serial_input,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 );
  output \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  output [0:0]mu_config_cs_serial_input;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;

  wire [21:0]D;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ;
  wire [21:0]Q;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0_88 DUT
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay
   (\probeDelay1_reg[9]_0 ,
    shift_en_reg,
    SRL_Q_O,
    E,
    out,
    Q,
    SRL_D_I,
    \probeDelay1_reg[0]_0 );
  output [9:0]\probeDelay1_reg[9]_0 ;
  output shift_en_reg;
  output SRL_Q_O;
  input [0:0]E;
  input [0:0]out;
  input [9:0]Q;
  input SRL_D_I;
  input \probeDelay1_reg[0]_0 ;

  wire [0:0]E;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [0:0]out;
  wire \probeDelay1_reg[0]_0 ;
  wire [9:0]\probeDelay1_reg[9]_0 ;
  wire shift_en_reg;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1 DUT
       (.E(E),
        .PROBES_I({\probeDelay1_reg[9]_0 [9],Q[9],\probeDelay1_reg[9]_0 [8],Q[8],\probeDelay1_reg[9]_0 [7],Q[7],\probeDelay1_reg[9]_0 [6],Q[6],\probeDelay1_reg[9]_0 [5],Q[5],\probeDelay1_reg[9]_0 [4],Q[4],\probeDelay1_reg[9]_0 [3],Q[3],\probeDelay1_reg[9]_0 [2],Q[2],\probeDelay1_reg[9]_0 [1],Q[1],\probeDelay1_reg[9]_0 [0],Q[0]}),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .out(out),
        .shift_en_reg(shift_en_reg));
  FDRE \probeDelay1_reg[0] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[0]),
        .Q(\probeDelay1_reg[9]_0 [0]),
        .R(1'b0));
  FDRE \probeDelay1_reg[1] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[1]),
        .Q(\probeDelay1_reg[9]_0 [1]),
        .R(1'b0));
  FDRE \probeDelay1_reg[2] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[2]),
        .Q(\probeDelay1_reg[9]_0 [2]),
        .R(1'b0));
  FDRE \probeDelay1_reg[3] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[3]),
        .Q(\probeDelay1_reg[9]_0 [3]),
        .R(1'b0));
  FDRE \probeDelay1_reg[4] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[4]),
        .Q(\probeDelay1_reg[9]_0 [4]),
        .R(1'b0));
  FDRE \probeDelay1_reg[5] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[5]),
        .Q(\probeDelay1_reg[9]_0 [5]),
        .R(1'b0));
  FDRE \probeDelay1_reg[6] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[6]),
        .Q(\probeDelay1_reg[9]_0 [6]),
        .R(1'b0));
  FDRE \probeDelay1_reg[7] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[7]),
        .Q(\probeDelay1_reg[9]_0 [7]),
        .R(1'b0));
  FDRE \probeDelay1_reg[8] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[8]),
        .Q(\probeDelay1_reg[9]_0 [8]),
        .R(1'b0));
  FDRE \probeDelay1_reg[9] 
       (.C(\probeDelay1_reg[0]_0 ),
        .CE(1'b1),
        .D(Q[9]),
        .Q(\probeDelay1_reg[9]_0 [9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA_nodelay" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_254
   (shift_en_reg,
    shift_en_reg_0,
    E,
    out,
    PROBES_I,
    SRL_D_I);
  output shift_en_reg;
  output shift_en_reg_0;
  input [0:0]E;
  input [0:0]out;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire [0:0]E;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire [0:0]out;
  wire shift_en_reg;
  wire shift_en_reg_0;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1_255 DUT
       (.E(E),
        .PROBES_I(PROBES_I),
        .SRL_D_I(SRL_D_I),
        .out(out),
        .shift_en_reg(shift_en_reg),
        .shift_en_reg_0(shift_en_reg_0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_allx_typeA_nodelay" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_262
   (DOUT_O,
    SRL_Q_O,
    \iwcnt_reg[0] ,
    out,
    Q,
    SRL_D_I,
    \probeDelay1_reg[9]_0 );
  output DOUT_O;
  output SRL_Q_O;
  input [0:0]\iwcnt_reg[0] ;
  input [0:0]out;
  input [9:0]Q;
  input SRL_D_I;
  input \probeDelay1_reg[9]_0 ;

  wire DOUT_O;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [9:0]all_dly2;
  wire [0:0]\iwcnt_reg[0] ;
  wire [0:0]out;
  wire \probeDelay1_reg[9]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1_263 DUT
       (.DOUT_O(DOUT_O),
        .PROBES_I({all_dly2[9],Q[9],all_dly2[8],Q[8],all_dly2[7],Q[7],all_dly2[6],Q[6],all_dly2[5],Q[5],all_dly2[4],Q[4],all_dly2[3],Q[3],all_dly2[2],Q[2],all_dly2[1],Q[1],all_dly2[0],Q[0]}),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .\iwcnt_reg[0] (\iwcnt_reg[0] ),
        .out(out));
  FDRE \probeDelay1_reg[0] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[0]),
        .Q(all_dly2[0]),
        .R(1'b0));
  FDRE \probeDelay1_reg[1] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[1]),
        .Q(all_dly2[1]),
        .R(1'b0));
  FDRE \probeDelay1_reg[2] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[2]),
        .Q(all_dly2[2]),
        .R(1'b0));
  FDRE \probeDelay1_reg[3] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[3]),
        .Q(all_dly2[3]),
        .R(1'b0));
  FDRE \probeDelay1_reg[4] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[4]),
        .Q(all_dly2[4]),
        .R(1'b0));
  FDRE \probeDelay1_reg[5] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[5]),
        .Q(all_dly2[5]),
        .R(1'b0));
  FDRE \probeDelay1_reg[6] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[6]),
        .Q(all_dly2[6]),
        .R(1'b0));
  FDRE \probeDelay1_reg[7] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[7]),
        .Q(all_dly2[7]),
        .R(1'b0));
  FDRE \probeDelay1_reg[8] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[8]),
        .Q(all_dly2[8]),
        .R(1'b0));
  FDRE \probeDelay1_reg[9] 
       (.C(\probeDelay1_reg[9]_0 ),
        .CE(1'b1),
        .D(Q[9]),
        .Q(all_dly2[9]),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer
   (out,
    dout_reg1_reg_0,
    dout_reg0_reg_0,
    din_reg_reg_0,
    arm_ctrl,
    last_din);
  output out;
  output [0:0]dout_reg1_reg_0;
  input dout_reg0_reg_0;
  input [0:0]din_reg_reg_0;
  input arm_ctrl;
  input last_din;

  wire arm_ctrl;
  (* shreg_extract = "no" *) wire din_reg;
  wire din_reg_i_1__0_n_0;
  wire [0:0]din_reg_reg_0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
  wire dout_reg0_reg_0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
  wire [0:0]dout_reg1_reg_0;
  wire last_din;
  (* async_reg = "true" *) wire temp_reg0;
  (* async_reg = "true" *) wire temp_reg1;

  assign out = dout_reg1;
  LUT4 #(
    .INIT(16'hBE82)) 
    din_reg_i_1__0
       (.I0(arm_ctrl),
        .I1(temp_reg1),
        .I2(din_reg),
        .I3(din_reg),
        .O(din_reg_i_1__0_n_0));
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    din_reg_reg
       (.C(din_reg_reg_0),
        .CE(1'b1),
        .D(din_reg_i_1__0_n_0),
        .Q(din_reg),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \dout_pulse[0]_i_1__0 
       (.I0(dout_reg1),
        .I1(last_din),
        .O(dout_reg1_reg_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg0_reg
       (.C(dout_reg0_reg_0),
        .CE(1'b1),
        .D(din_reg),
        .Q(dout_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg1_reg
       (.C(dout_reg0_reg_0),
        .CE(1'b1),
        .D(dout_reg0),
        .Q(dout_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg0_reg
       (.C(din_reg_reg_0),
        .CE(1'b1),
        .D(dout_reg1),
        .Q(temp_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg1_reg
       (.C(din_reg_reg_0),
        .CE(1'b1),
        .D(temp_reg0),
        .Q(temp_reg1),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_async_edge_xfer" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_227
   (dout_reg1_reg_0,
    dout_reg1_reg_1,
    out,
    temp_reg1_reg_0,
    Q,
    \SEQUENCER_STATE_O_reg[8] ,
    current_state);
  output [0:0]dout_reg1_reg_0;
  output dout_reg1_reg_1;
  input [0:0]out;
  input temp_reg1_reg_0;
  input [0:0]Q;
  input \SEQUENCER_STATE_O_reg[8] ;
  input [0:0]current_state;

  wire [0:0]Q;
  wire \SEQUENCER_STATE_O_reg[8] ;
  wire [0:0]current_state;
  (* shreg_extract = "no" *) wire din_reg;
  wire din_reg_i_1__1_n_0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
  wire dout_reg1_reg_1;
  wire [0:0]out;
  (* async_reg = "true" *) wire temp_reg0;
  (* async_reg = "true" *) wire temp_reg1;
  wire temp_reg1_reg_0;

  assign dout_reg1_reg_0[0] = dout_reg1;
  LUT3 #(
    .INIT(8'h02)) 
    \SEQUENCER_STATE_O[15]_i_1 
       (.I0(dout_reg1),
        .I1(\SEQUENCER_STATE_O_reg[8] ),
        .I2(current_state),
        .O(dout_reg1_reg_1));
  LUT4 #(
    .INIT(16'h7D41)) 
    din_reg_i_1__1
       (.I0(Q),
        .I1(temp_reg1),
        .I2(din_reg),
        .I3(din_reg),
        .O(din_reg_i_1__1_n_0));
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    din_reg_reg
       (.C(temp_reg1_reg_0),
        .CE(1'b1),
        .D(din_reg_i_1__1_n_0),
        .Q(din_reg),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg0_reg
       (.C(out),
        .CE(1'b1),
        .D(din_reg),
        .Q(dout_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg1_reg
       (.C(out),
        .CE(1'b1),
        .D(dout_reg0),
        .Q(dout_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg0_reg
       (.C(temp_reg1_reg_0),
        .CE(1'b1),
        .D(dout_reg1),
        .Q(temp_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg1_reg
       (.C(temp_reg1_reg_0),
        .CE(1'b1),
        .D(temp_reg0),
        .Q(temp_reg1),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_async_edge_xfer" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_228
   (out,
    D,
    dout_reg0_reg_0,
    din_reg_reg_0,
    halt_ctrl,
    last_din);
  output out;
  output [0:0]D;
  input dout_reg0_reg_0;
  input [0:0]din_reg_reg_0;
  input halt_ctrl;
  input last_din;

  wire [0:0]D;
  (* shreg_extract = "no" *) wire din_reg;
  wire din_reg_i_1_n_0;
  wire [0:0]din_reg_reg_0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
  wire dout_reg0_reg_0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
  wire halt_ctrl;
  wire last_din;
  (* async_reg = "true" *) wire temp_reg0;
  (* async_reg = "true" *) wire temp_reg1;

  assign out = dout_reg1;
  LUT4 #(
    .INIT(16'hBE82)) 
    din_reg_i_1
       (.I0(halt_ctrl),
        .I1(temp_reg1),
        .I2(din_reg),
        .I3(din_reg),
        .O(din_reg_i_1_n_0));
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    din_reg_reg
       (.C(din_reg_reg_0),
        .CE(1'b1),
        .D(din_reg_i_1_n_0),
        .Q(din_reg),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \dout_pulse[0]_i_1 
       (.I0(dout_reg1),
        .I1(last_din),
        .O(D));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg0_reg
       (.C(dout_reg0_reg_0),
        .CE(1'b1),
        .D(din_reg),
        .Q(dout_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg1_reg
       (.C(dout_reg0_reg_0),
        .CE(1'b1),
        .D(dout_reg0),
        .Q(dout_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg0_reg
       (.C(din_reg_reg_0),
        .CE(1'b1),
        .D(dout_reg1),
        .Q(temp_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg1_reg
       (.C(din_reg_reg_0),
        .CE(1'b1),
        .D(temp_reg0),
        .Q(temp_reg1),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_async_edge_xfer" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_229
   (dout_reg1_reg_0,
    out,
    temp_reg0_reg_0,
    halt_out);
  output [0:0]dout_reg1_reg_0;
  input [0:0]out;
  input temp_reg0_reg_0;
  input halt_out;

  (* shreg_extract = "no" *) wire din_reg;
  wire din_reg_i_1__2_n_0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
  (* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
  wire halt_out;
  wire [0:0]out;
  (* async_reg = "true" *) wire temp_reg0;
  wire temp_reg0_reg_0;
  (* async_reg = "true" *) wire temp_reg1;

  assign dout_reg1_reg_0[0] = dout_reg1;
  LUT4 #(
    .INIT(16'hBE82)) 
    din_reg_i_1__2
       (.I0(halt_out),
        .I1(temp_reg1),
        .I2(din_reg),
        .I3(din_reg),
        .O(din_reg_i_1__2_n_0));
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    din_reg_reg
       (.C(temp_reg0_reg_0),
        .CE(1'b1),
        .D(din_reg_i_1__2_n_0),
        .Q(din_reg),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg0_reg
       (.C(out),
        .CE(1'b1),
        .D(din_reg),
        .Q(dout_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* SHREG_EXTRACT = "no" *) 
  FDRE #(
    .INIT(1'b0)) 
    dout_reg1_reg
       (.C(out),
        .CE(1'b1),
        .D(dout_reg0),
        .Q(dout_reg1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg0_reg
       (.C(temp_reg0_reg_0),
        .CE(1'b1),
        .D(dout_reg1),
        .Q(temp_reg0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    temp_reg1_reg
       (.C(temp_reg0_reg_0),
        .CE(1'b1),
        .D(temp_reg0),
        .Q(temp_reg1),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4
   (E,
    cfg_data_0,
    \iwcnt_reg[0] ,
    SRL_Q_O,
    A,
    out);
  output [0:0]E;
  output cfg_data_0;
  input [0:0]\iwcnt_reg[0] ;
  input SRL_Q_O;
  input [3:0]A;
  input [0:0]out;

  wire [3:0]A;
  wire [0:0]E;
  wire SRL_Q_O;
  wire cfg_data_0;
  wire [0:0]\iwcnt_reg[0] ;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRLC16E 
       (.A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .CE(\iwcnt_reg[0] ),
        .CLK(out),
        .D(SRL_Q_O),
        .Q(E),
        .Q15(cfg_data_0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_cfglut4" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4_258
   (E,
    cfg_data_0,
    \iscnt_reg[9] ,
    cfg_data_1,
    A,
    out);
  output [0:0]E;
  output cfg_data_0;
  input [0:0]\iscnt_reg[9] ;
  input cfg_data_1;
  input [3:0]A;
  input [0:0]out;

  wire [3:0]A;
  wire [0:0]E;
  wire cfg_data_0;
  wire cfg_data_1;
  wire [0:0]\iscnt_reg[9] ;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRLC16E 
       (.A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .CE(\iscnt_reg[9] ),
        .CLK(out),
        .D(cfg_data_1),
        .Q(E),
        .Q15(cfg_data_0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5
   (wcnt_hcmp_ce,
    SRL_D_I,
    E,
    SRL_Q_O,
    A,
    out);
  output wcnt_hcmp_ce;
  output SRL_D_I;
  input [0:0]E;
  input SRL_Q_O;
  input [4:0]A;
  input [0:0]out;

  wire [4:0]A;
  wire [0:0]E;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [0:0]out;
  wire wcnt_hcmp_ce;

  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32 
       (.A(A),
        .CE(E),
        .CLK(out),
        .D(SRL_Q_O),
        .Q(wcnt_hcmp_ce),
        .Q31(SRL_D_I));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_cfglut5" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_252
   (wcnt_lcmp_ce,
    SRL_D_I,
    E,
    cfg_data_0,
    A,
    out);
  output wcnt_lcmp_ce;
  output SRL_D_I;
  input [0:0]E;
  input cfg_data_0;
  input [4:0]A;
  input [0:0]out;

  wire [4:0]A;
  wire [0:0]E;
  wire SRL_D_I;
  wire cfg_data_0;
  wire [0:0]out;
  wire wcnt_lcmp_ce;

  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32 
       (.A(A),
        .CE(E),
        .CLK(out),
        .D(cfg_data_0),
        .Q(wcnt_lcmp_ce),
        .Q31(SRL_D_I));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_cfglut5" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_259
   (scnt_cmp_ce,
    cfg_data_1_0,
    u_scnt_cmp_q,
    cfg_data_0,
    A,
    out);
  output scnt_cmp_ce;
  output cfg_data_1_0;
  input [0:0]u_scnt_cmp_q;
  input cfg_data_0;
  input [4:0]A;
  input [0:0]out;

  wire [4:0]A;
  wire cfg_data_0;
  wire cfg_data_1_0;
  wire [0:0]out;
  wire scnt_cmp_ce;
  wire [0:0]u_scnt_cmp_q;

  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32 
       (.A(A),
        .CE(u_scnt_cmp_q),
        .CLK(out),
        .D(cfg_data_0),
        .Q(scnt_cmp_ce),
        .Q31(cfg_data_1_0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6
   (cfg_data_1,
    cmp_reset,
    E,
    cfg_data_0,
    A,
    out,
    u_wcnt_hcmp_q);
  output cfg_data_1;
  output cmp_reset;
  input [0:0]E;
  input cfg_data_0;
  input [4:0]A;
  input [0:0]out;
  input [0:0]u_wcnt_hcmp_q;

  wire [4:0]A;
  wire [0:0]E;
  wire \I_YESLUT6.SRL_Q31 ;
  wire \I_YESLUT6.SRL_Q_0 ;
  wire \I_YESLUT6.SRL_Q_1 ;
  wire cfg_data_0;
  wire cfg_data_1;
  wire cmp_reset;
  wire [0:0]out;
  wire [0:0]u_wcnt_hcmp_q;

  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_A 
       (.A(A),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31 ),
        .Q(\I_YESLUT6.SRL_Q_1 ),
        .Q31(cfg_data_1));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_B 
       (.A(A),
        .CE(E),
        .CLK(out),
        .D(cfg_data_0),
        .Q(\I_YESLUT6.SRL_Q_0 ),
        .Q31(\I_YESLUT6.SRL_Q31 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_scnt_cmp_q_i_1
       (.I0(\I_YESLUT6.SRL_Q_1 ),
        .I1(u_wcnt_hcmp_q),
        .I2(\I_YESLUT6.SRL_Q_0 ),
        .O(cmp_reset));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_cfglut6" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6_260
   (SRL_D_I,
    SR,
    \iscnt_reg[0] ,
    cfg_data_1_0,
    A,
    out,
    \iscnt_reg[0]_0 );
  output SRL_D_I;
  output [0:0]SR;
  input [0:0]\iscnt_reg[0] ;
  input cfg_data_1_0;
  input [4:0]A;
  input [0:0]out;
  input [0:0]\iscnt_reg[0]_0 ;

  wire [4:0]A;
  wire \I_YESLUT6.SRL_Q31 ;
  wire \I_YESLUT6.SRL_Q_0 ;
  wire \I_YESLUT6.SRL_Q_1 ;
  wire [0:0]SR;
  wire SRL_D_I;
  wire cfg_data_1_0;
  wire [0:0]\iscnt_reg[0] ;
  wire [0:0]\iscnt_reg[0]_0 ;
  wire [0:0]out;

  LUT3 #(
    .INIT(8'hB8)) 
    \G_COUNTER[0].U_COUNTER_i_1 
       (.I0(\I_YESLUT6.SRL_Q_1 ),
        .I1(\iscnt_reg[0]_0 ),
        .I2(\I_YESLUT6.SRL_Q_0 ),
        .O(SR));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_A 
       (.A(A),
        .CE(\iscnt_reg[0] ),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31 ),
        .Q(\I_YESLUT6.SRL_Q_1 ),
        .Q31(SRL_D_I));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_B 
       (.A(A),
        .CE(\iscnt_reg[0] ),
        .CLK(out),
        .D(cfg_data_1_0),
        .Q(\I_YESLUT6.SRL_Q_0 ),
        .Q31(\I_YESLUT6.SRL_Q31 ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_cfglut6" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6__parameterized0
   (D,
    CAP_DONE_O_reg,
    E,
    SRL_Q_O,
    A,
    out,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
    CAP_DONE_O_reg_0,
    Q,
    wcnt_hcmp);
  output [0:0]D;
  output CAP_DONE_O_reg;
  input [0:0]E;
  input SRL_Q_O;
  input [4:0]A;
  input [0:0]out;
  input \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  input CAP_DONE_O_reg_0;
  input [1:0]Q;
  input wcnt_hcmp;

  wire [4:0]A;
  wire CAP_DONE_O_reg;
  wire CAP_DONE_O_reg_0;
  wire [0:0]D;
  wire [0:0]E;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  wire \I_YESLUT6.SRL_MUX ;
  wire \I_YESLUT6.SRL_Q31 ;
  wire \I_YESLUT6.SRL_Q_0 ;
  wire \I_YESLUT6.SRL_Q_1 ;
  wire [1:0]Q;
  wire SRL_Q_O;
  wire cap_done_i;
  wire [0:0]out;
  wire wcnt_hcmp;

  LUT4 #(
    .INIT(16'hA0AE)) 
    CAP_DONE_O_i_1
       (.I0(CAP_DONE_O_reg_0),
        .I1(cap_done_i),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(CAP_DONE_O_reg));
  LUT3 #(
    .INIT(8'hB8)) 
    \I_YESLUT6.I_YES_OREG.O_reg_i_1 
       (.I0(\I_YESLUT6.SRL_Q_1 ),
        .I1(wcnt_hcmp),
        .I2(\I_YESLUT6.SRL_Q_0 ),
        .O(\I_YESLUT6.SRL_MUX ));
  FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg 
       (.C(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .CE(1'b1),
        .D(\I_YESLUT6.SRL_MUX ),
        .Q(cap_done_i),
        .R(1'b0));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_A 
       (.A(A),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31 ),
        .Q(\I_YESLUT6.SRL_Q_1 ),
        .Q31(D));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_B 
       (.A(A),
        .CE(E),
        .CLK(out),
        .D(SRL_Q_O),
        .Q(\I_YESLUT6.SRL_Q_0 ),
        .Q31(\I_YESLUT6.SRL_Q31 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7
   (\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
    in0,
    CAP_DONE_O_reg,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ,
    E,
    cfg_data_0,
    A,
    out,
    Q,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_2 ,
    wcnt_hcmp,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_3 ,
    trigger_reg,
    douta0,
    \cntcmpsel_reg[1] ,
    trig_out_fsm);
  output [0:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  output [0:0]in0;
  output CAP_DONE_O_reg;
  output \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
  input [0:0]E;
  input cfg_data_0;
  input [3:0]A;
  input [0:0]out;
  input [0:0]Q;
  input \I_YESLUT6.I_YES_OREG.O_reg_reg_2 ;
  input wcnt_hcmp;
  input [0:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_3 ;
  input trigger_reg;
  input [0:0]douta0;
  input \cntcmpsel_reg[1] ;
  input trig_out_fsm;

  wire [3:0]A;
  wire CAP_DONE_O_reg;
  wire [0:0]E;
  wire [0:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_2 ;
  wire [0:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_3 ;
  wire \I_YESLUT6.SRL_MUX8_n_0 ;
  wire \I_YESLUT6.SRL_Q31_0 ;
  wire \I_YESLUT6.SRL_Q31_1 ;
  wire \I_YESLUT6.SRL_Q31_2 ;
  wire \I_YESLUT6.SRL_Q_0 ;
  wire \I_YESLUT6.SRL_Q_1 ;
  wire \I_YESLUT6.SRL_Q_2 ;
  wire \I_YESLUT6.SRL_Q_3 ;
  wire [0:0]Q;
  wire cfg_data_0;
  wire \cntcmpsel_reg[1] ;
  wire [0:0]douta0;
  wire [0:0]in0;
  wire [0:0]out;
  wire trig_out_fsm;
  wire trigger_reg;
  wire wcnt_hcmp;

  FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg 
       (.C(\I_YESLUT6.I_YES_OREG.O_reg_reg_2 ),
        .CE(1'b1),
        .D(\I_YESLUT6.SRL_MUX8_n_0 ),
        .Q(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .R(Q));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \I_YESLUT6.SRL_MUX8 
       (.I0(\I_YESLUT6.SRL_Q_3 ),
        .I1(\I_YESLUT6.SRL_Q_2 ),
        .I2(wcnt_hcmp),
        .I3(\I_YESLUT6.SRL_Q_1 ),
        .I4(\I_YESLUT6.I_YES_OREG.O_reg_reg_3 ),
        .I5(\I_YESLUT6.SRL_Q_0 ),
        .O(\I_YESLUT6.SRL_MUX8_n_0 ));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_A 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 }),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31_2 ),
        .Q(\I_YESLUT6.SRL_Q_3 ),
        .Q31(in0));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_B 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 }),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31_1 ),
        .Q(\I_YESLUT6.SRL_Q_2 ),
        .Q31(\I_YESLUT6.SRL_Q31_2 ));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_C 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 }),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31_0 ),
        .Q(\I_YESLUT6.SRL_Q_1 ),
        .Q31(\I_YESLUT6.SRL_Q31_1 ));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_D 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 }),
        .CE(E),
        .CLK(out),
        .D(cfg_data_0),
        .Q(\I_YESLUT6.SRL_Q_0 ),
        .Q31(\I_YESLUT6.SRL_Q31_0 ));
  LUT2 #(
    .INIT(4'h4)) 
    \cntcmpsel[1]_i_2 
       (.I0(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .I1(\cntcmpsel_reg[1] ),
        .O(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
  LUT6 #(
    .INIT(64'hF000F00000400000)) 
    trigger_i_1
       (.I0(trigger_reg),
        .I1(douta0),
        .I2(\cntcmpsel_reg[1] ),
        .I3(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .I4(A[0]),
        .I5(trig_out_fsm),
        .O(CAP_DONE_O_reg));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_cfglut7" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7_251
   (\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
    cfg_data_0,
    dout_reg1_reg,
    CAP_DONE_O_reg,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ,
    itrigger_in,
    E,
    capture_ctrl_config_serial_output,
    A,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_2 ,
    out,
    Q,
    \I_YESLUT6.I_YES_OREG.O_reg_reg_3 ,
    wcnt_hcmp,
    douta0,
    \current_state_reg[0] ,
    capture_fsm,
    trig_out_fsm,
    itrigger_out_reg,
    basic_trigger,
    CAPTURE_O_reg);
  output [0:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  output cfg_data_0;
  output dout_reg1_reg;
  output CAP_DONE_O_reg;
  output \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
  output itrigger_in;
  input [0:0]E;
  input capture_ctrl_config_serial_output;
  input [2:0]A;
  input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_2 ;
  input [0:0]out;
  input [0:0]Q;
  input \I_YESLUT6.I_YES_OREG.O_reg_reg_3 ;
  input wcnt_hcmp;
  input [0:0]douta0;
  input \current_state_reg[0] ;
  input capture_fsm;
  input trig_out_fsm;
  input itrigger_out_reg;
  input basic_trigger;
  input CAPTURE_O_reg;

  wire [2:0]A;
  wire CAPTURE_O_reg;
  wire CAP_DONE_O_reg;
  wire [0:0]E;
  wire [0:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
  wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg_2 ;
  wire \I_YESLUT6.I_YES_OREG.O_reg_reg_3 ;
  wire \I_YESLUT6.SRL_MUX8__0 ;
  wire \I_YESLUT6.SRL_Q31_0 ;
  wire \I_YESLUT6.SRL_Q31_1 ;
  wire \I_YESLUT6.SRL_Q31_2 ;
  wire \I_YESLUT6.SRL_Q_0 ;
  wire \I_YESLUT6.SRL_Q_1 ;
  wire \I_YESLUT6.SRL_Q_2 ;
  wire \I_YESLUT6.SRL_Q_3 ;
  wire [0:0]Q;
  wire basic_trigger;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm;
  wire cfg_data_0;
  wire \current_state_reg[0] ;
  wire dout_reg1_reg;
  wire [0:0]douta0;
  wire itrigger_in;
  wire itrigger_out_reg;
  wire [0:0]out;
  wire trig_out_fsm;
  wire wcnt_hcmp;

  LUT6 #(
    .INIT(64'hF080F00000800000)) 
    CAPTURE_O_i_1
       (.I0(CAP_DONE_O_reg),
        .I1(douta0),
        .I2(\current_state_reg[0] ),
        .I3(\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]),
        .I4(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .I5(capture_fsm),
        .O(dout_reg1_reg));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \G_COUNTER[0].U_COUNTER_i_5 
       (.I0(CAPTURE_O_reg),
        .I1(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .I2(\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]),
        .I3(trig_out_fsm),
        .O(CAP_DONE_O_reg));
  FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg 
       (.C(\I_YESLUT6.I_YES_OREG.O_reg_reg_3 ),
        .CE(1'b1),
        .D(\I_YESLUT6.SRL_MUX8__0 ),
        .Q(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .R(Q));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \I_YESLUT6.SRL_MUX8 
       (.I0(\I_YESLUT6.SRL_Q_3 ),
        .I1(\I_YESLUT6.SRL_Q_2 ),
        .I2(wcnt_hcmp),
        .I3(\I_YESLUT6.SRL_Q_1 ),
        .I4(\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [1]),
        .I5(\I_YESLUT6.SRL_Q_0 ),
        .O(\I_YESLUT6.SRL_MUX8__0 ));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_A 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]}),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31_2 ),
        .Q(\I_YESLUT6.SRL_Q_3 ),
        .Q31(cfg_data_0));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_B 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]}),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31_1 ),
        .Q(\I_YESLUT6.SRL_Q_2 ),
        .Q31(\I_YESLUT6.SRL_Q31_2 ));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_C 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]}),
        .CE(E),
        .CLK(out),
        .D(\I_YESLUT6.SRL_Q31_0 ),
        .Q(\I_YESLUT6.SRL_Q_1 ),
        .Q31(\I_YESLUT6.SRL_Q31_1 ));
  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "inst/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \I_YESLUT6.U_SRL32_D 
       (.A({A,\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]}),
        .CE(E),
        .CLK(out),
        .D(capture_ctrl_config_serial_output),
        .Q(\I_YESLUT6.SRL_Q_0 ),
        .Q31(\I_YESLUT6.SRL_Q31_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \cntcmpsel[1]_i_1 
       (.I0(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .I1(\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]),
        .I2(\current_state_reg[0] ),
        .O(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
  LUT5 #(
    .INIT(32'h20222000)) 
    itrigger_out_i_1
       (.I0(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
        .I1(\I_YESLUT6.I_YES_OREG.O_reg_reg_2 [0]),
        .I2(trig_out_fsm),
        .I3(itrigger_out_reg),
        .I4(basic_trigger),
        .O(itrigger_in));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_generic_memrd
   (data_out_en,
    D,
    \curr_read_block_reg[2]_0 ,
    \input_data_reg[65]_0 ,
    \input_data_reg[64]_0 ,
    Q,
    \input_data_reg[63]_0 ,
    \input_data_reg[62]_0 ,
    \input_data_reg[61]_0 ,
    \input_data_reg[60]_0 ,
    \input_data_reg[59]_0 ,
    \input_data_reg[58]_0 ,
    \input_data_reg[57]_0 ,
    \input_data_reg[56]_0 ,
    \input_data_reg[55]_0 ,
    \input_data_reg[54]_0 ,
    \input_data_reg[53]_0 ,
    \input_data_reg[52]_0 ,
    \input_data_reg[51]_0 ,
    \input_data_reg[50]_0 ,
    out,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    \input_data_reg[65]_1 ,
    SR,
    read_data_en,
    read_reset_addr,
    \current_state_reg[3]_0 );
  output data_out_en;
  output [0:0]D;
  output \curr_read_block_reg[2]_0 ;
  output \input_data_reg[65]_0 ;
  output \input_data_reg[64]_0 ;
  output [9:0]Q;
  output \input_data_reg[63]_0 ;
  output \input_data_reg[62]_0 ;
  output \input_data_reg[61]_0 ;
  output \input_data_reg[60]_0 ;
  output \input_data_reg[59]_0 ;
  output \input_data_reg[58]_0 ;
  output \input_data_reg[57]_0 ;
  output \input_data_reg[56]_0 ;
  output \input_data_reg[55]_0 ;
  output \input_data_reg[54]_0 ;
  output \input_data_reg[53]_0 ;
  output \input_data_reg[52]_0 ;
  output \input_data_reg[51]_0 ;
  output \input_data_reg[50]_0 ;
  input [0:0]out;
  input \xsdb_reg_reg[1] ;
  input \xsdb_reg_reg[0] ;
  input [65:0]\input_data_reg[65]_1 ;
  input [0:0]SR;
  input read_data_en;
  input [9:0]read_reset_addr;
  input [0:0]\current_state_reg[3]_0 ;

  wire [0:0]D;
  wire [9:0]Q;
  wire [0:0]SR;
  wire [2:0]curr_read_block;
  wire \curr_read_block[0]_i_1_n_0 ;
  wire \curr_read_block[1]_i_1_n_0 ;
  wire \curr_read_block[2]_i_1_n_0 ;
  wire \curr_read_block_reg[2]_0 ;
  wire \current_state[0]_i_2_n_0 ;
  wire \current_state[0]_i_3_n_0 ;
  wire \current_state[1]_i_2_n_0 ;
  wire \current_state[3]_i_2__49_n_0 ;
  wire \current_state[4]_i_2_n_0 ;
  wire \current_state[6]_i_2_n_0 ;
  wire [0:0]\current_state_reg[3]_0 ;
  wire \current_state_reg_n_0_[0] ;
  wire \current_state_reg_n_0_[1] ;
  wire \current_state_reg_n_0_[2] ;
  wire \current_state_reg_n_0_[3] ;
  wire \current_state_reg_n_0_[4] ;
  wire \current_state_reg_n_0_[5] ;
  wire \current_state_reg_n_0_[6] ;
  wire data_out_en;
  wire [65:0]input_data;
  wire \input_data_reg[50]_0 ;
  wire \input_data_reg[51]_0 ;
  wire \input_data_reg[52]_0 ;
  wire \input_data_reg[53]_0 ;
  wire \input_data_reg[54]_0 ;
  wire \input_data_reg[55]_0 ;
  wire \input_data_reg[56]_0 ;
  wire \input_data_reg[57]_0 ;
  wire \input_data_reg[58]_0 ;
  wire \input_data_reg[59]_0 ;
  wire \input_data_reg[60]_0 ;
  wire \input_data_reg[61]_0 ;
  wire \input_data_reg[62]_0 ;
  wire \input_data_reg[63]_0 ;
  wire \input_data_reg[64]_0 ;
  wire \input_data_reg[65]_0 ;
  wire [65:0]\input_data_reg[65]_1 ;
  wire \multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ;
  wire \multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ;
  wire [6:0]next_state;
  wire [0:0]out;
  wire p_0_in;
  wire read_addr;
  wire \read_addr[0]_i_1_n_0 ;
  wire \read_addr[1]_i_1_n_0 ;
  wire \read_addr[2]_i_1_n_0 ;
  wire \read_addr[3]_i_1_n_0 ;
  wire \read_addr[4]_i_1_n_0 ;
  wire \read_addr[4]_i_2_n_0 ;
  wire \read_addr[5]_i_1_n_0 ;
  wire \read_addr[6]_i_1_n_0 ;
  wire \read_addr[7]_i_1_n_0 ;
  wire \read_addr[7]_i_2_n_0 ;
  wire \read_addr[8]_i_1_n_0 ;
  wire \read_addr[8]_i_2_n_0 ;
  wire \read_addr[9]_i_2_n_0 ;
  wire \read_addr[9]_i_3_n_0 ;
  wire read_data_en;
  wire read_en_temp;
  wire [9:0]read_reset_addr;
  wire \xsdb_reg[0]_i_2_n_0 ;
  wire \xsdb_reg[1]_i_2_n_0 ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[1] ;

  LUT2 #(
    .INIT(4'hE)) 
    \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 
       (.I0(p_0_in),
        .I1(read_en_temp),
        .O(D));
  LUT4 #(
    .INIT(16'h0344)) 
    \curr_read_block[0]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\current_state[6]_i_2_n_0 ),
        .I2(next_state[0]),
        .I3(curr_read_block[0]),
        .O(\curr_read_block[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT5 #(
    .INIT(32'h101F4040)) 
    \curr_read_block[1]_i_1 
       (.I0(curr_read_block[2]),
        .I1(curr_read_block[0]),
        .I2(\current_state[6]_i_2_n_0 ),
        .I3(next_state[0]),
        .I4(curr_read_block[1]),
        .O(\curr_read_block[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT5 #(
    .INIT(32'h000F8080)) 
    \curr_read_block[2]_i_1 
       (.I0(curr_read_block[1]),
        .I1(curr_read_block[0]),
        .I2(\current_state[6]_i_2_n_0 ),
        .I3(next_state[0]),
        .I4(curr_read_block[2]),
        .O(\curr_read_block[2]_i_1_n_0 ));
  FDRE \curr_read_block_reg[0] 
       (.C(out),
        .CE(1'b1),
        .D(\curr_read_block[0]_i_1_n_0 ),
        .Q(curr_read_block[0]),
        .R(1'b0));
  FDRE \curr_read_block_reg[1] 
       (.C(out),
        .CE(1'b1),
        .D(\curr_read_block[1]_i_1_n_0 ),
        .Q(curr_read_block[1]),
        .R(1'b0));
  FDRE \curr_read_block_reg[2] 
       (.C(out),
        .CE(1'b1),
        .D(\curr_read_block[2]_i_1_n_0 ),
        .Q(curr_read_block[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFCFFFCFCDF)) 
    \current_state[0]_i_1__50 
       (.I0(read_data_en),
        .I1(\current_state[0]_i_2_n_0 ),
        .I2(\current_state_reg_n_0_[0] ),
        .I3(\current_state_reg_n_0_[1] ),
        .I4(\current_state[0]_i_3_n_0 ),
        .I5(\current_state_reg_n_0_[2] ),
        .O(next_state[0]));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT4 #(
    .INIT(16'hFEE8)) 
    \current_state[0]_i_2 
       (.I0(\current_state_reg_n_0_[3] ),
        .I1(\current_state_reg_n_0_[4] ),
        .I2(\current_state_reg_n_0_[5] ),
        .I3(\current_state_reg_n_0_[6] ),
        .O(\current_state[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[0]_i_3 
       (.I0(\current_state_reg_n_0_[5] ),
        .I1(\current_state_reg_n_0_[6] ),
        .I2(\current_state_reg_n_0_[3] ),
        .I3(\current_state_reg_n_0_[4] ),
        .O(\current_state[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0002020000020000)) 
    \current_state[1]_i_1__50 
       (.I0(\current_state[1]_i_2_n_0 ),
        .I1(\current_state_reg_n_0_[1] ),
        .I2(\current_state_reg_n_0_[2] ),
        .I3(\current_state_reg_n_0_[0] ),
        .I4(\current_state_reg_n_0_[6] ),
        .I5(read_data_en),
        .O(next_state[1]));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \current_state[1]_i_2 
       (.I0(\current_state_reg_n_0_[3] ),
        .I1(\current_state_reg_n_0_[4] ),
        .I2(\current_state_reg_n_0_[5] ),
        .O(\current_state[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT5 #(
    .INIT(32'h00200028)) 
    \current_state[2]_i_1__50 
       (.I0(\current_state[3]_i_2__49_n_0 ),
        .I1(\current_state_reg_n_0_[2] ),
        .I2(\current_state_reg_n_0_[1] ),
        .I3(\current_state_reg_n_0_[5] ),
        .I4(\current_state_reg[3]_0 ),
        .O(next_state[2]));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT5 #(
    .INIT(32'h02200200)) 
    \current_state[3]_i_1__50 
       (.I0(\current_state[3]_i_2__49_n_0 ),
        .I1(\current_state_reg_n_0_[1] ),
        .I2(\current_state_reg_n_0_[2] ),
        .I3(\current_state_reg_n_0_[5] ),
        .I4(\current_state_reg[3]_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \current_state[3]_i_2__49 
       (.I0(\current_state_reg_n_0_[3] ),
        .I1(\current_state_reg_n_0_[4] ),
        .I2(\current_state_reg_n_0_[0] ),
        .I3(\current_state_reg_n_0_[6] ),
        .O(\current_state[3]_i_2__49_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT5 #(
    .INIT(32'h000002A0)) 
    \current_state[4]_i_1 
       (.I0(\current_state[4]_i_2_n_0 ),
        .I1(read_data_en),
        .I2(\current_state_reg_n_0_[3] ),
        .I3(\current_state_reg_n_0_[4] ),
        .I4(\current_state_reg_n_0_[2] ),
        .O(next_state[4]));
  LUT4 #(
    .INIT(16'h0001)) 
    \current_state[4]_i_2 
       (.I0(\current_state_reg_n_0_[5] ),
        .I1(\current_state_reg_n_0_[6] ),
        .I2(\current_state_reg_n_0_[0] ),
        .I3(\current_state_reg_n_0_[1] ),
        .O(\current_state[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \current_state[5]_i_1 
       (.I0(\current_state[6]_i_2_n_0 ),
        .I1(curr_read_block[2]),
        .O(next_state[5]));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \current_state[6]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\current_state[6]_i_2_n_0 ),
        .O(next_state[6]));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT5 #(
    .INIT(32'h00000800)) 
    \current_state[6]_i_2 
       (.I0(\current_state[4]_i_2_n_0 ),
        .I1(\current_state_reg_n_0_[4] ),
        .I2(\current_state_reg_n_0_[2] ),
        .I3(read_data_en),
        .I4(\current_state_reg_n_0_[3] ),
        .O(\current_state[6]_i_2_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \current_state_reg[0] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(\current_state_reg_n_0_[0] ),
        .S(SR));
  FDRE #(
    .INIT(1'b0)) 
    \current_state_reg[1] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(\current_state_reg_n_0_[1] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \current_state_reg[2] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(\current_state_reg_n_0_[2] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \current_state_reg[3] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(\current_state_reg_n_0_[3] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \current_state_reg[4] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[4]),
        .Q(\current_state_reg_n_0_[4] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \current_state_reg[5] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[5]),
        .Q(\current_state_reg_n_0_[5] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \current_state_reg[6] 
       (.C(out),
        .CE(1'b1),
        .D(next_state[6]),
        .Q(\current_state_reg_n_0_[6] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[0] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [0]),
        .Q(input_data[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[10] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [10]),
        .Q(input_data[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[11] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [11]),
        .Q(input_data[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[12] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [12]),
        .Q(input_data[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[13] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [13]),
        .Q(input_data[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[14] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [14]),
        .Q(input_data[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[15] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [15]),
        .Q(input_data[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[16] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [16]),
        .Q(input_data[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[17] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [17]),
        .Q(input_data[17]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[18] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [18]),
        .Q(input_data[18]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[19] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [19]),
        .Q(input_data[19]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[1] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [1]),
        .Q(input_data[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[20] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [20]),
        .Q(input_data[20]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[21] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [21]),
        .Q(input_data[21]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[22] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [22]),
        .Q(input_data[22]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[23] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [23]),
        .Q(input_data[23]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[24] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [24]),
        .Q(input_data[24]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[25] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [25]),
        .Q(input_data[25]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[26] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [26]),
        .Q(input_data[26]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[27] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [27]),
        .Q(input_data[27]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[28] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [28]),
        .Q(input_data[28]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[29] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [29]),
        .Q(input_data[29]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[2] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [2]),
        .Q(input_data[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[30] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [30]),
        .Q(input_data[30]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[31] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [31]),
        .Q(input_data[31]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[32] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [32]),
        .Q(input_data[32]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[33] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [33]),
        .Q(input_data[33]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[34] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [34]),
        .Q(input_data[34]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[35] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [35]),
        .Q(input_data[35]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[36] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [36]),
        .Q(input_data[36]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[37] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [37]),
        .Q(input_data[37]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[38] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [38]),
        .Q(input_data[38]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[39] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [39]),
        .Q(input_data[39]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[3] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [3]),
        .Q(input_data[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[40] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [40]),
        .Q(input_data[40]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[41] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [41]),
        .Q(input_data[41]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[42] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [42]),
        .Q(input_data[42]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[43] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [43]),
        .Q(input_data[43]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[44] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [44]),
        .Q(input_data[44]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[45] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [45]),
        .Q(input_data[45]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[46] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [46]),
        .Q(input_data[46]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[47] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [47]),
        .Q(input_data[47]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[48] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [48]),
        .Q(input_data[48]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[49] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [49]),
        .Q(input_data[49]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[4] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [4]),
        .Q(input_data[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[50] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [50]),
        .Q(input_data[50]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[51] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [51]),
        .Q(input_data[51]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[52] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [52]),
        .Q(input_data[52]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[53] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [53]),
        .Q(input_data[53]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[54] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [54]),
        .Q(input_data[54]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[55] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [55]),
        .Q(input_data[55]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[56] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [56]),
        .Q(input_data[56]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[57] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [57]),
        .Q(input_data[57]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[58] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [58]),
        .Q(input_data[58]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[59] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [59]),
        .Q(input_data[59]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[5] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [5]),
        .Q(input_data[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[60] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [60]),
        .Q(input_data[60]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[61] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [61]),
        .Q(input_data[61]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[62] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [62]),
        .Q(input_data[62]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[63] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [63]),
        .Q(input_data[63]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[64] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [64]),
        .Q(input_data[64]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[65] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [65]),
        .Q(input_data[65]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[6] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [6]),
        .Q(input_data[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[7] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [7]),
        .Q(input_data[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[8] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [8]),
        .Q(input_data[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \input_data_reg[9] 
       (.C(out),
        .CE(1'b1),
        .D(\input_data_reg[65]_1 [9]),
        .Q(input_data[9]),
        .R(1'b0));
  (* srl_bus_name = "inst/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg " *) 
  (* srl_name = "inst/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[2]_srl3 " *) 
  SRL16E \multiple_enable_latency.enable_out_reg[2]_srl3 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(out),
        .D(next_state[3]),
        .Q(\multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ));
  FDRE \multiple_enable_latency.enable_out_reg[3] 
       (.C(out),
        .CE(1'b1),
        .D(\multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ),
        .Q(data_out_en),
        .R(1'b0));
  FDRE \multiple_read_latency.read_en_temp_reg 
       (.C(out),
        .CE(1'b1),
        .D(p_0_in),
        .Q(read_en_temp),
        .R(1'b0));
  (* srl_bus_name = "inst/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg " *) 
  (* srl_name = "inst/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[2]_srl3 " *) 
  SRL16E \multiple_read_latency.read_enable_out_reg[2]_srl3 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(out),
        .D(next_state[1]),
        .Q(\multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ));
  FDRE \multiple_read_latency.read_enable_out_reg[3] 
       (.C(out),
        .CE(1'b1),
        .D(\multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ),
        .Q(p_0_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \read_addr[0]_i_1 
       (.I0(read_reset_addr[0]),
        .I1(next_state[0]),
        .I2(Q[0]),
        .O(\read_addr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT4 #(
    .INIT(16'h8BB8)) 
    \read_addr[1]_i_1 
       (.I0(read_reset_addr[1]),
        .I1(next_state[0]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\read_addr[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8BB8B8B8)) 
    \read_addr[2]_i_1 
       (.I0(read_reset_addr[2]),
        .I1(next_state[0]),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\read_addr[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8BB8B8B8B8B8B8B8)) 
    \read_addr[3]_i_1 
       (.I0(read_reset_addr[3]),
        .I1(next_state[0]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(Q[2]),
        .O(\read_addr[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \read_addr[4]_i_1 
       (.I0(read_reset_addr[4]),
        .I1(next_state[0]),
        .I2(\read_addr[4]_i_2_n_0 ),
        .I3(Q[4]),
        .O(\read_addr[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \read_addr[4]_i_2 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(\read_addr[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8BB8)) 
    \read_addr[5]_i_1 
       (.I0(read_reset_addr[5]),
        .I1(next_state[0]),
        .I2(Q[5]),
        .I3(\read_addr[7]_i_2_n_0 ),
        .O(\read_addr[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8BB8B8B8)) 
    \read_addr[6]_i_1 
       (.I0(read_reset_addr[6]),
        .I1(next_state[0]),
        .I2(Q[6]),
        .I3(\read_addr[7]_i_2_n_0 ),
        .I4(Q[5]),
        .O(\read_addr[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8BB8B8B8B8B8B8B8)) 
    \read_addr[7]_i_1 
       (.I0(read_reset_addr[7]),
        .I1(next_state[0]),
        .I2(Q[7]),
        .I3(Q[5]),
        .I4(\read_addr[7]_i_2_n_0 ),
        .I5(Q[6]),
        .O(\read_addr[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \read_addr[7]_i_2 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\read_addr[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8BB8B8B8B8B8B8B8)) 
    \read_addr[8]_i_1 
       (.I0(read_reset_addr[8]),
        .I1(next_state[0]),
        .I2(Q[8]),
        .I3(Q[6]),
        .I4(\read_addr[8]_i_2_n_0 ),
        .I5(Q[7]),
        .O(\read_addr[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \read_addr[8]_i_2 
       (.I0(Q[5]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[4]),
        .O(\read_addr[8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \read_addr[9]_i_1 
       (.I0(\current_state[6]_i_2_n_0 ),
        .I1(curr_read_block[2]),
        .I2(next_state[0]),
        .O(read_addr));
  LUT5 #(
    .INIT(32'h8BB8B8B8)) 
    \read_addr[9]_i_2 
       (.I0(read_reset_addr[9]),
        .I1(next_state[0]),
        .I2(Q[9]),
        .I3(\read_addr[9]_i_3_n_0 ),
        .I4(Q[8]),
        .O(\read_addr[9]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \read_addr[9]_i_3 
       (.I0(Q[7]),
        .I1(Q[5]),
        .I2(\read_addr[7]_i_2_n_0 ),
        .I3(Q[6]),
        .O(\read_addr[9]_i_3_n_0 ));
  FDRE \read_addr_reg[0] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \read_addr_reg[1] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \read_addr_reg[2] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \read_addr_reg[3] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \read_addr_reg[4] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[4]_i_1_n_0 ),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \read_addr_reg[5] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[5]_i_1_n_0 ),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \read_addr_reg[6] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[6]_i_1_n_0 ),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \read_addr_reg[7] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[7]_i_1_n_0 ),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \read_addr_reg[8] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[8]_i_1_n_0 ),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \read_addr_reg[9] 
       (.C(out),
        .CE(read_addr),
        .D(\read_addr[9]_i_2_n_0 ),
        .Q(Q[9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg[0]_i_1 
       (.I0(input_data[64]),
        .I1(curr_read_block[2]),
        .I2(\xsdb_reg[0]_i_2_n_0 ),
        .I3(data_out_en),
        .I4(\xsdb_reg_reg[0] ),
        .O(\input_data_reg[64]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg[15]_i_1 
       (.I0(curr_read_block[2]),
        .I1(data_out_en),
        .O(\curr_read_block_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg[1]_i_1 
       (.I0(input_data[65]),
        .I1(curr_read_block[2]),
        .I2(\xsdb_reg[1]_i_2_n_0 ),
        .I3(data_out_en),
        .I4(\xsdb_reg_reg[1] ),
        .O(\input_data_reg[65]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[0]_i_2 
       (.I0(input_data[48]),
        .I1(input_data[32]),
        .I2(curr_read_block[1]),
        .I3(input_data[16]),
        .I4(curr_read_block[0]),
        .I5(input_data[0]),
        .O(\xsdb_reg[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[10]_i_1 
       (.I0(input_data[58]),
        .I1(input_data[42]),
        .I2(curr_read_block[1]),
        .I3(input_data[26]),
        .I4(curr_read_block[0]),
        .I5(input_data[10]),
        .O(\input_data_reg[58]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[11]_i_1 
       (.I0(input_data[59]),
        .I1(input_data[43]),
        .I2(curr_read_block[1]),
        .I3(input_data[27]),
        .I4(curr_read_block[0]),
        .I5(input_data[11]),
        .O(\input_data_reg[59]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[12]_i_1 
       (.I0(input_data[60]),
        .I1(input_data[44]),
        .I2(curr_read_block[1]),
        .I3(input_data[28]),
        .I4(curr_read_block[0]),
        .I5(input_data[12]),
        .O(\input_data_reg[60]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[13]_i_1 
       (.I0(input_data[61]),
        .I1(input_data[45]),
        .I2(curr_read_block[1]),
        .I3(input_data[29]),
        .I4(curr_read_block[0]),
        .I5(input_data[13]),
        .O(\input_data_reg[61]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[14]_i_1 
       (.I0(input_data[62]),
        .I1(input_data[46]),
        .I2(curr_read_block[1]),
        .I3(input_data[30]),
        .I4(curr_read_block[0]),
        .I5(input_data[14]),
        .O(\input_data_reg[62]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[15]_i_2__5 
       (.I0(input_data[63]),
        .I1(input_data[47]),
        .I2(curr_read_block[1]),
        .I3(input_data[31]),
        .I4(curr_read_block[0]),
        .I5(input_data[15]),
        .O(\input_data_reg[63]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[1]_i_2 
       (.I0(input_data[49]),
        .I1(input_data[33]),
        .I2(curr_read_block[1]),
        .I3(input_data[17]),
        .I4(curr_read_block[0]),
        .I5(input_data[1]),
        .O(\xsdb_reg[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[2]_i_1 
       (.I0(input_data[50]),
        .I1(input_data[34]),
        .I2(curr_read_block[1]),
        .I3(input_data[18]),
        .I4(curr_read_block[0]),
        .I5(input_data[2]),
        .O(\input_data_reg[50]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[3]_i_1 
       (.I0(input_data[51]),
        .I1(input_data[35]),
        .I2(curr_read_block[1]),
        .I3(input_data[19]),
        .I4(curr_read_block[0]),
        .I5(input_data[3]),
        .O(\input_data_reg[51]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[4]_i_1 
       (.I0(input_data[52]),
        .I1(input_data[36]),
        .I2(curr_read_block[1]),
        .I3(input_data[20]),
        .I4(curr_read_block[0]),
        .I5(input_data[4]),
        .O(\input_data_reg[52]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[5]_i_1 
       (.I0(input_data[53]),
        .I1(input_data[37]),
        .I2(curr_read_block[1]),
        .I3(input_data[21]),
        .I4(curr_read_block[0]),
        .I5(input_data[5]),
        .O(\input_data_reg[53]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[6]_i_1 
       (.I0(input_data[54]),
        .I1(input_data[38]),
        .I2(curr_read_block[1]),
        .I3(input_data[22]),
        .I4(curr_read_block[0]),
        .I5(input_data[6]),
        .O(\input_data_reg[54]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[7]_i_1 
       (.I0(input_data[55]),
        .I1(input_data[39]),
        .I2(curr_read_block[1]),
        .I3(input_data[23]),
        .I4(curr_read_block[0]),
        .I5(input_data[7]),
        .O(\input_data_reg[55]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[8]_i_1 
       (.I0(input_data[56]),
        .I1(input_data[40]),
        .I2(curr_read_block[1]),
        .I3(input_data[24]),
        .I4(curr_read_block[0]),
        .I5(input_data[8]),
        .O(\input_data_reg[56]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \xsdb_reg[9]_i_1 
       (.I0(input_data[57]),
        .I1(input_data[41]),
        .I2(curr_read_block[1]),
        .I3(input_data[25]),
        .I4(curr_read_block[0]),
        .I5(input_data[9]),
        .O(\input_data_reg[57]_0 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_223 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_0
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_219 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_1
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_215 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_10
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_179 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_11
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_175 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_12
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_171 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_13
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_167 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_14
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_163 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_15
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_159 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_16
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_155 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_17
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_151 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_18
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_147 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_19
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_143 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_2
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_211 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_20
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_139 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_21
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_135 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_22
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_131 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_23
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_127 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_24
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_123 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_25
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_119 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_26
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_115 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_27
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_111 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_28
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_107 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_29
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_103 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_3
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_207 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_30
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_99 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_31
   (Q,
    shift_en_reg,
    \yes_output_reg.dout_reg_reg_0 ,
    qual_strg_config_cs_serial_output,
    \parallel_dout_reg[15] ,
    out,
    D,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [11:0]Q;
  output [0:0]shift_en_reg;
  output \yes_output_reg.dout_reg_reg_0 ;
  input qual_strg_config_cs_serial_output;
  input [0:0]\parallel_dout_reg[15] ;
  input [0:0]out;
  input [11:0]D;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]\parallel_dout_reg[15] ;
  wire qual_strg_config_cs_serial_output;
  wire [0:0]shift_en_reg;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0  = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
        .qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
        .shift_en_reg(shift_en_reg));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_4
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_203 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_5
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_199 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_6
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_195 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_7
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_191 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_8
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_187 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_9
   (tc_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]tc_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input [0:0]out;
  input [11:0]D;
  input [11:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [11:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [11:0]Q;
  wire match_dout;
  wire [0:0]out;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_183 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .out(out),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0
   (D,
    Q,
    mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \probeDelay1_reg[15] ,
    \probeDelay1_reg[16] ,
    probe0);
  output [20:0]D;
  output [20:0]Q;
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input [15:0]\probeDelay1_reg[15] ;
  input \probeDelay1_reg[16] ;
  input [4:0]probe0;

  wire [20:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [20:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [4:0]probe0;
  wire [15:0]\probeDelay1_reg[15] ;
  wire \probeDelay1_reg[16] ;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0_92 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .probe0(probe0),
        .\probeDelay1_reg[15]_0 (\probeDelay1_reg[15] ),
        .\probeDelay1_reg[16]_0 (\probeDelay1_reg[16] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0_33
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [20:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [20:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0_77 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0_34
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [20:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [20:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0_72 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0_35
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [20:0]D;
  input [20:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [20:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [20:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_87 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_32
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_82 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_36
   (D,
    Q,
    mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \probeDelay1_reg[0] ,
    probe1);
  output [21:0]D;
  output [21:0]Q;
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \probeDelay1_reg[0] ;
  input [21:0]probe1;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [21:0]probe1;
  wire \probeDelay1_reg[0] ;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_63 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .probe1(probe1),
        .\probeDelay1_reg[0]_0 (\probeDelay1_reg[0] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_37
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_58 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_38
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_53 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_39
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_48 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_40
   (D,
    Q,
    mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ,
    \probeDelay1_reg[0] ,
    probe2);
  output [21:0]D;
  output [21:0]Q;
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  input \probeDelay1_reg[0] ;
  input [21:0]probe2;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  wire [21:0]probe2;
  wire \probeDelay1_reg[0] ;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1_43 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out),
        .probe2(probe2),
        .\probeDelay1_reg[0]_0 (\probeDelay1_reg[0] ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1_41
   (mu_config_cs_serial_input,
    \yes_output_reg.dout_reg_reg_0 ,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    out,
    D,
    Q,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ,
    \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 );
  output [0:0]mu_config_cs_serial_input;
  output [0:0]\yes_output_reg.dout_reg_reg_0 ;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input [0:0]out;
  input [21:0]D;
  input [21:0]Q;
  input [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  input \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;

  wire [21:0]D;
  wire [0:0]\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ;
  wire \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ;
  wire [21:0]Q;
  wire match_dout;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]out;
  (* async_reg = "true" *) wire \yes_output_reg.dout_reg ;

  assign \yes_output_reg.dout_reg_reg_0 [0] = \yes_output_reg.dout_reg ;
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.D(D),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg (match_dout),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ),
        .\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_1 (\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .Q(Q),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .out(out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \yes_output_reg.dout_reg_reg 
       (.C(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg_0 ),
        .CE(1'b1),
        .D(match_dout),
        .Q(\yes_output_reg.dout_reg ),
        .R(\I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay
   (shift_en_reg,
    shift_en_reg_0,
    E,
    out,
    PROBES_I,
    SRL_D_I);
  output shift_en_reg;
  output shift_en_reg_0;
  input [0:0]E;
  input [0:0]out;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire [0:0]E;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire [0:0]out;
  wire shift_en_reg;
  wire shift_en_reg_0;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_254 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.E(E),
        .PROBES_I(PROBES_I),
        .SRL_D_I(SRL_D_I),
        .out(out),
        .shift_en_reg(shift_en_reg),
        .shift_en_reg_0(shift_en_reg_0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match_nodelay" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_253
   (\probeDelay1_reg[9] ,
    shift_en_reg,
    SRL_Q_O,
    E,
    out,
    Q,
    SRL_D_I,
    \probeDelay1_reg[0] );
  output [9:0]\probeDelay1_reg[9] ;
  output shift_en_reg;
  output SRL_Q_O;
  input [0:0]E;
  input [0:0]out;
  input [9:0]Q;
  input SRL_D_I;
  input \probeDelay1_reg[0] ;

  wire [0:0]E;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [0:0]out;
  wire \probeDelay1_reg[0] ;
  wire [9:0]\probeDelay1_reg[9] ;
  wire shift_en_reg;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.E(E),
        .Q(Q),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .out(out),
        .\probeDelay1_reg[0]_0 (\probeDelay1_reg[0] ),
        .\probeDelay1_reg[9]_0 (\probeDelay1_reg[9] ),
        .shift_en_reg(shift_en_reg));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_match_nodelay" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_261
   (DOUT_O,
    SRL_Q_O,
    \iwcnt_reg[0] ,
    out,
    Q,
    SRL_D_I,
    \probeDelay1_reg[9] );
  output DOUT_O;
  output SRL_Q_O;
  input [0:0]\iwcnt_reg[0] ;
  input [0:0]out;
  input [9:0]Q;
  input SRL_D_I;
  input \probeDelay1_reg[9] ;

  wire DOUT_O;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [0:0]\iwcnt_reg[0] ;
  wire [0:0]out;
  wire \probeDelay1_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_262 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst 
       (.DOUT_O(DOUT_O),
        .Q(Q),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .\iwcnt_reg[0] (\iwcnt_reg[0] ),
        .out(out),
        .\probeDelay1_reg[9]_0 (\probeDelay1_reg[9] ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection
   (last_din,
    D,
    \dout_pulse_reg[1]_0 ,
    out,
    last_din_reg_0,
    Q,
    \dout_pulse_reg[0]_0 );
  output last_din;
  output [0:0]D;
  output [0:0]\dout_pulse_reg[1]_0 ;
  input out;
  input last_din_reg_0;
  input [0:0]Q;
  input [0:0]\dout_pulse_reg[0]_0 ;

  wire [0:0]D;
  wire [0:0]Q;
  wire \dout_pulse[1]_i_1__0_n_0 ;
  wire [0:0]\dout_pulse_reg[0]_0 ;
  wire [0:0]\dout_pulse_reg[1]_0 ;
  wire last_din;
  wire last_din_reg_0;
  wire out;
  wire [1:1]p_0_in;

  LUT3 #(
    .INIT(8'hF4)) 
    \dout_pulse[1]_i_1__0 
       (.I0(last_din),
        .I1(out),
        .I2(p_0_in),
        .O(\dout_pulse[1]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \dout_pulse_reg[0] 
       (.C(last_din_reg_0),
        .CE(1'b1),
        .D(\dout_pulse_reg[0]_0 ),
        .Q(p_0_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \dout_pulse_reg[1] 
       (.C(last_din_reg_0),
        .CE(1'b1),
        .D(\dout_pulse[1]_i_1__0_n_0 ),
        .Q(\dout_pulse_reg[1]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    last_din_reg
       (.C(last_din_reg_0),
        .CE(1'b1),
        .D(out),
        .Q(last_din),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \reset_out[0]_i_1 
       (.I0(Q),
        .I1(\dout_pulse_reg[1]_0 ),
        .O(D));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_0_rising_edge_detection" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection_230
   (last_din,
    halt_out_reg,
    SS,
    out,
    last_din_reg_0,
    halt_out,
    Q,
    halt_out_reg_0,
    prev_cap_done,
    cap_done,
    D);
  output last_din;
  output halt_out_reg;
  output [0:0]SS;
  input out;
  input last_din_reg_0;
  input halt_out;
  input [0:0]Q;
  input [0:0]halt_out_reg_0;
  input prev_cap_done;
  input cap_done;
  input [0:0]D;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SS;
  wire cap_done;
  wire \dout_pulse[1]_i_1_n_0 ;
  wire halt_in_detection;
  wire halt_out;
  wire halt_out_reg;
  wire [0:0]halt_out_reg_0;
  wire last_din;
  wire last_din_reg_0;
  wire out;
  wire [1:1]p_0_in;
  wire prev_cap_done;

  LUT3 #(
    .INIT(8'hF4)) 
    \dout_pulse[1]_i_1 
       (.I0(last_din),
        .I1(out),
        .I2(p_0_in),
        .O(\dout_pulse[1]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \dout_pulse_reg[0] 
       (.C(last_din_reg_0),
        .CE(1'b1),
        .D(D),
        .Q(p_0_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \dout_pulse_reg[1] 
       (.C(last_din_reg_0),
        .CE(1'b1),
        .D(\dout_pulse[1]_i_1_n_0 ),
        .Q(halt_in_detection),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00AE)) 
    halt_out_i_1
       (.I0(halt_out),
        .I1(halt_in_detection),
        .I2(Q),
        .I3(halt_out_reg_0),
        .O(halt_out_reg));
  FDRE #(
    .INIT(1'b0)) 
    last_din_reg
       (.C(last_din_reg_0),
        .CE(1'b1),
        .D(out),
        .Q(last_din),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hBA)) 
    \reset_out[5]_i_1 
       (.I0(halt_in_detection),
        .I1(prev_cap_done),
        .I2(cap_done),
        .O(SS));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized24
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[9] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
    \xsdb_reg_reg[5] ,
    s_daddr_o,
    \slaveRegDo_mux_0[15]_i_3 ,
    \slaveRegDo_mux_0[9]_i_3 ,
    \slaveRegDo_mux_0[3]_i_7 ,
    \slaveRegDo_mux_0[2]_i_6 ,
    \slaveRegDo_mux_0[6]_i_7 ,
    \slaveRegDo_mux_0[0]_i_6 ,
    \slaveRegDo_mux_0[14]_i_3 ,
    \slaveRegDo_mux_0[13]_i_3 ,
    \slaveRegDo_mux_0[12]_i_3 ,
    \slaveRegDo_mux_0[11]_i_3 ,
    \slaveRegDo_mux_0[5]_i_3 ,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0] );
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output [4:0]\xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[9] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  output \xsdb_reg_reg[5] ;
  input [8:0]s_daddr_o;
  input \slaveRegDo_mux_0[15]_i_3 ;
  input \slaveRegDo_mux_0[9]_i_3 ;
  input \slaveRegDo_mux_0[3]_i_7 ;
  input \slaveRegDo_mux_0[2]_i_6 ;
  input \slaveRegDo_mux_0[6]_i_7 ;
  input \slaveRegDo_mux_0[0]_i_6 ;
  input \slaveRegDo_mux_0[14]_i_3 ;
  input \slaveRegDo_mux_0[13]_i_3 ;
  input \slaveRegDo_mux_0[12]_i_3 ;
  input \slaveRegDo_mux_0[11]_i_3 ;
  input \slaveRegDo_mux_0[5]_i_3 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0] ;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  wire [8:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[0]_i_6 ;
  wire \slaveRegDo_mux_0[11]_i_3 ;
  wire \slaveRegDo_mux_0[12]_i_3 ;
  wire \slaveRegDo_mux_0[13]_i_3 ;
  wire \slaveRegDo_mux_0[14]_i_3 ;
  wire \slaveRegDo_mux_0[15]_i_3 ;
  wire \slaveRegDo_mux_0[2]_i_6 ;
  wire \slaveRegDo_mux_0[3]_i_7 ;
  wire \slaveRegDo_mux_0[5]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_7 ;
  wire \slaveRegDo_mux_0[9]_i_3 ;
  wire \xsdb_reg_reg[0] ;
  wire [4:0]\xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_242 \I_EN_CTL_EQ1.U_CTL 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\slaveRegDo_mux_0[0]_i_6 (\slaveRegDo_mux_0[0]_i_6 ),
        .\slaveRegDo_mux_0[11]_i_3 (\slaveRegDo_mux_0[11]_i_3 ),
        .\slaveRegDo_mux_0[12]_i_3 (\slaveRegDo_mux_0[12]_i_3 ),
        .\slaveRegDo_mux_0[13]_i_3 (\slaveRegDo_mux_0[13]_i_3 ),
        .\slaveRegDo_mux_0[14]_i_3 (\slaveRegDo_mux_0[14]_i_3 ),
        .\slaveRegDo_mux_0[15]_i_3 (\slaveRegDo_mux_0[15]_i_3 ),
        .\slaveRegDo_mux_0[2]_i_6 (\slaveRegDo_mux_0[2]_i_6 ),
        .\slaveRegDo_mux_0[3]_i_7 (\slaveRegDo_mux_0[3]_i_7 ),
        .\slaveRegDo_mux_0[5]_i_3 (\slaveRegDo_mux_0[5]_i_3 ),
        .\slaveRegDo_mux_0[6]_i_7 (\slaveRegDo_mux_0[6]_i_7 ),
        .\slaveRegDo_mux_0[9]_i_3 (\slaveRegDo_mux_0[9]_i_3 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized25
   (\xsdb_reg_reg[4] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[8] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    halt_ctrl,
    \xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[0] ,
    scnt_cmp_temp,
    wcnt_lcmp_temp,
    wcnt_hcmp_temp,
    \xsdb_reg_reg[0]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 ,
    \slaveRegDo_mux_0[10]_i_3 ,
    Q,
    \slaveRegDo_mux_0[1]_i_2 ,
    \slaveRegDo_mux_0[1]_i_2_0 ,
    s_di_o,
    s_dclk_o,
    DOUT_O,
    u_wcnt_lcmp_q,
    u_wcnt_hcmp_q);
  output \xsdb_reg_reg[4] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[8] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output halt_ctrl;
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[2] ;
  output \xsdb_reg_reg[0] ;
  output scnt_cmp_temp;
  output wcnt_lcmp_temp;
  output wcnt_hcmp_temp;
  input \xsdb_reg_reg[0]_0 ;
  input [3:0]s_daddr_o;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;
  input [4:0]\slaveRegDo_mux_0[10]_i_3 ;
  input [0:0]Q;
  input [0:0]\slaveRegDo_mux_0[1]_i_2 ;
  input \slaveRegDo_mux_0[1]_i_2_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input DOUT_O;
  input u_wcnt_lcmp_q;
  input u_wcnt_hcmp_q;

  wire DOUT_O;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire [0:0]Q;
  wire halt_ctrl;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire scnt_cmp_temp;
  wire [4:0]\slaveRegDo_mux_0[10]_i_3 ;
  wire [0:0]\slaveRegDo_mux_0[1]_i_2 ;
  wire \slaveRegDo_mux_0[1]_i_2_0 ;
  wire u_wcnt_hcmp_q;
  wire u_wcnt_lcmp_q;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp_temp;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized0 \I_EN_CTL_EQ1.U_CTL 
       (.DOUT_O(DOUT_O),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
        .Q(Q),
        .halt_ctrl(halt_ctrl),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .scnt_cmp_temp(scnt_cmp_temp),
        .\slaveRegDo_mux_0[10]_i_3 (\slaveRegDo_mux_0[10]_i_3 ),
        .\slaveRegDo_mux_0[1]_i_2 (\slaveRegDo_mux_0[1]_i_2 ),
        .\slaveRegDo_mux_0[1]_i_2_0 (\slaveRegDo_mux_0[1]_i_2_0 ),
        .u_wcnt_hcmp_q(u_wcnt_hcmp_q),
        .u_wcnt_lcmp_q(u_wcnt_lcmp_q),
        .wcnt_hcmp_temp(wcnt_hcmp_temp),
        .wcnt_lcmp_temp(wcnt_lcmp_temp),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 ),
        .\xsdb_reg_reg[0]_3 (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized26
   (\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \xsdb_reg_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ,
    \xsdb_reg_reg[1] ,
    s_daddr_o,
    Q,
    \slaveRegDo_mux_0[0]_i_2 ,
    \slaveRegDo_mux_0[3]_i_3 ,
    \slaveRegDo_mux_0[2]_i_2 ,
    \slaveRegDo_mux_0[6]_i_3 ,
    \slaveRegDo_mux_0[0]_i_2_0 ,
    s_den_o,
    D,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \xsdb_reg_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  output [0:0]\xsdb_reg_reg[1] ;
  input [1:0]s_daddr_o;
  input [3:0]Q;
  input \slaveRegDo_mux_0[0]_i_2 ;
  input \slaveRegDo_mux_0[3]_i_3 ;
  input \slaveRegDo_mux_0[2]_i_2 ;
  input \slaveRegDo_mux_0[6]_i_3 ;
  input \slaveRegDo_mux_0[0]_i_2_0 ;
  input s_den_o;
  input [4:0]D;
  input s_dclk_o;

  wire [4:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  wire [3:0]Q;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire \slaveRegDo_mux_0[0]_i_2 ;
  wire \slaveRegDo_mux_0[0]_i_2_0 ;
  wire \slaveRegDo_mux_0[2]_i_2 ;
  wire \slaveRegDo_mux_0[3]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_3 ;
  wire [0:0]\xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[2] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_241 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .\slaveRegDo_mux_0[0]_i_2 (\slaveRegDo_mux_0[0]_i_2 ),
        .\slaveRegDo_mux_0[0]_i_2_0 (\slaveRegDo_mux_0[0]_i_2_0 ),
        .\slaveRegDo_mux_0[2]_i_2 (\slaveRegDo_mux_0[2]_i_2 ),
        .\slaveRegDo_mux_0[3]_i_3 (\slaveRegDo_mux_0[3]_i_3 ),
        .\slaveRegDo_mux_0[6]_i_3 (\slaveRegDo_mux_0[6]_i_3 ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized27
   (Q,
    s_den_o,
    \xsdb_reg_reg[9] ,
    s_dclk_o);
  output [9:0]Q;
  input s_den_o;
  input [9:0]\xsdb_reg_reg[9] ;
  input s_dclk_o;

  wire [9:0]Q;
  wire s_dclk_o;
  wire s_den_o;
  wire [9:0]\xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_231 \I_EN_STAT_EQ1.U_STAT 
       (.Q(Q),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized39
   (\xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    \xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[3] ,
    in0,
    \xsdb_reg_reg[1] ,
    SR,
    \slaveRegDo_mux_0[4]_i_2 ,
    s_daddr_o,
    read_reset_addr,
    \slaveRegDo_mux_0[9]_i_3 ,
    \xsdb_reg_reg[0] ,
    \xsdb_reg_reg[0]_0 ,
    \slaveRegDo_mux_0_reg[9] ,
    \slaveRegDo_mux_0_reg[9]_0 ,
    \slaveRegDo_mux_0_reg[9]_1 ,
    \slaveRegDo_mux_0_reg[9]_2 ,
    Q,
    \slaveRegDo_mux_0[8]_i_3 ,
    \slaveRegDo_mux_0[7]_i_3 ,
    \slaveRegDo_mux_0[5]_i_3 ,
    \slaveRegDo_mux_0[4]_i_2_0 ,
    s_di_o,
    s_dclk_o);
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[4] ;
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[3] ;
  output in0;
  output \xsdb_reg_reg[1] ;
  output [0:0]SR;
  input \slaveRegDo_mux_0[4]_i_2 ;
  input [4:0]s_daddr_o;
  input [4:0]read_reset_addr;
  input \slaveRegDo_mux_0[9]_i_3 ;
  input \xsdb_reg_reg[0] ;
  input \xsdb_reg_reg[0]_0 ;
  input \slaveRegDo_mux_0_reg[9] ;
  input \slaveRegDo_mux_0_reg[9]_0 ;
  input \slaveRegDo_mux_0_reg[9]_1 ;
  input \slaveRegDo_mux_0_reg[9]_2 ;
  input [0:0]Q;
  input \slaveRegDo_mux_0[8]_i_3 ;
  input \slaveRegDo_mux_0[7]_i_3 ;
  input \slaveRegDo_mux_0[5]_i_3 ;
  input \slaveRegDo_mux_0[4]_i_2_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [0:0]Q;
  wire [0:0]SR;
  wire in0;
  wire [4:0]read_reset_addr;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[4]_i_2 ;
  wire \slaveRegDo_mux_0[4]_i_2_0 ;
  wire \slaveRegDo_mux_0[5]_i_3 ;
  wire \slaveRegDo_mux_0[7]_i_3 ;
  wire \slaveRegDo_mux_0[8]_i_3 ;
  wire \slaveRegDo_mux_0[9]_i_3 ;
  wire \slaveRegDo_mux_0_reg[9] ;
  wire \slaveRegDo_mux_0_reg[9]_0 ;
  wire \slaveRegDo_mux_0_reg[9]_1 ;
  wire \slaveRegDo_mux_0_reg[9]_2 ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_247 \I_EN_CTL_EQ1.U_CTL 
       (.Q(Q),
        .SR(SR),
        .in0(in0),
        .read_reset_addr(read_reset_addr),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\slaveRegDo_mux_0[4]_i_2 (\slaveRegDo_mux_0[4]_i_2 ),
        .\slaveRegDo_mux_0[4]_i_2_0 (\slaveRegDo_mux_0[4]_i_2_0 ),
        .\slaveRegDo_mux_0[5]_i_3 (\slaveRegDo_mux_0[5]_i_3 ),
        .\slaveRegDo_mux_0[7]_i_3 (\slaveRegDo_mux_0[7]_i_3 ),
        .\slaveRegDo_mux_0[8]_i_3 (\slaveRegDo_mux_0[8]_i_3 ),
        .\slaveRegDo_mux_0[9]_i_3_0 (\slaveRegDo_mux_0[9]_i_3 ),
        .\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
        .\slaveRegDo_mux_0_reg[9]_0 (\slaveRegDo_mux_0_reg[9]_0 ),
        .\slaveRegDo_mux_0_reg[9]_1 (\slaveRegDo_mux_0_reg[9]_1 ),
        .\slaveRegDo_mux_0_reg[9]_2 (\slaveRegDo_mux_0_reg[9]_2 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized40
   (\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[12] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[6] ,
    \xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[10] ,
    read_reset_addr,
    s_dwe_o,
    s_den_o,
    s_daddr_o,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[10] ;
  output [9:0]read_reset_addr;
  input s_dwe_o;
  input s_den_o;
  input [12:0]s_daddr_o;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  wire [9:0]read_reset_addr;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_246 \I_EN_CTL_EQ1.U_CTL 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[6] (\G_1PIPE_IFACE.s_daddr_r_reg[6] ),
        .read_reset_addr(read_reset_addr),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_di_o(s_di_o),
        .s_dwe_o(s_dwe_o),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized41
   (D,
    \G_1PIPE_IFACE.s_daddr_r_reg[7] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    \slaveRegDo_mux_0_reg[2] ,
    \slaveRegDo_mux_0_reg[1] ,
    \slaveRegDo_mux_0_reg[2]_0 ,
    \slaveRegDo_mux_0_reg[1]_0 ,
    \slaveRegDo_mux_0_reg[15] ,
    \slaveRegDo_mux_0_reg[0] ,
    \slaveRegDo_mux_0_reg[1]_1 ,
    \slaveRegDo_mux_0_reg[1]_2 ,
    \slaveRegDo_mux_0_reg[15]_0 ,
    s_dwe_o,
    s_den_o,
    \xsdb_reg_reg[0] ,
    \slaveRegDo_mux_0_reg[3] ,
    \slaveRegDo_mux_0_reg[1]_3 ,
    \slaveRegDo_mux_0_reg[3]_0 ,
    \slaveRegDo_mux_0_reg[2]_1 ,
    \slaveRegDo_mux_0_reg[2]_2 ,
    \slaveRegDo_mux_0_reg[15]_1 ,
    \slaveRegDo_mux_0_reg[15]_2 ,
    \slaveRegDo_mux_0_reg[14] ,
    \slaveRegDo_mux_0_reg[14]_0 ,
    \slaveRegDo_mux_0_reg[13] ,
    \slaveRegDo_mux_0_reg[13]_0 ,
    \slaveRegDo_mux_0_reg[12] ,
    \slaveRegDo_mux_0_reg[12]_0 ,
    \slaveRegDo_mux_0_reg[11] ,
    \slaveRegDo_mux_0_reg[11]_0 ,
    \slaveRegDo_mux_0_reg[0]_0 ,
    \slaveRegDo_mux_0_reg[0]_1 ,
    \slaveRegDo_mux_0_reg[1]_4 ,
    \slaveRegDo_mux_0_reg[1]_5 ,
    \slaveRegDo_mux_0[15]_i_3 ,
    \slaveRegDo_mux_0[15]_i_3_0 ,
    \slaveRegDo_mux_0[14]_i_3 ,
    \slaveRegDo_mux_0[14]_i_3_0 ,
    \slaveRegDo_mux_0[13]_i_3 ,
    \slaveRegDo_mux_0[13]_i_3_0 ,
    \slaveRegDo_mux_0[12]_i_3 ,
    \slaveRegDo_mux_0[12]_i_3_0 ,
    \slaveRegDo_mux_0[11]_i_3 ,
    \slaveRegDo_mux_0[11]_i_3_0 ,
    \slaveRegDo_mux_0[10]_i_3 ,
    \slaveRegDo_mux_0[10]_i_3_0 ,
    read_reset_addr,
    \slaveRegDo_mux_0[6]_i_3 ,
    \slaveRegDo_mux_0[3]_i_3 ,
    in0,
    \slaveRegDo_mux_0[1]_i_2 ,
    SR,
    s_di_o,
    s_dclk_o);
  output [2:0]D;
  output \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  output \xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[4] ;
  input \slaveRegDo_mux_0_reg[2] ;
  input \slaveRegDo_mux_0_reg[1] ;
  input \slaveRegDo_mux_0_reg[2]_0 ;
  input \slaveRegDo_mux_0_reg[1]_0 ;
  input [7:0]\slaveRegDo_mux_0_reg[15] ;
  input \slaveRegDo_mux_0_reg[0] ;
  input [1:0]\slaveRegDo_mux_0_reg[1]_1 ;
  input \slaveRegDo_mux_0_reg[1]_2 ;
  input \slaveRegDo_mux_0_reg[15]_0 ;
  input s_dwe_o;
  input s_den_o;
  input \xsdb_reg_reg[0] ;
  input \slaveRegDo_mux_0_reg[3] ;
  input \slaveRegDo_mux_0_reg[1]_3 ;
  input \slaveRegDo_mux_0_reg[3]_0 ;
  input \slaveRegDo_mux_0_reg[2]_1 ;
  input \slaveRegDo_mux_0_reg[2]_2 ;
  input \slaveRegDo_mux_0_reg[15]_1 ;
  input \slaveRegDo_mux_0_reg[15]_2 ;
  input \slaveRegDo_mux_0_reg[14] ;
  input \slaveRegDo_mux_0_reg[14]_0 ;
  input \slaveRegDo_mux_0_reg[13] ;
  input \slaveRegDo_mux_0_reg[13]_0 ;
  input \slaveRegDo_mux_0_reg[12] ;
  input \slaveRegDo_mux_0_reg[12]_0 ;
  input \slaveRegDo_mux_0_reg[11] ;
  input \slaveRegDo_mux_0_reg[11]_0 ;
  input \slaveRegDo_mux_0_reg[0]_0 ;
  input \slaveRegDo_mux_0_reg[0]_1 ;
  input \slaveRegDo_mux_0_reg[1]_4 ;
  input \slaveRegDo_mux_0_reg[1]_5 ;
  input \slaveRegDo_mux_0[15]_i_3 ;
  input \slaveRegDo_mux_0[15]_i_3_0 ;
  input \slaveRegDo_mux_0[14]_i_3 ;
  input \slaveRegDo_mux_0[14]_i_3_0 ;
  input \slaveRegDo_mux_0[13]_i_3 ;
  input \slaveRegDo_mux_0[13]_i_3_0 ;
  input \slaveRegDo_mux_0[12]_i_3 ;
  input \slaveRegDo_mux_0[12]_i_3_0 ;
  input \slaveRegDo_mux_0[11]_i_3 ;
  input \slaveRegDo_mux_0[11]_i_3_0 ;
  input \slaveRegDo_mux_0[10]_i_3 ;
  input \slaveRegDo_mux_0[10]_i_3_0 ;
  input [4:0]read_reset_addr;
  input \slaveRegDo_mux_0[6]_i_3 ;
  input \slaveRegDo_mux_0[3]_i_3 ;
  input in0;
  input \slaveRegDo_mux_0[1]_i_2 ;
  input [0:0]SR;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [2:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  wire [0:0]SR;
  wire in0;
  wire [4:0]read_reset_addr;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \slaveRegDo_mux_0[10]_i_3 ;
  wire \slaveRegDo_mux_0[10]_i_3_0 ;
  wire \slaveRegDo_mux_0[11]_i_3 ;
  wire \slaveRegDo_mux_0[11]_i_3_0 ;
  wire \slaveRegDo_mux_0[12]_i_3 ;
  wire \slaveRegDo_mux_0[12]_i_3_0 ;
  wire \slaveRegDo_mux_0[13]_i_3 ;
  wire \slaveRegDo_mux_0[13]_i_3_0 ;
  wire \slaveRegDo_mux_0[14]_i_3 ;
  wire \slaveRegDo_mux_0[14]_i_3_0 ;
  wire \slaveRegDo_mux_0[15]_i_3 ;
  wire \slaveRegDo_mux_0[15]_i_3_0 ;
  wire \slaveRegDo_mux_0[1]_i_2 ;
  wire \slaveRegDo_mux_0[3]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_3 ;
  wire \slaveRegDo_mux_0_reg[0] ;
  wire \slaveRegDo_mux_0_reg[0]_0 ;
  wire \slaveRegDo_mux_0_reg[0]_1 ;
  wire \slaveRegDo_mux_0_reg[11] ;
  wire \slaveRegDo_mux_0_reg[11]_0 ;
  wire \slaveRegDo_mux_0_reg[12] ;
  wire \slaveRegDo_mux_0_reg[12]_0 ;
  wire \slaveRegDo_mux_0_reg[13] ;
  wire \slaveRegDo_mux_0_reg[13]_0 ;
  wire \slaveRegDo_mux_0_reg[14] ;
  wire \slaveRegDo_mux_0_reg[14]_0 ;
  wire [7:0]\slaveRegDo_mux_0_reg[15] ;
  wire \slaveRegDo_mux_0_reg[15]_0 ;
  wire \slaveRegDo_mux_0_reg[15]_1 ;
  wire \slaveRegDo_mux_0_reg[15]_2 ;
  wire \slaveRegDo_mux_0_reg[1] ;
  wire \slaveRegDo_mux_0_reg[1]_0 ;
  wire [1:0]\slaveRegDo_mux_0_reg[1]_1 ;
  wire \slaveRegDo_mux_0_reg[1]_2 ;
  wire \slaveRegDo_mux_0_reg[1]_3 ;
  wire \slaveRegDo_mux_0_reg[1]_4 ;
  wire \slaveRegDo_mux_0_reg[1]_5 ;
  wire \slaveRegDo_mux_0_reg[2] ;
  wire \slaveRegDo_mux_0_reg[2]_0 ;
  wire \slaveRegDo_mux_0_reg[2]_1 ;
  wire \slaveRegDo_mux_0_reg[2]_2 ;
  wire \slaveRegDo_mux_0_reg[3] ;
  wire \slaveRegDo_mux_0_reg[3]_0 ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_245 \I_EN_CTL_EQ1.U_CTL 
       (.D(D),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
        .SR(SR),
        .in0(in0),
        .read_reset_addr(read_reset_addr),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_di_o(s_di_o),
        .s_dwe_o(s_dwe_o),
        .\slaveRegDo_mux_0[10]_i_3 (\slaveRegDo_mux_0[10]_i_3 ),
        .\slaveRegDo_mux_0[10]_i_3_0 (\slaveRegDo_mux_0[10]_i_3_0 ),
        .\slaveRegDo_mux_0[11]_i_3_0 (\slaveRegDo_mux_0[11]_i_3 ),
        .\slaveRegDo_mux_0[11]_i_3_1 (\slaveRegDo_mux_0[11]_i_3_0 ),
        .\slaveRegDo_mux_0[12]_i_3_0 (\slaveRegDo_mux_0[12]_i_3 ),
        .\slaveRegDo_mux_0[12]_i_3_1 (\slaveRegDo_mux_0[12]_i_3_0 ),
        .\slaveRegDo_mux_0[13]_i_3_0 (\slaveRegDo_mux_0[13]_i_3 ),
        .\slaveRegDo_mux_0[13]_i_3_1 (\slaveRegDo_mux_0[13]_i_3_0 ),
        .\slaveRegDo_mux_0[14]_i_3_0 (\slaveRegDo_mux_0[14]_i_3 ),
        .\slaveRegDo_mux_0[14]_i_3_1 (\slaveRegDo_mux_0[14]_i_3_0 ),
        .\slaveRegDo_mux_0[15]_i_3_0 (\slaveRegDo_mux_0[15]_i_3 ),
        .\slaveRegDo_mux_0[15]_i_3_1 (\slaveRegDo_mux_0[15]_i_3_0 ),
        .\slaveRegDo_mux_0[1]_i_2_0 (\slaveRegDo_mux_0[1]_i_2 ),
        .\slaveRegDo_mux_0[3]_i_3_0 (\slaveRegDo_mux_0[3]_i_3 ),
        .\slaveRegDo_mux_0[6]_i_3 (\slaveRegDo_mux_0[6]_i_3 ),
        .\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
        .\slaveRegDo_mux_0_reg[0]_0 (\slaveRegDo_mux_0_reg[0]_0 ),
        .\slaveRegDo_mux_0_reg[0]_1 (\slaveRegDo_mux_0_reg[0]_1 ),
        .\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
        .\slaveRegDo_mux_0_reg[11]_0 (\slaveRegDo_mux_0_reg[11]_0 ),
        .\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
        .\slaveRegDo_mux_0_reg[12]_0 (\slaveRegDo_mux_0_reg[12]_0 ),
        .\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
        .\slaveRegDo_mux_0_reg[13]_0 (\slaveRegDo_mux_0_reg[13]_0 ),
        .\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
        .\slaveRegDo_mux_0_reg[14]_0 (\slaveRegDo_mux_0_reg[14]_0 ),
        .\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
        .\slaveRegDo_mux_0_reg[15]_0 (\slaveRegDo_mux_0_reg[15]_0 ),
        .\slaveRegDo_mux_0_reg[15]_1 (\slaveRegDo_mux_0_reg[15]_1 ),
        .\slaveRegDo_mux_0_reg[15]_2 (\slaveRegDo_mux_0_reg[15]_2 ),
        .\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
        .\slaveRegDo_mux_0_reg[1]_0 (\slaveRegDo_mux_0_reg[1]_0 ),
        .\slaveRegDo_mux_0_reg[1]_1 (\slaveRegDo_mux_0_reg[1]_1 ),
        .\slaveRegDo_mux_0_reg[1]_2 (\slaveRegDo_mux_0_reg[1]_2 ),
        .\slaveRegDo_mux_0_reg[1]_3 (\slaveRegDo_mux_0_reg[1]_3 ),
        .\slaveRegDo_mux_0_reg[1]_4 (\slaveRegDo_mux_0_reg[1]_4 ),
        .\slaveRegDo_mux_0_reg[1]_5 (\slaveRegDo_mux_0_reg[1]_5 ),
        .\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
        .\slaveRegDo_mux_0_reg[2]_0 (\slaveRegDo_mux_0_reg[2]_0 ),
        .\slaveRegDo_mux_0_reg[2]_1 (\slaveRegDo_mux_0_reg[2]_1 ),
        .\slaveRegDo_mux_0_reg[2]_2 (\slaveRegDo_mux_0_reg[2]_2 ),
        .\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
        .\slaveRegDo_mux_0_reg[3]_0 (\slaveRegDo_mux_0_reg[3]_0 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized42
   (\xsdb_reg_reg[15] ,
    D,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[5] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[6] ,
    \xsdb_reg_reg[9] ,
    \slaveRegDo_mux_0[4]_i_2 ,
    s_daddr_o,
    \slaveRegDo_mux_0[8]_i_3 ,
    \slaveRegDo_mux_0[8]_i_3_0 ,
    \slaveRegDo_mux_0[7]_i_3 ,
    \slaveRegDo_mux_0[7]_i_3_0 ,
    \slaveRegDo_mux_0[5]_i_3 ,
    \slaveRegDo_mux_0[5]_i_3_0 ,
    \slaveRegDo_mux_0[4]_i_2_0 ,
    \slaveRegDo_mux_0[4]_i_2_1 ,
    \slaveRegDo_mux_0_reg[4] ,
    \slaveRegDo_mux_0_reg[4]_0 ,
    \slaveRegDo_mux_0_reg[4]_1 ,
    \slaveRegDo_mux_0_reg[4]_2 ,
    \slaveRegDo_mux_0_reg[4]_3 ,
    \slaveRegDo_mux_0_reg[5] ,
    \slaveRegDo_mux_0_reg[4]_4 ,
    \slaveRegDo_mux_0_reg[5]_0 ,
    Q,
    \slaveRegDo_mux_0_reg[7] ,
    \slaveRegDo_mux_0_reg[7]_0 ,
    \slaveRegDo_mux_0_reg[8] ,
    \slaveRegDo_mux_0_reg[8]_0 ,
    \slaveRegDo_mux_0_reg[5]_1 ,
    \slaveRegDo_mux_0_reg[5]_2 ,
    \slaveRegDo_mux_0[9]_i_3 ,
    \slaveRegDo_mux_0[9]_i_3_0 ,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0] );
  output [10:0]\xsdb_reg_reg[15] ;
  output [0:0]D;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[5] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  output \xsdb_reg_reg[9] ;
  input \slaveRegDo_mux_0[4]_i_2 ;
  input [7:0]s_daddr_o;
  input \slaveRegDo_mux_0[8]_i_3 ;
  input \slaveRegDo_mux_0[8]_i_3_0 ;
  input \slaveRegDo_mux_0[7]_i_3 ;
  input \slaveRegDo_mux_0[7]_i_3_0 ;
  input \slaveRegDo_mux_0[5]_i_3 ;
  input \slaveRegDo_mux_0[5]_i_3_0 ;
  input \slaveRegDo_mux_0[4]_i_2_0 ;
  input \slaveRegDo_mux_0[4]_i_2_1 ;
  input \slaveRegDo_mux_0_reg[4] ;
  input \slaveRegDo_mux_0_reg[4]_0 ;
  input \slaveRegDo_mux_0_reg[4]_1 ;
  input \slaveRegDo_mux_0_reg[4]_2 ;
  input \slaveRegDo_mux_0_reg[4]_3 ;
  input \slaveRegDo_mux_0_reg[5] ;
  input \slaveRegDo_mux_0_reg[4]_4 ;
  input \slaveRegDo_mux_0_reg[5]_0 ;
  input [3:0]Q;
  input \slaveRegDo_mux_0_reg[7] ;
  input \slaveRegDo_mux_0_reg[7]_0 ;
  input \slaveRegDo_mux_0_reg[8] ;
  input \slaveRegDo_mux_0_reg[8]_0 ;
  input \slaveRegDo_mux_0_reg[5]_1 ;
  input \slaveRegDo_mux_0_reg[5]_2 ;
  input \slaveRegDo_mux_0[9]_i_3 ;
  input \slaveRegDo_mux_0[9]_i_3_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0] ;

  wire [0:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  wire [3:0]Q;
  wire [7:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[4]_i_2 ;
  wire \slaveRegDo_mux_0[4]_i_2_0 ;
  wire \slaveRegDo_mux_0[4]_i_2_1 ;
  wire \slaveRegDo_mux_0[5]_i_3 ;
  wire \slaveRegDo_mux_0[5]_i_3_0 ;
  wire \slaveRegDo_mux_0[7]_i_3 ;
  wire \slaveRegDo_mux_0[7]_i_3_0 ;
  wire \slaveRegDo_mux_0[8]_i_3 ;
  wire \slaveRegDo_mux_0[8]_i_3_0 ;
  wire \slaveRegDo_mux_0[9]_i_3 ;
  wire \slaveRegDo_mux_0[9]_i_3_0 ;
  wire \slaveRegDo_mux_0_reg[4] ;
  wire \slaveRegDo_mux_0_reg[4]_0 ;
  wire \slaveRegDo_mux_0_reg[4]_1 ;
  wire \slaveRegDo_mux_0_reg[4]_2 ;
  wire \slaveRegDo_mux_0_reg[4]_3 ;
  wire \slaveRegDo_mux_0_reg[4]_4 ;
  wire \slaveRegDo_mux_0_reg[5] ;
  wire \slaveRegDo_mux_0_reg[5]_0 ;
  wire \slaveRegDo_mux_0_reg[5]_1 ;
  wire \slaveRegDo_mux_0_reg[5]_2 ;
  wire \slaveRegDo_mux_0_reg[7] ;
  wire \slaveRegDo_mux_0_reg[7]_0 ;
  wire \slaveRegDo_mux_0_reg[8] ;
  wire \slaveRegDo_mux_0_reg[8]_0 ;
  wire \xsdb_reg_reg[0] ;
  wire [10:0]\xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_244 \I_EN_CTL_EQ1.U_CTL 
       (.D(D),
        .\G_1PIPE_IFACE.s_daddr_r_reg[6] (\G_1PIPE_IFACE.s_daddr_r_reg[6] ),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\slaveRegDo_mux_0[4]_i_2_0 (\slaveRegDo_mux_0[4]_i_2 ),
        .\slaveRegDo_mux_0[4]_i_2_1 (\slaveRegDo_mux_0[4]_i_2_0 ),
        .\slaveRegDo_mux_0[4]_i_2_2 (\slaveRegDo_mux_0[4]_i_2_1 ),
        .\slaveRegDo_mux_0[5]_i_3_0 (\slaveRegDo_mux_0[5]_i_3 ),
        .\slaveRegDo_mux_0[5]_i_3_1 (\slaveRegDo_mux_0[5]_i_3_0 ),
        .\slaveRegDo_mux_0[7]_i_3_0 (\slaveRegDo_mux_0[7]_i_3 ),
        .\slaveRegDo_mux_0[7]_i_3_1 (\slaveRegDo_mux_0[7]_i_3_0 ),
        .\slaveRegDo_mux_0[8]_i_3_0 (\slaveRegDo_mux_0[8]_i_3 ),
        .\slaveRegDo_mux_0[8]_i_3_1 (\slaveRegDo_mux_0[8]_i_3_0 ),
        .\slaveRegDo_mux_0[9]_i_3 (\slaveRegDo_mux_0[9]_i_3 ),
        .\slaveRegDo_mux_0[9]_i_3_0 (\slaveRegDo_mux_0[9]_i_3_0 ),
        .\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
        .\slaveRegDo_mux_0_reg[4]_0 (\slaveRegDo_mux_0_reg[4]_0 ),
        .\slaveRegDo_mux_0_reg[4]_1 (\slaveRegDo_mux_0_reg[4]_1 ),
        .\slaveRegDo_mux_0_reg[4]_2 (\slaveRegDo_mux_0_reg[4]_2 ),
        .\slaveRegDo_mux_0_reg[4]_3 (\slaveRegDo_mux_0_reg[4]_3 ),
        .\slaveRegDo_mux_0_reg[4]_4 (\slaveRegDo_mux_0_reg[4]_4 ),
        .\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
        .\slaveRegDo_mux_0_reg[5]_0 (\slaveRegDo_mux_0_reg[5]_0 ),
        .\slaveRegDo_mux_0_reg[5]_1 (\slaveRegDo_mux_0_reg[5]_1 ),
        .\slaveRegDo_mux_0_reg[5]_2 (\slaveRegDo_mux_0_reg[5]_2 ),
        .\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
        .\slaveRegDo_mux_0_reg[7]_0 (\slaveRegDo_mux_0_reg[7]_0 ),
        .\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
        .\slaveRegDo_mux_0_reg[8]_0 (\slaveRegDo_mux_0_reg[8]_0 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized43
   (\xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    s_daddr_o,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 ,
    s_di_o,
    s_dclk_o);
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[4] ;
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[2] ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_243 \I_EN_CTL_EQ1.U_CTL 
       (.s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 ),
        .\xsdb_reg_reg[0]_3 (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized44
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
    \xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    s_daddr_o,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 ,
    \slaveRegDo_mux_0_reg[6] ,
    \slaveRegDo_mux_0_reg[10] ,
    \slaveRegDo_mux_0_reg[6]_0 ,
    \slaveRegDo_mux_0_reg[10]_0 ,
    \slaveRegDo_mux_0_reg[10]_1 ,
    \slaveRegDo_mux_0[15]_i_3 ,
    \slaveRegDo_mux_0[15]_i_3_0 ,
    \slaveRegDo_mux_0[14]_i_3 ,
    \slaveRegDo_mux_0[13]_i_3 ,
    \slaveRegDo_mux_0[12]_i_3 ,
    \slaveRegDo_mux_0[11]_i_3 ,
    \slaveRegDo_mux_0[10]_i_3 ,
    \slaveRegDo_mux_0[6]_i_3 ,
    \slaveRegDo_mux_0[3]_i_3 ,
    \slaveRegDo_mux_0[2]_i_2 ,
    \slaveRegDo_mux_0[1]_i_2 ,
    \slaveRegDo_mux_0[0]_i_2 ,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[2] ;
  output [1:0]\xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[4] ;
  input [4:0]s_daddr_o;
  input \xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;
  input \slaveRegDo_mux_0_reg[6] ;
  input \slaveRegDo_mux_0_reg[10] ;
  input \slaveRegDo_mux_0_reg[6]_0 ;
  input \slaveRegDo_mux_0_reg[10]_0 ;
  input \slaveRegDo_mux_0_reg[10]_1 ;
  input \slaveRegDo_mux_0[15]_i_3 ;
  input [10:0]\slaveRegDo_mux_0[15]_i_3_0 ;
  input \slaveRegDo_mux_0[14]_i_3 ;
  input \slaveRegDo_mux_0[13]_i_3 ;
  input \slaveRegDo_mux_0[12]_i_3 ;
  input \slaveRegDo_mux_0[11]_i_3 ;
  input \slaveRegDo_mux_0[10]_i_3 ;
  input \slaveRegDo_mux_0[6]_i_3 ;
  input \slaveRegDo_mux_0[3]_i_3 ;
  input \slaveRegDo_mux_0[2]_i_2 ;
  input \slaveRegDo_mux_0[1]_i_2 ;
  input \slaveRegDo_mux_0[0]_i_2 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[0]_i_2 ;
  wire \slaveRegDo_mux_0[10]_i_3 ;
  wire \slaveRegDo_mux_0[11]_i_3 ;
  wire \slaveRegDo_mux_0[12]_i_3 ;
  wire \slaveRegDo_mux_0[13]_i_3 ;
  wire \slaveRegDo_mux_0[14]_i_3 ;
  wire \slaveRegDo_mux_0[15]_i_3 ;
  wire [10:0]\slaveRegDo_mux_0[15]_i_3_0 ;
  wire \slaveRegDo_mux_0[1]_i_2 ;
  wire \slaveRegDo_mux_0[2]_i_2 ;
  wire \slaveRegDo_mux_0[3]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_3 ;
  wire \slaveRegDo_mux_0_reg[10] ;
  wire \slaveRegDo_mux_0_reg[10]_0 ;
  wire \slaveRegDo_mux_0_reg[10]_1 ;
  wire \slaveRegDo_mux_0_reg[6] ;
  wire \slaveRegDo_mux_0_reg[6]_0 ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[2] ;
  wire [1:0]\xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized1 \I_EN_CTL_EQ1.U_CTL 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\slaveRegDo_mux_0[0]_i_2 (\slaveRegDo_mux_0[0]_i_2 ),
        .\slaveRegDo_mux_0[10]_i_3_0 (\slaveRegDo_mux_0[10]_i_3 ),
        .\slaveRegDo_mux_0[11]_i_3 (\slaveRegDo_mux_0[11]_i_3 ),
        .\slaveRegDo_mux_0[12]_i_3 (\slaveRegDo_mux_0[12]_i_3 ),
        .\slaveRegDo_mux_0[13]_i_3 (\slaveRegDo_mux_0[13]_i_3 ),
        .\slaveRegDo_mux_0[14]_i_3 (\slaveRegDo_mux_0[14]_i_3 ),
        .\slaveRegDo_mux_0[15]_i_3 (\slaveRegDo_mux_0[15]_i_3 ),
        .\slaveRegDo_mux_0[15]_i_3_0 (\slaveRegDo_mux_0[15]_i_3_0 ),
        .\slaveRegDo_mux_0[1]_i_2 (\slaveRegDo_mux_0[1]_i_2 ),
        .\slaveRegDo_mux_0[2]_i_2 (\slaveRegDo_mux_0[2]_i_2 ),
        .\slaveRegDo_mux_0[3]_i_3 (\slaveRegDo_mux_0[3]_i_3 ),
        .\slaveRegDo_mux_0[6]_i_3_0 (\slaveRegDo_mux_0[6]_i_3 ),
        .\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
        .\slaveRegDo_mux_0_reg[10]_0 (\slaveRegDo_mux_0_reg[10]_0 ),
        .\slaveRegDo_mux_0_reg[10]_1 (\slaveRegDo_mux_0_reg[10]_1 ),
        .\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
        .\slaveRegDo_mux_0_reg[6]_0 (\slaveRegDo_mux_0_reg[6]_0 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 ),
        .\xsdb_reg_reg[0]_3 (\xsdb_reg_reg[0]_2 ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[2]_1 (\xsdb_reg_reg[2]_0 ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized45
   (slaveRegDo_80,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0] ,
    s_daddr_o,
    \xsdb_reg_reg[0]_0 );
  output [15:0]slaveRegDo_80;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0] ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_0 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_80;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2_240 \I_EN_CTL_EQ1.U_CTL 
       (.s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .slaveRegDo_80(slaveRegDo_80),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized46
   (slaveRegDo_81,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0] ,
    s_daddr_o,
    \xsdb_reg_reg[0]_0 );
  output [15:0]slaveRegDo_81;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0] ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_0 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_81;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_239 \I_EN_CTL_EQ1.U_CTL 
       (.s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .slaveRegDo_81(slaveRegDo_81),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized47
   (slaveRegDo_82,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0] ,
    s_daddr_o,
    \xsdb_reg_reg[0]_0 );
  output [15:0]slaveRegDo_82;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0] ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_0 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_82;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2 \I_EN_CTL_EQ1.U_CTL 
       (.s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .slaveRegDo_82(slaveRegDo_82),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized48
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[4] ,
    \xsdb_reg_reg[15] ,
    s_daddr_o,
    \slaveRegDo_mux_0_reg[7] ,
    \slaveRegDo_mux_0_reg[8] ,
    \slaveRegDo_mux_0_reg[9] ,
    \slaveRegDo_mux_0_reg[4] ,
    \slaveRegDo_mux_0_reg[0] ,
    \slaveRegDo_mux_0_reg[1] ,
    \slaveRegDo_mux_0_reg[2] ,
    \slaveRegDo_mux_0_reg[3] ,
    \slaveRegDo_mux_0_reg[4]_0 ,
    \slaveRegDo_mux_0_reg[5] ,
    \slaveRegDo_mux_0_reg[6] ,
    \slaveRegDo_mux_0_reg[10] ,
    \slaveRegDo_mux_0_reg[11] ,
    \slaveRegDo_mux_0_reg[12] ,
    \slaveRegDo_mux_0_reg[13] ,
    \slaveRegDo_mux_0_reg[14] ,
    \xsdb_reg_reg[0] ,
    s_den_o,
    s_dwe_o,
    \slaveRegDo_mux_0_reg[15] ,
    slaveRegDo_84,
    \slaveRegDo_mux_0_reg[3]_0 ,
    \slaveRegDo_mux_0_reg[5]_0 ,
    \slaveRegDo_mux_0_reg[6]_0 ,
    \slaveRegDo_mux_0_reg[7]_0 ,
    \slaveRegDo_mux_0_reg[8]_0 ,
    \slaveRegDo_mux_0_reg[9]_0 ,
    \slaveRegDo_mux_0_reg[10]_0 ,
    \slaveRegDo_mux_0_reg[11]_0 ,
    \slaveRegDo_mux_0_reg[12]_0 ,
    \slaveRegDo_mux_0_reg[13]_0 ,
    \slaveRegDo_mux_0_reg[14]_0 ,
    \slaveRegDo_mux_0_reg[15]_0 ,
    slaveRegDo_82,
    slaveRegDo_81,
    slaveRegDo_80,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  output \xsdb_reg_reg[15] ;
  input [6:0]s_daddr_o;
  input \slaveRegDo_mux_0_reg[7] ;
  input \slaveRegDo_mux_0_reg[8] ;
  input \slaveRegDo_mux_0_reg[9] ;
  input \slaveRegDo_mux_0_reg[4] ;
  input \slaveRegDo_mux_0_reg[0] ;
  input \slaveRegDo_mux_0_reg[1] ;
  input \slaveRegDo_mux_0_reg[2] ;
  input \slaveRegDo_mux_0_reg[3] ;
  input \slaveRegDo_mux_0_reg[4]_0 ;
  input \slaveRegDo_mux_0_reg[5] ;
  input \slaveRegDo_mux_0_reg[6] ;
  input \slaveRegDo_mux_0_reg[10] ;
  input \slaveRegDo_mux_0_reg[11] ;
  input \slaveRegDo_mux_0_reg[12] ;
  input \slaveRegDo_mux_0_reg[13] ;
  input \slaveRegDo_mux_0_reg[14] ;
  input \xsdb_reg_reg[0] ;
  input s_den_o;
  input s_dwe_o;
  input \slaveRegDo_mux_0_reg[15] ;
  input [11:0]slaveRegDo_84;
  input \slaveRegDo_mux_0_reg[3]_0 ;
  input \slaveRegDo_mux_0_reg[5]_0 ;
  input \slaveRegDo_mux_0_reg[6]_0 ;
  input \slaveRegDo_mux_0_reg[7]_0 ;
  input \slaveRegDo_mux_0_reg[8]_0 ;
  input \slaveRegDo_mux_0_reg[9]_0 ;
  input \slaveRegDo_mux_0_reg[10]_0 ;
  input \slaveRegDo_mux_0_reg[11]_0 ;
  input \slaveRegDo_mux_0_reg[12]_0 ;
  input \slaveRegDo_mux_0_reg[13]_0 ;
  input \slaveRegDo_mux_0_reg[14]_0 ;
  input \slaveRegDo_mux_0_reg[15]_0 ;
  input [15:0]slaveRegDo_82;
  input [15:0]slaveRegDo_81;
  input [15:0]slaveRegDo_80;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  wire [6:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire [15:0]slaveRegDo_80;
  wire [15:0]slaveRegDo_81;
  wire [15:0]slaveRegDo_82;
  wire [11:0]slaveRegDo_84;
  wire \slaveRegDo_mux_0_reg[0] ;
  wire \slaveRegDo_mux_0_reg[10] ;
  wire \slaveRegDo_mux_0_reg[10]_0 ;
  wire \slaveRegDo_mux_0_reg[11] ;
  wire \slaveRegDo_mux_0_reg[11]_0 ;
  wire \slaveRegDo_mux_0_reg[12] ;
  wire \slaveRegDo_mux_0_reg[12]_0 ;
  wire \slaveRegDo_mux_0_reg[13] ;
  wire \slaveRegDo_mux_0_reg[13]_0 ;
  wire \slaveRegDo_mux_0_reg[14] ;
  wire \slaveRegDo_mux_0_reg[14]_0 ;
  wire \slaveRegDo_mux_0_reg[15] ;
  wire \slaveRegDo_mux_0_reg[15]_0 ;
  wire \slaveRegDo_mux_0_reg[1] ;
  wire \slaveRegDo_mux_0_reg[2] ;
  wire \slaveRegDo_mux_0_reg[3] ;
  wire \slaveRegDo_mux_0_reg[3]_0 ;
  wire \slaveRegDo_mux_0_reg[4] ;
  wire \slaveRegDo_mux_0_reg[4]_0 ;
  wire \slaveRegDo_mux_0_reg[5] ;
  wire \slaveRegDo_mux_0_reg[5]_0 ;
  wire \slaveRegDo_mux_0_reg[6] ;
  wire \slaveRegDo_mux_0_reg[6]_0 ;
  wire \slaveRegDo_mux_0_reg[7] ;
  wire \slaveRegDo_mux_0_reg[7]_0 ;
  wire \slaveRegDo_mux_0_reg[8] ;
  wire \slaveRegDo_mux_0_reg[8]_0 ;
  wire \slaveRegDo_mux_0_reg[9] ;
  wire \slaveRegDo_mux_0_reg[9]_0 ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[15] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_238 \I_EN_CTL_EQ1.U_CTL 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_di_o(s_di_o),
        .s_dwe_o(s_dwe_o),
        .slaveRegDo_80(slaveRegDo_80),
        .slaveRegDo_81(slaveRegDo_81),
        .slaveRegDo_82(slaveRegDo_82),
        .slaveRegDo_84(slaveRegDo_84),
        .\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
        .\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
        .\slaveRegDo_mux_0_reg[10]_0 (\slaveRegDo_mux_0_reg[10]_0 ),
        .\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
        .\slaveRegDo_mux_0_reg[11]_0 (\slaveRegDo_mux_0_reg[11]_0 ),
        .\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
        .\slaveRegDo_mux_0_reg[12]_0 (\slaveRegDo_mux_0_reg[12]_0 ),
        .\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
        .\slaveRegDo_mux_0_reg[13]_0 (\slaveRegDo_mux_0_reg[13]_0 ),
        .\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
        .\slaveRegDo_mux_0_reg[14]_0 (\slaveRegDo_mux_0_reg[14]_0 ),
        .\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
        .\slaveRegDo_mux_0_reg[15]_0 (\slaveRegDo_mux_0_reg[15]_0 ),
        .\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
        .\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
        .\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
        .\slaveRegDo_mux_0_reg[3]_0 (\slaveRegDo_mux_0_reg[3]_0 ),
        .\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
        .\slaveRegDo_mux_0_reg[4]_0 (\slaveRegDo_mux_0_reg[4]_0 ),
        .\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
        .\slaveRegDo_mux_0_reg[5]_0 (\slaveRegDo_mux_0_reg[5]_0 ),
        .\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
        .\slaveRegDo_mux_0_reg[6]_0 (\slaveRegDo_mux_0_reg[6]_0 ),
        .\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
        .\slaveRegDo_mux_0_reg[7]_0 (\slaveRegDo_mux_0_reg[7]_0 ),
        .\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
        .\slaveRegDo_mux_0_reg[8]_0 (\slaveRegDo_mux_0_reg[8]_0 ),
        .\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
        .\slaveRegDo_mux_0_reg[9]_0 (\slaveRegDo_mux_0_reg[9]_0 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized49
   (\xsdb_reg_reg[4] ,
    \xsdb_reg_reg[15] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    s_daddr_o,
    \slaveRegDo_mux_0[4]_i_4 ,
    \slaveRegDo_mux_0[2]_i_3 ,
    \slaveRegDo_mux_0[1]_i_3 ,
    \slaveRegDo_mux_0[0]_i_3 ,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[0]_1 );
  output \xsdb_reg_reg[4] ;
  output [11:0]\xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[2] ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  input [2:0]s_daddr_o;
  input \slaveRegDo_mux_0[4]_i_4 ;
  input \slaveRegDo_mux_0[2]_i_3 ;
  input \slaveRegDo_mux_0[1]_i_3 ;
  input \slaveRegDo_mux_0[0]_i_3 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[0]_1 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[0]_i_3 ;
  wire \slaveRegDo_mux_0[1]_i_3 ;
  wire \slaveRegDo_mux_0[2]_i_3 ;
  wire \slaveRegDo_mux_0[4]_i_4 ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire [11:0]\xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[4] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_237 \I_EN_CTL_EQ1.U_CTL 
       (.s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\slaveRegDo_mux_0[0]_i_3 (\slaveRegDo_mux_0[0]_i_3 ),
        .\slaveRegDo_mux_0[1]_i_3 (\slaveRegDo_mux_0[1]_i_3 ),
        .\slaveRegDo_mux_0[2]_i_3 (\slaveRegDo_mux_0[2]_i_3 ),
        .\slaveRegDo_mux_0[4]_i_4 (\slaveRegDo_mux_0[4]_i_4 ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized50
   (\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[0] ,
    \xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    s_daddr_o,
    s_den_o,
    s_dwe_o,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[4] ;
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[2] ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  input [12:0]s_daddr_o;
  input s_den_o;
  input s_dwe_o;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_236 \I_EN_CTL_EQ1.U_CTL 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_di_o(s_di_o),
        .s_dwe_o(s_dwe_o),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized52
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    s_den_o,
    out,
    s_dclk_o,
    \slaveRegDo_mux_2_reg[3] ,
    s_daddr_o,
    s_do_o,
    \slaveRegDo_mux_2_reg[3]_0 ,
    \slaveRegDo_mux_2_reg[3]_1 );
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  input s_den_o;
  input out;
  input s_dclk_o;
  input \slaveRegDo_mux_2_reg[3] ;
  input [4:0]s_daddr_o;
  input [0:0]s_do_o;
  input \slaveRegDo_mux_2_reg[3]_0 ;
  input \slaveRegDo_mux_2_reg[3]_1 ;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire out;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [0:0]s_do_o;
  wire \slaveRegDo_mux_2_reg[3] ;
  wire \slaveRegDo_mux_2_reg[3]_0 ;
  wire \slaveRegDo_mux_2_reg[3]_1 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_235 \I_EN_STAT_EQ1.U_STAT 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
        .out(out),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_do_o(s_do_o),
        .\slaveRegDo_mux_2_reg[3] (\slaveRegDo_mux_2_reg[3] ),
        .\slaveRegDo_mux_2_reg[3]_0 (\slaveRegDo_mux_2_reg[3]_0 ),
        .\slaveRegDo_mux_2_reg[3]_1 (\slaveRegDo_mux_2_reg[3]_1 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized54
   (D,
    \slaveRegDo_mux_2_reg[1] ,
    \slaveRegDo_mux_2_reg[1]_0 ,
    s_do_o,
    \slaveRegDo_mux_2_reg[0] ,
    \slaveRegDo_mux_2_reg[0]_0 ,
    \slaveRegDo_mux_2_reg[0]_1 ,
    \slaveRegDo_mux_2_reg[0]_2 ,
    \slaveRegDo_mux_2_reg[0]_3 ,
    \slaveRegDo_mux_2_reg[0]_4 ,
    s_daddr_o,
    \slaveRegDo_mux_2_reg[1]_1 ,
    \slaveRegDo_mux_2_reg[1]_2 ,
    \slaveRegDo_mux_2_reg[1]_3 ,
    s_den_o,
    \xsdb_reg_reg[1] ,
    s_dclk_o);
  output [1:0]D;
  input \slaveRegDo_mux_2_reg[1] ;
  input [0:0]\slaveRegDo_mux_2_reg[1]_0 ;
  input [1:0]s_do_o;
  input \slaveRegDo_mux_2_reg[0] ;
  input \slaveRegDo_mux_2_reg[0]_0 ;
  input \slaveRegDo_mux_2_reg[0]_1 ;
  input \slaveRegDo_mux_2_reg[0]_2 ;
  input \slaveRegDo_mux_2_reg[0]_3 ;
  input \slaveRegDo_mux_2_reg[0]_4 ;
  input [1:0]s_daddr_o;
  input \slaveRegDo_mux_2_reg[1]_1 ;
  input \slaveRegDo_mux_2_reg[1]_2 ;
  input \slaveRegDo_mux_2_reg[1]_3 ;
  input s_den_o;
  input [1:0]\xsdb_reg_reg[1] ;
  input s_dclk_o;

  wire [1:0]D;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [1:0]s_do_o;
  wire \slaveRegDo_mux_2_reg[0] ;
  wire \slaveRegDo_mux_2_reg[0]_0 ;
  wire \slaveRegDo_mux_2_reg[0]_1 ;
  wire \slaveRegDo_mux_2_reg[0]_2 ;
  wire \slaveRegDo_mux_2_reg[0]_3 ;
  wire \slaveRegDo_mux_2_reg[0]_4 ;
  wire \slaveRegDo_mux_2_reg[1] ;
  wire [0:0]\slaveRegDo_mux_2_reg[1]_0 ;
  wire \slaveRegDo_mux_2_reg[1]_1 ;
  wire \slaveRegDo_mux_2_reg[1]_2 ;
  wire \slaveRegDo_mux_2_reg[1]_3 ;
  wire [1:0]\xsdb_reg_reg[1] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_234 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_do_o(s_do_o),
        .\slaveRegDo_mux_2_reg[0] (\slaveRegDo_mux_2_reg[0] ),
        .\slaveRegDo_mux_2_reg[0]_0 (\slaveRegDo_mux_2_reg[0]_0 ),
        .\slaveRegDo_mux_2_reg[0]_1 (\slaveRegDo_mux_2_reg[0]_1 ),
        .\slaveRegDo_mux_2_reg[0]_2 (\slaveRegDo_mux_2_reg[0]_2 ),
        .\slaveRegDo_mux_2_reg[0]_3 (\slaveRegDo_mux_2_reg[0]_3 ),
        .\slaveRegDo_mux_2_reg[0]_4 (\slaveRegDo_mux_2_reg[0]_4 ),
        .\slaveRegDo_mux_2_reg[1] (\slaveRegDo_mux_2_reg[1] ),
        .\slaveRegDo_mux_2_reg[1]_0 (\slaveRegDo_mux_2_reg[1]_0 ),
        .\slaveRegDo_mux_2_reg[1]_1 (\slaveRegDo_mux_2_reg[1]_1 ),
        .\slaveRegDo_mux_2_reg[1]_2 (\slaveRegDo_mux_2_reg[1]_2 ),
        .\slaveRegDo_mux_2_reg[1]_3 (\slaveRegDo_mux_2_reg[1]_3 ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized55
   (\xsdb_reg_reg[3] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    \xsdb_reg_reg[3]_0 ,
    s_den_o,
    flag3_temp,
    s_dclk_o,
    flag2_temp,
    flag1_temp,
    flag0_temp);
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[2] ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  input \xsdb_reg_reg[3]_0 ;
  input s_den_o;
  input flag3_temp;
  input s_dclk_o;
  input flag2_temp;
  input flag1_temp;
  input flag0_temp;

  wire flag0_temp;
  wire flag1_temp;
  wire flag2_temp;
  wire flag3_temp;
  wire s_dclk_o;
  wire s_den_o;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[3]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_232 \I_EN_STAT_EQ1.U_STAT 
       (.flag0_temp(flag0_temp),
        .flag1_temp(flag1_temp),
        .flag2_temp(flag2_temp),
        .flag3_temp(flag3_temp),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized56
   (\xsdb_reg_reg[5] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[13] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[4] ,
    \G_1PIPE_IFACE.s_den_r_reg ,
    D,
    \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    \slaveRegDo_mux_2_reg[15] ,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_2_reg[15]_0 ,
    \slaveRegDo_mux_2_reg[5] ,
    s_den_o,
    \xsdb_reg_reg[15] ,
    \slaveRegDo_mux_2_reg[4] ,
    \slaveRegDo_mux_2_reg[4]_0 ,
    \slaveRegDo_mux_2_reg[2] ,
    \slaveRegDo_mux_2_reg[4]_1 ,
    \slaveRegDo_mux_2_reg[4]_2 ,
    \slaveRegDo_mux_2_reg[2]_0 ,
    \slaveRegDo_mux_2_reg[2]_1 ,
    SEQUENCER_STATE_O,
    s_dclk_o);
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[13] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  output \G_1PIPE_IFACE.s_den_r_reg ;
  output [1:0]D;
  output \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  input \slaveRegDo_mux_2_reg[15] ;
  input [12:0]s_do_o;
  input [3:0]s_daddr_o;
  input \slaveRegDo_mux_2_reg[15]_0 ;
  input \slaveRegDo_mux_2_reg[5] ;
  input s_den_o;
  input \xsdb_reg_reg[15] ;
  input \slaveRegDo_mux_2_reg[4] ;
  input \slaveRegDo_mux_2_reg[4]_0 ;
  input \slaveRegDo_mux_2_reg[2] ;
  input \slaveRegDo_mux_2_reg[4]_1 ;
  input \slaveRegDo_mux_2_reg[4]_2 ;
  input \slaveRegDo_mux_2_reg[2]_0 ;
  input \slaveRegDo_mux_2_reg[2]_1 ;
  input [15:0]SEQUENCER_STATE_O;
  input s_dclk_o;

  wire [1:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
  wire \G_1PIPE_IFACE.s_den_r_reg ;
  wire [15:0]SEQUENCER_STATE_O;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [12:0]s_do_o;
  wire \slaveRegDo_mux_2_reg[15] ;
  wire \slaveRegDo_mux_2_reg[15]_0 ;
  wire \slaveRegDo_mux_2_reg[2] ;
  wire \slaveRegDo_mux_2_reg[2]_0 ;
  wire \slaveRegDo_mux_2_reg[2]_1 ;
  wire \slaveRegDo_mux_2_reg[4] ;
  wire \slaveRegDo_mux_2_reg[4]_0 ;
  wire \slaveRegDo_mux_2_reg[4]_1 ;
  wire \slaveRegDo_mux_2_reg[4]_2 ;
  wire \slaveRegDo_mux_2_reg[5] ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_233 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
        .\G_1PIPE_IFACE.s_den_r_reg (\G_1PIPE_IFACE.s_den_r_reg ),
        .SEQUENCER_STATE_O(SEQUENCER_STATE_O),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_den_o(s_den_o),
        .s_do_o(s_do_o),
        .\slaveRegDo_mux_2_reg[15] (\slaveRegDo_mux_2_reg[15] ),
        .\slaveRegDo_mux_2_reg[15]_0 (\slaveRegDo_mux_2_reg[15]_0 ),
        .\slaveRegDo_mux_2_reg[2] (\slaveRegDo_mux_2_reg[2] ),
        .\slaveRegDo_mux_2_reg[2]_0 (\slaveRegDo_mux_2_reg[2]_0 ),
        .\slaveRegDo_mux_2_reg[2]_1 (\slaveRegDo_mux_2_reg[2]_1 ),
        .\slaveRegDo_mux_2_reg[4] (\slaveRegDo_mux_2_reg[4] ),
        .\slaveRegDo_mux_2_reg[4]_0 (\slaveRegDo_mux_2_reg[4]_0 ),
        .\slaveRegDo_mux_2_reg[4]_1 (\slaveRegDo_mux_2_reg[4]_1 ),
        .\slaveRegDo_mux_2_reg[4]_2 (\slaveRegDo_mux_2_reg[4]_2 ),
        .\slaveRegDo_mux_2_reg[5] (\slaveRegDo_mux_2_reg[5] ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* C_ADDR_W = "13" *) (* C_CTLRST_VAL = "47'b00000000000000000000000000000000000000000000000" *) (* C_DATA_W = "16" *) 
(* C_EN_CTL = "0" *) (* C_EN_STAT = "1" *) (* C_REG_ADDR = "13'b0100010010000" *) 
(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized57
   (s_do_o,
    dout_o,
    rst_reg_i,
    din_i,
    s_daddr_i,
    s_di_i,
    s_den_i,
    s_dwe_i,
    s_dclk_i);
  output [15:0]s_do_o;
  output [15:0]dout_o;
  input rst_reg_i;
  input [15:0]din_i;
  input [12:0]s_daddr_i;
  input [15:0]s_di_i;
  input s_den_i;
  input s_dwe_i;
  input s_dclk_i;

  wire \<const0> ;
  wire [15:0]din_i;
  wire s_dclk_i;
  wire s_den_i;
  wire [15:0]s_do_o;

  assign dout_o[15] = \<const0> ;
  assign dout_o[14] = \<const0> ;
  assign dout_o[13] = \<const0> ;
  assign dout_o[12] = \<const0> ;
  assign dout_o[11] = \<const0> ;
  assign dout_o[10] = \<const0> ;
  assign dout_o[9] = \<const0> ;
  assign dout_o[8] = \<const0> ;
  assign dout_o[7] = \<const0> ;
  assign dout_o[6] = \<const0> ;
  assign dout_o[5] = \<const0> ;
  assign dout_o[4] = \<const0> ;
  assign dout_o[3] = \<const0> ;
  assign dout_o[2] = \<const0> ;
  assign dout_o[1] = \<const0> ;
  assign dout_o[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_250 \I_EN_STAT_EQ1.U_STAT 
       (.din_i(din_i),
        .s_dclk_i(s_dclk_i),
        .s_den_i(s_den_i),
        .s_do_o(s_do_o));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl
   (\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[6] ,
    \xsdb_reg_reg[15]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_0 ,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  output [15:0]\xsdb_reg_reg[15]_0 ;
  input [12:0]s_daddr_o;
  input \xsdb_reg_reg[0]_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \xsdb_reg[15]_i_1__6_n_0 ;
  wire \xsdb_reg[15]_i_2__4_n_0 ;
  wire \xsdb_reg[15]_i_3__0_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire [15:0]\xsdb_reg_reg[15]_0 ;

  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    drdy_ff9_i_2
       (.I0(s_daddr_o[6]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[9]),
        .I4(s_daddr_o[5]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[6] ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \xsdb_reg[15]_i_1__6 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[12]),
        .I2(\xsdb_reg[15]_i_2__4_n_0 ),
        .I3(\xsdb_reg_reg[0]_0 ),
        .I4(\xsdb_reg[15]_i_3__0_n_0 ),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
        .O(\xsdb_reg[15]_i_1__6_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \xsdb_reg[15]_i_2__4 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[11]),
        .O(\xsdb_reg[15]_i_2__4_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \xsdb_reg[15]_i_3__0 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .O(\xsdb_reg[15]_i_3__0_n_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \xsdb_reg[15]_i_4 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[6] ),
        .I1(s_daddr_o[10]),
        .I2(s_daddr_o[8]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[10] ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg[15]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[15]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[15]_0 [11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[15]_0 [12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[15]_0 [13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[15]_0 [14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 [15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[15]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[15]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[15]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[15]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[15]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[15]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[15]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[15]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__6_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[15]_0 [9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_236
   (\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[0] ,
    \xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    s_daddr_o,
    s_den_o,
    s_dwe_o,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[10]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[4]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  input [12:0]s_daddr_o;
  input s_den_o;
  input s_dwe_o;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \xsdb_reg[15]_i_1__14_n_0 ;
  wire \xsdb_reg[15]_i_4__1_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;

  LUT6 #(
    .INIT(64'h0000020000000000)) 
    \xsdb_reg[15]_i_1__14 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
        .O(\xsdb_reg[15]_i_1__14_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \xsdb_reg[15]_i_2__2 
       (.I0(s_daddr_o[12]),
        .I1(s_daddr_o[9]),
        .I2(s_daddr_o[10]),
        .I3(s_daddr_o[11]),
        .I4(\xsdb_reg[15]_i_4__1_n_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[12] ));
  LUT3 #(
    .INIT(8'h80)) 
    \xsdb_reg[15]_i_2__3 
       (.I0(s_daddr_o[0]),
        .I1(s_den_o),
        .I2(s_dwe_o),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[0] ));
  LUT4 #(
    .INIT(16'hFFEF)) 
    \xsdb_reg[15]_i_4__1 
       (.I0(s_daddr_o[6]),
        .I1(s_daddr_o[8]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[5]),
        .O(\xsdb_reg[15]_i_4__1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg[0]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[10]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[11]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[12]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[13]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[14]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[2]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[4]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[5]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[6]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[7]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[8]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__14_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[9]_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_237
   (\xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[15]_0 ,
    s_daddr_o,
    \slaveRegDo_mux_0[4]_i_4 ,
    \slaveRegDo_mux_0[2]_i_3 ,
    \slaveRegDo_mux_0[1]_i_3 ,
    \slaveRegDo_mux_0[0]_i_3 ,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 );
  output \xsdb_reg_reg[4]_0 ;
  output \xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  output [11:0]\xsdb_reg_reg[15]_0 ;
  input [2:0]s_daddr_o;
  input \slaveRegDo_mux_0[4]_i_4 ;
  input \slaveRegDo_mux_0[2]_i_3 ;
  input \slaveRegDo_mux_0[1]_i_3 ;
  input \slaveRegDo_mux_0[0]_i_3 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [4:0]slaveRegDo_84;
  wire \slaveRegDo_mux_0[0]_i_3 ;
  wire \slaveRegDo_mux_0[1]_i_3 ;
  wire \slaveRegDo_mux_0[2]_i_3 ;
  wire \slaveRegDo_mux_0[4]_i_4 ;
  wire \xsdb_reg[15]_i_1__4_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire [11:0]\xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[4]_0 ;

  LUT4 #(
    .INIT(16'h00E2)) 
    \slaveRegDo_mux_0[0]_i_8 
       (.I0(slaveRegDo_84[0]),
        .I1(s_daddr_o[0]),
        .I2(\slaveRegDo_mux_0[0]_i_3 ),
        .I3(s_daddr_o[1]),
        .O(\xsdb_reg_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \slaveRegDo_mux_0[1]_i_8 
       (.I0(slaveRegDo_84[1]),
        .I1(s_daddr_o[0]),
        .I2(\slaveRegDo_mux_0[1]_i_3 ),
        .I3(s_daddr_o[1]),
        .O(\xsdb_reg_reg[1]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \slaveRegDo_mux_0[2]_i_8 
       (.I0(slaveRegDo_84[2]),
        .I1(s_daddr_o[0]),
        .I2(\slaveRegDo_mux_0[2]_i_3 ),
        .I3(s_daddr_o[1]),
        .O(\xsdb_reg_reg[2]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \slaveRegDo_mux_0[4]_i_12 
       (.I0(slaveRegDo_84[4]),
        .I1(s_daddr_o[0]),
        .I2(\slaveRegDo_mux_0[4]_i_4 ),
        .I3(s_daddr_o[1]),
        .O(\xsdb_reg_reg[4]_0 ));
  LUT5 #(
    .INIT(32'h00200000)) 
    \xsdb_reg[15]_i_1__4 
       (.I0(\xsdb_reg_reg[0]_1 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg_reg[0]_2 ),
        .O(\xsdb_reg[15]_i_1__4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_84[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[15]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[15]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[15]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[15]_0 [9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[15]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 [11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_84[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_84[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[15]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_84[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[15]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[15]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[15]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[15]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__4_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[15]_0 [5]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_238
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[4] ,
    \xsdb_reg_reg[15]_0 ,
    s_daddr_o,
    \slaveRegDo_mux_0_reg[7] ,
    \slaveRegDo_mux_0_reg[8] ,
    \slaveRegDo_mux_0_reg[9] ,
    \slaveRegDo_mux_0_reg[4] ,
    \slaveRegDo_mux_0_reg[0] ,
    \slaveRegDo_mux_0_reg[1] ,
    \slaveRegDo_mux_0_reg[2] ,
    \slaveRegDo_mux_0_reg[3] ,
    \slaveRegDo_mux_0_reg[4]_0 ,
    \slaveRegDo_mux_0_reg[5] ,
    \slaveRegDo_mux_0_reg[6] ,
    \slaveRegDo_mux_0_reg[10] ,
    \slaveRegDo_mux_0_reg[11] ,
    \slaveRegDo_mux_0_reg[12] ,
    \slaveRegDo_mux_0_reg[13] ,
    \slaveRegDo_mux_0_reg[14] ,
    \xsdb_reg_reg[0]_0 ,
    s_den_o,
    s_dwe_o,
    \slaveRegDo_mux_0_reg[15] ,
    slaveRegDo_84,
    \slaveRegDo_mux_0_reg[3]_0 ,
    \slaveRegDo_mux_0_reg[5]_0 ,
    \slaveRegDo_mux_0_reg[6]_0 ,
    \slaveRegDo_mux_0_reg[7]_0 ,
    \slaveRegDo_mux_0_reg[8]_0 ,
    \slaveRegDo_mux_0_reg[9]_0 ,
    \slaveRegDo_mux_0_reg[10]_0 ,
    \slaveRegDo_mux_0_reg[11]_0 ,
    \slaveRegDo_mux_0_reg[12]_0 ,
    \slaveRegDo_mux_0_reg[13]_0 ,
    \slaveRegDo_mux_0_reg[14]_0 ,
    \slaveRegDo_mux_0_reg[15]_0 ,
    slaveRegDo_82,
    slaveRegDo_81,
    slaveRegDo_80,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  output \xsdb_reg_reg[15]_0 ;
  input [6:0]s_daddr_o;
  input \slaveRegDo_mux_0_reg[7] ;
  input \slaveRegDo_mux_0_reg[8] ;
  input \slaveRegDo_mux_0_reg[9] ;
  input \slaveRegDo_mux_0_reg[4] ;
  input \slaveRegDo_mux_0_reg[0] ;
  input \slaveRegDo_mux_0_reg[1] ;
  input \slaveRegDo_mux_0_reg[2] ;
  input \slaveRegDo_mux_0_reg[3] ;
  input \slaveRegDo_mux_0_reg[4]_0 ;
  input \slaveRegDo_mux_0_reg[5] ;
  input \slaveRegDo_mux_0_reg[6] ;
  input \slaveRegDo_mux_0_reg[10] ;
  input \slaveRegDo_mux_0_reg[11] ;
  input \slaveRegDo_mux_0_reg[12] ;
  input \slaveRegDo_mux_0_reg[13] ;
  input \slaveRegDo_mux_0_reg[14] ;
  input \xsdb_reg_reg[0]_0 ;
  input s_den_o;
  input s_dwe_o;
  input \slaveRegDo_mux_0_reg[15] ;
  input [11:0]slaveRegDo_84;
  input \slaveRegDo_mux_0_reg[3]_0 ;
  input \slaveRegDo_mux_0_reg[5]_0 ;
  input \slaveRegDo_mux_0_reg[6]_0 ;
  input \slaveRegDo_mux_0_reg[7]_0 ;
  input \slaveRegDo_mux_0_reg[8]_0 ;
  input \slaveRegDo_mux_0_reg[9]_0 ;
  input \slaveRegDo_mux_0_reg[10]_0 ;
  input \slaveRegDo_mux_0_reg[11]_0 ;
  input \slaveRegDo_mux_0_reg[12]_0 ;
  input \slaveRegDo_mux_0_reg[13]_0 ;
  input \slaveRegDo_mux_0_reg[14]_0 ;
  input \slaveRegDo_mux_0_reg[15]_0 ;
  input [15:0]slaveRegDo_82;
  input [15:0]slaveRegDo_81;
  input [15:0]slaveRegDo_80;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  wire [6:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire [15:0]slaveRegDo_80;
  wire [15:0]slaveRegDo_81;
  wire [15:0]slaveRegDo_82;
  wire [11:0]slaveRegDo_84;
  wire \slaveRegDo_mux_0[0]_i_7_n_0 ;
  wire \slaveRegDo_mux_0[10]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[10]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[11]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[11]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[12]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[12]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[13]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[13]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[14]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[14]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[15]_i_8_n_0 ;
  wire \slaveRegDo_mux_0[1]_i_7_n_0 ;
  wire \slaveRegDo_mux_0[2]_i_7_n_0 ;
  wire \slaveRegDo_mux_0[3]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[3]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[4]_i_11_n_0 ;
  wire \slaveRegDo_mux_0[5]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[5]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[6]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[6]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[7]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[7]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[8]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[8]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[9]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[9]_i_4_n_0 ;
  wire \slaveRegDo_mux_0_reg[0] ;
  wire \slaveRegDo_mux_0_reg[10] ;
  wire \slaveRegDo_mux_0_reg[10]_0 ;
  wire \slaveRegDo_mux_0_reg[11] ;
  wire \slaveRegDo_mux_0_reg[11]_0 ;
  wire \slaveRegDo_mux_0_reg[12] ;
  wire \slaveRegDo_mux_0_reg[12]_0 ;
  wire \slaveRegDo_mux_0_reg[13] ;
  wire \slaveRegDo_mux_0_reg[13]_0 ;
  wire \slaveRegDo_mux_0_reg[14] ;
  wire \slaveRegDo_mux_0_reg[14]_0 ;
  wire \slaveRegDo_mux_0_reg[15] ;
  wire \slaveRegDo_mux_0_reg[15]_0 ;
  wire \slaveRegDo_mux_0_reg[1] ;
  wire \slaveRegDo_mux_0_reg[2] ;
  wire \slaveRegDo_mux_0_reg[3] ;
  wire \slaveRegDo_mux_0_reg[3]_0 ;
  wire \slaveRegDo_mux_0_reg[4] ;
  wire \slaveRegDo_mux_0_reg[4]_0 ;
  wire \slaveRegDo_mux_0_reg[5] ;
  wire \slaveRegDo_mux_0_reg[5]_0 ;
  wire \slaveRegDo_mux_0_reg[6] ;
  wire \slaveRegDo_mux_0_reg[6]_0 ;
  wire \slaveRegDo_mux_0_reg[7] ;
  wire \slaveRegDo_mux_0_reg[7]_0 ;
  wire \slaveRegDo_mux_0_reg[8] ;
  wire \slaveRegDo_mux_0_reg[8]_0 ;
  wire \slaveRegDo_mux_0_reg[9] ;
  wire \slaveRegDo_mux_0_reg[9]_0 ;
  wire \xsdb_reg[15]_i_1__9_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg_n_0_[0] ;
  wire \xsdb_reg_reg_n_0_[10] ;
  wire \xsdb_reg_reg_n_0_[11] ;
  wire \xsdb_reg_reg_n_0_[12] ;
  wire \xsdb_reg_reg_n_0_[13] ;
  wire \xsdb_reg_reg_n_0_[14] ;
  wire \xsdb_reg_reg_n_0_[15] ;
  wire \xsdb_reg_reg_n_0_[1] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[3] ;
  wire \xsdb_reg_reg_n_0_[4] ;
  wire \xsdb_reg_reg_n_0_[5] ;
  wire \xsdb_reg_reg_n_0_[6] ;
  wire \xsdb_reg_reg_n_0_[7] ;
  wire \xsdb_reg_reg_n_0_[8] ;
  wire \xsdb_reg_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'hFFFFFFABFFFFFFFB)) 
    \slaveRegDo_mux_0[0]_i_3 
       (.I0(\slaveRegDo_mux_0_reg[4] ),
        .I1(\slaveRegDo_mux_0[0]_i_7_n_0 ),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(\slaveRegDo_mux_0_reg[0] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[0]_i_7 
       (.I0(\xsdb_reg_reg_n_0_[0] ),
        .I1(slaveRegDo_82[0]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[0]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[0]),
        .O(\slaveRegDo_mux_0[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[10]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[10]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[10] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[10]_i_2 
       (.I0(\slaveRegDo_mux_0[10]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[6]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[10]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[10]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[10] ),
        .I1(slaveRegDo_82[10]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[10]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[10]),
        .O(\slaveRegDo_mux_0[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[11]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[11]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[11] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[11]_i_2 
       (.I0(\slaveRegDo_mux_0[11]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[7]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[11]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[11]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[11] ),
        .I1(slaveRegDo_82[11]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[11]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[11]),
        .O(\slaveRegDo_mux_0[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[12]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[12]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[12] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[12]_i_2 
       (.I0(\slaveRegDo_mux_0[12]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[8]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[12]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[12]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[12] ),
        .I1(slaveRegDo_82[12]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[12]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[12]),
        .O(\slaveRegDo_mux_0[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[13]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[13]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[13] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[13]_i_2 
       (.I0(\slaveRegDo_mux_0[13]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[9]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[13]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[13]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[13] ),
        .I1(slaveRegDo_82[13]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[13]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[13]),
        .O(\slaveRegDo_mux_0[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[14]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[14]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[14] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[14]_i_2 
       (.I0(\slaveRegDo_mux_0[14]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[10]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[14]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[14]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[14] ),
        .I1(slaveRegDo_82[14]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[14]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[14]),
        .O(\slaveRegDo_mux_0[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[15]_i_4 
       (.I0(\slaveRegDo_mux_0[15]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[11]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[15]_0 ),
        .I5(s_daddr_o[1]),
        .O(\xsdb_reg_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[15]_i_8 
       (.I0(\xsdb_reg_reg_n_0_[15] ),
        .I1(slaveRegDo_82[15]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[15]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[15]),
        .O(\slaveRegDo_mux_0[15]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFABFFFFFFFB)) 
    \slaveRegDo_mux_0[1]_i_3 
       (.I0(\slaveRegDo_mux_0_reg[4] ),
        .I1(\slaveRegDo_mux_0[1]_i_7_n_0 ),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(\slaveRegDo_mux_0_reg[1] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[1]_i_7 
       (.I0(\xsdb_reg_reg_n_0_[1] ),
        .I1(slaveRegDo_82[1]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[1]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[1]),
        .O(\slaveRegDo_mux_0[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFABFFFFFFFB)) 
    \slaveRegDo_mux_0[2]_i_3 
       (.I0(\slaveRegDo_mux_0_reg[4] ),
        .I1(\slaveRegDo_mux_0[2]_i_7_n_0 ),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(\slaveRegDo_mux_0_reg[2] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[2]_i_7 
       (.I0(\xsdb_reg_reg_n_0_[2] ),
        .I1(slaveRegDo_82[2]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[2]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[2]),
        .O(\slaveRegDo_mux_0[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[3]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[3]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[3] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[3]_i_2 
       (.I0(\slaveRegDo_mux_0[3]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[0]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[3]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[3]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[3] ),
        .I1(slaveRegDo_82[3]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[3]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[3]),
        .O(\slaveRegDo_mux_0[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[4]_i_11 
       (.I0(\xsdb_reg_reg_n_0_[4] ),
        .I1(slaveRegDo_82[4]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[4]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[4]),
        .O(\slaveRegDo_mux_0[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFABFFFFFFFB)) 
    \slaveRegDo_mux_0[4]_i_4 
       (.I0(\slaveRegDo_mux_0_reg[4] ),
        .I1(\slaveRegDo_mux_0[4]_i_11_n_0 ),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(\slaveRegDo_mux_0_reg[4]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[5]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[5]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[5] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[5]_i_2 
       (.I0(\slaveRegDo_mux_0[5]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[1]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[5]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[5]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[5] ),
        .I1(slaveRegDo_82[5]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[5]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[5]),
        .O(\slaveRegDo_mux_0[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[6]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[6]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[6] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[6]_i_2 
       (.I0(\slaveRegDo_mux_0[6]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[2]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[6]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[6]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[6] ),
        .I1(slaveRegDo_82[6]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[6]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[6]),
        .O(\slaveRegDo_mux_0[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[7]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[7]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[7] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3] ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[7]_i_2 
       (.I0(\slaveRegDo_mux_0[7]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[3]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[7]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[7]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[7] ),
        .I1(slaveRegDo_82[7]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[7]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[7]),
        .O(\slaveRegDo_mux_0[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[8]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[8]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[8] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[8]_i_2 
       (.I0(\slaveRegDo_mux_0[8]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[4]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[8]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[8]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[8] ),
        .I1(slaveRegDo_82[8]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[8]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[8]),
        .O(\slaveRegDo_mux_0[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00100000001000FF)) 
    \slaveRegDo_mux_0[9]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(\slaveRegDo_mux_0[9]_i_2_n_0 ),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .I5(\slaveRegDo_mux_0_reg[9] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \slaveRegDo_mux_0[9]_i_2 
       (.I0(\slaveRegDo_mux_0[9]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] ),
        .I2(slaveRegDo_84[5]),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0_reg[9]_0 ),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_0[9]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[9] ),
        .I1(slaveRegDo_82[9]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_81[9]),
        .I4(s_daddr_o[0]),
        .I5(slaveRegDo_80[9]),
        .O(\slaveRegDo_mux_0[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0200000000000000)) 
    \xsdb_reg[15]_i_1__9 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[2]),
        .I2(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .I3(s_den_o),
        .I4(s_dwe_o),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
        .O(\xsdb_reg[15]_i_1__9_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \xsdb_reg[15]_i_3__1 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1] ));
  LUT2 #(
    .INIT(4'h1)) 
    \xsdb_reg[15]_i_4__0 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[4] ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__9_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg_n_0_[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_239
   (slaveRegDo_81,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_1 );
  output [15:0]slaveRegDo_81;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_0 ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_1 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_81;
  wire \xsdb_reg[15]_i_1__2_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;

  LUT5 #(
    .INIT(32'h02000000)) 
    \xsdb_reg[15]_i_1__2 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg_reg[0]_1 ),
        .O(\xsdb_reg[15]_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_81[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_81[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_81[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_81[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_81[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_81[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_81[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_81[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_81[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_81[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_81[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_81[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_81[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_81[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_81[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__2_n_0 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_81[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_242
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \xsdb_reg_reg[9]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[10]_0 ,
    s_daddr_o,
    \slaveRegDo_mux_0[15]_i_3 ,
    \slaveRegDo_mux_0[9]_i_3 ,
    \slaveRegDo_mux_0[3]_i_7 ,
    \slaveRegDo_mux_0[2]_i_6 ,
    \slaveRegDo_mux_0[6]_i_7 ,
    \slaveRegDo_mux_0[0]_i_6 ,
    \slaveRegDo_mux_0[14]_i_3 ,
    \slaveRegDo_mux_0[13]_i_3 ,
    \slaveRegDo_mux_0[12]_i_3 ,
    \slaveRegDo_mux_0[11]_i_3 ,
    \slaveRegDo_mux_0[5]_i_3 ,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_0 );
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \xsdb_reg_reg[9]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  output \xsdb_reg_reg[5]_0 ;
  output [4:0]\xsdb_reg_reg[10]_0 ;
  input [8:0]s_daddr_o;
  input \slaveRegDo_mux_0[15]_i_3 ;
  input \slaveRegDo_mux_0[9]_i_3 ;
  input \slaveRegDo_mux_0[3]_i_7 ;
  input \slaveRegDo_mux_0[2]_i_6 ;
  input \slaveRegDo_mux_0[6]_i_7 ;
  input \slaveRegDo_mux_0[0]_i_6 ;
  input \slaveRegDo_mux_0[14]_i_3 ;
  input \slaveRegDo_mux_0[13]_i_3 ;
  input \slaveRegDo_mux_0[12]_i_3 ;
  input \slaveRegDo_mux_0[11]_i_3 ;
  input \slaveRegDo_mux_0[5]_i_3 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_0 ;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
  wire [8:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_6;
  wire \slaveRegDo_mux_0[0]_i_6 ;
  wire \slaveRegDo_mux_0[11]_i_3 ;
  wire \slaveRegDo_mux_0[12]_i_3 ;
  wire \slaveRegDo_mux_0[13]_i_3 ;
  wire \slaveRegDo_mux_0[14]_i_3 ;
  wire \slaveRegDo_mux_0[15]_i_3 ;
  wire \slaveRegDo_mux_0[2]_i_6 ;
  wire \slaveRegDo_mux_0[3]_i_7 ;
  wire \slaveRegDo_mux_0[5]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_7 ;
  wire \slaveRegDo_mux_0[9]_i_3 ;
  wire \xsdb_reg[15]_i_1_n_0 ;
  wire \xsdb_reg[15]_i_3_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire [4:0]\xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[9]_0 ;

  LUT6 #(
    .INIT(64'h0000A80800000505)) 
    \slaveRegDo_mux_0[0]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(slaveRegDo_6[0]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[0]_i_6 ),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[2]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hBFBFBFFFFFFFBFFF)) 
    \slaveRegDo_mux_0[11]_i_7 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_6[11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_0[11]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ));
  LUT6 #(
    .INIT(64'hBFBFBFFFFFFFBFFF)) 
    \slaveRegDo_mux_0[12]_i_7 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_6[12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_0[12]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ));
  LUT6 #(
    .INIT(64'hBFBFBFFFFFFFBFFF)) 
    \slaveRegDo_mux_0[13]_i_7 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_6[13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_0[13]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ));
  LUT6 #(
    .INIT(64'hBFBFBFFFFFFFBFFF)) 
    \slaveRegDo_mux_0[14]_i_7 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_6[14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_0[14]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'h4040400000004000)) 
    \slaveRegDo_mux_0[15]_i_7 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(slaveRegDo_6[15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_0[15]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3] ));
  LUT6 #(
    .INIT(64'h0000A8080000A0A0)) 
    \slaveRegDo_mux_0[2]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(slaveRegDo_6[2]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[2]_i_6 ),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[2]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000A8080000A0A0)) 
    \slaveRegDo_mux_0[3]_i_8 
       (.I0(s_daddr_o[1]),
        .I1(slaveRegDo_6[3]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[3]_i_7 ),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[2]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1] ));
  LUT6 #(
    .INIT(64'hFFFF1DFFFFFFCCFF)) 
    \slaveRegDo_mux_0[5]_i_7 
       (.I0(slaveRegDo_6[5]),
        .I1(s_daddr_o[0]),
        .I2(\slaveRegDo_mux_0[5]_i_3 ),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[1]),
        .O(\xsdb_reg_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h0000A80800000505)) 
    \slaveRegDo_mux_0[6]_i_8 
       (.I0(s_daddr_o[1]),
        .I1(slaveRegDo_6[6]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[6]_i_7 ),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[2]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hFFFF1FFFFFFFDFFF)) 
    \slaveRegDo_mux_0[9]_i_7 
       (.I0(slaveRegDo_6[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_0[9]_i_3 ),
        .O(\xsdb_reg_reg[9]_0 ));
  LUT5 #(
    .INIT(32'h00800000)) 
    \xsdb_reg[15]_i_1 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg[15]_i_3_n_0 ),
        .O(\xsdb_reg[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \xsdb_reg[15]_i_3 
       (.I0(s_daddr_o[5]),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[8]),
        .I5(s_daddr_o[7]),
        .O(\xsdb_reg[15]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_6[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[10]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_6[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_6[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_6[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_6[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_6[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[10]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_6[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_6[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[10]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_6[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_6[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[10]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[10]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1_n_0 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_243
   (\xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 ,
    \xsdb_reg_reg[0]_3 ,
    s_di_o,
    s_dclk_o);
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[10]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[4]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;
  input \xsdb_reg_reg[0]_3 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \xsdb_reg[15]_i_1__11_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[0]_3 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;

  LUT6 #(
    .INIT(64'h0000000004000000)) 
    \xsdb_reg[15]_i_1__11 
       (.I0(s_daddr_o[0]),
        .I1(\xsdb_reg_reg[0]_1 ),
        .I2(\xsdb_reg_reg[0]_2 ),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[2]),
        .I5(\xsdb_reg_reg[0]_3 ),
        .O(\xsdb_reg[15]_i_1__11_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg[0]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[10]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[11]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[12]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[13]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[14]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[2]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[4]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[5]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[6]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[7]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[8]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__11_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[9]_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_244
   (D,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[6] ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[15]_0 ,
    \slaveRegDo_mux_0[4]_i_2_0 ,
    s_daddr_o,
    \slaveRegDo_mux_0[8]_i_3_0 ,
    \slaveRegDo_mux_0[8]_i_3_1 ,
    \slaveRegDo_mux_0[7]_i_3_0 ,
    \slaveRegDo_mux_0[7]_i_3_1 ,
    \slaveRegDo_mux_0[5]_i_3_0 ,
    \slaveRegDo_mux_0[5]_i_3_1 ,
    \slaveRegDo_mux_0[4]_i_2_1 ,
    \slaveRegDo_mux_0[4]_i_2_2 ,
    \slaveRegDo_mux_0_reg[4] ,
    \slaveRegDo_mux_0_reg[4]_0 ,
    \slaveRegDo_mux_0_reg[4]_1 ,
    \slaveRegDo_mux_0_reg[4]_2 ,
    \slaveRegDo_mux_0_reg[4]_3 ,
    \slaveRegDo_mux_0_reg[5] ,
    \slaveRegDo_mux_0_reg[4]_4 ,
    \slaveRegDo_mux_0_reg[5]_0 ,
    Q,
    \slaveRegDo_mux_0_reg[7] ,
    \slaveRegDo_mux_0_reg[7]_0 ,
    \slaveRegDo_mux_0_reg[8] ,
    \slaveRegDo_mux_0_reg[8]_0 ,
    \slaveRegDo_mux_0_reg[5]_1 ,
    \slaveRegDo_mux_0_reg[5]_2 ,
    \slaveRegDo_mux_0[9]_i_3 ,
    \slaveRegDo_mux_0[9]_i_3_0 ,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_0 );
  output [0:0]D;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  output \xsdb_reg_reg[9]_0 ;
  output [10:0]\xsdb_reg_reg[15]_0 ;
  input \slaveRegDo_mux_0[4]_i_2_0 ;
  input [7:0]s_daddr_o;
  input \slaveRegDo_mux_0[8]_i_3_0 ;
  input \slaveRegDo_mux_0[8]_i_3_1 ;
  input \slaveRegDo_mux_0[7]_i_3_0 ;
  input \slaveRegDo_mux_0[7]_i_3_1 ;
  input \slaveRegDo_mux_0[5]_i_3_0 ;
  input \slaveRegDo_mux_0[5]_i_3_1 ;
  input \slaveRegDo_mux_0[4]_i_2_1 ;
  input \slaveRegDo_mux_0[4]_i_2_2 ;
  input \slaveRegDo_mux_0_reg[4] ;
  input \slaveRegDo_mux_0_reg[4]_0 ;
  input \slaveRegDo_mux_0_reg[4]_1 ;
  input \slaveRegDo_mux_0_reg[4]_2 ;
  input \slaveRegDo_mux_0_reg[4]_3 ;
  input \slaveRegDo_mux_0_reg[5] ;
  input \slaveRegDo_mux_0_reg[4]_4 ;
  input \slaveRegDo_mux_0_reg[5]_0 ;
  input [3:0]Q;
  input \slaveRegDo_mux_0_reg[7] ;
  input \slaveRegDo_mux_0_reg[7]_0 ;
  input \slaveRegDo_mux_0_reg[8] ;
  input \slaveRegDo_mux_0_reg[8]_0 ;
  input \slaveRegDo_mux_0_reg[5]_1 ;
  input \slaveRegDo_mux_0_reg[5]_2 ;
  input \slaveRegDo_mux_0[9]_i_3 ;
  input \slaveRegDo_mux_0[9]_i_3_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_0 ;

  wire [0:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  wire [3:0]Q;
  wire [7:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [9:4]slaveRegDo_18;
  wire \slaveRegDo_mux_0[4]_i_2_0 ;
  wire \slaveRegDo_mux_0[4]_i_2_1 ;
  wire \slaveRegDo_mux_0[4]_i_2_2 ;
  wire \slaveRegDo_mux_0[4]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[4]_i_6_n_0 ;
  wire \slaveRegDo_mux_0[5]_i_3_0 ;
  wire \slaveRegDo_mux_0[5]_i_3_1 ;
  wire \slaveRegDo_mux_0[5]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[7]_i_3_0 ;
  wire \slaveRegDo_mux_0[7]_i_3_1 ;
  wire \slaveRegDo_mux_0[7]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[8]_i_3_0 ;
  wire \slaveRegDo_mux_0[8]_i_3_1 ;
  wire \slaveRegDo_mux_0[8]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[9]_i_3 ;
  wire \slaveRegDo_mux_0[9]_i_3_0 ;
  wire \slaveRegDo_mux_0_reg[4] ;
  wire \slaveRegDo_mux_0_reg[4]_0 ;
  wire \slaveRegDo_mux_0_reg[4]_1 ;
  wire \slaveRegDo_mux_0_reg[4]_2 ;
  wire \slaveRegDo_mux_0_reg[4]_3 ;
  wire \slaveRegDo_mux_0_reg[4]_4 ;
  wire \slaveRegDo_mux_0_reg[5] ;
  wire \slaveRegDo_mux_0_reg[5]_0 ;
  wire \slaveRegDo_mux_0_reg[5]_1 ;
  wire \slaveRegDo_mux_0_reg[5]_2 ;
  wire \slaveRegDo_mux_0_reg[7] ;
  wire \slaveRegDo_mux_0_reg[7]_0 ;
  wire \slaveRegDo_mux_0_reg[8] ;
  wire \slaveRegDo_mux_0_reg[8]_0 ;
  wire \xsdb_reg[15]_i_1__0_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire [10:0]\xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;

  LUT6 #(
    .INIT(64'h0047FFFF00470000)) 
    \slaveRegDo_mux_0[4]_i_1 
       (.I0(\slaveRegDo_mux_0[4]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[4] ),
        .I2(\slaveRegDo_mux_0_reg[4]_0 ),
        .I3(s_daddr_o[5]),
        .I4(\slaveRegDo_mux_0_reg[4]_1 ),
        .I5(\slaveRegDo_mux_0_reg[4]_2 ),
        .O(D));
  LUT6 #(
    .INIT(64'h2F2020202F202F20)) 
    \slaveRegDo_mux_0[4]_i_2 
       (.I0(\slaveRegDo_mux_0[4]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[4]_3 ),
        .I2(\slaveRegDo_mux_0_reg[5] ),
        .I3(\slaveRegDo_mux_0_reg[4]_4 ),
        .I4(\slaveRegDo_mux_0_reg[5]_0 ),
        .I5(Q[0]),
        .O(\slaveRegDo_mux_0[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFAFAABFBFFFFABFB)) 
    \slaveRegDo_mux_0[4]_i_6 
       (.I0(\slaveRegDo_mux_0[4]_i_2_0 ),
        .I1(slaveRegDo_18[4]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[4]_i_2_1 ),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_0[4]_i_2_2 ),
        .O(\slaveRegDo_mux_0[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h2F2020202F202F20)) 
    \slaveRegDo_mux_0[5]_i_3 
       (.I0(\slaveRegDo_mux_0[5]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[5]_1 ),
        .I2(\slaveRegDo_mux_0_reg[5] ),
        .I3(\slaveRegDo_mux_0_reg[5]_2 ),
        .I4(\slaveRegDo_mux_0_reg[5]_0 ),
        .I5(Q[1]),
        .O(\xsdb_reg_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hFAFAABFBFFFFABFB)) 
    \slaveRegDo_mux_0[5]_i_5 
       (.I0(\slaveRegDo_mux_0[4]_i_2_0 ),
        .I1(slaveRegDo_18[5]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[5]_i_3_0 ),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_0[5]_i_3_1 ),
        .O(\slaveRegDo_mux_0[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h2F2020202F202F20)) 
    \slaveRegDo_mux_0[7]_i_3 
       (.I0(\slaveRegDo_mux_0[7]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[7] ),
        .I2(\slaveRegDo_mux_0_reg[5] ),
        .I3(\slaveRegDo_mux_0_reg[7]_0 ),
        .I4(\slaveRegDo_mux_0_reg[5]_0 ),
        .I5(Q[2]),
        .O(\xsdb_reg_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hFAFAABFBFFFFABFB)) 
    \slaveRegDo_mux_0[7]_i_5 
       (.I0(\slaveRegDo_mux_0[4]_i_2_0 ),
        .I1(slaveRegDo_18[7]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[7]_i_3_0 ),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_0[7]_i_3_1 ),
        .O(\slaveRegDo_mux_0[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h2F2020202F202F20)) 
    \slaveRegDo_mux_0[8]_i_3 
       (.I0(\slaveRegDo_mux_0[8]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[8] ),
        .I2(\slaveRegDo_mux_0_reg[5] ),
        .I3(\slaveRegDo_mux_0_reg[8]_0 ),
        .I4(\slaveRegDo_mux_0_reg[5]_0 ),
        .I5(Q[3]),
        .O(\xsdb_reg_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hFAFAABFBFFFFABFB)) 
    \slaveRegDo_mux_0[8]_i_5 
       (.I0(\slaveRegDo_mux_0[4]_i_2_0 ),
        .I1(slaveRegDo_18[8]),
        .I2(s_daddr_o[0]),
        .I3(\slaveRegDo_mux_0[8]_i_3_0 ),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_0[8]_i_3_1 ),
        .O(\slaveRegDo_mux_0[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000033E200E2)) 
    \slaveRegDo_mux_0[9]_i_6 
       (.I0(slaveRegDo_18[9]),
        .I1(s_daddr_o[0]),
        .I2(\slaveRegDo_mux_0[9]_i_3 ),
        .I3(s_daddr_o[1]),
        .I4(\slaveRegDo_mux_0[9]_i_3_0 ),
        .I5(\slaveRegDo_mux_0[4]_i_2_0 ),
        .O(\xsdb_reg_reg[9]_0 ));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    \xsdb_reg[15]_i_1__0 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[2]),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[6] ),
        .O(\xsdb_reg[15]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \xsdb_reg[15]_i_3__2 
       (.I0(s_daddr_o[5]),
        .I1(s_daddr_o[4]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[6] ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg[15]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[15]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[15]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[15]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[15]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[15]_0 [9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[15]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[15]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[15]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_18[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_18[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[15]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_18[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_18[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__0_n_0 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_18[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_245
   (D,
    \G_1PIPE_IFACE.s_daddr_r_reg[7] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    \slaveRegDo_mux_0_reg[2] ,
    \slaveRegDo_mux_0_reg[1] ,
    \slaveRegDo_mux_0_reg[2]_0 ,
    \slaveRegDo_mux_0_reg[1]_0 ,
    \slaveRegDo_mux_0_reg[15] ,
    \slaveRegDo_mux_0_reg[0] ,
    \slaveRegDo_mux_0_reg[1]_1 ,
    \slaveRegDo_mux_0_reg[1]_2 ,
    \slaveRegDo_mux_0_reg[15]_0 ,
    s_dwe_o,
    s_den_o,
    \xsdb_reg_reg[0]_0 ,
    \slaveRegDo_mux_0_reg[3] ,
    \slaveRegDo_mux_0_reg[1]_3 ,
    \slaveRegDo_mux_0_reg[3]_0 ,
    \slaveRegDo_mux_0_reg[2]_1 ,
    \slaveRegDo_mux_0_reg[2]_2 ,
    \slaveRegDo_mux_0_reg[15]_1 ,
    \slaveRegDo_mux_0_reg[15]_2 ,
    \slaveRegDo_mux_0_reg[14] ,
    \slaveRegDo_mux_0_reg[14]_0 ,
    \slaveRegDo_mux_0_reg[13] ,
    \slaveRegDo_mux_0_reg[13]_0 ,
    \slaveRegDo_mux_0_reg[12] ,
    \slaveRegDo_mux_0_reg[12]_0 ,
    \slaveRegDo_mux_0_reg[11] ,
    \slaveRegDo_mux_0_reg[11]_0 ,
    \slaveRegDo_mux_0_reg[0]_0 ,
    \slaveRegDo_mux_0_reg[0]_1 ,
    \slaveRegDo_mux_0_reg[1]_4 ,
    \slaveRegDo_mux_0_reg[1]_5 ,
    \slaveRegDo_mux_0[15]_i_3_0 ,
    \slaveRegDo_mux_0[15]_i_3_1 ,
    \slaveRegDo_mux_0[14]_i_3_0 ,
    \slaveRegDo_mux_0[14]_i_3_1 ,
    \slaveRegDo_mux_0[13]_i_3_0 ,
    \slaveRegDo_mux_0[13]_i_3_1 ,
    \slaveRegDo_mux_0[12]_i_3_0 ,
    \slaveRegDo_mux_0[12]_i_3_1 ,
    \slaveRegDo_mux_0[11]_i_3_0 ,
    \slaveRegDo_mux_0[11]_i_3_1 ,
    \slaveRegDo_mux_0[10]_i_3 ,
    \slaveRegDo_mux_0[10]_i_3_0 ,
    read_reset_addr,
    \slaveRegDo_mux_0[6]_i_3 ,
    \slaveRegDo_mux_0[3]_i_3_0 ,
    in0,
    \slaveRegDo_mux_0[1]_i_2_0 ,
    SR,
    s_di_o,
    s_dclk_o);
  output [2:0]D;
  output \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  output \xsdb_reg_reg[10]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[4]_0 ;
  input \slaveRegDo_mux_0_reg[2] ;
  input \slaveRegDo_mux_0_reg[1] ;
  input \slaveRegDo_mux_0_reg[2]_0 ;
  input \slaveRegDo_mux_0_reg[1]_0 ;
  input [7:0]\slaveRegDo_mux_0_reg[15] ;
  input \slaveRegDo_mux_0_reg[0] ;
  input [1:0]\slaveRegDo_mux_0_reg[1]_1 ;
  input \slaveRegDo_mux_0_reg[1]_2 ;
  input \slaveRegDo_mux_0_reg[15]_0 ;
  input s_dwe_o;
  input s_den_o;
  input \xsdb_reg_reg[0]_0 ;
  input \slaveRegDo_mux_0_reg[3] ;
  input \slaveRegDo_mux_0_reg[1]_3 ;
  input \slaveRegDo_mux_0_reg[3]_0 ;
  input \slaveRegDo_mux_0_reg[2]_1 ;
  input \slaveRegDo_mux_0_reg[2]_2 ;
  input \slaveRegDo_mux_0_reg[15]_1 ;
  input \slaveRegDo_mux_0_reg[15]_2 ;
  input \slaveRegDo_mux_0_reg[14] ;
  input \slaveRegDo_mux_0_reg[14]_0 ;
  input \slaveRegDo_mux_0_reg[13] ;
  input \slaveRegDo_mux_0_reg[13]_0 ;
  input \slaveRegDo_mux_0_reg[12] ;
  input \slaveRegDo_mux_0_reg[12]_0 ;
  input \slaveRegDo_mux_0_reg[11] ;
  input \slaveRegDo_mux_0_reg[11]_0 ;
  input \slaveRegDo_mux_0_reg[0]_0 ;
  input \slaveRegDo_mux_0_reg[0]_1 ;
  input \slaveRegDo_mux_0_reg[1]_4 ;
  input \slaveRegDo_mux_0_reg[1]_5 ;
  input \slaveRegDo_mux_0[15]_i_3_0 ;
  input \slaveRegDo_mux_0[15]_i_3_1 ;
  input \slaveRegDo_mux_0[14]_i_3_0 ;
  input \slaveRegDo_mux_0[14]_i_3_1 ;
  input \slaveRegDo_mux_0[13]_i_3_0 ;
  input \slaveRegDo_mux_0[13]_i_3_1 ;
  input \slaveRegDo_mux_0[12]_i_3_0 ;
  input \slaveRegDo_mux_0[12]_i_3_1 ;
  input \slaveRegDo_mux_0[11]_i_3_0 ;
  input \slaveRegDo_mux_0[11]_i_3_1 ;
  input \slaveRegDo_mux_0[10]_i_3 ;
  input \slaveRegDo_mux_0[10]_i_3_0 ;
  input [4:0]read_reset_addr;
  input \slaveRegDo_mux_0[6]_i_3 ;
  input \slaveRegDo_mux_0[3]_i_3_0 ;
  input in0;
  input \slaveRegDo_mux_0[1]_i_2_0 ;
  input [0:0]SR;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [2:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
  wire [0:0]SR;
  wire in0;
  wire [4:0]read_reset_addr;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \slaveRegDo_mux_0[0]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[0]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[10]_i_3 ;
  wire \slaveRegDo_mux_0[10]_i_3_0 ;
  wire \slaveRegDo_mux_0[11]_i_3_0 ;
  wire \slaveRegDo_mux_0[11]_i_3_1 ;
  wire \slaveRegDo_mux_0[11]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[12]_i_3_0 ;
  wire \slaveRegDo_mux_0[12]_i_3_1 ;
  wire \slaveRegDo_mux_0[12]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[13]_i_3_0 ;
  wire \slaveRegDo_mux_0[13]_i_3_1 ;
  wire \slaveRegDo_mux_0[13]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[14]_i_3_0 ;
  wire \slaveRegDo_mux_0[14]_i_3_1 ;
  wire \slaveRegDo_mux_0[14]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[15]_i_3_0 ;
  wire \slaveRegDo_mux_0[15]_i_3_1 ;
  wire \slaveRegDo_mux_0[15]_i_3_n_0 ;
  wire \slaveRegDo_mux_0[15]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[1]_i_2_0 ;
  wire \slaveRegDo_mux_0[1]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[1]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[2]_i_2_n_0 ;
  wire \slaveRegDo_mux_0[2]_i_4_n_0 ;
  wire \slaveRegDo_mux_0[3]_i_3_0 ;
  wire \slaveRegDo_mux_0[3]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[6]_i_3 ;
  wire \slaveRegDo_mux_0_reg[0] ;
  wire \slaveRegDo_mux_0_reg[0]_0 ;
  wire \slaveRegDo_mux_0_reg[0]_1 ;
  wire \slaveRegDo_mux_0_reg[11] ;
  wire \slaveRegDo_mux_0_reg[11]_0 ;
  wire \slaveRegDo_mux_0_reg[12] ;
  wire \slaveRegDo_mux_0_reg[12]_0 ;
  wire \slaveRegDo_mux_0_reg[13] ;
  wire \slaveRegDo_mux_0_reg[13]_0 ;
  wire \slaveRegDo_mux_0_reg[14] ;
  wire \slaveRegDo_mux_0_reg[14]_0 ;
  wire [7:0]\slaveRegDo_mux_0_reg[15] ;
  wire \slaveRegDo_mux_0_reg[15]_0 ;
  wire \slaveRegDo_mux_0_reg[15]_1 ;
  wire \slaveRegDo_mux_0_reg[15]_2 ;
  wire \slaveRegDo_mux_0_reg[1] ;
  wire \slaveRegDo_mux_0_reg[1]_0 ;
  wire [1:0]\slaveRegDo_mux_0_reg[1]_1 ;
  wire \slaveRegDo_mux_0_reg[1]_2 ;
  wire \slaveRegDo_mux_0_reg[1]_3 ;
  wire \slaveRegDo_mux_0_reg[1]_4 ;
  wire \slaveRegDo_mux_0_reg[1]_5 ;
  wire \slaveRegDo_mux_0_reg[2] ;
  wire \slaveRegDo_mux_0_reg[2]_0 ;
  wire \slaveRegDo_mux_0_reg[2]_1 ;
  wire \slaveRegDo_mux_0_reg[2]_2 ;
  wire \slaveRegDo_mux_0_reg[3] ;
  wire \slaveRegDo_mux_0_reg[3]_0 ;
  wire \xsdb_reg[15]_i_1__12_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg_n_0_[0] ;
  wire \xsdb_reg_reg_n_0_[10] ;
  wire \xsdb_reg_reg_n_0_[11] ;
  wire \xsdb_reg_reg_n_0_[12] ;
  wire \xsdb_reg_reg_n_0_[13] ;
  wire \xsdb_reg_reg_n_0_[14] ;
  wire \xsdb_reg_reg_n_0_[15] ;
  wire \xsdb_reg_reg_n_0_[1] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[3] ;
  wire \xsdb_reg_reg_n_0_[6] ;

  LUT6 #(
    .INIT(64'h0047FFFF00470000)) 
    \slaveRegDo_mux_0[0]_i_1 
       (.I0(\slaveRegDo_mux_0[0]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[1] ),
        .I2(\slaveRegDo_mux_0_reg[0] ),
        .I3(\slaveRegDo_mux_0_reg[15] [6]),
        .I4(\slaveRegDo_mux_0_reg[1]_0 ),
        .I5(\slaveRegDo_mux_0_reg[1]_1 [0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[0]_i_2 
       (.I0(\slaveRegDo_mux_0[0]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[0]_0 ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[0]_1 ),
        .O(\slaveRegDo_mux_0[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[0]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[0] ),
        .I1(read_reset_addr[0]),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(SR),
        .O(\slaveRegDo_mux_0[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[10]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[10] ),
        .I1(\slaveRegDo_mux_0[10]_i_3 ),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[10]_i_3_0 ),
        .O(\xsdb_reg_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[11]_i_3 
       (.I0(\slaveRegDo_mux_0[11]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[11] ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[11]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[11]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[11] ),
        .I1(\slaveRegDo_mux_0[11]_i_3_0 ),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[11]_i_3_1 ),
        .O(\slaveRegDo_mux_0[11]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[12]_i_3 
       (.I0(\slaveRegDo_mux_0[12]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[12] ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[12]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[12]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[12] ),
        .I1(\slaveRegDo_mux_0[12]_i_3_0 ),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[12]_i_3_1 ),
        .O(\slaveRegDo_mux_0[12]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[13]_i_3 
       (.I0(\slaveRegDo_mux_0[13]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[13] ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[13]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[13]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[13] ),
        .I1(\slaveRegDo_mux_0[13]_i_3_0 ),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[13]_i_3_1 ),
        .O(\slaveRegDo_mux_0[13]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[14]_i_3 
       (.I0(\slaveRegDo_mux_0[14]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[14] ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[14]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[14]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[14] ),
        .I1(\slaveRegDo_mux_0[14]_i_3_0 ),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[14]_i_3_1 ),
        .O(\slaveRegDo_mux_0[14]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0202020202020E02)) 
    \slaveRegDo_mux_0[15]_i_2 
       (.I0(\slaveRegDo_mux_0[15]_i_3_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [7]),
        .I2(\slaveRegDo_mux_0_reg[15] [5]),
        .I3(\slaveRegDo_mux_0_reg[15]_0 ),
        .I4(\slaveRegDo_mux_0_reg[15] [4]),
        .I5(\slaveRegDo_mux_0_reg[15] [3]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[7] ));
  LUT6 #(
    .INIT(64'h3808FFFF38080000)) 
    \slaveRegDo_mux_0[15]_i_3 
       (.I0(\slaveRegDo_mux_0[15]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[15]_1 ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[15]_2 ),
        .O(\slaveRegDo_mux_0[15]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[15]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[15] ),
        .I1(\slaveRegDo_mux_0[15]_i_3_0 ),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_1 ),
        .O(\slaveRegDo_mux_0[15]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0047FFFF00470000)) 
    \slaveRegDo_mux_0[1]_i_1 
       (.I0(\slaveRegDo_mux_0[1]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[1] ),
        .I2(\slaveRegDo_mux_0_reg[1]_2 ),
        .I3(\slaveRegDo_mux_0_reg[15] [6]),
        .I4(\slaveRegDo_mux_0_reg[1]_0 ),
        .I5(\slaveRegDo_mux_0_reg[1]_1 [1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[1]_i_2 
       (.I0(\slaveRegDo_mux_0[1]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[1]_4 ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[1]_5 ),
        .O(\slaveRegDo_mux_0[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[1]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[1] ),
        .I1(read_reset_addr[1]),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[1]_i_2_0 ),
        .O(\slaveRegDo_mux_0[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAAA303FAAAA)) 
    \slaveRegDo_mux_0[2]_i_1 
       (.I0(\slaveRegDo_mux_0_reg[2] ),
        .I1(\slaveRegDo_mux_0[2]_i_2_n_0 ),
        .I2(\slaveRegDo_mux_0_reg[1] ),
        .I3(\slaveRegDo_mux_0_reg[2]_0 ),
        .I4(\slaveRegDo_mux_0_reg[1]_0 ),
        .I5(\slaveRegDo_mux_0_reg[15] [6]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[2]_i_2 
       (.I0(\slaveRegDo_mux_0[2]_i_4_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[2]_1 ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[2]_2 ),
        .O(\slaveRegDo_mux_0[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[2]_i_4 
       (.I0(\xsdb_reg_reg_n_0_[2] ),
        .I1(read_reset_addr[2]),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(in0),
        .O(\slaveRegDo_mux_0[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[3]_i_3 
       (.I0(\slaveRegDo_mux_0[3]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[15] [2]),
        .I2(\slaveRegDo_mux_0_reg[15] [3]),
        .I3(\slaveRegDo_mux_0_reg[3] ),
        .I4(\slaveRegDo_mux_0_reg[1]_3 ),
        .I5(\slaveRegDo_mux_0_reg[3]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2] ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[3]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[3] ),
        .I1(read_reset_addr[3]),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[3]_i_3_0 ),
        .O(\slaveRegDo_mux_0[3]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_0[6]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[6] ),
        .I1(read_reset_addr[4]),
        .I2(\slaveRegDo_mux_0_reg[15] [1]),
        .I3(\slaveRegDo_mux_0_reg[15] [0]),
        .I4(\slaveRegDo_mux_0[6]_i_3 ),
        .O(\xsdb_reg_reg[6]_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \xsdb_reg[15]_i_1__12 
       (.I0(s_dwe_o),
        .I1(s_den_o),
        .I2(\slaveRegDo_mux_0_reg[15] [0]),
        .I3(\xsdb_reg_reg[0]_0 ),
        .O(\xsdb_reg[15]_i_1__12_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[4]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[5]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[7]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[8]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__12_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[9]_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_246
   (\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[12] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[6] ,
    \xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[10]_0 ,
    read_reset_addr,
    s_dwe_o,
    s_den_o,
    s_daddr_o,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[10]_0 ;
  output [9:0]read_reset_addr;
  input s_dwe_o;
  input s_den_o;
  input [12:0]s_daddr_o;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  wire [9:0]read_reset_addr;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \xsdb_reg[15]_i_1__13_n_0 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15]_0 ;

  LUT4 #(
    .INIT(16'h0080)) 
    \xsdb_reg[15]_i_1__13 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
        .I1(s_dwe_o),
        .I2(s_den_o),
        .I3(s_daddr_o[0]),
        .O(\xsdb_reg[15]_i_1__13_n_0 ));
  LUT5 #(
    .INIT(32'h00800000)) 
    \xsdb_reg[15]_i_2__0 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[1]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[4] ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \xsdb_reg[15]_i_2__1 
       (.I0(s_daddr_o[12]),
        .I1(s_daddr_o[9]),
        .I2(s_daddr_o[10]),
        .I3(s_daddr_o[11]),
        .I4(\G_1PIPE_IFACE.s_daddr_r_reg[6] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[12] ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \xsdb_reg[15]_i_5 
       (.I0(s_daddr_o[6]),
        .I1(s_daddr_o[8]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[7]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[6] ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[0]),
        .Q(read_reset_addr[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[10]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[11]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[12]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[13]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[14]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[1]),
        .Q(read_reset_addr[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[2]),
        .Q(read_reset_addr[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[3]),
        .Q(read_reset_addr[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[4]),
        .Q(read_reset_addr[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[5]),
        .Q(read_reset_addr[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[6]),
        .Q(read_reset_addr[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[7]),
        .Q(read_reset_addr[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[8]),
        .Q(read_reset_addr[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__13_n_0 ),
        .D(s_di_o[9]),
        .Q(read_reset_addr[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_247
   (\xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[3]_0 ,
    in0,
    \xsdb_reg_reg[1]_0 ,
    SR,
    \slaveRegDo_mux_0[4]_i_2 ,
    s_daddr_o,
    read_reset_addr,
    \slaveRegDo_mux_0[9]_i_3_0 ,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[0]_1 ,
    \slaveRegDo_mux_0_reg[9] ,
    \slaveRegDo_mux_0_reg[9]_0 ,
    \slaveRegDo_mux_0_reg[9]_1 ,
    \slaveRegDo_mux_0_reg[9]_2 ,
    Q,
    \slaveRegDo_mux_0[8]_i_3 ,
    \slaveRegDo_mux_0[7]_i_3 ,
    \slaveRegDo_mux_0[5]_i_3 ,
    \slaveRegDo_mux_0[4]_i_2_0 ,
    s_di_o,
    s_dclk_o);
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[4]_0 ;
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[10]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output in0;
  output \xsdb_reg_reg[1]_0 ;
  output [0:0]SR;
  input \slaveRegDo_mux_0[4]_i_2 ;
  input [4:0]s_daddr_o;
  input [4:0]read_reset_addr;
  input \slaveRegDo_mux_0[9]_i_3_0 ;
  input \xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[0]_1 ;
  input \slaveRegDo_mux_0_reg[9] ;
  input \slaveRegDo_mux_0_reg[9]_0 ;
  input \slaveRegDo_mux_0_reg[9]_1 ;
  input \slaveRegDo_mux_0_reg[9]_2 ;
  input [0:0]Q;
  input \slaveRegDo_mux_0[8]_i_3 ;
  input \slaveRegDo_mux_0[7]_i_3 ;
  input \slaveRegDo_mux_0[5]_i_3 ;
  input \slaveRegDo_mux_0[4]_i_2_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [0:0]Q;
  wire [0:0]SR;
  wire in0;
  wire [4:0]read_reset_addr;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[4]_i_2 ;
  wire \slaveRegDo_mux_0[4]_i_2_0 ;
  wire \slaveRegDo_mux_0[5]_i_3 ;
  wire \slaveRegDo_mux_0[7]_i_3 ;
  wire \slaveRegDo_mux_0[8]_i_3 ;
  wire \slaveRegDo_mux_0[9]_i_3_0 ;
  wire \slaveRegDo_mux_0[9]_i_5_n_0 ;
  wire \slaveRegDo_mux_0_reg[9] ;
  wire \slaveRegDo_mux_0_reg[9]_0 ;
  wire \slaveRegDo_mux_0_reg[9]_1 ;
  wire \slaveRegDo_mux_0_reg[9]_2 ;
  wire \xsdb_reg[15]_i_1__5_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg_n_0_[4] ;
  wire \xsdb_reg_reg_n_0_[5] ;
  wire \xsdb_reg_reg_n_0_[7] ;
  wire \xsdb_reg_reg_n_0_[8] ;
  wire \xsdb_reg_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h00000000F8C83808)) 
    \slaveRegDo_mux_0[4]_i_7 
       (.I0(\xsdb_reg_reg_n_0_[4] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(read_reset_addr[0]),
        .I4(\slaveRegDo_mux_0[4]_i_2_0 ),
        .I5(\slaveRegDo_mux_0[4]_i_2 ),
        .O(\xsdb_reg_reg[4]_0 ));
  LUT6 #(
    .INIT(64'h00000000F8C83808)) 
    \slaveRegDo_mux_0[5]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[5] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(read_reset_addr[1]),
        .I4(\slaveRegDo_mux_0[5]_i_3 ),
        .I5(\slaveRegDo_mux_0[4]_i_2 ),
        .O(\xsdb_reg_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h00000000F8C83808)) 
    \slaveRegDo_mux_0[7]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[7] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(read_reset_addr[2]),
        .I4(\slaveRegDo_mux_0[7]_i_3 ),
        .I5(\slaveRegDo_mux_0[4]_i_2 ),
        .O(\xsdb_reg_reg[7]_0 ));
  LUT6 #(
    .INIT(64'h00000000F8C83808)) 
    \slaveRegDo_mux_0[8]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[8] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(read_reset_addr[3]),
        .I4(\slaveRegDo_mux_0[8]_i_3 ),
        .I5(\slaveRegDo_mux_0[4]_i_2 ),
        .O(\xsdb_reg_reg[8]_0 ));
  LUT6 #(
    .INIT(64'h2F2020202F202F20)) 
    \slaveRegDo_mux_0[9]_i_3 
       (.I0(\slaveRegDo_mux_0[9]_i_5_n_0 ),
        .I1(\slaveRegDo_mux_0_reg[9] ),
        .I2(\slaveRegDo_mux_0_reg[9]_0 ),
        .I3(\slaveRegDo_mux_0_reg[9]_1 ),
        .I4(\slaveRegDo_mux_0_reg[9]_2 ),
        .I5(Q),
        .O(\xsdb_reg_reg[9]_0 ));
  LUT6 #(
    .INIT(64'hAABFAFBFFABFFFBF)) 
    \slaveRegDo_mux_0[9]_i_5 
       (.I0(\slaveRegDo_mux_0[4]_i_2 ),
        .I1(\xsdb_reg_reg_n_0_[9] ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(read_reset_addr[4]),
        .I5(\slaveRegDo_mux_0[9]_i_3_0 ),
        .O(\slaveRegDo_mux_0[9]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \xsdb_reg[15]_i_1__5 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .I5(\xsdb_reg_reg[0]_1 ),
        .O(\xsdb_reg[15]_i_1__5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[0]),
        .Q(SR),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[10]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[11]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[12]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[13]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[14]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[2]),
        .Q(in0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[6]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__5_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg_n_0_[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_249
   (\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
    \xsdb_reg_reg[15]_0 ,
    s_dwe_o,
    D,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[0]_1 ,
    \I_EN_CTL_EQ1.temp_en_reg ,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
  output [15:0]\xsdb_reg_reg[15]_0 ;
  input s_dwe_o;
  input [5:0]D;
  input [0:0]\xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[0]_1 ;
  input \I_EN_CTL_EQ1.temp_en_reg ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire [5:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
  wire \I_EN_CTL_EQ1.temp_en_reg ;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire \xsdb_reg[15]_i_1__7_n_0 ;
  wire \xsdb_reg[15]_i_2_n_0 ;
  wire [0:0]\xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire [15:0]\xsdb_reg_reg[15]_0 ;

  LUT4 #(
    .INIT(16'h0080)) 
    \I_EN_CTL_EQ1.temp_en_i_2 
       (.I0(D[4]),
        .I1(D[2]),
        .I2(D[3]),
        .I3(\I_EN_CTL_EQ1.temp_en_reg ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[11] ));
  LUT2 #(
    .INIT(4'h2)) 
    \xsdb_reg[15]_i_1__7 
       (.I0(s_dwe_o),
        .I1(\xsdb_reg[15]_i_2_n_0 ),
        .O(\xsdb_reg[15]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEFFFFFFFFF)) 
    \xsdb_reg[15]_i_2 
       (.I0(D[1]),
        .I1(D[5]),
        .I2(\xsdb_reg_reg[0]_0 ),
        .I3(D[0]),
        .I4(\xsdb_reg_reg[0]_1 ),
        .I5(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
        .O(\xsdb_reg[15]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg[15]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg[15]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[15]_0 [11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[15]_0 [12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[15]_0 [13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[15]_0 [14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 [15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[15]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[15]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[15]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[15]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[15]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[15]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[15]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[15]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__7_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[15]_0 [9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized0
   (\xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    halt_ctrl,
    \xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[0]_0 ,
    scnt_cmp_temp,
    wcnt_lcmp_temp,
    wcnt_hcmp_temp,
    \xsdb_reg_reg[0]_1 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_2 ,
    \xsdb_reg_reg[0]_3 ,
    \slaveRegDo_mux_0[10]_i_3 ,
    Q,
    \slaveRegDo_mux_0[1]_i_2 ,
    \slaveRegDo_mux_0[1]_i_2_0 ,
    s_di_o,
    s_dclk_o,
    DOUT_O,
    u_wcnt_lcmp_q,
    u_wcnt_hcmp_q);
  output \xsdb_reg_reg[4]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output halt_ctrl;
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  output scnt_cmp_temp;
  output wcnt_lcmp_temp;
  output wcnt_hcmp_temp;
  input \xsdb_reg_reg[0]_1 ;
  input [3:0]s_daddr_o;
  input \xsdb_reg_reg[0]_2 ;
  input \xsdb_reg_reg[0]_3 ;
  input [4:0]\slaveRegDo_mux_0[10]_i_3 ;
  input [0:0]Q;
  input [0:0]\slaveRegDo_mux_0[1]_i_2 ;
  input \slaveRegDo_mux_0[1]_i_2_0 ;
  input [15:0]s_di_o;
  input s_dclk_o;
  input DOUT_O;
  input u_wcnt_lcmp_q;
  input u_wcnt_hcmp_q;

  wire DOUT_O;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire [0:0]Q;
  wire halt_ctrl;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire scnt_cmp_temp;
  wire [4:0]\slaveRegDo_mux_0[10]_i_3 ;
  wire [0:0]\slaveRegDo_mux_0[1]_i_2 ;
  wire \slaveRegDo_mux_0[1]_i_2_0 ;
  wire \slaveRegDo_mux_0[1]_i_9_n_0 ;
  wire u_wcnt_hcmp_q;
  wire u_wcnt_lcmp_q;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp_temp;
  wire \xsdb_reg[15]_i_1__8_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[0]_3 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg_n_0_[10] ;
  wire \xsdb_reg_reg_n_0_[4] ;
  wire \xsdb_reg_reg_n_0_[7] ;
  wire \xsdb_reg_reg_n_0_[8] ;

  LUT6 #(
    .INIT(64'hAFFBEFFBBFFBFFFB)) 
    \slaveRegDo_mux_0[10]_i_7 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(\xsdb_reg_reg_n_0_[10] ),
        .I5(\slaveRegDo_mux_0[10]_i_3 [4]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA888AAA8A)) 
    \slaveRegDo_mux_0[1]_i_6 
       (.I0(\slaveRegDo_mux_0[1]_i_9_n_0 ),
        .I1(s_daddr_o[1]),
        .I2(Q),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[1]_i_2 ),
        .I5(\slaveRegDo_mux_0[1]_i_2_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1] ));
  LUT6 #(
    .INIT(64'hDFDDDFFFFFFFFFFF)) 
    \slaveRegDo_mux_0[1]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .I2(halt_ctrl),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[10]_i_3 [0]),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF73FFFFFF7FFF)) 
    \slaveRegDo_mux_0[4]_i_9 
       (.I0(\xsdb_reg_reg_n_0_[4] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_0[10]_i_3 [1]),
        .O(\xsdb_reg_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hFFFF73FFFFFF7FFF)) 
    \slaveRegDo_mux_0[7]_i_7 
       (.I0(\xsdb_reg_reg_n_0_[7] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_0[10]_i_3 [2]),
        .O(\xsdb_reg_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hFFFF73FFFFFF7FFF)) 
    \slaveRegDo_mux_0[8]_i_7 
       (.I0(\xsdb_reg_reg_n_0_[8] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_0[10]_i_3 [3]),
        .O(\xsdb_reg_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT2 #(
    .INIT(4'h8)) 
    u_scnt_cmp_q_i_2
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(DOUT_O),
        .O(scnt_cmp_temp));
  LUT2 #(
    .INIT(4'h8)) 
    u_wcnt_hcmp_q_i_1
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(u_wcnt_hcmp_q),
        .O(wcnt_hcmp_temp));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT2 #(
    .INIT(4'h8)) 
    u_wcnt_lcmp_q_i_1
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(u_wcnt_lcmp_q),
        .O(wcnt_lcmp_temp));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    \xsdb_reg[15]_i_1__8 
       (.I0(\xsdb_reg_reg[0]_1 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[1]),
        .I4(\xsdb_reg_reg[0]_2 ),
        .I5(\xsdb_reg_reg[0]_3 ),
        .O(\xsdb_reg[15]_i_1__8_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg[0]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg[11]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg[12]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg[13]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg[14]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg[15]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[1]),
        .Q(halt_ctrl),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[2]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[5]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg[6]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__8_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[9]_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized1
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
    \xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[3]_1 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[2]_1 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_1 ,
    \xsdb_reg_reg[0]_2 ,
    \xsdb_reg_reg[0]_3 ,
    \slaveRegDo_mux_0_reg[6] ,
    \slaveRegDo_mux_0_reg[10] ,
    \slaveRegDo_mux_0_reg[6]_0 ,
    \slaveRegDo_mux_0_reg[10]_0 ,
    \slaveRegDo_mux_0_reg[10]_1 ,
    \slaveRegDo_mux_0[15]_i_3 ,
    \slaveRegDo_mux_0[15]_i_3_0 ,
    \slaveRegDo_mux_0[14]_i_3 ,
    \slaveRegDo_mux_0[13]_i_3 ,
    \slaveRegDo_mux_0[12]_i_3 ,
    \slaveRegDo_mux_0[11]_i_3 ,
    \slaveRegDo_mux_0[10]_i_3_0 ,
    \slaveRegDo_mux_0[6]_i_3_0 ,
    \slaveRegDo_mux_0[3]_i_3 ,
    \slaveRegDo_mux_0[2]_i_2 ,
    \slaveRegDo_mux_0[1]_i_2 ,
    \slaveRegDo_mux_0[0]_i_2 ,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[3]_1 ;
  output \xsdb_reg_reg[2]_0 ;
  output [1:0]\xsdb_reg_reg[2]_1 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[4]_0 ;
  input [4:0]s_daddr_o;
  input \xsdb_reg_reg[0]_1 ;
  input \xsdb_reg_reg[0]_2 ;
  input \xsdb_reg_reg[0]_3 ;
  input \slaveRegDo_mux_0_reg[6] ;
  input \slaveRegDo_mux_0_reg[10] ;
  input \slaveRegDo_mux_0_reg[6]_0 ;
  input \slaveRegDo_mux_0_reg[10]_0 ;
  input \slaveRegDo_mux_0_reg[10]_1 ;
  input \slaveRegDo_mux_0[15]_i_3 ;
  input [10:0]\slaveRegDo_mux_0[15]_i_3_0 ;
  input \slaveRegDo_mux_0[14]_i_3 ;
  input \slaveRegDo_mux_0[13]_i_3 ;
  input \slaveRegDo_mux_0[12]_i_3 ;
  input \slaveRegDo_mux_0[11]_i_3 ;
  input \slaveRegDo_mux_0[10]_i_3_0 ;
  input \slaveRegDo_mux_0[6]_i_3_0 ;
  input \slaveRegDo_mux_0[3]_i_3 ;
  input \slaveRegDo_mux_0[2]_i_2 ;
  input \slaveRegDo_mux_0[1]_i_2 ;
  input \slaveRegDo_mux_0[0]_i_2 ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \slaveRegDo_mux_0[0]_i_2 ;
  wire \slaveRegDo_mux_0[10]_i_3_0 ;
  wire \slaveRegDo_mux_0[10]_i_5_n_0 ;
  wire \slaveRegDo_mux_0[11]_i_3 ;
  wire \slaveRegDo_mux_0[12]_i_3 ;
  wire \slaveRegDo_mux_0[13]_i_3 ;
  wire \slaveRegDo_mux_0[14]_i_3 ;
  wire \slaveRegDo_mux_0[15]_i_3 ;
  wire [10:0]\slaveRegDo_mux_0[15]_i_3_0 ;
  wire \slaveRegDo_mux_0[1]_i_2 ;
  wire \slaveRegDo_mux_0[2]_i_2 ;
  wire \slaveRegDo_mux_0[3]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_3_0 ;
  wire \slaveRegDo_mux_0[6]_i_5_n_0 ;
  wire \slaveRegDo_mux_0_reg[10] ;
  wire \slaveRegDo_mux_0_reg[10]_0 ;
  wire \slaveRegDo_mux_0_reg[10]_1 ;
  wire \slaveRegDo_mux_0_reg[6] ;
  wire \slaveRegDo_mux_0_reg[6]_0 ;
  wire \xsdb_reg[15]_i_1__10_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[0]_2 ;
  wire \xsdb_reg_reg[0]_3 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire [1:0]\xsdb_reg_reg[2]_1 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[3]_1 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg_n_0_[0] ;
  wire \xsdb_reg_reg_n_0_[10] ;
  wire \xsdb_reg_reg_n_0_[11] ;
  wire \xsdb_reg_reg_n_0_[12] ;
  wire \xsdb_reg_reg_n_0_[13] ;
  wire \xsdb_reg_reg_n_0_[14] ;
  wire \xsdb_reg_reg_n_0_[15] ;
  wire \xsdb_reg_reg_n_0_[6] ;

  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[0]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[0] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[0]_i_2 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [0]),
        .O(\xsdb_reg_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[10]_i_3 
       (.I0(\slaveRegDo_mux_0[10]_i_5_n_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(\slaveRegDo_mux_0_reg[10]_0 ),
        .I4(\slaveRegDo_mux_0_reg[10] ),
        .I5(\slaveRegDo_mux_0_reg[10]_1 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[10]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[10] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[10]_i_3_0 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [5]),
        .O(\slaveRegDo_mux_0[10]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[11]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[11] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[11]_i_3 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [6]),
        .O(\xsdb_reg_reg[11]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[12]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[12] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[12]_i_3 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [7]),
        .O(\xsdb_reg_reg[12]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[13]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[13] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[13]_i_3 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [8]),
        .O(\xsdb_reg_reg[13]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[14]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[14] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[14]_i_3 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [9]),
        .O(\xsdb_reg_reg[14]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[15]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[15] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[15]_i_3 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [10]),
        .O(\xsdb_reg_reg[15]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[1]_i_5 
       (.I0(\xsdb_reg_reg[2]_1 [0]),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[1]_i_2 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [1]),
        .O(\xsdb_reg_reg[1]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[2]_i_5 
       (.I0(\xsdb_reg_reg[2]_1 [1]),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[2]_i_2 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [2]),
        .O(\xsdb_reg_reg[2]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[3]_i_6 
       (.I0(\xsdb_reg_reg[3]_1 ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[3]_i_3 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [3]),
        .O(\xsdb_reg_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hC7F7FFFFC7F70000)) 
    \slaveRegDo_mux_0[6]_i_3 
       (.I0(\slaveRegDo_mux_0[6]_i_5_n_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(\slaveRegDo_mux_0_reg[6] ),
        .I4(\slaveRegDo_mux_0_reg[10] ),
        .I5(\slaveRegDo_mux_0_reg[6]_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3] ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \slaveRegDo_mux_0[6]_i_5 
       (.I0(\xsdb_reg_reg_n_0_[6] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_0[6]_i_3_0 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_0[15]_i_3_0 [4]),
        .O(\slaveRegDo_mux_0[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \xsdb_reg[15]_i_1__10 
       (.I0(s_daddr_o[2]),
        .I1(\xsdb_reg_reg[0]_1 ),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[4]),
        .I4(\xsdb_reg_reg[0]_2 ),
        .I5(\xsdb_reg_reg[0]_3 ),
        .O(\xsdb_reg[15]_i_1__10_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[0]),
        .Q(\xsdb_reg_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[10]),
        .Q(\xsdb_reg_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[11]),
        .Q(\xsdb_reg_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[12]),
        .Q(\xsdb_reg_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[13]),
        .Q(\xsdb_reg_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[14]),
        .Q(\xsdb_reg_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[15]),
        .Q(\xsdb_reg_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[1]),
        .Q(\xsdb_reg_reg[2]_1 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[2]),
        .Q(\xsdb_reg_reg[2]_1 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[3]),
        .Q(\xsdb_reg_reg[3]_1 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[4]),
        .Q(\xsdb_reg_reg[4]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[5]),
        .Q(\xsdb_reg_reg[5]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[6]),
        .Q(\xsdb_reg_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[7]),
        .Q(\xsdb_reg_reg[7]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[8]),
        .Q(\xsdb_reg_reg[8]_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__10_n_0 ),
        .D(s_di_o[9]),
        .Q(\xsdb_reg_reg[9]_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2
   (slaveRegDo_82,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_1 );
  output [15:0]slaveRegDo_82;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_0 ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_1 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_82;
  wire \xsdb_reg[15]_i_1__3_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;

  LUT5 #(
    .INIT(32'h00200000)) 
    \xsdb_reg[15]_i_1__3 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg_reg[0]_1 ),
        .O(\xsdb_reg[15]_i_1__3_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_82[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_82[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_82[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_82[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_82[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_82[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_82[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_82[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_82[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_82[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_82[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_82[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_82[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_82[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_82[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__3_n_0 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_82[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_ctl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2_240
   (slaveRegDo_80,
    s_di_o,
    s_dclk_o,
    \xsdb_reg_reg[0]_0 ,
    s_daddr_o,
    \xsdb_reg_reg[0]_1 );
  output [15:0]slaveRegDo_80;
  input [15:0]s_di_o;
  input s_dclk_o;
  input \xsdb_reg_reg[0]_0 ;
  input [2:0]s_daddr_o;
  input \xsdb_reg_reg[0]_1 ;

  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_80;
  wire \xsdb_reg[15]_i_1__1_n_0 ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;

  LUT5 #(
    .INIT(32'h00020000)) 
    \xsdb_reg[15]_i_1__1 
       (.I0(\xsdb_reg_reg[0]_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg_reg[0]_1 ),
        .O(\xsdb_reg[15]_i_1__1_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_80[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_80[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_80[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_80[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_80[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_80[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_80[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_80[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_80[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_80[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_80[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_80[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_80[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_80[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_80[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(\xsdb_reg[15]_i_1__1_n_0 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_80[9]),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    s_daddr_o,
    \current_state_reg[3]_0 );
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input [1:0]s_daddr_o;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__1_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__1_n_0 ;
  wire \current_state[3]_i_3__1_n_0 ;
  wire \current_state[3]_i_4__1_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__1_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__1_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__1_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__1 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__1 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__1 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__1 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__1_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__1_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__1_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__1 
       (.I0(\current_state[3]_i_4__1_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__1_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__1_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__1 
       (.I0(\current_state[3]_i_4__1_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__1 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__1_n_0 ),
        .I2(\current_state[3]_i_4__1_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__1 
       (.I0(\current_state[3]_i_2__1_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__1_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__1_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__1 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[3]_i_3__1 
       (.I0(\current_state_reg[1]_1 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_0 ),
        .O(\current_state[3]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__1 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__1_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__1
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__1_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__1_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__1 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__1 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__1 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__1 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__1 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__1 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__1 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__1 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__1 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__1 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__1 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__1 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__1 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__1 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__1 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__1 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__1_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__1
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__1_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__1_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__0
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized0
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__2_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__2_n_0 ;
  wire \current_state[3]_i_3__2_n_0 ;
  wire \current_state[3]_i_4__2_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__2_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__2_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__2_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__2 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__2 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__2 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__2 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__2_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__2_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__2_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__2 
       (.I0(\current_state[3]_i_4__2_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__2_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__2_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__2 
       (.I0(\current_state[3]_i_4__2_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__2_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__2 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__2_n_0 ),
        .I2(\current_state[3]_i_4__2_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__2 
       (.I0(\current_state[3]_i_2__2_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__2_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__2_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__2 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \current_state[3]_i_3__2 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__2 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__2_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__2
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__2_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__2_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__2 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__2 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__2 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__2 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__2 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__2 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__2 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__2 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__2 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__2 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__2 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__2 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__2 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__2 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__2 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__2 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__2_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__2
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__2_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__2_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__1
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized1
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__3_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__3_n_0 ;
  wire \current_state[3]_i_3__3_n_0 ;
  wire \current_state[3]_i_4__3_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__3_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__3_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__3_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__3 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__3 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__3 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__3 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__3_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__3_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__3_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__3 
       (.I0(\current_state[3]_i_4__3_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__3_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__3_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__3 
       (.I0(\current_state[3]_i_4__3_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__3_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__3 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__3_n_0 ),
        .I2(\current_state[3]_i_4__3_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__3 
       (.I0(\current_state[3]_i_2__3_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__3_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__3_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__3 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \current_state[3]_i_3__3 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__3 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__3_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__3
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__3_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__3_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__3 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__3 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__3 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__3 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__3 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__3 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__3 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__3 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__3 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__3 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__3 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__3 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__3 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__3 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__3 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__3 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__3_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__3
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__3_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__3_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__2
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized10
   (D,
    E,
    mu_config_cs_serial_output,
    \slaveRegDo_mux_4_reg[0] ,
    \slaveRegDo_mux_4_reg[15] ,
    \slaveRegDo_mux_4_reg[15]_0 ,
    s_do_o,
    Q,
    \slaveRegDo_mux_4_reg[15]_1 ,
    \slaveRegDo_mux_4_reg[14] ,
    \slaveRegDo_mux_4_reg[14]_0 ,
    \slaveRegDo_mux_4_reg[13] ,
    \slaveRegDo_mux_4_reg[13]_0 ,
    \slaveRegDo_mux_4_reg[12] ,
    \slaveRegDo_mux_4_reg[12]_0 ,
    \slaveRegDo_mux_4_reg[11] ,
    \slaveRegDo_mux_4_reg[11]_0 ,
    \slaveRegDo_mux_4_reg[10] ,
    \slaveRegDo_mux_4_reg[10]_0 ,
    \slaveRegDo_mux_4_reg[9] ,
    \slaveRegDo_mux_4_reg[9]_0 ,
    \slaveRegDo_mux_4_reg[8] ,
    \slaveRegDo_mux_4_reg[8]_0 ,
    \slaveRegDo_mux_4_reg[7] ,
    \slaveRegDo_mux_4_reg[7]_0 ,
    \slaveRegDo_mux_4_reg[6] ,
    \slaveRegDo_mux_4_reg[6]_0 ,
    \slaveRegDo_mux_4_reg[5] ,
    \slaveRegDo_mux_4_reg[5]_0 ,
    \slaveRegDo_mux_4_reg[4] ,
    \slaveRegDo_mux_4_reg[4]_0 ,
    \slaveRegDo_mux_4_reg[3] ,
    \slaveRegDo_mux_4_reg[3]_0 ,
    \slaveRegDo_mux_4_reg[2] ,
    \slaveRegDo_mux_4_reg[2]_0 ,
    \slaveRegDo_mux_4_reg[1] ,
    \slaveRegDo_mux_4_reg[1]_0 ,
    \slaveRegDo_mux_4_reg[0]_0 ,
    \slaveRegDo_mux_4_reg[0]_1 ,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 );
  output [15:0]D;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input [3:0]\slaveRegDo_mux_4_reg[0] ;
  input \slaveRegDo_mux_4_reg[15] ;
  input \slaveRegDo_mux_4_reg[15]_0 ;
  input [15:0]s_do_o;
  input [15:0]Q;
  input [15:0]\slaveRegDo_mux_4_reg[15]_1 ;
  input \slaveRegDo_mux_4_reg[14] ;
  input \slaveRegDo_mux_4_reg[14]_0 ;
  input \slaveRegDo_mux_4_reg[13] ;
  input \slaveRegDo_mux_4_reg[13]_0 ;
  input \slaveRegDo_mux_4_reg[12] ;
  input \slaveRegDo_mux_4_reg[12]_0 ;
  input \slaveRegDo_mux_4_reg[11] ;
  input \slaveRegDo_mux_4_reg[11]_0 ;
  input \slaveRegDo_mux_4_reg[10] ;
  input \slaveRegDo_mux_4_reg[10]_0 ;
  input \slaveRegDo_mux_4_reg[9] ;
  input \slaveRegDo_mux_4_reg[9]_0 ;
  input \slaveRegDo_mux_4_reg[8] ;
  input \slaveRegDo_mux_4_reg[8]_0 ;
  input \slaveRegDo_mux_4_reg[7] ;
  input \slaveRegDo_mux_4_reg[7]_0 ;
  input \slaveRegDo_mux_4_reg[6] ;
  input \slaveRegDo_mux_4_reg[6]_0 ;
  input \slaveRegDo_mux_4_reg[5] ;
  input \slaveRegDo_mux_4_reg[5]_0 ;
  input \slaveRegDo_mux_4_reg[4] ;
  input \slaveRegDo_mux_4_reg[4]_0 ;
  input \slaveRegDo_mux_4_reg[3] ;
  input \slaveRegDo_mux_4_reg[3]_0 ;
  input \slaveRegDo_mux_4_reg[2] ;
  input \slaveRegDo_mux_4_reg[2]_0 ;
  input \slaveRegDo_mux_4_reg[1] ;
  input \slaveRegDo_mux_4_reg[1]_0 ;
  input \slaveRegDo_mux_4_reg[0]_0 ;
  input \slaveRegDo_mux_4_reg[0]_1 ;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;

  wire [15:0]D;
  wire [0:0]E;
  wire [15:0]Q;
  wire \cnt[3]_i_1__12_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__12_n_0 ;
  wire \current_state[3]_i_3__12_n_0 ;
  wire \current_state[3]_i_4__12_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__12_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__12_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__12_n_0;
  wire [15:0]\slaveRegDo_muConfig[4107]_12 ;
  wire \slaveRegDo_mux_4[0]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[10]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[11]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[12]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[13]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[14]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[15]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[1]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[2]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[3]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[4]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[5]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[6]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[7]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[8]_i_2_n_0 ;
  wire \slaveRegDo_mux_4[9]_i_2_n_0 ;
  wire [3:0]\slaveRegDo_mux_4_reg[0] ;
  wire \slaveRegDo_mux_4_reg[0]_0 ;
  wire \slaveRegDo_mux_4_reg[0]_1 ;
  wire \slaveRegDo_mux_4_reg[10] ;
  wire \slaveRegDo_mux_4_reg[10]_0 ;
  wire \slaveRegDo_mux_4_reg[11] ;
  wire \slaveRegDo_mux_4_reg[11]_0 ;
  wire \slaveRegDo_mux_4_reg[12] ;
  wire \slaveRegDo_mux_4_reg[12]_0 ;
  wire \slaveRegDo_mux_4_reg[13] ;
  wire \slaveRegDo_mux_4_reg[13]_0 ;
  wire \slaveRegDo_mux_4_reg[14] ;
  wire \slaveRegDo_mux_4_reg[14]_0 ;
  wire \slaveRegDo_mux_4_reg[15] ;
  wire \slaveRegDo_mux_4_reg[15]_0 ;
  wire [15:0]\slaveRegDo_mux_4_reg[15]_1 ;
  wire \slaveRegDo_mux_4_reg[1] ;
  wire \slaveRegDo_mux_4_reg[1]_0 ;
  wire \slaveRegDo_mux_4_reg[2] ;
  wire \slaveRegDo_mux_4_reg[2]_0 ;
  wire \slaveRegDo_mux_4_reg[3] ;
  wire \slaveRegDo_mux_4_reg[3]_0 ;
  wire \slaveRegDo_mux_4_reg[4] ;
  wire \slaveRegDo_mux_4_reg[4]_0 ;
  wire \slaveRegDo_mux_4_reg[5] ;
  wire \slaveRegDo_mux_4_reg[5]_0 ;
  wire \slaveRegDo_mux_4_reg[6] ;
  wire \slaveRegDo_mux_4_reg[6]_0 ;
  wire \slaveRegDo_mux_4_reg[7] ;
  wire \slaveRegDo_mux_4_reg[7]_0 ;
  wire \slaveRegDo_mux_4_reg[8] ;
  wire \slaveRegDo_mux_4_reg[8]_0 ;
  wire \slaveRegDo_mux_4_reg[9] ;
  wire \slaveRegDo_mux_4_reg[9]_0 ;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__12 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__12 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__12 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__12 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__12_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__12_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__12_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__12 
       (.I0(\current_state[3]_i_4__12_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__12_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__12_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__12 
       (.I0(\current_state[3]_i_4__12_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__12_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__12 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__12_n_0 ),
        .I2(\current_state[3]_i_4__12_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__12 
       (.I0(\current_state[3]_i_2__12_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__12_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__12_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__12 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__12_n_0 ));
  LUT4 #(
    .INIT(16'hFFBF)) 
    \current_state[3]_i_3__12 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [0]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(\current_state_reg[3]_1 ),
        .O(\current_state[3]_i_3__12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__12 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__12_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__12
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__12_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__12_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [1]),
        .Q(\slaveRegDo_muConfig[4107]_12 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [11]),
        .Q(\slaveRegDo_muConfig[4107]_12 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [12]),
        .Q(\slaveRegDo_muConfig[4107]_12 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [13]),
        .Q(\slaveRegDo_muConfig[4107]_12 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [14]),
        .Q(\slaveRegDo_muConfig[4107]_12 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [15]),
        .Q(\slaveRegDo_muConfig[4107]_12 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4107]_12 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [2]),
        .Q(\slaveRegDo_muConfig[4107]_12 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [3]),
        .Q(\slaveRegDo_muConfig[4107]_12 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [4]),
        .Q(\slaveRegDo_muConfig[4107]_12 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [5]),
        .Q(\slaveRegDo_muConfig[4107]_12 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [6]),
        .Q(\slaveRegDo_muConfig[4107]_12 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [7]),
        .Q(\slaveRegDo_muConfig[4107]_12 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [8]),
        .Q(\slaveRegDo_muConfig[4107]_12 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [9]),
        .Q(\slaveRegDo_muConfig[4107]_12 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4107]_12 [10]),
        .Q(\slaveRegDo_muConfig[4107]_12 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__12 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__12 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__12 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__12 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__12 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__12 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__12 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__12 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__12 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__12 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__12 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__12 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__12 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__12 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__12 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__12 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__12_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__12
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__12_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__12_n_0),
        .Q(E),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[0]_i_1 
       (.I0(\slaveRegDo_mux_4[0]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[0]_0 ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[0]_1 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[0]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [0]),
        .I1(s_do_o[0]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[0]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [0]),
        .O(\slaveRegDo_mux_4[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[10]_i_1 
       (.I0(\slaveRegDo_mux_4[10]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[10] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[10]_0 ),
        .O(D[10]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[10]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [10]),
        .I1(s_do_o[10]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[10]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [10]),
        .O(\slaveRegDo_mux_4[10]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[11]_i_1 
       (.I0(\slaveRegDo_mux_4[11]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[11] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[11]_0 ),
        .O(D[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[11]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [11]),
        .I1(s_do_o[11]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[11]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [11]),
        .O(\slaveRegDo_mux_4[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[12]_i_1 
       (.I0(\slaveRegDo_mux_4[12]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[12] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[12]_0 ),
        .O(D[12]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[12]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [12]),
        .I1(s_do_o[12]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[12]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [12]),
        .O(\slaveRegDo_mux_4[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[13]_i_1 
       (.I0(\slaveRegDo_mux_4[13]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[13] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[13]_0 ),
        .O(D[13]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[13]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [13]),
        .I1(s_do_o[13]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[13]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [13]),
        .O(\slaveRegDo_mux_4[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[14]_i_1 
       (.I0(\slaveRegDo_mux_4[14]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[14] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[14]_0 ),
        .O(D[14]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[14]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [14]),
        .I1(s_do_o[14]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[14]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [14]),
        .O(\slaveRegDo_mux_4[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[15]_i_1 
       (.I0(\slaveRegDo_mux_4[15]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[15] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[15]_0 ),
        .O(D[15]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[15]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [15]),
        .I1(s_do_o[15]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[15]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [15]),
        .O(\slaveRegDo_mux_4[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[1]_i_1 
       (.I0(\slaveRegDo_mux_4[1]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[1] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[1]_0 ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[1]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [1]),
        .I1(s_do_o[1]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[1]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [1]),
        .O(\slaveRegDo_mux_4[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[2]_i_1 
       (.I0(\slaveRegDo_mux_4[2]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[2] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[2]_0 ),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[2]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [2]),
        .I1(s_do_o[2]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[2]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [2]),
        .O(\slaveRegDo_mux_4[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[3]_i_1 
       (.I0(\slaveRegDo_mux_4[3]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[3] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[3]_0 ),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[3]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [3]),
        .I1(s_do_o[3]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[3]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [3]),
        .O(\slaveRegDo_mux_4[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[4]_i_1 
       (.I0(\slaveRegDo_mux_4[4]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[4] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[4]_0 ),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[4]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [4]),
        .I1(s_do_o[4]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[4]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [4]),
        .O(\slaveRegDo_mux_4[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[5]_i_1 
       (.I0(\slaveRegDo_mux_4[5]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[5] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[5]_0 ),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[5]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [5]),
        .I1(s_do_o[5]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[5]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [5]),
        .O(\slaveRegDo_mux_4[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[6]_i_1 
       (.I0(\slaveRegDo_mux_4[6]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[6] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[6]_0 ),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[6]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [6]),
        .I1(s_do_o[6]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[6]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [6]),
        .O(\slaveRegDo_mux_4[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[7]_i_1 
       (.I0(\slaveRegDo_mux_4[7]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[7] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[7]_0 ),
        .O(D[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[7]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [7]),
        .I1(s_do_o[7]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[7]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [7]),
        .O(\slaveRegDo_mux_4[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[8]_i_1 
       (.I0(\slaveRegDo_mux_4[8]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[8] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[8]_0 ),
        .O(D[8]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[8]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [8]),
        .I1(s_do_o[8]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[8]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [8]),
        .O(\slaveRegDo_mux_4[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \slaveRegDo_mux_4[9]_i_1 
       (.I0(\slaveRegDo_mux_4[9]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_4_reg[0] [3]),
        .I2(\slaveRegDo_mux_4_reg[9] ),
        .I3(\slaveRegDo_mux_4_reg[0] [2]),
        .I4(\slaveRegDo_mux_4_reg[9]_0 ),
        .O(D[9]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[9]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [9]),
        .I1(s_do_o[9]),
        .I2(\slaveRegDo_mux_4_reg[0] [1]),
        .I3(Q[9]),
        .I4(\slaveRegDo_mux_4_reg[0] [0]),
        .I5(\slaveRegDo_mux_4_reg[15]_1 [9]),
        .O(\slaveRegDo_mux_4[9]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__11
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized11
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 );
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__13_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__13_n_0 ;
  wire \current_state[3]_i_3__13_n_0 ;
  wire \current_state[3]_i_4__13_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire data_out_sel_i_1__13_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__13_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__13_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__13 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__13 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__13 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__13 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__13_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__13_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__13_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__13 
       (.I0(\current_state[3]_i_4__13_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__13_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__13_n_0 ),
        .O(next_state[0]));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__13 
       (.I0(\current_state[3]_i_4__13_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__13 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__13_n_0 ),
        .I2(\current_state[3]_i_4__13_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__13 
       (.I0(\current_state[3]_i_2__13_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__13_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__13_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__13 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \current_state[3]_i_3__13 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__13 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__13_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__13
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__13_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__13_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__13 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__13 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__13 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__13 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__13 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__13 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__13 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__13_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__13 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__13 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__13 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__13 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__13 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__13 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__13 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__13 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__13 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__13_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__13
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__13_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__13_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__12
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized12
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__14_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__14_n_0 ;
  wire \current_state[3]_i_3__14_n_0 ;
  wire \current_state[3]_i_4__14_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__14_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__14_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__14_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__14 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__14 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__14 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__14 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__14_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__14_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__14_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__14 
       (.I0(\current_state[3]_i_4__14_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__14_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__14_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__14 
       (.I0(\current_state[3]_i_4__14_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__14 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__14_n_0 ),
        .I2(\current_state[3]_i_4__14_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__14 
       (.I0(\current_state[3]_i_2__14_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__14_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__14_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__14 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__14_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__14 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[3]_0 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__14 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__14_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__14
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__14_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__14_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__14 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__14 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__14 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__14 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__14 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__14 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__14 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__14_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__14 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__14 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__14 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__14 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__14 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__14 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__14 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__14 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__14 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__14_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__14
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__14_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__14_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__13
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized13
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__15_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__15_n_0 ;
  wire \current_state[3]_i_3__15_n_0 ;
  wire \current_state[3]_i_4__15_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__15_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__15_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__15_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__15 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__15 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__15 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__15 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__15_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__15_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__15_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__15 
       (.I0(\current_state[3]_i_4__15_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__15_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__15_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__15 
       (.I0(\current_state[3]_i_4__15_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__15 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__15_n_0 ),
        .I2(\current_state[3]_i_4__15_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__15 
       (.I0(\current_state[3]_i_2__15_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__15_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__15_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__15 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__15_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__15 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[3]_0 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__15 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__15_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__15
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__15_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__15_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__15 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__15 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__15 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__15 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__15 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__15 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__15 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__15_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__15 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__15 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__15 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__15 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__15 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__15 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__15 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__15 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__15 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__15_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__15
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__15_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__15_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__14
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized14
   (\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ,
    E,
    tc_config_cs_serial_output,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15] ,
    s_do_o,
    \slaveRegDo_mux_5_reg[15]_i_5_0 ,
    \slaveRegDo_mux_5_reg[15]_i_5_1 ,
    \slaveRegDo_mux_5_reg[14] ,
    \slaveRegDo_mux_5_reg[13] ,
    \slaveRegDo_mux_5_reg[12] ,
    \slaveRegDo_mux_5_reg[11] ,
    \slaveRegDo_mux_5_reg[10] ,
    \slaveRegDo_mux_5_reg[9] ,
    \slaveRegDo_mux_5_reg[8] ,
    \slaveRegDo_mux_5_reg[7] ,
    \slaveRegDo_mux_5_reg[6] ,
    \slaveRegDo_mux_5_reg[5] ,
    \slaveRegDo_mux_5_reg[4] ,
    \slaveRegDo_mux_5_reg[3] ,
    \slaveRegDo_mux_5_reg[2] ,
    \slaveRegDo_mux_5_reg[1] ,
    \slaveRegDo_mux_5_reg[0] ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 );
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [2:0]s_daddr_o;
  input \slaveRegDo_mux_5_reg[15] ;
  input [15:0]s_do_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_5_0 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_5_1 ;
  input \slaveRegDo_mux_5_reg[14] ;
  input \slaveRegDo_mux_5_reg[13] ;
  input \slaveRegDo_mux_5_reg[12] ;
  input \slaveRegDo_mux_5_reg[11] ;
  input \slaveRegDo_mux_5_reg[10] ;
  input \slaveRegDo_mux_5_reg[9] ;
  input \slaveRegDo_mux_5_reg[8] ;
  input \slaveRegDo_mux_5_reg[7] ;
  input \slaveRegDo_mux_5_reg[6] ;
  input \slaveRegDo_mux_5_reg[5] ;
  input \slaveRegDo_mux_5_reg[4] ;
  input \slaveRegDo_mux_5_reg[3] ;
  input \slaveRegDo_mux_5_reg[2] ;
  input \slaveRegDo_mux_5_reg[1] ;
  input \slaveRegDo_mux_5_reg[0] ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;

  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ;
  wire \cnt[3]_i_1__16_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__16_n_0 ;
  wire \current_state[3]_i_3__16_n_0 ;
  wire \current_state[3]_i_4__16_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire data_out_sel_i_1__16_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__16_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__16_n_0;
  wire \slaveRegDo_mux_5[0]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[10]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[11]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[12]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[13]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[14]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[15]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[1]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[2]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[3]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[4]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[5]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[6]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[7]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[8]_i_12_n_0 ;
  wire \slaveRegDo_mux_5[9]_i_12_n_0 ;
  wire \slaveRegDo_mux_5_reg[0] ;
  wire \slaveRegDo_mux_5_reg[10] ;
  wire \slaveRegDo_mux_5_reg[11] ;
  wire \slaveRegDo_mux_5_reg[12] ;
  wire \slaveRegDo_mux_5_reg[13] ;
  wire \slaveRegDo_mux_5_reg[14] ;
  wire \slaveRegDo_mux_5_reg[15] ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_5_0 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_5_1 ;
  wire \slaveRegDo_mux_5_reg[1] ;
  wire \slaveRegDo_mux_5_reg[2] ;
  wire \slaveRegDo_mux_5_reg[3] ;
  wire \slaveRegDo_mux_5_reg[4] ;
  wire \slaveRegDo_mux_5_reg[5] ;
  wire \slaveRegDo_mux_5_reg[6] ;
  wire \slaveRegDo_mux_5_reg[7] ;
  wire \slaveRegDo_mux_5_reg[8] ;
  wire \slaveRegDo_mux_5_reg[9] ;
  wire [15:0]\slaveRegDo_tcConfig[5123]_16 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__16 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__16 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__16 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__16 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__16_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__16_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__16_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__16 
       (.I0(\current_state[3]_i_4__16_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__16_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__16_n_0 ),
        .O(next_state[0]));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__16 
       (.I0(\current_state[3]_i_4__16_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__16 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__16_n_0 ),
        .I2(\current_state[3]_i_4__16_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__16 
       (.I0(\current_state[3]_i_2__16_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__16_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__16_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__16 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \current_state[3]_i_3__16 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__16 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__16_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__16
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__16_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__16_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [1]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [11]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [12]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [13]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [14]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [15]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5123]_16 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [2]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [3]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [4]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [5]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [6]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [7]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [8]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [9]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5123]_16 [10]),
        .Q(\slaveRegDo_tcConfig[5123]_16 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__16 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__16 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__16 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__16 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__16 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__16 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__16 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__16_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__16 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__16 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__16 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__16 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__16 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__16 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__16 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__16 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__16 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__16_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__16
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__16_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__16_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [0]),
        .O(\slaveRegDo_mux_5[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [10]),
        .O(\slaveRegDo_mux_5[10]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [11]),
        .O(\slaveRegDo_mux_5[11]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [12]),
        .O(\slaveRegDo_mux_5[12]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [13]),
        .O(\slaveRegDo_mux_5[13]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [14]),
        .O(\slaveRegDo_mux_5[14]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [15]),
        .O(\slaveRegDo_mux_5[15]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [1]),
        .O(\slaveRegDo_mux_5[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [2]),
        .O(\slaveRegDo_mux_5[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [3]),
        .O(\slaveRegDo_mux_5[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [4]),
        .O(\slaveRegDo_mux_5[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [5]),
        .O(\slaveRegDo_mux_5[5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [6]),
        .O(\slaveRegDo_mux_5[6]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [7]),
        .O(\slaveRegDo_mux_5[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [8]),
        .O(\slaveRegDo_mux_5[8]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_16 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5_0 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_1 [9]),
        .O(\slaveRegDo_mux_5[9]_i_12_n_0 ));
  MUXF7 \slaveRegDo_mux_5_reg[0]_i_5 
       (.I0(\slaveRegDo_mux_5[0]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[0] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[10]_i_5 
       (.I0(\slaveRegDo_mux_5[10]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[10] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[11]_i_5 
       (.I0(\slaveRegDo_mux_5[11]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[11] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[12]_i_5 
       (.I0(\slaveRegDo_mux_5[12]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[12] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[13]_i_5 
       (.I0(\slaveRegDo_mux_5[13]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[13] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[14]_i_5 
       (.I0(\slaveRegDo_mux_5[14]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[14] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[15]_i_5 
       (.I0(\slaveRegDo_mux_5[15]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[15] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[1]_i_5 
       (.I0(\slaveRegDo_mux_5[1]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[1] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[2]_i_5 
       (.I0(\slaveRegDo_mux_5[2]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[2] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[3]_i_5 
       (.I0(\slaveRegDo_mux_5[3]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[3] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[4]_i_5 
       (.I0(\slaveRegDo_mux_5[4]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[4] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[5]_i_5 
       (.I0(\slaveRegDo_mux_5[5]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[5] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[6]_i_5 
       (.I0(\slaveRegDo_mux_5[6]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[6] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[7]_i_5 
       (.I0(\slaveRegDo_mux_5[7]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[7] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[8]_i_5 
       (.I0(\slaveRegDo_mux_5[8]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[8] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[9]_i_5 
       (.I0(\slaveRegDo_mux_5[9]_i_12_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[9] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ),
        .S(s_daddr_o[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__15
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized15
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__17_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__17_n_0 ;
  wire \current_state[3]_i_3__17_n_0 ;
  wire \current_state[3]_i_4__17_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__17_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__17_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__17_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__17 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__17 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__17 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__17 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__17_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__17_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__17_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__17 
       (.I0(\current_state[3]_i_4__17_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__17_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__17_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__17 
       (.I0(\current_state[3]_i_4__17_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__17 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__17_n_0 ),
        .I2(\current_state[3]_i_4__17_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__17 
       (.I0(\current_state[3]_i_2__17_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__17_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__17_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__17 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \current_state[3]_i_3__17 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__17 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__17_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__17
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__17_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__17_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__17 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__17 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__17 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__17 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__17 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__17 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__17 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__17_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__17 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__17 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__17 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__17 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__17 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__17 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__17 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__17 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__17 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__17_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__17
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__17_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__17_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__16
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized16
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__18_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__18_n_0 ;
  wire \current_state[3]_i_3__18_n_0 ;
  wire \current_state[3]_i_4__18_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__18_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__18_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__18_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__18 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__18 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__18 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__18 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__18_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__18_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__18_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__18 
       (.I0(\current_state[3]_i_4__18_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__18_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__18_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__18 
       (.I0(\current_state[3]_i_4__18_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__18 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__18_n_0 ),
        .I2(\current_state[3]_i_4__18_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__18 
       (.I0(\current_state[3]_i_2__18_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__18_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__18_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__18 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__18_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__18 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[3]_0 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__18 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__18_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__18
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__18_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__18_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__18 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__18 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__18 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__18 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__18 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__18 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__18 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__18_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__18 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__18 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__18 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__18 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__18 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__18 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__18 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__18 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__18 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__18_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__18
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__18_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__18_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__17
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized17
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__19_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__19_n_0 ;
  wire \current_state[3]_i_3__19_n_0 ;
  wire \current_state[3]_i_4__19_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__19_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__19_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__19_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__19 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__19 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__19 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__19 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__19_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__19_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__19_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__19 
       (.I0(\current_state[3]_i_4__19_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__19_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__19_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__19 
       (.I0(\current_state[3]_i_4__19_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__19 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__19_n_0 ),
        .I2(\current_state[3]_i_4__19_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__19 
       (.I0(\current_state[3]_i_2__19_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__19_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__19_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__19 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__19_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__19 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[3]_0 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__19 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__19_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__19
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__19_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__19_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__19 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__19 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__19 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__19 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__19 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__19 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__19 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__19_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__19 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__19 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__19 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__19 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__19 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__19 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__19 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__19 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__19 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__19_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__19
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__19_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__19_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__18
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized18
   (\parallel_dout_reg[15]_0 ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[10]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[7]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    \parallel_dout_reg[4]_0 ,
    \parallel_dout_reg[3]_0 ,
    \parallel_dout_reg[2]_0 ,
    \parallel_dout_reg[1]_0 ,
    \parallel_dout_reg[0]_0 ,
    E,
    tc_config_cs_serial_output,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15]_i_5 ,
    \slaveRegDo_mux_5_reg[15]_i_5_0 ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \parallel_dout_reg[15]_0 ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[10]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[7]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output \parallel_dout_reg[4]_0 ;
  output \parallel_dout_reg[3]_0 ;
  output \parallel_dout_reg[2]_0 ;
  output \parallel_dout_reg[1]_0 ;
  output \parallel_dout_reg[0]_0 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [15:0]s_do_o;
  input [5:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_5 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_5_0 ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__20_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__20_n_0 ;
  wire \current_state[3]_i_3__20_n_0 ;
  wire \current_state[3]_i_4__20_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__20_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[0]_0 ;
  wire \parallel_dout_reg[10]_0 ;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire \parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[1]_0 ;
  wire \parallel_dout_reg[2]_0 ;
  wire \parallel_dout_reg[3]_0 ;
  wire \parallel_dout_reg[4]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[7]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__20_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__20_n_0;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_5 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_5_0 ;
  wire [15:0]\slaveRegDo_tcConfig[5127]_20 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__20 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__20 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__20 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__20 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__20_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__20_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__20_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__20 
       (.I0(\current_state[3]_i_4__20_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__20_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__20_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__20 
       (.I0(\current_state[3]_i_4__20_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__20 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__20_n_0 ),
        .I2(\current_state[3]_i_4__20_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__20 
       (.I0(\current_state[3]_i_2__20_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__20_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__20_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__20 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \current_state[3]_i_3__20 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__20 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__20_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__20
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__20_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__20_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [1]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [11]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [12]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [13]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [14]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [15]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5127]_20 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [2]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [3]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [4]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [5]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [6]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [7]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [8]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [9]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5127]_20 [10]),
        .Q(\slaveRegDo_tcConfig[5127]_20 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__20 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__20 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__20 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__20 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__20 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__20 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__20 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__20_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__20 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__20 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__20 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__20 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__20 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__20 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__20 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__20 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__20 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__20_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__20
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__20_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__20_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [0]),
        .O(\parallel_dout_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [10]),
        .O(\parallel_dout_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [15]),
        .O(\parallel_dout_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [1]),
        .O(\parallel_dout_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [2]),
        .O(\parallel_dout_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [3]),
        .O(\parallel_dout_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [4]),
        .O(\parallel_dout_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [7]),
        .O(\parallel_dout_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_20 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_5 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_5_0 [9]),
        .O(\parallel_dout_reg[9]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__19
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized19
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__21_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__21_n_0 ;
  wire \current_state[3]_i_3__21_n_0 ;
  wire \current_state[3]_i_4__21_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__21_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__21_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__21_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__21 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__21 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__21 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__21 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__21_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__21_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__21_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__21_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__21 
       (.I0(\current_state[3]_i_4__21_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__21_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__21_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__21 
       (.I0(\current_state[3]_i_4__21_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__21 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__21_n_0 ),
        .I2(\current_state[3]_i_4__21_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__21 
       (.I0(\current_state[3]_i_2__21_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__21_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__21_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__21 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__21_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \current_state[3]_i_3__21 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__21 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__21_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__21
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__21_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__21_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__21 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__21 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__21 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__21 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__21 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__21 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__21 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__21_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__21 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__21 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__21 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__21 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__21 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__21 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__21 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__21 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__21 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__21_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__21
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__21_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__21_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__20
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized2
   (\parallel_dout_reg[15]_0 ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[10]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[7]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    \parallel_dout_reg[4]_0 ,
    \parallel_dout_reg[3]_0 ,
    \parallel_dout_reg[2]_0 ,
    \parallel_dout_reg[1]_0 ,
    \parallel_dout_reg[0]_0 ,
    E,
    mu_config_cs_serial_output,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_4_reg[15] ,
    \slaveRegDo_mux_4_reg[15]_0 ,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \parallel_dout_reg[15]_0 ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[10]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[7]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output \parallel_dout_reg[4]_0 ;
  output \parallel_dout_reg[3]_0 ;
  output \parallel_dout_reg[2]_0 ;
  output \parallel_dout_reg[1]_0 ;
  output \parallel_dout_reg[0]_0 ;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input [15:0]s_do_o;
  input [1:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_4_reg[15] ;
  input [15:0]\slaveRegDo_mux_4_reg[15]_0 ;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__4_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__4_n_0 ;
  wire \current_state[3]_i_3__4_n_0 ;
  wire \current_state[3]_i_4__4_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__4_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[0]_0 ;
  wire \parallel_dout_reg[10]_0 ;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire \parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[1]_0 ;
  wire \parallel_dout_reg[2]_0 ;
  wire \parallel_dout_reg[3]_0 ;
  wire \parallel_dout_reg[4]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[7]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__4_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__4_n_0;
  wire [15:0]\slaveRegDo_muConfig[4099]_4 ;
  wire [15:0]\slaveRegDo_mux_4_reg[15] ;
  wire [15:0]\slaveRegDo_mux_4_reg[15]_0 ;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__4 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__4 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__4 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__4 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__4_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__4_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__4_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__4 
       (.I0(\current_state[3]_i_4__4_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__4_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__4_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__4 
       (.I0(\current_state[3]_i_4__4_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__4 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__4_n_0 ),
        .I2(\current_state[3]_i_4__4_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__4 
       (.I0(\current_state[3]_i_2__4_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__4_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__4_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__4 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__4_n_0 ));
  LUT4 #(
    .INIT(16'hFFBF)) 
    \current_state[3]_i_3__4 
       (.I0(\current_state_reg[1]_1 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_0 ),
        .O(\current_state[3]_i_3__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__4 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__4_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__4
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__4_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__4_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [1]),
        .Q(\slaveRegDo_muConfig[4099]_4 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [11]),
        .Q(\slaveRegDo_muConfig[4099]_4 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [12]),
        .Q(\slaveRegDo_muConfig[4099]_4 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [13]),
        .Q(\slaveRegDo_muConfig[4099]_4 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [14]),
        .Q(\slaveRegDo_muConfig[4099]_4 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [15]),
        .Q(\slaveRegDo_muConfig[4099]_4 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4099]_4 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [2]),
        .Q(\slaveRegDo_muConfig[4099]_4 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [3]),
        .Q(\slaveRegDo_muConfig[4099]_4 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [4]),
        .Q(\slaveRegDo_muConfig[4099]_4 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [5]),
        .Q(\slaveRegDo_muConfig[4099]_4 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [6]),
        .Q(\slaveRegDo_muConfig[4099]_4 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [7]),
        .Q(\slaveRegDo_muConfig[4099]_4 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [8]),
        .Q(\slaveRegDo_muConfig[4099]_4 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [9]),
        .Q(\slaveRegDo_muConfig[4099]_4 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4099]_4 [10]),
        .Q(\slaveRegDo_muConfig[4099]_4 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__4 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__4 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__4 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__4 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__4 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__4 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__4 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__4 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__4 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__4 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__4 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__4 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__4 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__4 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__4 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__4 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__4_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__4
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__4_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__4_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[0]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [0]),
        .O(\parallel_dout_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[10]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [10]),
        .O(\parallel_dout_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[11]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[12]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[13]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[14]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[15]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [15]),
        .O(\parallel_dout_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[1]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [1]),
        .O(\parallel_dout_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[2]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [2]),
        .O(\parallel_dout_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[3]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [3]),
        .O(\parallel_dout_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[4]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [4]),
        .O(\parallel_dout_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[5]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[6]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[7]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [7]),
        .O(\parallel_dout_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[8]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[9]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [9]),
        .O(\parallel_dout_reg[9]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__3
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized20
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__22_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__22_n_0 ;
  wire \current_state[3]_i_3__22_n_0 ;
  wire \current_state[3]_i_4__22_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__22_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__22_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__22_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__22 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__22 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__22 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__22 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__22_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__22_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__22_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__22_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__22 
       (.I0(\current_state[3]_i_4__22_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__22_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__22_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__22 
       (.I0(\current_state[3]_i_4__22_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__22 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__22_n_0 ),
        .I2(\current_state[3]_i_4__22_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__22 
       (.I0(\current_state[3]_i_2__22_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__22_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__22_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__22 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__22_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__22 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[3]_0 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__22 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__22_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__22
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__22_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__22_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__22 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__22 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__22 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__22 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__22 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__22 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__22 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__22_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__22 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__22 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__22 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__22 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__22 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__22 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__22 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__22 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__22 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__22_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__22
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__22_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__22_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__21
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized21
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__23_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__23_n_0 ;
  wire \current_state[3]_i_3__23_n_0 ;
  wire \current_state[3]_i_4__23_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__23_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__23_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__23_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__23 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__23 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__23 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__23 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__23_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__23_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__23_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__23_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__23 
       (.I0(\current_state[3]_i_4__23_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__23_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__23_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__23 
       (.I0(\current_state[3]_i_4__23_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__23 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__23_n_0 ),
        .I2(\current_state[3]_i_4__23_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__23 
       (.I0(\current_state[3]_i_2__23_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__23_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__23_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__23 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__23_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__23 
       (.I0(\current_state_reg[1]_1 ),
        .I1(\current_state_reg[3]_0 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__23 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__23_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__23
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__23_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__23_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__23 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__23 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__23 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__23 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__23 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__23 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__23 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__23_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__23 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__23 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__23 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__23 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__23 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__23 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__23 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__23 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__23 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__23_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__23
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__23_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__23_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__22
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized22
   (\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ,
    E,
    tc_config_cs_serial_output,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15] ,
    s_do_o,
    Q,
    \slaveRegDo_mux_5_reg[15]_i_4_0 ,
    \slaveRegDo_mux_5_reg[14] ,
    \slaveRegDo_mux_5_reg[13] ,
    \slaveRegDo_mux_5_reg[12] ,
    \slaveRegDo_mux_5_reg[11] ,
    \slaveRegDo_mux_5_reg[10] ,
    \slaveRegDo_mux_5_reg[9] ,
    \slaveRegDo_mux_5_reg[8] ,
    \slaveRegDo_mux_5_reg[7] ,
    \slaveRegDo_mux_5_reg[6] ,
    \slaveRegDo_mux_5_reg[5] ,
    \slaveRegDo_mux_5_reg[4] ,
    \slaveRegDo_mux_5_reg[3] ,
    \slaveRegDo_mux_5_reg[2] ,
    \slaveRegDo_mux_5_reg[1] ,
    \slaveRegDo_mux_5_reg[0] ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [5:0]s_daddr_o;
  input \slaveRegDo_mux_5_reg[15] ;
  input [15:0]s_do_o;
  input [15:0]Q;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_4_0 ;
  input \slaveRegDo_mux_5_reg[14] ;
  input \slaveRegDo_mux_5_reg[13] ;
  input \slaveRegDo_mux_5_reg[12] ;
  input \slaveRegDo_mux_5_reg[11] ;
  input \slaveRegDo_mux_5_reg[10] ;
  input \slaveRegDo_mux_5_reg[9] ;
  input \slaveRegDo_mux_5_reg[8] ;
  input \slaveRegDo_mux_5_reg[7] ;
  input \slaveRegDo_mux_5_reg[6] ;
  input \slaveRegDo_mux_5_reg[5] ;
  input \slaveRegDo_mux_5_reg[4] ;
  input \slaveRegDo_mux_5_reg[3] ;
  input \slaveRegDo_mux_5_reg[2] ;
  input \slaveRegDo_mux_5_reg[1] ;
  input \slaveRegDo_mux_5_reg[0] ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ;
  wire [15:0]Q;
  wire \cnt[3]_i_1__24_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__24_n_0 ;
  wire \current_state[3]_i_3__24_n_0 ;
  wire \current_state[3]_i_4__24_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__24_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__24_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__24_n_0;
  wire \slaveRegDo_mux_5[0]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[10]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[11]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[12]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[13]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[14]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[15]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[1]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[2]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[3]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[4]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[5]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[6]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[7]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[8]_i_10_n_0 ;
  wire \slaveRegDo_mux_5[9]_i_10_n_0 ;
  wire \slaveRegDo_mux_5_reg[0] ;
  wire \slaveRegDo_mux_5_reg[10] ;
  wire \slaveRegDo_mux_5_reg[11] ;
  wire \slaveRegDo_mux_5_reg[12] ;
  wire \slaveRegDo_mux_5_reg[13] ;
  wire \slaveRegDo_mux_5_reg[14] ;
  wire \slaveRegDo_mux_5_reg[15] ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_4_0 ;
  wire \slaveRegDo_mux_5_reg[1] ;
  wire \slaveRegDo_mux_5_reg[2] ;
  wire \slaveRegDo_mux_5_reg[3] ;
  wire \slaveRegDo_mux_5_reg[4] ;
  wire \slaveRegDo_mux_5_reg[5] ;
  wire \slaveRegDo_mux_5_reg[6] ;
  wire \slaveRegDo_mux_5_reg[7] ;
  wire \slaveRegDo_mux_5_reg[8] ;
  wire \slaveRegDo_mux_5_reg[9] ;
  wire [15:0]\slaveRegDo_tcConfig[5131]_24 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__24 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__24 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__24 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__24 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__24_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__24_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__24_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__24_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__24 
       (.I0(\current_state[3]_i_4__24_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__24_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__24_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__24 
       (.I0(\current_state[3]_i_4__24_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__24 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__24_n_0 ),
        .I2(\current_state[3]_i_4__24_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__24 
       (.I0(\current_state[3]_i_2__24_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__24_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__24_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__24 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__24_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \current_state[3]_i_3__24 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__24 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__24_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__24
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__24_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__24_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [1]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [11]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [12]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [13]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [14]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [15]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5131]_24 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [2]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [3]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [4]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [5]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [6]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [7]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [8]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [9]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5131]_24 [10]),
        .Q(\slaveRegDo_tcConfig[5131]_24 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__24 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__24 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__24 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__24 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__24 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__24 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__24 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__24_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__24 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__24 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__24 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__24 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__24 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__24 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__24 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__24 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__24 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__24_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__24
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__24_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__24_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(Q[0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [0]),
        .O(\slaveRegDo_mux_5[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(Q[10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [10]),
        .O(\slaveRegDo_mux_5[10]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(Q[11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [11]),
        .O(\slaveRegDo_mux_5[11]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(Q[12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [12]),
        .O(\slaveRegDo_mux_5[12]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(Q[13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [13]),
        .O(\slaveRegDo_mux_5[13]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(Q[14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [14]),
        .O(\slaveRegDo_mux_5[14]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(Q[15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [15]),
        .O(\slaveRegDo_mux_5[15]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(Q[1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [1]),
        .O(\slaveRegDo_mux_5[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(Q[2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [2]),
        .O(\slaveRegDo_mux_5[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(Q[3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [3]),
        .O(\slaveRegDo_mux_5[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(Q[4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [4]),
        .O(\slaveRegDo_mux_5[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(Q[5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [5]),
        .O(\slaveRegDo_mux_5[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(Q[6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [6]),
        .O(\slaveRegDo_mux_5[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(Q[7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [7]),
        .O(\slaveRegDo_mux_5[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(Q[8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [8]),
        .O(\slaveRegDo_mux_5[8]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_24 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(Q[9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [9]),
        .O(\slaveRegDo_mux_5[9]_i_10_n_0 ));
  MUXF7 \slaveRegDo_mux_5_reg[0]_i_4 
       (.I0(\slaveRegDo_mux_5[0]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[0] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[10]_i_4 
       (.I0(\slaveRegDo_mux_5[10]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[10] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[11]_i_4 
       (.I0(\slaveRegDo_mux_5[11]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[11] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[12]_i_4 
       (.I0(\slaveRegDo_mux_5[12]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[12] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[13]_i_4 
       (.I0(\slaveRegDo_mux_5[13]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[13] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[14]_i_4 
       (.I0(\slaveRegDo_mux_5[14]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[14] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[15]_i_4 
       (.I0(\slaveRegDo_mux_5[15]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[15] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[1]_i_4 
       (.I0(\slaveRegDo_mux_5[1]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[1] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[2]_i_4 
       (.I0(\slaveRegDo_mux_5[2]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[2] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[3]_i_4 
       (.I0(\slaveRegDo_mux_5[3]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[3] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[4]_i_4 
       (.I0(\slaveRegDo_mux_5[4]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[4] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[5]_i_4 
       (.I0(\slaveRegDo_mux_5[5]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[5] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[6]_i_4 
       (.I0(\slaveRegDo_mux_5[6]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[6] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[7]_i_4 
       (.I0(\slaveRegDo_mux_5[7]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[7] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[8]_i_4 
       (.I0(\slaveRegDo_mux_5[8]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[8] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[9]_i_4 
       (.I0(\slaveRegDo_mux_5[9]_i_10_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[9] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ),
        .S(s_daddr_o[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__23
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized23
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__25_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__25_n_0 ;
  wire \current_state[3]_i_3__25_n_0 ;
  wire \current_state[3]_i_4__25_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__25_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__25_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__25_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__25 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__25 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__25 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__25 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__25_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__25_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__25_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__25 
       (.I0(\current_state[3]_i_4__25_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__25_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__25_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__25 
       (.I0(\current_state[3]_i_4__25_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__25 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__25_n_0 ),
        .I2(\current_state[3]_i_4__25_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__25 
       (.I0(\current_state[3]_i_2__25_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__25_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__25_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__25 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    \current_state[3]_i_3__25 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__25 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__25_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__25
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__25_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__25_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__25 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__25 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__25 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__25 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__25 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__25 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__25 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__25_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__25 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__25 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__25 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__25 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__25 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__25 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__25 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__25 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__25 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__25_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__25
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__25_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__25_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__24
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized24
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__26_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__26_n_0 ;
  wire \current_state[3]_i_3__26_n_0 ;
  wire \current_state[3]_i_4__26_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__26_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__26_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__26_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__26 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__26 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__26 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__26 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__26_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__26_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__26_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__26 
       (.I0(\current_state[3]_i_4__26_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__26_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__26_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__26 
       (.I0(\current_state[3]_i_4__26_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__26 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__26_n_0 ),
        .I2(\current_state[3]_i_4__26_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__26 
       (.I0(\current_state[3]_i_2__26_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__26_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__26_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__26 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    \current_state[3]_i_3__26 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__26 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__26_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__26
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__26_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__26_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__26 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__26 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__26 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__26 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__26 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__26 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__26 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__26_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__26 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__26 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__26 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__26 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__26 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__26 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__26 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__26 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__26 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__26_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__26
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__26_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__26_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__25
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized25
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__27_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__27_n_0 ;
  wire \current_state[3]_i_3__27_n_0 ;
  wire \current_state[3]_i_4__27_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__27_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__27_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__27_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__27 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__27 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__27 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__27 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__27_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__27_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__27_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__27_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__27 
       (.I0(\current_state[3]_i_4__27_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__27_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__27_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__27 
       (.I0(\current_state[3]_i_4__27_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__27 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__27_n_0 ),
        .I2(\current_state[3]_i_4__27_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__27 
       (.I0(\current_state[3]_i_2__27_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__27_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__27_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__27 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__27_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    \current_state[3]_i_3__27 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__27 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__27_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__27
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__27_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__27_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__27 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__27 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__27 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__27 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__27 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__27 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__27 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__27_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__27 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__27 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__27 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__27 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__27 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__27 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__27 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__27 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__27 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__27_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__27
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__27_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__27_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__26
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized26
   (\parallel_dout_reg[15]_0 ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[10]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[7]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    \parallel_dout_reg[4]_0 ,
    \parallel_dout_reg[3]_0 ,
    \parallel_dout_reg[2]_0 ,
    \parallel_dout_reg[1]_0 ,
    \parallel_dout_reg[0]_0 ,
    E,
    tc_config_cs_serial_output,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15]_i_4 ,
    \slaveRegDo_mux_5_reg[15]_i_4_0 ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \parallel_dout_reg[15]_0 ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[10]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[7]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output \parallel_dout_reg[4]_0 ;
  output \parallel_dout_reg[3]_0 ;
  output \parallel_dout_reg[2]_0 ;
  output \parallel_dout_reg[1]_0 ;
  output \parallel_dout_reg[0]_0 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [15:0]s_do_o;
  input [5:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_4 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_4_0 ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__28_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__28_n_0 ;
  wire \current_state[3]_i_3__28_n_0 ;
  wire \current_state[3]_i_4__28_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__28_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[0]_0 ;
  wire \parallel_dout_reg[10]_0 ;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire \parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[1]_0 ;
  wire \parallel_dout_reg[2]_0 ;
  wire \parallel_dout_reg[3]_0 ;
  wire \parallel_dout_reg[4]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[7]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__28_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__28_n_0;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_4 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_4_0 ;
  wire [15:0]\slaveRegDo_tcConfig[5135]_28 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__28 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__28 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__28 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__28 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__28_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__28_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__28_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__28_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__28 
       (.I0(\current_state[3]_i_4__28_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__28_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__28_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__28 
       (.I0(\current_state[3]_i_4__28_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__28 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__28_n_0 ),
        .I2(\current_state[3]_i_4__28_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__28 
       (.I0(\current_state[3]_i_2__28_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__28_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__28_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__28 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__28_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    \current_state[3]_i_3__28 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__28 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__28_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__28
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__28_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__28_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [1]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [11]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [12]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [13]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [14]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [15]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5135]_28 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [2]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [3]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [4]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [5]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [6]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [7]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [8]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [9]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5135]_28 [10]),
        .Q(\slaveRegDo_tcConfig[5135]_28 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__28 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__28 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__28 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__28 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__28 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__28 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__28 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__28_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__28 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__28 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__28 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__28 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__28 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__28 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__28 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__28 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__28 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__28_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__28
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__28_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__28_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [0]),
        .O(\parallel_dout_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [10]),
        .O(\parallel_dout_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [15]),
        .O(\parallel_dout_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [1]),
        .O(\parallel_dout_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [2]),
        .O(\parallel_dout_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [3]),
        .O(\parallel_dout_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [4]),
        .O(\parallel_dout_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [7]),
        .O(\parallel_dout_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_28 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_4 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_4_0 [9]),
        .O(\parallel_dout_reg[9]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__27
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized27
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__29_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__29_n_0 ;
  wire \current_state[3]_i_3__29_n_0 ;
  wire \current_state[3]_i_4__29_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__29_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__29_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__29_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__29 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__29 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__29 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__29_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__29 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__29_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__29_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__29_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__29 
       (.I0(\current_state[3]_i_4__29_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__29_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__29_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__29 
       (.I0(\current_state[3]_i_4__29_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__29 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__29_n_0 ),
        .I2(\current_state[3]_i_4__29_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__29 
       (.I0(\current_state[3]_i_2__29_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__29_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__29_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__29 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \current_state[3]_i_3__29 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__29_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__29 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__29_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__29
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__29_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__29_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__29 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__29 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__29 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__29 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__29 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__29 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__29 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__29_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__29 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__29 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__29 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__29 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__29 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__29 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__29 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__29 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__29 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__29_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__29
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__29_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__29_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__28
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized28
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__30_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__30_n_0 ;
  wire \current_state[3]_i_3__30_n_0 ;
  wire \current_state[3]_i_4__30_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__30_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__30_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__30_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__30 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__30 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__30 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__30 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__30_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__30_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__30_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__30_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__30 
       (.I0(\current_state[3]_i_4__30_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__30_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__30_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__30 
       (.I0(\current_state[3]_i_4__30_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__30 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__30_n_0 ),
        .I2(\current_state[3]_i_4__30_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__30 
       (.I0(\current_state[3]_i_2__30_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__30_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__30_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__30 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__30_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \current_state[3]_i_3__30 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__30 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__30_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__30
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__30_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__30_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__30 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__30 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__30 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__30 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__30 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__30 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__30 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__30_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__30 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__30 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__30 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__30 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__30 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__30 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__30 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__30 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__30 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__30_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__30
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__30_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__30_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__29
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized29
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__31_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__31_n_0 ;
  wire \current_state[3]_i_3__31_n_0 ;
  wire \current_state[3]_i_4__31_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__31_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__31_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__31_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__31 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__31 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__31 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__31 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__31_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__31_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__31_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__31_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__31 
       (.I0(\current_state[3]_i_4__31_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__31_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__31_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__31 
       (.I0(\current_state[3]_i_4__31_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__31 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__31_n_0 ),
        .I2(\current_state[3]_i_4__31_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__31 
       (.I0(\current_state[3]_i_2__31_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__31_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__31_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__31 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__31_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \current_state[3]_i_3__31 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__31 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__31_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__31
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__31_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__31_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__31 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__31 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__31 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__31 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__31 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__31 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__31 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__31_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__31 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__31 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__31 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__31 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__31 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__31 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__31 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__31 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__31 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__31_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__31
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__31_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__31_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__30
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized3
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    s_daddr_o,
    \current_state_reg[3]_0 );
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input [1:0]s_daddr_o;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__5_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__5_n_0 ;
  wire \current_state[3]_i_3__5_n_0 ;
  wire \current_state[3]_i_4__5_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__5_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__5_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__5_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__5 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__5 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__5 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__5 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__5_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__5_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__5_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__5 
       (.I0(\current_state[3]_i_4__5_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__5_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__5_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__5 
       (.I0(\current_state[3]_i_4__5_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__5 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__5_n_0 ),
        .I2(\current_state[3]_i_4__5_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__5 
       (.I0(\current_state[3]_i_2__5_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__5_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__5_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__5 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__5_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[3]_i_3__5 
       (.I0(\current_state_reg[1]_1 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_0 ),
        .O(\current_state[3]_i_3__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__5 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__5_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__5
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__5_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__5_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__5 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__5 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__5 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__5 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__5 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__5 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__5 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__5 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__5 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__5 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__5 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__5 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__5 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__5 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__5 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__5 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__5_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__5
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__5_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__5_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__4
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized30
   (\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ,
    E,
    tc_config_cs_serial_output,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15] ,
    s_do_o,
    \slaveRegDo_mux_5_reg[15]_i_3_0 ,
    \slaveRegDo_mux_5_reg[15]_i_3_1 ,
    \slaveRegDo_mux_5_reg[14] ,
    \slaveRegDo_mux_5_reg[13] ,
    \slaveRegDo_mux_5_reg[12] ,
    \slaveRegDo_mux_5_reg[11] ,
    \slaveRegDo_mux_5_reg[10] ,
    \slaveRegDo_mux_5_reg[9] ,
    \slaveRegDo_mux_5_reg[8] ,
    \slaveRegDo_mux_5_reg[7] ,
    \slaveRegDo_mux_5_reg[6] ,
    \slaveRegDo_mux_5_reg[5] ,
    \slaveRegDo_mux_5_reg[4] ,
    \slaveRegDo_mux_5_reg[3] ,
    \slaveRegDo_mux_5_reg[2] ,
    \slaveRegDo_mux_5_reg[1] ,
    \slaveRegDo_mux_5_reg[0] ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [5:0]s_daddr_o;
  input \slaveRegDo_mux_5_reg[15] ;
  input [15:0]s_do_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_3_0 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_3_1 ;
  input \slaveRegDo_mux_5_reg[14] ;
  input \slaveRegDo_mux_5_reg[13] ;
  input \slaveRegDo_mux_5_reg[12] ;
  input \slaveRegDo_mux_5_reg[11] ;
  input \slaveRegDo_mux_5_reg[10] ;
  input \slaveRegDo_mux_5_reg[9] ;
  input \slaveRegDo_mux_5_reg[8] ;
  input \slaveRegDo_mux_5_reg[7] ;
  input \slaveRegDo_mux_5_reg[6] ;
  input \slaveRegDo_mux_5_reg[5] ;
  input \slaveRegDo_mux_5_reg[4] ;
  input \slaveRegDo_mux_5_reg[3] ;
  input \slaveRegDo_mux_5_reg[2] ;
  input \slaveRegDo_mux_5_reg[1] ;
  input \slaveRegDo_mux_5_reg[0] ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ;
  wire \cnt[3]_i_1__32_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__32_n_0 ;
  wire \current_state[3]_i_3__32_n_0 ;
  wire \current_state[3]_i_4__32_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__32_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__32_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__32_n_0;
  wire \slaveRegDo_mux_5[0]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[10]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[11]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[12]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[13]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[14]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[15]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[1]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[2]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[3]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[4]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[5]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[6]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[7]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[8]_i_8_n_0 ;
  wire \slaveRegDo_mux_5[9]_i_8_n_0 ;
  wire \slaveRegDo_mux_5_reg[0] ;
  wire \slaveRegDo_mux_5_reg[10] ;
  wire \slaveRegDo_mux_5_reg[11] ;
  wire \slaveRegDo_mux_5_reg[12] ;
  wire \slaveRegDo_mux_5_reg[13] ;
  wire \slaveRegDo_mux_5_reg[14] ;
  wire \slaveRegDo_mux_5_reg[15] ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_3_0 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_3_1 ;
  wire \slaveRegDo_mux_5_reg[1] ;
  wire \slaveRegDo_mux_5_reg[2] ;
  wire \slaveRegDo_mux_5_reg[3] ;
  wire \slaveRegDo_mux_5_reg[4] ;
  wire \slaveRegDo_mux_5_reg[5] ;
  wire \slaveRegDo_mux_5_reg[6] ;
  wire \slaveRegDo_mux_5_reg[7] ;
  wire \slaveRegDo_mux_5_reg[8] ;
  wire \slaveRegDo_mux_5_reg[9] ;
  wire [15:0]\slaveRegDo_tcConfig[5139]_32 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__32 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__32 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__32 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__32_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__32 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__32_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__32_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__32_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__32_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__32 
       (.I0(\current_state[3]_i_4__32_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__32_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__32_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__32 
       (.I0(\current_state[3]_i_4__32_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__32 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__32_n_0 ),
        .I2(\current_state[3]_i_4__32_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__32 
       (.I0(\current_state[3]_i_2__32_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__32_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__32_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__32 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__32_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \current_state[3]_i_3__32 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__32_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__32 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__32_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__32
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__32_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__32_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [1]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [11]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [12]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [13]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [14]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [15]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5139]_32 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [2]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [3]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [4]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [5]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [6]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [7]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [8]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [9]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5139]_32 [10]),
        .Q(\slaveRegDo_tcConfig[5139]_32 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__32 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__32 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__32 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__32 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__32 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__32 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__32 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__32_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__32 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__32 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__32 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__32 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__32 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__32 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__32 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__32 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__32 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__32_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__32
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__32_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__32_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [0]),
        .O(\slaveRegDo_mux_5[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [10]),
        .O(\slaveRegDo_mux_5[10]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [11]),
        .O(\slaveRegDo_mux_5[11]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [12]),
        .O(\slaveRegDo_mux_5[12]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [13]),
        .O(\slaveRegDo_mux_5[13]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [14]),
        .O(\slaveRegDo_mux_5[14]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [15]),
        .O(\slaveRegDo_mux_5[15]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [1]),
        .O(\slaveRegDo_mux_5[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [2]),
        .O(\slaveRegDo_mux_5[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [3]),
        .O(\slaveRegDo_mux_5[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [4]),
        .O(\slaveRegDo_mux_5[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [5]),
        .O(\slaveRegDo_mux_5[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [6]),
        .O(\slaveRegDo_mux_5[6]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [7]),
        .O(\slaveRegDo_mux_5[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [8]),
        .O(\slaveRegDo_mux_5[8]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_32 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3_0 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_1 [9]),
        .O(\slaveRegDo_mux_5[9]_i_8_n_0 ));
  MUXF7 \slaveRegDo_mux_5_reg[0]_i_3 
       (.I0(\slaveRegDo_mux_5[0]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[0] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[10]_i_3 
       (.I0(\slaveRegDo_mux_5[10]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[10] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[11]_i_3 
       (.I0(\slaveRegDo_mux_5[11]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[11] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[12]_i_3 
       (.I0(\slaveRegDo_mux_5[12]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[12] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[13]_i_3 
       (.I0(\slaveRegDo_mux_5[13]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[13] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[14]_i_3 
       (.I0(\slaveRegDo_mux_5[14]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[14] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[15]_i_3 
       (.I0(\slaveRegDo_mux_5[15]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[15] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[1]_i_3 
       (.I0(\slaveRegDo_mux_5[1]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[1] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[2]_i_3 
       (.I0(\slaveRegDo_mux_5[2]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[2] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[3]_i_3 
       (.I0(\slaveRegDo_mux_5[3]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[3] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[4]_i_3 
       (.I0(\slaveRegDo_mux_5[4]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[4] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[5]_i_3 
       (.I0(\slaveRegDo_mux_5[5]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[5] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[6]_i_3 
       (.I0(\slaveRegDo_mux_5[6]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[6] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[7]_i_3 
       (.I0(\slaveRegDo_mux_5[7]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[7] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[8]_i_3 
       (.I0(\slaveRegDo_mux_5[8]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[8] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[9]_i_3 
       (.I0(\slaveRegDo_mux_5[9]_i_8_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[9] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 ),
        .S(s_daddr_o[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__31
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized31
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__33_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__33_n_0 ;
  wire \current_state[3]_i_3__33_n_0 ;
  wire \current_state[3]_i_4__33_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__33_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__33_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__33_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__33 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__33 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__33 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__33_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__33 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__33_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__33_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__33_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__33_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__33 
       (.I0(\current_state[3]_i_4__33_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__33_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__33_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__33 
       (.I0(\current_state[3]_i_4__33_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__33 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__33_n_0 ),
        .I2(\current_state[3]_i_4__33_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__33 
       (.I0(\current_state[3]_i_2__33_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__33_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__33_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__33 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__33_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__33 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__33_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__33 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__33_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__33
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__33_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__33_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__33 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__33 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__33 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__33 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__33 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__33 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__33 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__33_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__33 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__33 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__33 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__33 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__33 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__33 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__33 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__33 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__33 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__33_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__33
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__33_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__33_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__32
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized32
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__34_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__34_n_0 ;
  wire \current_state[3]_i_3__34_n_0 ;
  wire \current_state[3]_i_4__34_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__34_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__34_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__34_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__34 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__34 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__34 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__34_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__34 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__34_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__34_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__34_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__34_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__34 
       (.I0(\current_state[3]_i_4__34_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__34_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__34_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__34 
       (.I0(\current_state[3]_i_4__34_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__34 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__34_n_0 ),
        .I2(\current_state[3]_i_4__34_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__34 
       (.I0(\current_state[3]_i_2__34_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__34_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__34_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__34 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__34_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__34 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__34_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__34 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__34_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__34
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__34_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__34_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__34 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__34 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__34 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__34 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__34 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__34 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__34 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__34_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__34 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__34 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__34 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__34 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__34 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__34 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__34 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__34 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__34 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__34_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__34
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__34_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__34_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__33
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized33
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__35_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__35_n_0 ;
  wire \current_state[3]_i_3__35_n_0 ;
  wire \current_state[3]_i_4__35_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__35_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__35_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__35_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__35 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__35 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__35 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__35_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__35 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__35_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__35_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__35_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__35_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__35 
       (.I0(\current_state[3]_i_4__35_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__35_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__35_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__35 
       (.I0(\current_state[3]_i_4__35_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__35 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__35_n_0 ),
        .I2(\current_state[3]_i_4__35_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__35 
       (.I0(\current_state[3]_i_2__35_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__35_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__35_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__35 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__35_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__35 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__35_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__35 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__35_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__35
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__35_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__35_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__35 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__35 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__35 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__35 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__35 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__35 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__35 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__35_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__35 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__35 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__35 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__35 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__35 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__35 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__35 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__35 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__35 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__35_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__35
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__35_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__35_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__34
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34
   (\parallel_dout_reg[15]_0 ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[10]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[7]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    \parallel_dout_reg[4]_0 ,
    \parallel_dout_reg[3]_0 ,
    \parallel_dout_reg[2]_0 ,
    \parallel_dout_reg[1]_0 ,
    \parallel_dout_reg[0]_0 ,
    E,
    tc_config_cs_serial_output,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15]_i_3 ,
    \slaveRegDo_mux_5_reg[15]_i_3_0 ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \parallel_dout_reg[15]_0 ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[10]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[7]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output \parallel_dout_reg[4]_0 ;
  output \parallel_dout_reg[3]_0 ;
  output \parallel_dout_reg[2]_0 ;
  output \parallel_dout_reg[1]_0 ;
  output \parallel_dout_reg[0]_0 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [15:0]s_do_o;
  input [5:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_3 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_3_0 ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__36_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__36_n_0 ;
  wire \current_state[3]_i_3__36_n_0 ;
  wire \current_state[3]_i_4__36_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__36_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[0]_0 ;
  wire \parallel_dout_reg[10]_0 ;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire \parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[1]_0 ;
  wire \parallel_dout_reg[2]_0 ;
  wire \parallel_dout_reg[3]_0 ;
  wire \parallel_dout_reg[4]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[7]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__36_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__36_n_0;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_3 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_3_0 ;
  wire [15:0]\slaveRegDo_tcConfig[5143]_36 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__36 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__36 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__36 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__36 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__36_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__36_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__36_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__36 
       (.I0(\current_state[3]_i_4__36_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__36_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__36_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__36 
       (.I0(\current_state[3]_i_4__36_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__36 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__36_n_0 ),
        .I2(\current_state[3]_i_4__36_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__36 
       (.I0(\current_state[3]_i_2__36_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__36_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__36_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__36 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__36_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__36 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__36 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__36_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__36
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__36_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__36_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [1]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [11]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [12]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [13]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [14]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [15]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5143]_36 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [2]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [3]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [4]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [5]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [6]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [7]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [8]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [9]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5143]_36 [10]),
        .Q(\slaveRegDo_tcConfig[5143]_36 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__36 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__36 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__36 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__36 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__36 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__36 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__36 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__36_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__36 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__36 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__36 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__36 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__36 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__36 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__36 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__36 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__36 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__36_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__36
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__36_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__36_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [0]),
        .O(\parallel_dout_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [10]),
        .O(\parallel_dout_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [15]),
        .O(\parallel_dout_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [1]),
        .O(\parallel_dout_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [2]),
        .O(\parallel_dout_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [3]),
        .O(\parallel_dout_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [4]),
        .O(\parallel_dout_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [7]),
        .O(\parallel_dout_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_36 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_3 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_3_0 [9]),
        .O(\parallel_dout_reg[9]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__35
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized35
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__37_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__37_n_0 ;
  wire \current_state[3]_i_3__37_n_0 ;
  wire \current_state[3]_i_4__37_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__37_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__37_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__37_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__37 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__37 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__37 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__37_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__37 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__37_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__37_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__37_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__37_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__37 
       (.I0(\current_state[3]_i_4__37_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__37_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__37_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__37 
       (.I0(\current_state[3]_i_4__37_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__37 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__37_n_0 ),
        .I2(\current_state[3]_i_4__37_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__37 
       (.I0(\current_state[3]_i_2__37_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__37_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__37_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__37 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__37_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__37 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__37_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__37 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__37_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__37
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__37_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__37_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__37 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__37 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__37 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__37 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__37 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__37 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__37 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__37_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__37 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__37 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__37 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__37 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__37 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__37 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__37 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__37 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__37 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__37_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__37
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__37_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__37_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__36
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized36
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__38_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__38_n_0 ;
  wire \current_state[3]_i_3__38_n_0 ;
  wire \current_state[3]_i_4__38_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__38_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__38_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__38_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__38 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__38 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__38 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__38_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__38 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__38_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__38_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__38_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__38_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__38 
       (.I0(\current_state[3]_i_4__38_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__38_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__38_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__38 
       (.I0(\current_state[3]_i_4__38_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__38 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__38_n_0 ),
        .I2(\current_state[3]_i_4__38_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__38 
       (.I0(\current_state[3]_i_2__38_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__38_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__38_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__38 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__38_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__38 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__38_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__38 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__38_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__38
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__38_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__38_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__38 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__38 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__38 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__38 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__38 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__38 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__38 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__38_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__38 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__38 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__38 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__38 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__38 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__38 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__38 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__38 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__38 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__38_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__38
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__38_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__38_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__37
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized37
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__39_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__39_n_0 ;
  wire \current_state[3]_i_3__39_n_0 ;
  wire \current_state[3]_i_4__39_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__39_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__39_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__39_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__39 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__39 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__39 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__39_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__39 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__39_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__39_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__39_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__39_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__39 
       (.I0(\current_state[3]_i_4__39_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__39_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__39_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__39 
       (.I0(\current_state[3]_i_4__39_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__39 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__39_n_0 ),
        .I2(\current_state[3]_i_4__39_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__39 
       (.I0(\current_state[3]_i_2__39_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__39_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__39_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__39 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__39_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__39 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__39_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__39 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__39_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__39
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__39_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__39_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__39 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__39 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__39 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__39 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__39 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__39 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__39 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__39_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__39 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__39 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__39 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__39 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__39 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__39 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__39 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__39 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__39 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__39_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__39
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__39_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__39_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__38
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized38
   (D,
    E,
    tc_config_cs_serial_output,
    \slaveRegDo_mux_5_reg[15] ,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15]_0 ,
    \slaveRegDo_mux_5_reg[15]_1 ,
    \slaveRegDo_mux_5_reg[15]_2 ,
    s_do_o,
    \slaveRegDo_mux_5_reg[15]_i_2_0 ,
    \slaveRegDo_mux_5_reg[15]_i_2_1 ,
    \slaveRegDo_mux_5_reg[14] ,
    \slaveRegDo_mux_5_reg[14]_0 ,
    \slaveRegDo_mux_5_reg[14]_1 ,
    \slaveRegDo_mux_5_reg[14]_2 ,
    \slaveRegDo_mux_5_reg[13] ,
    \slaveRegDo_mux_5_reg[13]_0 ,
    \slaveRegDo_mux_5_reg[13]_1 ,
    \slaveRegDo_mux_5_reg[13]_2 ,
    \slaveRegDo_mux_5_reg[12] ,
    \slaveRegDo_mux_5_reg[12]_0 ,
    \slaveRegDo_mux_5_reg[12]_1 ,
    \slaveRegDo_mux_5_reg[12]_2 ,
    \slaveRegDo_mux_5_reg[11] ,
    \slaveRegDo_mux_5_reg[11]_0 ,
    \slaveRegDo_mux_5_reg[11]_1 ,
    \slaveRegDo_mux_5_reg[11]_2 ,
    \slaveRegDo_mux_5_reg[10] ,
    \slaveRegDo_mux_5_reg[10]_0 ,
    \slaveRegDo_mux_5_reg[10]_1 ,
    \slaveRegDo_mux_5_reg[10]_2 ,
    \slaveRegDo_mux_5_reg[9] ,
    \slaveRegDo_mux_5_reg[9]_0 ,
    \slaveRegDo_mux_5_reg[9]_1 ,
    \slaveRegDo_mux_5_reg[9]_2 ,
    \slaveRegDo_mux_5_reg[8] ,
    \slaveRegDo_mux_5_reg[8]_0 ,
    \slaveRegDo_mux_5_reg[8]_1 ,
    \slaveRegDo_mux_5_reg[8]_2 ,
    \slaveRegDo_mux_5_reg[7] ,
    \slaveRegDo_mux_5_reg[7]_0 ,
    \slaveRegDo_mux_5_reg[7]_1 ,
    \slaveRegDo_mux_5_reg[7]_2 ,
    \slaveRegDo_mux_5_reg[6] ,
    \slaveRegDo_mux_5_reg[6]_0 ,
    \slaveRegDo_mux_5_reg[6]_1 ,
    \slaveRegDo_mux_5_reg[6]_2 ,
    \slaveRegDo_mux_5_reg[5] ,
    \slaveRegDo_mux_5_reg[5]_0 ,
    \slaveRegDo_mux_5_reg[5]_1 ,
    \slaveRegDo_mux_5_reg[5]_2 ,
    \slaveRegDo_mux_5_reg[4] ,
    \slaveRegDo_mux_5_reg[4]_0 ,
    \slaveRegDo_mux_5_reg[4]_1 ,
    \slaveRegDo_mux_5_reg[4]_2 ,
    \slaveRegDo_mux_5_reg[3] ,
    \slaveRegDo_mux_5_reg[3]_0 ,
    \slaveRegDo_mux_5_reg[3]_1 ,
    \slaveRegDo_mux_5_reg[3]_2 ,
    \slaveRegDo_mux_5_reg[2] ,
    \slaveRegDo_mux_5_reg[2]_0 ,
    \slaveRegDo_mux_5_reg[2]_1 ,
    \slaveRegDo_mux_5_reg[2]_2 ,
    \slaveRegDo_mux_5_reg[1] ,
    \slaveRegDo_mux_5_reg[1]_0 ,
    \slaveRegDo_mux_5_reg[1]_1 ,
    \slaveRegDo_mux_5_reg[1]_2 ,
    \slaveRegDo_mux_5_reg[0] ,
    \slaveRegDo_mux_5_reg[0]_0 ,
    \slaveRegDo_mux_5_reg[0]_1 ,
    \slaveRegDo_mux_5_reg[0]_2 ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output [15:0]D;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input \slaveRegDo_mux_5_reg[15] ;
  input [5:0]s_daddr_o;
  input \slaveRegDo_mux_5_reg[15]_0 ;
  input \slaveRegDo_mux_5_reg[15]_1 ;
  input \slaveRegDo_mux_5_reg[15]_2 ;
  input [15:0]s_do_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_2_0 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_2_1 ;
  input \slaveRegDo_mux_5_reg[14] ;
  input \slaveRegDo_mux_5_reg[14]_0 ;
  input \slaveRegDo_mux_5_reg[14]_1 ;
  input \slaveRegDo_mux_5_reg[14]_2 ;
  input \slaveRegDo_mux_5_reg[13] ;
  input \slaveRegDo_mux_5_reg[13]_0 ;
  input \slaveRegDo_mux_5_reg[13]_1 ;
  input \slaveRegDo_mux_5_reg[13]_2 ;
  input \slaveRegDo_mux_5_reg[12] ;
  input \slaveRegDo_mux_5_reg[12]_0 ;
  input \slaveRegDo_mux_5_reg[12]_1 ;
  input \slaveRegDo_mux_5_reg[12]_2 ;
  input \slaveRegDo_mux_5_reg[11] ;
  input \slaveRegDo_mux_5_reg[11]_0 ;
  input \slaveRegDo_mux_5_reg[11]_1 ;
  input \slaveRegDo_mux_5_reg[11]_2 ;
  input \slaveRegDo_mux_5_reg[10] ;
  input \slaveRegDo_mux_5_reg[10]_0 ;
  input \slaveRegDo_mux_5_reg[10]_1 ;
  input \slaveRegDo_mux_5_reg[10]_2 ;
  input \slaveRegDo_mux_5_reg[9] ;
  input \slaveRegDo_mux_5_reg[9]_0 ;
  input \slaveRegDo_mux_5_reg[9]_1 ;
  input \slaveRegDo_mux_5_reg[9]_2 ;
  input \slaveRegDo_mux_5_reg[8] ;
  input \slaveRegDo_mux_5_reg[8]_0 ;
  input \slaveRegDo_mux_5_reg[8]_1 ;
  input \slaveRegDo_mux_5_reg[8]_2 ;
  input \slaveRegDo_mux_5_reg[7] ;
  input \slaveRegDo_mux_5_reg[7]_0 ;
  input \slaveRegDo_mux_5_reg[7]_1 ;
  input \slaveRegDo_mux_5_reg[7]_2 ;
  input \slaveRegDo_mux_5_reg[6] ;
  input \slaveRegDo_mux_5_reg[6]_0 ;
  input \slaveRegDo_mux_5_reg[6]_1 ;
  input \slaveRegDo_mux_5_reg[6]_2 ;
  input \slaveRegDo_mux_5_reg[5] ;
  input \slaveRegDo_mux_5_reg[5]_0 ;
  input \slaveRegDo_mux_5_reg[5]_1 ;
  input \slaveRegDo_mux_5_reg[5]_2 ;
  input \slaveRegDo_mux_5_reg[4] ;
  input \slaveRegDo_mux_5_reg[4]_0 ;
  input \slaveRegDo_mux_5_reg[4]_1 ;
  input \slaveRegDo_mux_5_reg[4]_2 ;
  input \slaveRegDo_mux_5_reg[3] ;
  input \slaveRegDo_mux_5_reg[3]_0 ;
  input \slaveRegDo_mux_5_reg[3]_1 ;
  input \slaveRegDo_mux_5_reg[3]_2 ;
  input \slaveRegDo_mux_5_reg[2] ;
  input \slaveRegDo_mux_5_reg[2]_0 ;
  input \slaveRegDo_mux_5_reg[2]_1 ;
  input \slaveRegDo_mux_5_reg[2]_2 ;
  input \slaveRegDo_mux_5_reg[1] ;
  input \slaveRegDo_mux_5_reg[1]_0 ;
  input \slaveRegDo_mux_5_reg[1]_1 ;
  input \slaveRegDo_mux_5_reg[1]_2 ;
  input \slaveRegDo_mux_5_reg[0] ;
  input \slaveRegDo_mux_5_reg[0]_0 ;
  input \slaveRegDo_mux_5_reg[0]_1 ;
  input \slaveRegDo_mux_5_reg[0]_2 ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [15:0]D;
  wire [0:0]E;
  wire \cnt[3]_i_1__40_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__40_n_0 ;
  wire \current_state[3]_i_3__40_n_0 ;
  wire \current_state[3]_i_4__40_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__40_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__40_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__40_n_0;
  wire \slaveRegDo_mux_5[0]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[10]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[11]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[12]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[13]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[14]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[15]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[1]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[2]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[3]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[4]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[5]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[6]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[7]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[8]_i_6_n_0 ;
  wire \slaveRegDo_mux_5[9]_i_6_n_0 ;
  wire \slaveRegDo_mux_5_reg[0] ;
  wire \slaveRegDo_mux_5_reg[0]_0 ;
  wire \slaveRegDo_mux_5_reg[0]_1 ;
  wire \slaveRegDo_mux_5_reg[0]_2 ;
  wire \slaveRegDo_mux_5_reg[0]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[10] ;
  wire \slaveRegDo_mux_5_reg[10]_0 ;
  wire \slaveRegDo_mux_5_reg[10]_1 ;
  wire \slaveRegDo_mux_5_reg[10]_2 ;
  wire \slaveRegDo_mux_5_reg[10]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[11] ;
  wire \slaveRegDo_mux_5_reg[11]_0 ;
  wire \slaveRegDo_mux_5_reg[11]_1 ;
  wire \slaveRegDo_mux_5_reg[11]_2 ;
  wire \slaveRegDo_mux_5_reg[11]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[12] ;
  wire \slaveRegDo_mux_5_reg[12]_0 ;
  wire \slaveRegDo_mux_5_reg[12]_1 ;
  wire \slaveRegDo_mux_5_reg[12]_2 ;
  wire \slaveRegDo_mux_5_reg[12]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[13] ;
  wire \slaveRegDo_mux_5_reg[13]_0 ;
  wire \slaveRegDo_mux_5_reg[13]_1 ;
  wire \slaveRegDo_mux_5_reg[13]_2 ;
  wire \slaveRegDo_mux_5_reg[13]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[14] ;
  wire \slaveRegDo_mux_5_reg[14]_0 ;
  wire \slaveRegDo_mux_5_reg[14]_1 ;
  wire \slaveRegDo_mux_5_reg[14]_2 ;
  wire \slaveRegDo_mux_5_reg[14]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[15] ;
  wire \slaveRegDo_mux_5_reg[15]_0 ;
  wire \slaveRegDo_mux_5_reg[15]_1 ;
  wire \slaveRegDo_mux_5_reg[15]_2 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_2_0 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_2_1 ;
  wire \slaveRegDo_mux_5_reg[15]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[1] ;
  wire \slaveRegDo_mux_5_reg[1]_0 ;
  wire \slaveRegDo_mux_5_reg[1]_1 ;
  wire \slaveRegDo_mux_5_reg[1]_2 ;
  wire \slaveRegDo_mux_5_reg[1]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[2] ;
  wire \slaveRegDo_mux_5_reg[2]_0 ;
  wire \slaveRegDo_mux_5_reg[2]_1 ;
  wire \slaveRegDo_mux_5_reg[2]_2 ;
  wire \slaveRegDo_mux_5_reg[2]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[3] ;
  wire \slaveRegDo_mux_5_reg[3]_0 ;
  wire \slaveRegDo_mux_5_reg[3]_1 ;
  wire \slaveRegDo_mux_5_reg[3]_2 ;
  wire \slaveRegDo_mux_5_reg[3]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[4] ;
  wire \slaveRegDo_mux_5_reg[4]_0 ;
  wire \slaveRegDo_mux_5_reg[4]_1 ;
  wire \slaveRegDo_mux_5_reg[4]_2 ;
  wire \slaveRegDo_mux_5_reg[4]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[5] ;
  wire \slaveRegDo_mux_5_reg[5]_0 ;
  wire \slaveRegDo_mux_5_reg[5]_1 ;
  wire \slaveRegDo_mux_5_reg[5]_2 ;
  wire \slaveRegDo_mux_5_reg[5]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[6] ;
  wire \slaveRegDo_mux_5_reg[6]_0 ;
  wire \slaveRegDo_mux_5_reg[6]_1 ;
  wire \slaveRegDo_mux_5_reg[6]_2 ;
  wire \slaveRegDo_mux_5_reg[6]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[7] ;
  wire \slaveRegDo_mux_5_reg[7]_0 ;
  wire \slaveRegDo_mux_5_reg[7]_1 ;
  wire \slaveRegDo_mux_5_reg[7]_2 ;
  wire \slaveRegDo_mux_5_reg[7]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[8] ;
  wire \slaveRegDo_mux_5_reg[8]_0 ;
  wire \slaveRegDo_mux_5_reg[8]_1 ;
  wire \slaveRegDo_mux_5_reg[8]_2 ;
  wire \slaveRegDo_mux_5_reg[8]_i_2_n_0 ;
  wire \slaveRegDo_mux_5_reg[9] ;
  wire \slaveRegDo_mux_5_reg[9]_0 ;
  wire \slaveRegDo_mux_5_reg[9]_1 ;
  wire \slaveRegDo_mux_5_reg[9]_2 ;
  wire \slaveRegDo_mux_5_reg[9]_i_2_n_0 ;
  wire [15:0]\slaveRegDo_tcConfig[5147]_40 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__40 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__40 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__40 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__40_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__40 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__40_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__40_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__40_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__40_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__40 
       (.I0(\current_state[3]_i_4__40_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__40_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__40_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__40 
       (.I0(\current_state[3]_i_4__40_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__40 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__40_n_0 ),
        .I2(\current_state[3]_i_4__40_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__40 
       (.I0(\current_state[3]_i_2__40_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__40_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__40_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__40 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__40_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \current_state[3]_i_3__40 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__40_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__40 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__40_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__40
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__40_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__40_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [1]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [11]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [12]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [13]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [14]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [15]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5147]_40 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [2]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [3]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [4]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [5]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [6]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [7]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [8]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [9]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5147]_40 [10]),
        .Q(\slaveRegDo_tcConfig[5147]_40 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__40 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__40 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__40 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__40 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__40 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__40 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__40 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__40_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__40 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__40 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__40 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__40 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__40 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__40 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__40 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__40 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__40 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__40_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__40
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__40_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__40_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[0]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[0] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[0]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[0]_1 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [0]),
        .O(\slaveRegDo_mux_5[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[10]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[10] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[10]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[10]_1 ),
        .O(D[10]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [10]),
        .O(\slaveRegDo_mux_5[10]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[11]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[11] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[11]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[11]_1 ),
        .O(D[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [11]),
        .O(\slaveRegDo_mux_5[11]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[12]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[12] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[12]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[12]_1 ),
        .O(D[12]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [12]),
        .O(\slaveRegDo_mux_5[12]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[13]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[13] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[13]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[13]_1 ),
        .O(D[13]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [13]),
        .O(\slaveRegDo_mux_5[13]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[14]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[14] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[14]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[14]_1 ),
        .O(D[14]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [14]),
        .O(\slaveRegDo_mux_5[14]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[15]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[15] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[15]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[15]_1 ),
        .O(D[15]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [15]),
        .O(\slaveRegDo_mux_5[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[1]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[1] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[1]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[1]_1 ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [1]),
        .O(\slaveRegDo_mux_5[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[2]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[2] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[2]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[2]_1 ),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [2]),
        .O(\slaveRegDo_mux_5[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[3]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[3] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[3]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[3]_1 ),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [3]),
        .O(\slaveRegDo_mux_5[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[4]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[4] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[4]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[4]_1 ),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [4]),
        .O(\slaveRegDo_mux_5[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[5]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[5] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[5]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[5]_1 ),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [5]),
        .O(\slaveRegDo_mux_5[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[6]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[6] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[6]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[6]_1 ),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [6]),
        .O(\slaveRegDo_mux_5[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[7]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[7] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[7]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[7]_1 ),
        .O(D[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [7]),
        .O(\slaveRegDo_mux_5[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[8]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[8] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[8]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[8]_1 ),
        .O(D[8]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [8]),
        .O(\slaveRegDo_mux_5[8]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_1 
       (.I0(\slaveRegDo_mux_5_reg[9]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[9] ),
        .I2(s_daddr_o[4]),
        .I3(\slaveRegDo_mux_5_reg[9]_0 ),
        .I4(s_daddr_o[3]),
        .I5(\slaveRegDo_mux_5_reg[9]_1 ),
        .O(D[9]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_40 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2_0 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_1 [9]),
        .O(\slaveRegDo_mux_5[9]_i_6_n_0 ));
  MUXF7 \slaveRegDo_mux_5_reg[0]_i_2 
       (.I0(\slaveRegDo_mux_5[0]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[0]_2 ),
        .O(\slaveRegDo_mux_5_reg[0]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[10]_i_2 
       (.I0(\slaveRegDo_mux_5[10]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[10]_2 ),
        .O(\slaveRegDo_mux_5_reg[10]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[11]_i_2 
       (.I0(\slaveRegDo_mux_5[11]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[11]_2 ),
        .O(\slaveRegDo_mux_5_reg[11]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[12]_i_2 
       (.I0(\slaveRegDo_mux_5[12]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[12]_2 ),
        .O(\slaveRegDo_mux_5_reg[12]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[13]_i_2 
       (.I0(\slaveRegDo_mux_5[13]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[13]_2 ),
        .O(\slaveRegDo_mux_5_reg[13]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[14]_i_2 
       (.I0(\slaveRegDo_mux_5[14]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[14]_2 ),
        .O(\slaveRegDo_mux_5_reg[14]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[15]_i_2 
       (.I0(\slaveRegDo_mux_5[15]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[15]_2 ),
        .O(\slaveRegDo_mux_5_reg[15]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[1]_i_2 
       (.I0(\slaveRegDo_mux_5[1]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[1]_2 ),
        .O(\slaveRegDo_mux_5_reg[1]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[2]_i_2 
       (.I0(\slaveRegDo_mux_5[2]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[2]_2 ),
        .O(\slaveRegDo_mux_5_reg[2]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[3]_i_2 
       (.I0(\slaveRegDo_mux_5[3]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[3]_2 ),
        .O(\slaveRegDo_mux_5_reg[3]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[4]_i_2 
       (.I0(\slaveRegDo_mux_5[4]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[4]_2 ),
        .O(\slaveRegDo_mux_5_reg[4]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[5]_i_2 
       (.I0(\slaveRegDo_mux_5[5]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[5]_2 ),
        .O(\slaveRegDo_mux_5_reg[5]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[6]_i_2 
       (.I0(\slaveRegDo_mux_5[6]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[6]_2 ),
        .O(\slaveRegDo_mux_5_reg[6]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[7]_i_2 
       (.I0(\slaveRegDo_mux_5[7]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[7]_2 ),
        .O(\slaveRegDo_mux_5_reg[7]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[8]_i_2 
       (.I0(\slaveRegDo_mux_5[8]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[8]_2 ),
        .O(\slaveRegDo_mux_5_reg[8]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  MUXF7 \slaveRegDo_mux_5_reg[9]_i_2 
       (.I0(\slaveRegDo_mux_5[9]_i_6_n_0 ),
        .I1(\slaveRegDo_mux_5_reg[9]_2 ),
        .O(\slaveRegDo_mux_5_reg[9]_i_2_n_0 ),
        .S(s_daddr_o[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__39
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized39
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__41_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__41_n_0 ;
  wire \current_state[3]_i_3__41_n_0 ;
  wire \current_state[3]_i_4__41_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__41_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__41_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__41_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__41 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__41 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__41 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__41_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__41 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__41_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__41_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__41_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__41_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__41 
       (.I0(\current_state[3]_i_4__41_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__41_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__41_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__41 
       (.I0(\current_state[3]_i_4__41_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__41 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__41_n_0 ),
        .I2(\current_state[3]_i_4__41_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__41 
       (.I0(\current_state[3]_i_2__41_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__41_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__41_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__41 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__41_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBFFF)) 
    \current_state[3]_i_3__41 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__41_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__41 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__41_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__41
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__41_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__41_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__41 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__41 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__41 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__41 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__41 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__41 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__41 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__41_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__41 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__41 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__41 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__41 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__41 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__41 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__41 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__41 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__41 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__41_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__41
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__41_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__41_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__40
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized4
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__6_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__6_n_0 ;
  wire \current_state[3]_i_3__6_n_0 ;
  wire \current_state[3]_i_4__6_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__6_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__6_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__6_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__6 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__6 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__6 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__6 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__6_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__6_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__6_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__6 
       (.I0(\current_state[3]_i_4__6_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__6_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__6_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__6 
       (.I0(\current_state[3]_i_4__6_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__6_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__6 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__6_n_0 ),
        .I2(\current_state[3]_i_4__6_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__6 
       (.I0(\current_state[3]_i_2__6_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__6_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__6_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__6 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \current_state[3]_i_3__6 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__6 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__6_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__6
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__6_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__6_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__6 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__6 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__6 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__6 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__6 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__6 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__6 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__6 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__6 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__6 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__6 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__6 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__6 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__6 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__6 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__6 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__6_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__6
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__6_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__6_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__5
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized40
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__42_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__42_n_0 ;
  wire \current_state[3]_i_3__42_n_0 ;
  wire \current_state[3]_i_4__42_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__42_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__42_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__42_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__42 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__42 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__42 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__42_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__42 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__42_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__42_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__42_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__42_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__42 
       (.I0(\current_state[3]_i_4__42_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__42_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__42_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__42 
       (.I0(\current_state[3]_i_4__42_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__42 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__42_n_0 ),
        .I2(\current_state[3]_i_4__42_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__42 
       (.I0(\current_state[3]_i_2__42_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__42_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__42_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__42 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__42_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBFFF)) 
    \current_state[3]_i_3__42 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__42_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__42 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__42_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__42
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__42_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__42_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__42 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__42 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__42 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__42 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__42 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__42 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__42 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__42_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__42 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__42 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__42 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__42 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__42 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__42 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__42 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__42 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__42 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__42_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__42
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__42_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__42_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__41
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized41
   (s_do_o,
    E,
    tc_config_cs_serial_output,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 ,
    s_daddr_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;
  input [3:0]s_daddr_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__43_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__43_n_0 ;
  wire \current_state[3]_i_3__43_n_0 ;
  wire \current_state[3]_i_4__43_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__43_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__43_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__43_n_0;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__43 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__43 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__43 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__43_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__43 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__43_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__43_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__43_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__43_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__43 
       (.I0(\current_state[3]_i_4__43_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__43_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__43_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__43 
       (.I0(\current_state[3]_i_4__43_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__43 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__43_n_0 ),
        .I2(\current_state[3]_i_4__43_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__43 
       (.I0(\current_state[3]_i_2__43_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__43_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__43_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__43 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__43_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBFFF)) 
    \current_state[3]_i_3__43 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__43_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__43 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__43_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__43
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__43_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__43_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__43 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__43 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__43 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__43 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__43 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__43 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__43 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__43_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__43 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__43 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__43 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__43 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__43 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__43 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__43 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__43 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__43 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__43_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__43
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__43_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__43_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__42
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized42
   (\parallel_dout_reg[15]_0 ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[10]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[7]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    \parallel_dout_reg[4]_0 ,
    \parallel_dout_reg[3]_0 ,
    \parallel_dout_reg[2]_0 ,
    \parallel_dout_reg[1]_0 ,
    \parallel_dout_reg[0]_0 ,
    E,
    tc_config_cs_serial_output,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_5_reg[15]_i_2 ,
    \slaveRegDo_mux_5_reg[15]_i_2_0 ,
    s_dclk_o,
    tc_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \parallel_dout_reg[15]_0 ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[10]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[7]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output \parallel_dout_reg[4]_0 ;
  output \parallel_dout_reg[3]_0 ;
  output \parallel_dout_reg[2]_0 ;
  output \parallel_dout_reg[1]_0 ;
  output \parallel_dout_reg[0]_0 ;
  output [0:0]E;
  output [0:0]tc_config_cs_serial_output;
  input [15:0]s_do_o;
  input [5:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_2 ;
  input [15:0]\slaveRegDo_mux_5_reg[15]_i_2_0 ;
  input s_dclk_o;
  input [0:0]tc_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__44_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__44_n_0 ;
  wire \current_state[3]_i_3__44_n_0 ;
  wire \current_state[3]_i_4__44_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__44_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[0]_0 ;
  wire \parallel_dout_reg[10]_0 ;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire \parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[1]_0 ;
  wire \parallel_dout_reg[2]_0 ;
  wire \parallel_dout_reg[3]_0 ;
  wire \parallel_dout_reg[4]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[7]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [5:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__44_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__44_n_0;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_2 ;
  wire [15:0]\slaveRegDo_mux_5_reg[15]_i_2_0 ;
  wire [15:0]\slaveRegDo_tcConfig[5151]_44 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__44 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__44 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__44 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__44_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__44 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__44_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__44_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__44_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__44_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__44 
       (.I0(\current_state[3]_i_4__44_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__44_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__44_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__44 
       (.I0(\current_state[3]_i_4__44_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__44 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__44_n_0 ),
        .I2(\current_state[3]_i_4__44_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__44 
       (.I0(\current_state[3]_i_2__44_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__44_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__44_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__44 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__44_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBFFF)) 
    \current_state[3]_i_3__44 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[5]),
        .I5(\current_state_reg[1]_0 ),
        .O(\current_state[3]_i_3__44_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__44 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__44_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__44
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__44_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__44_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [1]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [11]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [12]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [13]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [14]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [15]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5151]_44 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [2]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [3]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [4]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [5]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [6]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [7]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [8]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [9]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_tcConfig[5151]_44 [10]),
        .Q(\slaveRegDo_tcConfig[5151]_44 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__44 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__44 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__44 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__44 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__44 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__44 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__44 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__44_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__44 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__44 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__44 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__44 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__44 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__44 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__44 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__44 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__44 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__44_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__44
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__44_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__44_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[0]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [0]),
        .O(\parallel_dout_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[10]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [10]),
        .O(\parallel_dout_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[11]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[12]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[13]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[14]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[15]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [15]),
        .O(\parallel_dout_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[1]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [1]),
        .O(\parallel_dout_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[2]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [2]),
        .O(\parallel_dout_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[3]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [3]),
        .O(\parallel_dout_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[4]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [4]),
        .O(\parallel_dout_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[5]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[6]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[7]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [7]),
        .O(\parallel_dout_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[8]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_5[9]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_44 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_5_reg[15]_i_2 [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_5_reg[15]_i_2_0 [9]),
        .O(\parallel_dout_reg[9]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__43
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized43
   (s_do_o,
    E,
    CFG_CNT_DIN,
    s_dclk_o,
    CFG_CNT_DOUT,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    \current_state_reg[3]_1 );
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]CFG_CNT_DIN;
  input s_dclk_o;
  input [0:0]CFG_CNT_DOUT;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input [1:0]s_daddr_o;
  input \current_state_reg[3]_1 ;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [0:0]E;
  wire \cnt[3]_i_1__45_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__45_n_0 ;
  wire \current_state[3]_i_3__45_n_0 ;
  wire \current_state[3]_i_4__45_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__45_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__45_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__45_n_0;

  LUT3 #(
    .INIT(8'hB8)) 
    \G_COUNTER[0].U_COUNTER_i_4 
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__45 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__45 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__45 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__45_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__45 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__45_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__45_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__45_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__45_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__45 
       (.I0(\current_state[3]_i_4__45_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__45_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__45_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__45 
       (.I0(\current_state[3]_i_4__45_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__45_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__45 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__45_n_0 ),
        .I2(\current_state[3]_i_4__45_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__45 
       (.I0(\current_state[3]_i_2__45_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__45_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__45_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__45 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__45_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[3]_i_3__45 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_1 ),
        .O(\current_state[3]_i_3__45_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__45 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__45_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__45
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__45_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__45_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(CFG_CNT_DOUT),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__45 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__45 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__45 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__45 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__45 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__45 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__45 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__45_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__45 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__45 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__45 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__45 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__45 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__45 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__45 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__45 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__45 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__45_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__45
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__45_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__45_n_0),
        .Q(E),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized44
   (s_do_o,
    E,
    CFG_CNT_DIN,
    s_dclk_o,
    CFG_CNT_DOUT,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    D,
    \current_state_reg[3]_2 );
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]CFG_CNT_DIN;
  input s_dclk_o;
  input [0:0]CFG_CNT_DOUT;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]D;
  input [0:0]\current_state_reg[3]_2 ;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [2:0]D;
  wire [0:0]E;
  wire \cnt[3]_i_1__46_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__46_n_0 ;
  wire \current_state[3]_i_3__46_n_0 ;
  wire \current_state[3]_i_4__46_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire [0:0]\current_state_reg[3]_2 ;
  wire data_out_sel_i_1__46_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__46_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__46_n_0;

  LUT3 #(
    .INIT(8'hB8)) 
    \G_COUNTER[1].U_COUNTER_i_3 
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__46 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__46 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__46 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__46_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__46 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__46_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__46_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__46_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__46_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__46 
       (.I0(\current_state[3]_i_4__46_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__46_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__46_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__46 
       (.I0(\current_state[3]_i_4__46_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__46_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__46 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__46_n_0 ),
        .I2(\current_state[3]_i_4__46_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__46 
       (.I0(\current_state[3]_i_2__46_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__46_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__46_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__46 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__46_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__46 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(D[1]),
        .I3(D[0]),
        .I4(\current_state_reg[3]_2 ),
        .I5(D[2]),
        .O(\current_state[3]_i_3__46_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__46 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__46_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__46
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__46_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__46_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(CFG_CNT_DOUT),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__46 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__46 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__46 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__46 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__46 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__46 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__46 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__46_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__46 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__46 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__46 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__46 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__46 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__46 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__46 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__46 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__46 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__46_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__46
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__46_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__46_n_0),
        .Q(E),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized45
   (D,
    E,
    CFG_CNT_DIN,
    \slaveRegDo_mux_6_reg[0] ,
    \slaveRegDo_mux_6_reg[0]_0 ,
    Q,
    s_do_o,
    \slaveRegDo_mux_6_reg[15] ,
    s_daddr_o,
    \slaveRegDo_mux_6_reg[15]_0 ,
    s_dclk_o,
    CFG_CNT_DOUT,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_den_o);
  output [15:0]D;
  output [0:0]E;
  output [0:0]CFG_CNT_DIN;
  input \slaveRegDo_mux_6_reg[0] ;
  input \slaveRegDo_mux_6_reg[0]_0 ;
  input [15:0]Q;
  input [15:0]s_do_o;
  input [15:0]\slaveRegDo_mux_6_reg[15] ;
  input [4:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_6_reg[15]_0 ;
  input s_dclk_o;
  input [0:0]CFG_CNT_DOUT;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input s_den_o;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [15:0]D;
  wire [0:0]E;
  wire [15:0]Q;
  wire \cnt[3]_i_1__47_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__47_n_0 ;
  wire \current_state[3]_i_3__47_n_0 ;
  wire \current_state[3]_i_4__47_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__47_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__47_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__47_n_0;
  wire [15:0]\slaveRegDo_cntConfig[6146]_47 ;
  wire \slaveRegDo_mux_6[0]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[10]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[11]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[12]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[13]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[14]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[15]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[1]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[2]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[3]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[4]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[5]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[6]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[7]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[8]_i_2_n_0 ;
  wire \slaveRegDo_mux_6[9]_i_2_n_0 ;
  wire \slaveRegDo_mux_6_reg[0] ;
  wire \slaveRegDo_mux_6_reg[0]_0 ;
  wire [15:0]\slaveRegDo_mux_6_reg[15] ;
  wire [15:0]\slaveRegDo_mux_6_reg[15]_0 ;

  LUT3 #(
    .INIT(8'hB8)) 
    \G_COUNTER[2].U_COUNTER_i_3 
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__47 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__47 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__47 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__47_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__47 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__47_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__47_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__47_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__47_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__47 
       (.I0(\current_state[3]_i_4__47_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__47_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__47_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__47 
       (.I0(\current_state[3]_i_4__47_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__47_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__47 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__47_n_0 ),
        .I2(\current_state[3]_i_4__47_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__47 
       (.I0(\current_state[3]_i_2__47_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__47_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__47_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__47 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__47_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFFFFFFFFFFF)) 
    \current_state[3]_i_3__47 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(s_den_o),
        .I5(s_daddr_o[4]),
        .O(\current_state[3]_i_3__47_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__47 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__47_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__47
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__47_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__47_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [1]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [11]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [12]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [13]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [14]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [15]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(CFG_CNT_DOUT),
        .Q(\slaveRegDo_cntConfig[6146]_47 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [2]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [3]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [4]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [5]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [6]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [7]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [8]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [9]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_cntConfig[6146]_47 [10]),
        .Q(\slaveRegDo_cntConfig[6146]_47 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__47 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__47 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__47 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__47 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__47 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__47 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__47 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__47_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__47 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__47 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__47 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__47 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__47 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__47 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__47 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__47 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__47 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__47_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__47
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__47_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__47_n_0),
        .Q(E),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[0]_i_1 
       (.I0(\slaveRegDo_mux_6[0]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \slaveRegDo_mux_6[0]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [0]),
        .I1(s_do_o[0]),
        .I2(\slaveRegDo_mux_6_reg[15] [0]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_6_reg[15]_0 [0]),
        .O(\slaveRegDo_mux_6[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[10]_i_1 
       (.I0(\slaveRegDo_mux_6[10]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[10]),
        .O(D[10]));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \slaveRegDo_mux_6[10]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [10]),
        .I1(s_do_o[10]),
        .I2(\slaveRegDo_mux_6_reg[15] [10]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_6_reg[15]_0 [10]),
        .O(\slaveRegDo_mux_6[10]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[11]_i_1 
       (.I0(\slaveRegDo_mux_6[11]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[11]),
        .O(D[11]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[11]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [11]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [11]),
        .I2(\slaveRegDo_mux_6_reg[15] [11]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[11]),
        .O(\slaveRegDo_mux_6[11]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[12]_i_1 
       (.I0(\slaveRegDo_mux_6[12]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[12]),
        .O(D[12]));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \slaveRegDo_mux_6[12]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [12]),
        .I1(s_do_o[12]),
        .I2(\slaveRegDo_mux_6_reg[15] [12]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_6_reg[15]_0 [12]),
        .O(\slaveRegDo_mux_6[12]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[13]_i_1 
       (.I0(\slaveRegDo_mux_6[13]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[13]),
        .O(D[13]));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \slaveRegDo_mux_6[13]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [13]),
        .I1(s_do_o[13]),
        .I2(\slaveRegDo_mux_6_reg[15] [13]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_6_reg[15]_0 [13]),
        .O(\slaveRegDo_mux_6[13]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[14]_i_1 
       (.I0(\slaveRegDo_mux_6[14]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[14]),
        .O(D[14]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[14]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [14]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [14]),
        .I2(\slaveRegDo_mux_6_reg[15] [14]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[14]),
        .O(\slaveRegDo_mux_6[14]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[15]_i_1 
       (.I0(\slaveRegDo_mux_6[15]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[15]),
        .O(D[15]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[15]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [15]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [15]),
        .I2(\slaveRegDo_mux_6_reg[15] [15]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[15]),
        .O(\slaveRegDo_mux_6[15]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[1]_i_1 
       (.I0(\slaveRegDo_mux_6[1]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[1]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [1]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [1]),
        .I2(\slaveRegDo_mux_6_reg[15] [1]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[1]),
        .O(\slaveRegDo_mux_6[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[2]_i_1 
       (.I0(\slaveRegDo_mux_6[2]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[2]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [2]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [2]),
        .I2(\slaveRegDo_mux_6_reg[15] [2]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[2]),
        .O(\slaveRegDo_mux_6[2]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[3]_i_1 
       (.I0(\slaveRegDo_mux_6[3]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[3]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [3]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [3]),
        .I2(\slaveRegDo_mux_6_reg[15] [3]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[3]),
        .O(\slaveRegDo_mux_6[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[4]_i_1 
       (.I0(\slaveRegDo_mux_6[4]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[4]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[4]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [4]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [4]),
        .I2(\slaveRegDo_mux_6_reg[15] [4]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[4]),
        .O(\slaveRegDo_mux_6[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[5]_i_1 
       (.I0(\slaveRegDo_mux_6[5]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[5]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \slaveRegDo_mux_6[5]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [5]),
        .I1(s_do_o[5]),
        .I2(\slaveRegDo_mux_6_reg[15] [5]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_6_reg[15]_0 [5]),
        .O(\slaveRegDo_mux_6[5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[6]_i_1 
       (.I0(\slaveRegDo_mux_6[6]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[6]),
        .O(D[6]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[6]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [6]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [6]),
        .I2(\slaveRegDo_mux_6_reg[15] [6]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[6]),
        .O(\slaveRegDo_mux_6[6]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[7]_i_1 
       (.I0(\slaveRegDo_mux_6[7]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[7]),
        .O(D[7]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[7]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [7]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [7]),
        .I2(\slaveRegDo_mux_6_reg[15] [7]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[7]),
        .O(\slaveRegDo_mux_6[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[8]_i_1 
       (.I0(\slaveRegDo_mux_6[8]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[8]),
        .O(D[8]));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \slaveRegDo_mux_6[8]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [8]),
        .I1(\slaveRegDo_mux_6_reg[15]_0 [8]),
        .I2(\slaveRegDo_mux_6_reg[15] [8]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_do_o[8]),
        .O(\slaveRegDo_mux_6[8]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \slaveRegDo_mux_6[9]_i_1 
       (.I0(\slaveRegDo_mux_6[9]_i_2_n_0 ),
        .I1(\slaveRegDo_mux_6_reg[0] ),
        .I2(\slaveRegDo_mux_6_reg[0]_0 ),
        .I3(Q[9]),
        .O(D[9]));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \slaveRegDo_mux_6[9]_i_2 
       (.I0(\slaveRegDo_cntConfig[6146]_47 [9]),
        .I1(s_do_o[9]),
        .I2(\slaveRegDo_mux_6_reg[15] [9]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_6_reg[15]_0 [9]),
        .O(\slaveRegDo_mux_6[9]_i_2_n_0 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized46
   (\G_1PIPE_IFACE.s_di_r_reg[15] ,
    s_do_o,
    E,
    CFG_CNT_DIN,
    s_di_o,
    s_dclk_o,
    CFG_CNT_DOUT,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    \current_state_reg[3]_1 );
  output \G_1PIPE_IFACE.s_di_r_reg[15] ;
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]CFG_CNT_DIN;
  input [15:0]s_di_o;
  input s_dclk_o;
  input [0:0]CFG_CNT_DOUT;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input [1:0]s_daddr_o;
  input \current_state_reg[3]_1 ;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
  wire \cnt[3]_i_1__48_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__48_n_0 ;
  wire \current_state[3]_i_3__48_n_0 ;
  wire \current_state[3]_i_4__48_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__48_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__48_n_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__48_n_0;

  LUT3 #(
    .INIT(8'hB8)) 
    \G_COUNTER[3].U_COUNTER_i_3 
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__48 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__48 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__48 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__48_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__48 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__48_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__48_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__48_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__48_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__48 
       (.I0(\current_state[3]_i_4__48_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__48_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__48_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__48 
       (.I0(\current_state[3]_i_4__48_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__48_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__48 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__48_n_0 ),
        .I2(\current_state[3]_i_4__48_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__48 
       (.I0(\current_state[3]_i_2__48_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__48_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__48_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__48 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__48_n_0 ));
  LUT4 #(
    .INIT(16'hFFBF)) 
    \current_state[3]_i_3__48 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_1 ),
        .O(\current_state[3]_i_3__48_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__48 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__48_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__48
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__48_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__48_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(CFG_CNT_DOUT),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__48 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__48 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__48 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__48 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__48 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__48 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT1 #(
    .INIT(2'h1)) 
    \shadow[15]_i_1 
       (.I0(s_di_o[15]),
        .O(\G_1PIPE_IFACE.s_di_r_reg[15] ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__48 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__48_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__48 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__48 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__48 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__48 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__48 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__48 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__48 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__48 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__48 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__48_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__48
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__48_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__48_n_0),
        .Q(E),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized47
   (E,
    qual_strg_config_cs_serial_output,
    Q,
    s_dclk_o,
    \shadow_reg[15]_0 ,
    \parallel_dout_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    \current_state_reg[3]_1 );
  output [0:0]E;
  output qual_strg_config_cs_serial_output;
  output [15:0]Q;
  input s_dclk_o;
  input \shadow_reg[15]_0 ;
  input [0:0]\parallel_dout_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input [1:0]s_daddr_o;
  input \current_state_reg[3]_1 ;

  wire [0:0]E;
  wire [15:0]Q;
  wire \cnt[3]_i_1_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2_n_0 ;
  wire \current_state[3]_i_3_n_0 ;
  wire \current_state[3]_i_4_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [0:0]\parallel_dout_reg[15]_0 ;
  wire qual_strg_config_cs_serial_output;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_2_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1 
       (.I0(\current_state[3]_i_4_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1 
       (.I0(\current_state[3]_i_4_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2_n_0 ),
        .I2(\current_state[3]_i_4_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1 
       (.I0(\current_state[3]_i_2_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[3]_i_3 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_1 ),
        .O(\current_state[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[1]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[11]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[12]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[13]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[14]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[15]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\parallel_dout_reg[15]_0 ),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[2]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[3]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[4]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[5]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[6]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[7]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[8]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[9]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(Q[10]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_2 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_2_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(\parallel_dout_reg[15]_0 ),
        .O(qual_strg_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized48
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ,
    \xsdb_reg_reg[15] ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    E,
    capture_ctrl_config_serial_output,
    s_daddr_o,
    \slaveRegDo_mux_3_reg[0] ,
    \slaveRegDo_mux_3_reg[1] ,
    \slaveRegDo_mux_3_reg[2] ,
    \slaveRegDo_mux_3_reg[3] ,
    \slaveRegDo_mux_3_reg[4] ,
    \slaveRegDo_mux_3_reg[7] ,
    \slaveRegDo_mux_3_reg[7]_0 ,
    Q,
    \slaveRegDo_mux_3_reg[15] ,
    \slaveRegDo_mux_3_reg[15]_0 ,
    \slaveRegDo_mux_3_reg[15]_1 ,
    D,
    \slaveRegDo_mux_3_reg[14] ,
    \slaveRegDo_mux_3_reg[13] ,
    \slaveRegDo_mux_3_reg[12] ,
    \slaveRegDo_mux_3_reg[11] ,
    \slaveRegDo_mux_3_reg[10] ,
    \slaveRegDo_mux_3_reg[9] ,
    \slaveRegDo_mux_3_reg[8] ,
    \slaveRegDo_mux_3_reg[7]_1 ,
    \slaveRegDo_mux_3_reg[6] ,
    \slaveRegDo_mux_3_reg[5] ,
    \slaveRegDo_mux_3_reg[4]_0 ,
    \slaveRegDo_mux_3_reg[3]_0 ,
    \slaveRegDo_mux_3_reg[2]_0 ,
    \slaveRegDo_mux_3_reg[1]_0 ,
    \slaveRegDo_mux_3_reg[0]_0 ,
    s_dclk_o,
    \parallel_dout_reg[15]_0 ,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    s_den_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  output \xsdb_reg_reg[15] ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output [0:0]E;
  output capture_ctrl_config_serial_output;
  input [12:0]s_daddr_o;
  input \slaveRegDo_mux_3_reg[0] ;
  input \slaveRegDo_mux_3_reg[1] ;
  input \slaveRegDo_mux_3_reg[2] ;
  input \slaveRegDo_mux_3_reg[3] ;
  input \slaveRegDo_mux_3_reg[4] ;
  input \slaveRegDo_mux_3_reg[7] ;
  input \slaveRegDo_mux_3_reg[7]_0 ;
  input [2:0]Q;
  input \slaveRegDo_mux_3_reg[15] ;
  input \slaveRegDo_mux_3_reg[15]_0 ;
  input [15:0]\slaveRegDo_mux_3_reg[15]_1 ;
  input [15:0]D;
  input \slaveRegDo_mux_3_reg[14] ;
  input \slaveRegDo_mux_3_reg[13] ;
  input \slaveRegDo_mux_3_reg[12] ;
  input \slaveRegDo_mux_3_reg[11] ;
  input \slaveRegDo_mux_3_reg[10] ;
  input \slaveRegDo_mux_3_reg[9] ;
  input \slaveRegDo_mux_3_reg[8] ;
  input \slaveRegDo_mux_3_reg[7]_1 ;
  input \slaveRegDo_mux_3_reg[6] ;
  input \slaveRegDo_mux_3_reg[5] ;
  input \slaveRegDo_mux_3_reg[4]_0 ;
  input \slaveRegDo_mux_3_reg[3]_0 ;
  input \slaveRegDo_mux_3_reg[2]_0 ;
  input \slaveRegDo_mux_3_reg[1]_0 ;
  input \slaveRegDo_mux_3_reg[0]_0 ;
  input s_dclk_o;
  input [0:0]\parallel_dout_reg[15]_0 ;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input s_den_o;

  wire [15:0]D;
  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire [2:0]Q;
  wire capture_ctrl_config_serial_output;
  wire \cnt[3]_i_1__0_n_0 ;
  wire [3:0]cnt_reg__0__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__0_n_0 ;
  wire \current_state[3]_i_3__0_n_0 ;
  wire \current_state[3]_i_4__0_n_0 ;
  wire \current_state[3]_i_5_n_0 ;
  wire \current_state[3]_i_6_n_0 ;
  wire data_out_sel_i_1__0_n_0;
  wire data_out_sel_reg_n_0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire [0:0]\parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__0_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__0_n_0;
  wire [15:0]slaveRegDo_fff;
  wire \slaveRegDo_mux_3[0]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[10]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[15]_i_3_n_0 ;
  wire \slaveRegDo_mux_3[1]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[2]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[3]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[4]_i_2_n_0 ;
  wire \slaveRegDo_mux_3[7]_i_2_n_0 ;
  wire \slaveRegDo_mux_3_reg[0] ;
  wire \slaveRegDo_mux_3_reg[0]_0 ;
  wire \slaveRegDo_mux_3_reg[10] ;
  wire \slaveRegDo_mux_3_reg[11] ;
  wire \slaveRegDo_mux_3_reg[12] ;
  wire \slaveRegDo_mux_3_reg[13] ;
  wire \slaveRegDo_mux_3_reg[14] ;
  wire \slaveRegDo_mux_3_reg[15] ;
  wire \slaveRegDo_mux_3_reg[15]_0 ;
  wire [15:0]\slaveRegDo_mux_3_reg[15]_1 ;
  wire \slaveRegDo_mux_3_reg[1] ;
  wire \slaveRegDo_mux_3_reg[1]_0 ;
  wire \slaveRegDo_mux_3_reg[2] ;
  wire \slaveRegDo_mux_3_reg[2]_0 ;
  wire \slaveRegDo_mux_3_reg[3] ;
  wire \slaveRegDo_mux_3_reg[3]_0 ;
  wire \slaveRegDo_mux_3_reg[4] ;
  wire \slaveRegDo_mux_3_reg[4]_0 ;
  wire \slaveRegDo_mux_3_reg[5] ;
  wire \slaveRegDo_mux_3_reg[6] ;
  wire \slaveRegDo_mux_3_reg[7] ;
  wire \slaveRegDo_mux_3_reg[7]_0 ;
  wire \slaveRegDo_mux_3_reg[7]_1 ;
  wire \slaveRegDo_mux_3_reg[8] ;
  wire \slaveRegDo_mux_3_reg[9] ;
  wire \xsdb_reg_reg[15] ;

  LUT3 #(
    .INIT(8'hB8)) 
    \I_YESLUT6.U_SRL32_D_i_1 
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(\parallel_dout_reg[15]_0 ),
        .O(capture_ctrl_config_serial_output));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__0 
       (.I0(cnt_reg__0__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__0 
       (.I0(cnt_reg__0__0[0]),
        .I1(cnt_reg__0__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__0 
       (.I0(cnt_reg__0__0[1]),
        .I1(cnt_reg__0__0[0]),
        .I2(cnt_reg__0__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__0 
       (.I0(cnt_reg__0__0[2]),
        .I1(cnt_reg__0__0[0]),
        .I2(cnt_reg__0__0[1]),
        .I3(cnt_reg__0__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0__0[0]),
        .R(\cnt[3]_i_1__0_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0__0[1]),
        .R(\cnt[3]_i_1__0_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0__0[2]),
        .R(\cnt[3]_i_1__0_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0__0[3]),
        .R(\cnt[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__0 
       (.I0(\current_state[3]_i_4__0_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__0_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__0_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__0 
       (.I0(\current_state[3]_i_4__0_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__0_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__0 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__0_n_0 ),
        .I2(\current_state[3]_i_4__0_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__0 
       (.I0(\current_state[3]_i_2__0_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__0_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__0_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__0 
       (.I0(cnt_reg__0__0[2]),
        .I1(cnt_reg__0__0[0]),
        .I2(cnt_reg__0__0[1]),
        .I3(cnt_reg__0__0[3]),
        .O(\current_state[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBFFFFFFF)) 
    \current_state[3]_i_3__0 
       (.I0(\current_state[3]_i_5_n_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(\current_state[3]_i_6_n_0 ),
        .O(\current_state[3]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__0 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__0_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_5 
       (.I0(s_daddr_o[7]),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[9]),
        .I3(s_daddr_o[8]),
        .O(\current_state[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFFFFFFFFFFFF)) 
    \current_state[3]_i_6 
       (.I0(s_daddr_o[12]),
        .I1(s_den_o),
        .I2(s_daddr_o[10]),
        .I3(s_daddr_o[11]),
        .I4(s_daddr_o[1]),
        .I5(s_daddr_o[0]),
        .O(\current_state[3]_i_6_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__0
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__0_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__0_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[1]),
        .Q(slaveRegDo_fff[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[11]),
        .Q(slaveRegDo_fff[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[12]),
        .Q(slaveRegDo_fff[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[13]),
        .Q(slaveRegDo_fff[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[14]),
        .Q(slaveRegDo_fff[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[15]),
        .Q(slaveRegDo_fff[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\parallel_dout_reg[15]_0 ),
        .Q(slaveRegDo_fff[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[2]),
        .Q(slaveRegDo_fff[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[3]),
        .Q(slaveRegDo_fff[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[4]),
        .Q(slaveRegDo_fff[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[5]),
        .Q(slaveRegDo_fff[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[6]),
        .Q(slaveRegDo_fff[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[7]),
        .Q(slaveRegDo_fff[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[8]),
        .Q(slaveRegDo_fff[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[9]),
        .Q(slaveRegDo_fff[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(slaveRegDo_fff[10]),
        .Q(slaveRegDo_fff[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__0 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__0 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__0 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__0 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__0 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__0 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__0 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__0 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__0 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__0 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__0 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__0 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__0 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__0 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__0 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__0 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__0_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__0
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__0_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__0_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hBCB08C808C808C80)) 
    \slaveRegDo_mux_3[0]_i_1 
       (.I0(\slaveRegDo_mux_3[0]_i_2_n_0 ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(\slaveRegDo_mux_3_reg[0] ),
        .I4(s_daddr_o[0]),
        .I5(s_daddr_o[1]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[0]_i_2 
       (.I0(slaveRegDo_fff[0]),
        .I1(\slaveRegDo_mux_3_reg[0]_0 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [0]),
        .I4(s_daddr_o[0]),
        .I5(D[0]),
        .O(\slaveRegDo_mux_3[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hB0B0B0B080B08080)) 
    \slaveRegDo_mux_3[10]_i_1 
       (.I0(\slaveRegDo_mux_3[10]_i_2_n_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(\slaveRegDo_mux_3_reg[7]_0 ),
        .I4(Q[1]),
        .I5(\slaveRegDo_mux_3_reg[7] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[10]_i_2 
       (.I0(slaveRegDo_fff[10]),
        .I1(\slaveRegDo_mux_3_reg[10] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [10]),
        .I4(s_daddr_o[0]),
        .I5(D[10]),
        .O(\slaveRegDo_mux_3[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[11]_i_3 
       (.I0(slaveRegDo_fff[11]),
        .I1(\slaveRegDo_mux_3_reg[11] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [11]),
        .I4(s_daddr_o[0]),
        .I5(D[11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[12]_i_2 
       (.I0(slaveRegDo_fff[12]),
        .I1(\slaveRegDo_mux_3_reg[12] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [12]),
        .I4(s_daddr_o[0]),
        .I5(D[12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[13]_i_2 
       (.I0(slaveRegDo_fff[13]),
        .I1(\slaveRegDo_mux_3_reg[13] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [13]),
        .I4(s_daddr_o[0]),
        .I5(D[13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[14]_i_2 
       (.I0(slaveRegDo_fff[14]),
        .I1(\slaveRegDo_mux_3_reg[14] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [14]),
        .I4(s_daddr_o[0]),
        .I5(D[14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAAAAFF0C00000000)) 
    \slaveRegDo_mux_3[15]_i_2 
       (.I0(\slaveRegDo_mux_3[15]_i_3_n_0 ),
        .I1(Q[2]),
        .I2(\slaveRegDo_mux_3_reg[7]_0 ),
        .I3(\slaveRegDo_mux_3_reg[15] ),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\xsdb_reg_reg[15] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[15]_i_3 
       (.I0(slaveRegDo_fff[15]),
        .I1(\slaveRegDo_mux_3_reg[15]_0 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [15]),
        .I4(s_daddr_o[0]),
        .I5(D[15]),
        .O(\slaveRegDo_mux_3[15]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hB080)) 
    \slaveRegDo_mux_3[1]_i_1 
       (.I0(\slaveRegDo_mux_3[1]_i_2_n_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(\slaveRegDo_mux_3_reg[1] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[1]_i_2 
       (.I0(slaveRegDo_fff[1]),
        .I1(\slaveRegDo_mux_3_reg[1]_0 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [1]),
        .I4(s_daddr_o[0]),
        .I5(D[1]),
        .O(\slaveRegDo_mux_3[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hB080)) 
    \slaveRegDo_mux_3[2]_i_1 
       (.I0(\slaveRegDo_mux_3[2]_i_2_n_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(\slaveRegDo_mux_3_reg[2] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[2]_i_2 
       (.I0(slaveRegDo_fff[2]),
        .I1(\slaveRegDo_mux_3_reg[2]_0 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [2]),
        .I4(s_daddr_o[0]),
        .I5(D[2]),
        .O(\slaveRegDo_mux_3[2]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hB080)) 
    \slaveRegDo_mux_3[3]_i_1 
       (.I0(\slaveRegDo_mux_3[3]_i_2_n_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(\slaveRegDo_mux_3_reg[3] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[3]_i_2 
       (.I0(slaveRegDo_fff[3]),
        .I1(\slaveRegDo_mux_3_reg[3]_0 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [3]),
        .I4(s_daddr_o[0]),
        .I5(D[3]),
        .O(\slaveRegDo_mux_3[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hB080)) 
    \slaveRegDo_mux_3[4]_i_1 
       (.I0(\slaveRegDo_mux_3[4]_i_2_n_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(\slaveRegDo_mux_3_reg[4] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[4]_i_2 
       (.I0(slaveRegDo_fff[4]),
        .I1(\slaveRegDo_mux_3_reg[4]_0 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [4]),
        .I4(s_daddr_o[0]),
        .I5(D[4]),
        .O(\slaveRegDo_mux_3[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[5]_i_2 
       (.I0(slaveRegDo_fff[5]),
        .I1(\slaveRegDo_mux_3_reg[5] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [5]),
        .I4(s_daddr_o[0]),
        .I5(D[5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[6]_i_2 
       (.I0(slaveRegDo_fff[6]),
        .I1(\slaveRegDo_mux_3_reg[6] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [6]),
        .I4(s_daddr_o[0]),
        .I5(D[6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hB080B0B0B080B080)) 
    \slaveRegDo_mux_3[7]_i_1 
       (.I0(\slaveRegDo_mux_3[7]_i_2_n_0 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[3]),
        .I3(\slaveRegDo_mux_3_reg[7] ),
        .I4(\slaveRegDo_mux_3_reg[7]_0 ),
        .I5(Q[0]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[7]_i_2 
       (.I0(slaveRegDo_fff[7]),
        .I1(\slaveRegDo_mux_3_reg[7]_1 ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [7]),
        .I4(s_daddr_o[0]),
        .I5(D[7]),
        .O(\slaveRegDo_mux_3[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[8]_i_2 
       (.I0(slaveRegDo_fff[8]),
        .I1(\slaveRegDo_mux_3_reg[8] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [8]),
        .I4(s_daddr_o[0]),
        .I5(D[8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_3[9]_i_2 
       (.I0(slaveRegDo_fff[9]),
        .I1(\slaveRegDo_mux_3_reg[9] ),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_3_reg[15]_1 [9]),
        .I4(s_daddr_o[0]),
        .I5(D[9]),
        .O(\parallel_dout_reg[9]_0 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized5
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__7_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__7_n_0 ;
  wire \current_state[3]_i_3__7_n_0 ;
  wire \current_state[3]_i_4__7_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__7_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__7_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__7_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__7 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__7 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__7 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__7 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__7_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__7_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__7_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__7 
       (.I0(\current_state[3]_i_4__7_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__7_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__7_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__7 
       (.I0(\current_state[3]_i_4__7_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__7_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__7 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__7_n_0 ),
        .I2(\current_state[3]_i_4__7_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__7 
       (.I0(\current_state[3]_i_2__7_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__7_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__7_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__7 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \current_state[3]_i_3__7 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__7 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__7_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__7
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__7_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__7_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__7 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__7 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__7 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__7 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__7 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__7 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__7 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__7 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__7 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__7 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__7 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__7 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__7 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__7 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__7 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__7 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__7_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__7
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__7_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__7_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__6
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized6
   (\parallel_dout_reg[15]_0 ,
    \parallel_dout_reg[14]_0 ,
    \parallel_dout_reg[13]_0 ,
    \parallel_dout_reg[12]_0 ,
    \parallel_dout_reg[11]_0 ,
    \parallel_dout_reg[10]_0 ,
    \parallel_dout_reg[9]_0 ,
    \parallel_dout_reg[8]_0 ,
    \parallel_dout_reg[7]_0 ,
    \parallel_dout_reg[6]_0 ,
    \parallel_dout_reg[5]_0 ,
    \parallel_dout_reg[4]_0 ,
    \parallel_dout_reg[3]_0 ,
    \parallel_dout_reg[2]_0 ,
    \parallel_dout_reg[1]_0 ,
    \parallel_dout_reg[0]_0 ,
    E,
    mu_config_cs_serial_output,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_4_reg[15] ,
    \slaveRegDo_mux_4_reg[15]_0 ,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[1]_0 ,
    \current_state_reg[1]_1 ,
    \current_state_reg[3]_0 );
  output \parallel_dout_reg[15]_0 ;
  output \parallel_dout_reg[14]_0 ;
  output \parallel_dout_reg[13]_0 ;
  output \parallel_dout_reg[12]_0 ;
  output \parallel_dout_reg[11]_0 ;
  output \parallel_dout_reg[10]_0 ;
  output \parallel_dout_reg[9]_0 ;
  output \parallel_dout_reg[8]_0 ;
  output \parallel_dout_reg[7]_0 ;
  output \parallel_dout_reg[6]_0 ;
  output \parallel_dout_reg[5]_0 ;
  output \parallel_dout_reg[4]_0 ;
  output \parallel_dout_reg[3]_0 ;
  output \parallel_dout_reg[2]_0 ;
  output \parallel_dout_reg[1]_0 ;
  output \parallel_dout_reg[0]_0 ;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input [15:0]s_do_o;
  input [1:0]s_daddr_o;
  input [15:0]\slaveRegDo_mux_4_reg[15] ;
  input [15:0]\slaveRegDo_mux_4_reg[15]_0 ;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[1]_0 ;
  input \current_state_reg[1]_1 ;
  input \current_state_reg[3]_0 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__8_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__8_n_0 ;
  wire \current_state[3]_i_3__8_n_0 ;
  wire \current_state[3]_i_4__8_n_0 ;
  wire \current_state_reg[1]_0 ;
  wire \current_state_reg[1]_1 ;
  wire \current_state_reg[3]_0 ;
  wire data_out_sel_i_1__8_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire \parallel_dout_reg[0]_0 ;
  wire \parallel_dout_reg[10]_0 ;
  wire \parallel_dout_reg[11]_0 ;
  wire \parallel_dout_reg[12]_0 ;
  wire \parallel_dout_reg[13]_0 ;
  wire \parallel_dout_reg[14]_0 ;
  wire \parallel_dout_reg[15]_0 ;
  wire \parallel_dout_reg[1]_0 ;
  wire \parallel_dout_reg[2]_0 ;
  wire \parallel_dout_reg[3]_0 ;
  wire \parallel_dout_reg[4]_0 ;
  wire \parallel_dout_reg[5]_0 ;
  wire \parallel_dout_reg[6]_0 ;
  wire \parallel_dout_reg[7]_0 ;
  wire \parallel_dout_reg[8]_0 ;
  wire \parallel_dout_reg[9]_0 ;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__8_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__8_n_0;
  wire [15:0]\slaveRegDo_muConfig[4103]_8 ;
  wire [15:0]\slaveRegDo_mux_4_reg[15] ;
  wire [15:0]\slaveRegDo_mux_4_reg[15]_0 ;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__8 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__8 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__8 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__8 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__8_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__8_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__8_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__8 
       (.I0(\current_state[3]_i_4__8_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__8_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__8_n_0 ),
        .O(next_state[0]));
  LUT5 #(
    .INIT(32'h00000080)) 
    \current_state[1]_i_1__8 
       (.I0(\current_state[3]_i_4__8_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state_reg[1]_0 ),
        .I4(\current_state_reg[1]_1 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__8 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__8_n_0 ),
        .I2(\current_state[3]_i_4__8_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__8 
       (.I0(\current_state[3]_i_2__8_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__8_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__8_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__8 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__8_n_0 ));
  LUT4 #(
    .INIT(16'hFFBF)) 
    \current_state[3]_i_3__8 
       (.I0(\current_state_reg[1]_1 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_0 ),
        .O(\current_state[3]_i_3__8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__8 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__8_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__8
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__8_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__8_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [1]),
        .Q(\slaveRegDo_muConfig[4103]_8 [0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [11]),
        .Q(\slaveRegDo_muConfig[4103]_8 [10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [12]),
        .Q(\slaveRegDo_muConfig[4103]_8 [11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [13]),
        .Q(\slaveRegDo_muConfig[4103]_8 [12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [14]),
        .Q(\slaveRegDo_muConfig[4103]_8 [13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [15]),
        .Q(\slaveRegDo_muConfig[4103]_8 [14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4103]_8 [15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [2]),
        .Q(\slaveRegDo_muConfig[4103]_8 [1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [3]),
        .Q(\slaveRegDo_muConfig[4103]_8 [2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [4]),
        .Q(\slaveRegDo_muConfig[4103]_8 [3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [5]),
        .Q(\slaveRegDo_muConfig[4103]_8 [4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [6]),
        .Q(\slaveRegDo_muConfig[4103]_8 [5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [7]),
        .Q(\slaveRegDo_muConfig[4103]_8 [6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [8]),
        .Q(\slaveRegDo_muConfig[4103]_8 [7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [9]),
        .Q(\slaveRegDo_muConfig[4103]_8 [8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\slaveRegDo_muConfig[4103]_8 [10]),
        .Q(\slaveRegDo_muConfig[4103]_8 [9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__8 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__8 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__8 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__8 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__8 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__8 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__8 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__8 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__8 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__8 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__8 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__8 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__8 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__8 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__8 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__8 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__8_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__8
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__8_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__8_n_0),
        .Q(E),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[0]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [0]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [0]),
        .O(\parallel_dout_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[10]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [10]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [10]),
        .O(\parallel_dout_reg[10]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[11]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [11]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [11]),
        .O(\parallel_dout_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[12]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [12]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [12]),
        .O(\parallel_dout_reg[12]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[13]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [13]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [13]),
        .O(\parallel_dout_reg[13]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[14]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [14]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [14]),
        .O(\parallel_dout_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[15]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [15]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [15]),
        .O(\parallel_dout_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[1]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [1]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [1]),
        .O(\parallel_dout_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[2]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [2]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [2]),
        .O(\parallel_dout_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[3]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [3]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [3]),
        .O(\parallel_dout_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[4]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [4]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [4]),
        .O(\parallel_dout_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[5]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [5]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [5]),
        .O(\parallel_dout_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[6]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [6]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [6]),
        .O(\parallel_dout_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[7]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [7]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [7]),
        .O(\parallel_dout_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[8]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [8]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [8]),
        .O(\parallel_dout_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \slaveRegDo_mux_4[9]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_4_reg[15] [9]),
        .I4(s_daddr_o[0]),
        .I5(\slaveRegDo_mux_4_reg[15]_0 [9]),
        .O(\parallel_dout_reg[9]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__7
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized7
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    s_daddr_o,
    \current_state_reg[3]_1 );
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input [1:0]s_daddr_o;
  input \current_state_reg[3]_1 ;

  wire [0:0]E;
  wire \cnt[3]_i_1__9_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__9_n_0 ;
  wire \current_state[3]_i_3__9_n_0 ;
  wire \current_state[3]_i_4__9_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__9_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__9_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__9_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__9 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__9 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__9 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__9 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__9_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__9_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__9_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__9 
       (.I0(\current_state[3]_i_4__9_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__9_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__9_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__9 
       (.I0(\current_state[3]_i_4__9_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__9_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__9 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__9_n_0 ),
        .I2(\current_state[3]_i_4__9_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__9 
       (.I0(\current_state[3]_i_2__9_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__9_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__9_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__9 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__9_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \current_state[3]_i_3__9 
       (.I0(\current_state_reg[3]_0 ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\current_state_reg[3]_1 ),
        .O(\current_state[3]_i_3__9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__9 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__9_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__9
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__9_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__9_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__9 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__9 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__9 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__9 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__9 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__9 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__9 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__9_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__9 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__9 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__9 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__9 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__9 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__9 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__9 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__9 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__9 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__9_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__9
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__9_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__9_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__8
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized8
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__10_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__10_n_0 ;
  wire \current_state[3]_i_3__10_n_0 ;
  wire \current_state[3]_i_4__10_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__10_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__10_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__10_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__10 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__10 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__10 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__10 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__10_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__10_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__10_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__10 
       (.I0(\current_state[3]_i_4__10_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__10_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__10_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__10 
       (.I0(\current_state[3]_i_4__10_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__10_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__10 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__10_n_0 ),
        .I2(\current_state[3]_i_4__10_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__10 
       (.I0(\current_state[3]_i_2__10_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__10_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__10_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__10 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \current_state[3]_i_3__10 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__10 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__10_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__10
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__10_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__10_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__10 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__10 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__10 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__10 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__10 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__10 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__10 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__10 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__10 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__10 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__10 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__10 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__10 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__10 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__10 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__10 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__10_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__10
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__10_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__10_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__9
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_p2s" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized9
   (s_do_o,
    E,
    mu_config_cs_serial_output,
    s_dclk_o,
    mu_config_cs_serial_input,
    \shadow_reg[15]_0 ,
    s_di_o,
    s_dwe_o,
    \current_state_reg[3]_0 ,
    \current_state_reg[3]_1 ,
    s_daddr_o,
    s_den_o);
  output [15:0]s_do_o;
  output [0:0]E;
  output [0:0]mu_config_cs_serial_output;
  input s_dclk_o;
  input [0:0]mu_config_cs_serial_input;
  input \shadow_reg[15]_0 ;
  input [14:0]s_di_o;
  input s_dwe_o;
  input \current_state_reg[3]_0 ;
  input \current_state_reg[3]_1 ;
  input [2:0]s_daddr_o;
  input s_den_o;

  wire [0:0]E;
  wire \cnt[3]_i_1__11_n_0 ;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire \current_state[3]_i_2__11_n_0 ;
  wire \current_state[3]_i_3__11_n_0 ;
  wire \current_state[3]_i_4__11_n_0 ;
  wire \current_state_reg[3]_0 ;
  wire \current_state_reg[3]_1 ;
  wire data_out_sel_i_1__11_n_0;
  wire data_out_sel_reg_n_0;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire [2:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [14:0]s_di_o;
  wire [15:0]s_do_o;
  wire s_dwe_o;
  wire serial_dout;
  wire [14:0]shadow;
  wire \shadow[15]_i_1__11_n_0 ;
  wire \shadow_reg[15]_0 ;
  wire \shadow_reg_n_0_[0] ;
  wire \shadow_reg_n_0_[10] ;
  wire \shadow_reg_n_0_[11] ;
  wire \shadow_reg_n_0_[12] ;
  wire \shadow_reg_n_0_[13] ;
  wire \shadow_reg_n_0_[14] ;
  wire \shadow_reg_n_0_[15] ;
  wire \shadow_reg_n_0_[1] ;
  wire \shadow_reg_n_0_[2] ;
  wire \shadow_reg_n_0_[3] ;
  wire \shadow_reg_n_0_[4] ;
  wire \shadow_reg_n_0_[5] ;
  wire \shadow_reg_n_0_[6] ;
  wire \shadow_reg_n_0_[7] ;
  wire \shadow_reg_n_0_[8] ;
  wire \shadow_reg_n_0_[9] ;
  wire shift_en_i_1__11_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \cnt[0]_i_1__11 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt[1]_i_1__11 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \cnt[2]_i_1__11 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
  LUT4 #(
    .INIT(16'hFFEB)) 
    \cnt[3]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .O(\cnt[3]_i_1__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \cnt[3]_i_2__11 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
  FDRE \cnt_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(\cnt[3]_i_1__11_n_0 ));
  FDRE \cnt_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(\cnt[3]_i_1__11_n_0 ));
  FDRE \cnt_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(\cnt[3]_i_1__11_n_0 ));
  FDRE \cnt_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(\cnt[3]_i_1__11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF55FD55FD55FD)) 
    \current_state[0]_i_1__11 
       (.I0(\current_state[3]_i_4__11_n_0 ),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\current_state[3]_i_2__11_n_0 ),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_3__11_n_0 ),
        .O(next_state[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    \current_state[1]_i_1__11 
       (.I0(\current_state[3]_i_4__11_n_0 ),
        .I1(current_state[0]),
        .I2(s_dwe_o),
        .I3(\current_state[3]_i_3__11_n_0 ),
        .O(next_state[1]));
  LUT4 #(
    .INIT(16'hE0A0)) 
    \current_state[2]_i_1__11 
       (.I0(current_state[1]),
        .I1(\current_state[3]_i_2__11_n_0 ),
        .I2(\current_state[3]_i_4__11_n_0 ),
        .I3(current_state[2]),
        .O(next_state[2]));
  LUT6 #(
    .INIT(64'h888F888800000000)) 
    \current_state[3]_i_1__11 
       (.I0(\current_state[3]_i_2__11_n_0 ),
        .I1(current_state[3]),
        .I2(\current_state[3]_i_3__11_n_0 ),
        .I3(s_dwe_o),
        .I4(current_state[0]),
        .I5(\current_state[3]_i_4__11_n_0 ),
        .O(next_state[3]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \current_state[3]_i_2__11 
       (.I0(cnt_reg__0[2]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[1]),
        .I3(cnt_reg__0[3]),
        .O(\current_state[3]_i_2__11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \current_state[3]_i_3__11 
       (.I0(\current_state_reg[3]_0 ),
        .I1(\current_state_reg[3]_1 ),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_den_o),
        .I5(s_daddr_o[2]),
        .O(\current_state[3]_i_3__11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \current_state[3]_i_4__11 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\current_state[3]_i_4__11_n_0 ));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
  (* FSM_ENCODED_STATES = "REG:0010,P2S:0100,IDLE:0001,S2P:1000" *) 
  FDRE \current_state_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    data_out_sel_i_1__11
       (.I0(current_state[1]),
        .I1(current_state[2]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(data_out_sel_i_1__11_n_0));
  FDRE data_out_sel_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(data_out_sel_i_1__11_n_0),
        .Q(data_out_sel_reg_n_0),
        .R(1'b0));
  FDRE \parallel_dout_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \parallel_dout_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \parallel_dout_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \parallel_dout_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \parallel_dout_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \parallel_dout_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \parallel_dout_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \parallel_dout_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \parallel_dout_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \parallel_dout_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \parallel_dout_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \parallel_dout_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \parallel_dout_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \parallel_dout_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \parallel_dout_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \parallel_dout_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
  FDRE serial_dout_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow_reg_n_0_[0] ),
        .Q(serial_dout),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[0]_i_1__11 
       (.I0(\shadow_reg_n_0_[1] ),
        .I1(s_di_o[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[0]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[10]_i_1__11 
       (.I0(\shadow_reg_n_0_[11] ),
        .I1(s_di_o[10]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[10]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[11]_i_1__11 
       (.I0(\shadow_reg_n_0_[12] ),
        .I1(s_di_o[11]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[11]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[12]_i_1__11 
       (.I0(\shadow_reg_n_0_[13] ),
        .I1(s_di_o[12]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[12]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[13]_i_1__11 
       (.I0(\shadow_reg_n_0_[14] ),
        .I1(s_di_o[13]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[13]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[14]_i_1__11 
       (.I0(\shadow_reg_n_0_[15] ),
        .I1(s_di_o[14]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[14]));
  LUT4 #(
    .INIT(16'h0004)) 
    \shadow[15]_i_1__11 
       (.I0(current_state[2]),
        .I1(current_state[1]),
        .I2(current_state[3]),
        .I3(current_state[0]),
        .O(\shadow[15]_i_1__11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[1]_i_1__11 
       (.I0(\shadow_reg_n_0_[2] ),
        .I1(s_di_o[1]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[1]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[2]_i_1__11 
       (.I0(\shadow_reg_n_0_[3] ),
        .I1(s_di_o[2]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[2]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[3]_i_1__11 
       (.I0(\shadow_reg_n_0_[4] ),
        .I1(s_di_o[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[3]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[4]_i_1__11 
       (.I0(\shadow_reg_n_0_[5] ),
        .I1(s_di_o[4]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[4]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[5]_i_1__11 
       (.I0(\shadow_reg_n_0_[6] ),
        .I1(s_di_o[5]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[5]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[6]_i_1__11 
       (.I0(\shadow_reg_n_0_[7] ),
        .I1(s_di_o[6]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[6]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[7]_i_1__11 
       (.I0(\shadow_reg_n_0_[8] ),
        .I1(s_di_o[7]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[7]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[8]_i_1__11 
       (.I0(\shadow_reg_n_0_[9] ),
        .I1(s_di_o[8]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[8]));
  LUT6 #(
    .INIT(64'h0000000000000CA0)) 
    \shadow[9]_i_1__11 
       (.I0(\shadow_reg_n_0_[10] ),
        .I1(s_di_o[9]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .I4(current_state[3]),
        .I5(current_state[0]),
        .O(shadow[9]));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[0]),
        .Q(\shadow_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[10] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[10]),
        .Q(\shadow_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[11] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[11]),
        .Q(\shadow_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[12] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[12]),
        .Q(\shadow_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[13] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[13]),
        .Q(\shadow_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[14] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[14]),
        .Q(\shadow_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[15] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\shadow[15]_i_1__11_n_0 ),
        .Q(\shadow_reg_n_0_[15] ),
        .R(\shadow_reg[15]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[1]),
        .Q(\shadow_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[2] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[2]),
        .Q(\shadow_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[3] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[3]),
        .Q(\shadow_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[4] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[4]),
        .Q(\shadow_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[5] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[5]),
        .Q(\shadow_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[6] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[6]),
        .Q(\shadow_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[7] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[7]),
        .Q(\shadow_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[8] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[8]),
        .Q(\shadow_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \shadow_reg[9] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shadow[9]),
        .Q(\shadow_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'h0014)) 
    shift_en_i_1__11
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(shift_en_i_1__11_n_0));
  FDRE shift_en_reg
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(shift_en_i_1__11_n_0),
        .Q(E),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    u_srlD_i_1__10
       (.I0(serial_dout),
        .I1(data_out_sel_reg_n_0),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat
   (\xsdb_reg_reg[15]_0 ,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[15]_1 ,
    data_out_en,
    \xsdb_reg_reg[15]_2 ,
    s_dclk_o,
    \xsdb_reg_reg[14]_1 ,
    \xsdb_reg_reg[13]_1 ,
    \xsdb_reg_reg[12]_1 ,
    \xsdb_reg_reg[11]_1 ,
    \xsdb_reg_reg[10]_1 ,
    \xsdb_reg_reg[9]_1 ,
    \xsdb_reg_reg[8]_1 ,
    \xsdb_reg_reg[7]_1 ,
    \xsdb_reg_reg[6]_1 ,
    \xsdb_reg_reg[5]_1 ,
    \xsdb_reg_reg[4]_1 ,
    \xsdb_reg_reg[3]_1 ,
    \xsdb_reg_reg[2]_1 ,
    \xsdb_reg_reg[1]_1 ,
    \xsdb_reg_reg[0]_1 );
  output \xsdb_reg_reg[15]_0 ;
  output \xsdb_reg_reg[14]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[10]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[4]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[15]_1 ;
  input data_out_en;
  input \xsdb_reg_reg[15]_2 ;
  input s_dclk_o;
  input \xsdb_reg_reg[14]_1 ;
  input \xsdb_reg_reg[13]_1 ;
  input \xsdb_reg_reg[12]_1 ;
  input \xsdb_reg_reg[11]_1 ;
  input \xsdb_reg_reg[10]_1 ;
  input \xsdb_reg_reg[9]_1 ;
  input \xsdb_reg_reg[8]_1 ;
  input \xsdb_reg_reg[7]_1 ;
  input \xsdb_reg_reg[6]_1 ;
  input \xsdb_reg_reg[5]_1 ;
  input \xsdb_reg_reg[4]_1 ;
  input \xsdb_reg_reg[3]_1 ;
  input \xsdb_reg_reg[2]_1 ;
  input \xsdb_reg_reg[1]_1 ;
  input \xsdb_reg_reg[0]_1 ;

  wire data_out_en;
  wire s_dclk_o;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[0]_1 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[10]_1 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[11]_1 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[12]_1 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[13]_1 ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[14]_1 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[15]_1 ;
  wire \xsdb_reg_reg[15]_2 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[1]_1 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[2]_1 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[3]_1 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[4]_1 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[5]_1 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[6]_1 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[7]_1 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[8]_1 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg[9]_1 ;

  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\xsdb_reg_reg[0]_1 ),
        .Q(\xsdb_reg_reg[0]_0 ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[10]_1 ),
        .Q(\xsdb_reg_reg[10]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[11]_1 ),
        .Q(\xsdb_reg_reg[11]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[12]_1 ),
        .Q(\xsdb_reg_reg[12]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[13]_1 ),
        .Q(\xsdb_reg_reg[13]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[14]_1 ),
        .Q(\xsdb_reg_reg[14]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[15]_2 ),
        .Q(\xsdb_reg_reg[15]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(\xsdb_reg_reg[1]_1 ),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[2]_1 ),
        .Q(\xsdb_reg_reg[2]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[3]_1 ),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[4]_1 ),
        .Q(\xsdb_reg_reg[4]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[5]_1 ),
        .Q(\xsdb_reg_reg[5]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[6]_1 ),
        .Q(\xsdb_reg_reg[6]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[7]_1 ),
        .Q(\xsdb_reg_reg[7]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[8]_1 ),
        .Q(\xsdb_reg_reg[8]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(data_out_en),
        .D(\xsdb_reg_reg[9]_1 ),
        .Q(\xsdb_reg_reg[9]_0 ),
        .R(\xsdb_reg_reg[15]_1 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_231
   (Q,
    s_den_o,
    \xsdb_reg_reg[9]_0 ,
    s_dclk_o);
  output [9:0]Q;
  input s_den_o;
  input [9:0]\xsdb_reg_reg[9]_0 ;
  input s_dclk_o;

  wire [9:0]Q;
  wire s_dclk_o;
  wire s_den_o;
  wire [9:0]\xsdb_reg_reg[9]_0 ;

  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[9]_0 [9]),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_232
   (\xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    \xsdb_reg_reg[3]_1 ,
    s_den_o,
    flag3_temp,
    s_dclk_o,
    flag2_temp,
    flag1_temp,
    flag0_temp);
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[2]_0 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  input \xsdb_reg_reg[3]_1 ;
  input s_den_o;
  input flag3_temp;
  input s_dclk_o;
  input flag2_temp;
  input flag1_temp;
  input flag0_temp;

  wire flag0_temp;
  wire flag1_temp;
  wire flag2_temp;
  wire flag3_temp;
  wire s_dclk_o;
  wire s_den_o;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[3]_1 ;

  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(flag0_temp),
        .Q(\xsdb_reg_reg[0]_0 ),
        .R(\xsdb_reg_reg[3]_1 ));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(flag1_temp),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(\xsdb_reg_reg[3]_1 ));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(flag2_temp),
        .Q(\xsdb_reg_reg[2]_0 ),
        .R(\xsdb_reg_reg[3]_1 ));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(flag3_temp),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(\xsdb_reg_reg[3]_1 ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_233
   (\xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[4] ,
    \G_1PIPE_IFACE.s_den_r_reg ,
    D,
    \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 ,
    \slaveRegDo_mux_2_reg[15] ,
    s_do_o,
    s_daddr_o,
    \slaveRegDo_mux_2_reg[15]_0 ,
    \slaveRegDo_mux_2_reg[5] ,
    s_den_o,
    \xsdb_reg_reg[15]_0 ,
    \slaveRegDo_mux_2_reg[4] ,
    \slaveRegDo_mux_2_reg[4]_0 ,
    \slaveRegDo_mux_2_reg[2] ,
    \slaveRegDo_mux_2_reg[4]_1 ,
    \slaveRegDo_mux_2_reg[4]_2 ,
    \slaveRegDo_mux_2_reg[2]_0 ,
    \slaveRegDo_mux_2_reg[2]_1 ,
    SEQUENCER_STATE_O,
    s_dclk_o);
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[7]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[10]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output \xsdb_reg_reg[12]_0 ;
  output \xsdb_reg_reg[13]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  output \G_1PIPE_IFACE.s_den_r_reg ;
  output [1:0]D;
  output \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
  output \xsdb_reg_reg[3]_0 ;
  output \xsdb_reg_reg[1]_0 ;
  output \xsdb_reg_reg[0]_0 ;
  input \slaveRegDo_mux_2_reg[15] ;
  input [12:0]s_do_o;
  input [3:0]s_daddr_o;
  input \slaveRegDo_mux_2_reg[15]_0 ;
  input \slaveRegDo_mux_2_reg[5] ;
  input s_den_o;
  input \xsdb_reg_reg[15]_0 ;
  input \slaveRegDo_mux_2_reg[4] ;
  input \slaveRegDo_mux_2_reg[4]_0 ;
  input \slaveRegDo_mux_2_reg[2] ;
  input \slaveRegDo_mux_2_reg[4]_1 ;
  input \slaveRegDo_mux_2_reg[4]_2 ;
  input \slaveRegDo_mux_2_reg[2]_0 ;
  input \slaveRegDo_mux_2_reg[2]_1 ;
  input [15:0]SEQUENCER_STATE_O;
  input s_dclk_o;

  wire [1:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
  wire \G_1PIPE_IFACE.s_den_r_reg ;
  wire [15:0]SEQUENCER_STATE_O;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [12:0]s_do_o;
  wire \slaveRegDo_mux_2[2]_i_3_n_0 ;
  wire \slaveRegDo_mux_2[4]_i_3_n_0 ;
  wire \slaveRegDo_mux_2_reg[15] ;
  wire \slaveRegDo_mux_2_reg[15]_0 ;
  wire \slaveRegDo_mux_2_reg[2] ;
  wire \slaveRegDo_mux_2_reg[2]_0 ;
  wire \slaveRegDo_mux_2_reg[2]_1 ;
  wire \slaveRegDo_mux_2_reg[4] ;
  wire \slaveRegDo_mux_2_reg[4]_0 ;
  wire \slaveRegDo_mux_2_reg[4]_1 ;
  wire \slaveRegDo_mux_2_reg[4]_2 ;
  wire \slaveRegDo_mux_2_reg[5] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg_n_0_[10] ;
  wire \xsdb_reg_reg_n_0_[11] ;
  wire \xsdb_reg_reg_n_0_[12] ;
  wire \xsdb_reg_reg_n_0_[13] ;
  wire \xsdb_reg_reg_n_0_[14] ;
  wire \xsdb_reg_reg_n_0_[15] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[4] ;
  wire \xsdb_reg_reg_n_0_[5] ;
  wire \xsdb_reg_reg_n_0_[6] ;
  wire \xsdb_reg_reg_n_0_[7] ;
  wire \xsdb_reg_reg_n_0_[8] ;
  wire \xsdb_reg_reg_n_0_[9] ;

  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[10]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[7]),
        .I2(\xsdb_reg_reg_n_0_[10] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[10]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[11]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[8]),
        .I2(\xsdb_reg_reg_n_0_[11] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[11]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[12]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[9]),
        .I2(\xsdb_reg_reg_n_0_[12] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[12]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[13]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[10]),
        .I2(\xsdb_reg_reg_n_0_[13] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[13]_0 ));
  LUT6 #(
    .INIT(64'h01000100FFFF0100)) 
    \slaveRegDo_mux_2[14]_i_1 
       (.I0(s_daddr_o[3]),
        .I1(\slaveRegDo_mux_2_reg[15]_0 ),
        .I2(\slaveRegDo_mux_2_reg[5] ),
        .I3(\xsdb_reg_reg_n_0_[14] ),
        .I4(s_do_o[11]),
        .I5(\slaveRegDo_mux_2_reg[15] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[4] ));
  LUT6 #(
    .INIT(64'h0100FFFF01000100)) 
    \slaveRegDo_mux_2[15]_i_2 
       (.I0(s_daddr_o[3]),
        .I1(\slaveRegDo_mux_2_reg[15]_0 ),
        .I2(\slaveRegDo_mux_2_reg[5] ),
        .I3(\xsdb_reg_reg_n_0_[15] ),
        .I4(\slaveRegDo_mux_2_reg[15] ),
        .I5(s_do_o[12]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hFFFF88F888888888)) 
    \slaveRegDo_mux_2[2]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[4] ),
        .I1(\slaveRegDo_mux_2_reg[4]_0 ),
        .I2(s_do_o[0]),
        .I3(\slaveRegDo_mux_2_reg[15] ),
        .I4(\slaveRegDo_mux_2[2]_i_3_n_0 ),
        .I5(\slaveRegDo_mux_2_reg[2] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h00000000E868C848)) 
    \slaveRegDo_mux_2[2]_i_3 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\xsdb_reg_reg_n_0_[2] ),
        .I4(\slaveRegDo_mux_2_reg[2]_0 ),
        .I5(\slaveRegDo_mux_2_reg[2]_1 ),
        .O(\slaveRegDo_mux_2[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF888B)) 
    \slaveRegDo_mux_2[4]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[4]_0 ),
        .I1(\slaveRegDo_mux_2_reg[4] ),
        .I2(\slaveRegDo_mux_2_reg[4]_1 ),
        .I3(\slaveRegDo_mux_2[4]_i_3_n_0 ),
        .I4(\slaveRegDo_mux_2_reg[4]_2 ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hFFFD0000FFFDFFFD)) 
    \slaveRegDo_mux_2[4]_i_3 
       (.I0(\xsdb_reg_reg_n_0_[4] ),
        .I1(s_daddr_o[3]),
        .I2(\slaveRegDo_mux_2_reg[15]_0 ),
        .I3(\slaveRegDo_mux_2_reg[5] ),
        .I4(\slaveRegDo_mux_2_reg[15] ),
        .I5(s_do_o[1]),
        .O(\slaveRegDo_mux_2[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[5]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[2]),
        .I2(\xsdb_reg_reg_n_0_[5] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[6]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[3]),
        .I2(\xsdb_reg_reg_n_0_[6] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[6]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[7]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[4]),
        .I2(\xsdb_reg_reg_n_0_[7] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[7]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[8]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[5]),
        .I2(\xsdb_reg_reg_n_0_[8] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[8]_0 ));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \slaveRegDo_mux_2[9]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[15] ),
        .I1(s_do_o[6]),
        .I2(\xsdb_reg_reg_n_0_[9] ),
        .I3(s_daddr_o[3]),
        .I4(\slaveRegDo_mux_2_reg[15]_0 ),
        .I5(\slaveRegDo_mux_2_reg[5] ),
        .O(\xsdb_reg_reg[9]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \xsdb_reg[3]_i_1__0 
       (.I0(s_den_o),
        .I1(\xsdb_reg_reg[15]_0 ),
        .O(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[0]),
        .Q(\xsdb_reg_reg[0]_0 ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[10]),
        .Q(\xsdb_reg_reg_n_0_[10] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[11]),
        .Q(\xsdb_reg_reg_n_0_[11] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[12]),
        .Q(\xsdb_reg_reg_n_0_[12] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[13]),
        .Q(\xsdb_reg_reg_n_0_[13] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[14]),
        .Q(\xsdb_reg_reg_n_0_[14] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[15]),
        .Q(\xsdb_reg_reg_n_0_[15] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[1]),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[3]),
        .Q(\xsdb_reg_reg[3]_0 ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[5]),
        .Q(\xsdb_reg_reg_n_0_[5] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[6]),
        .Q(\xsdb_reg_reg_n_0_[6] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[7]),
        .Q(\xsdb_reg_reg_n_0_[7] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[8]),
        .Q(\xsdb_reg_reg_n_0_[8] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(SEQUENCER_STATE_O[9]),
        .Q(\xsdb_reg_reg_n_0_[9] ),
        .R(\G_1PIPE_IFACE.s_den_r_reg ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_234
   (D,
    \slaveRegDo_mux_2_reg[1] ,
    \slaveRegDo_mux_2_reg[1]_0 ,
    s_do_o,
    \slaveRegDo_mux_2_reg[0] ,
    \slaveRegDo_mux_2_reg[0]_0 ,
    \slaveRegDo_mux_2_reg[0]_1 ,
    \slaveRegDo_mux_2_reg[0]_2 ,
    \slaveRegDo_mux_2_reg[0]_3 ,
    \slaveRegDo_mux_2_reg[0]_4 ,
    s_daddr_o,
    \slaveRegDo_mux_2_reg[1]_1 ,
    \slaveRegDo_mux_2_reg[1]_2 ,
    \slaveRegDo_mux_2_reg[1]_3 ,
    s_den_o,
    \xsdb_reg_reg[1]_0 ,
    s_dclk_o);
  output [1:0]D;
  input \slaveRegDo_mux_2_reg[1] ;
  input [0:0]\slaveRegDo_mux_2_reg[1]_0 ;
  input [1:0]s_do_o;
  input \slaveRegDo_mux_2_reg[0] ;
  input \slaveRegDo_mux_2_reg[0]_0 ;
  input \slaveRegDo_mux_2_reg[0]_1 ;
  input \slaveRegDo_mux_2_reg[0]_2 ;
  input \slaveRegDo_mux_2_reg[0]_3 ;
  input \slaveRegDo_mux_2_reg[0]_4 ;
  input [1:0]s_daddr_o;
  input \slaveRegDo_mux_2_reg[1]_1 ;
  input \slaveRegDo_mux_2_reg[1]_2 ;
  input \slaveRegDo_mux_2_reg[1]_3 ;
  input s_den_o;
  input [1:0]\xsdb_reg_reg[1]_0 ;
  input s_dclk_o;

  wire [1:0]D;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [1:0]s_do_o;
  wire \slaveRegDo_mux_2[0]_i_3_n_0 ;
  wire \slaveRegDo_mux_2[1]_i_2_n_0 ;
  wire \slaveRegDo_mux_2_reg[0] ;
  wire \slaveRegDo_mux_2_reg[0]_0 ;
  wire \slaveRegDo_mux_2_reg[0]_1 ;
  wire \slaveRegDo_mux_2_reg[0]_2 ;
  wire \slaveRegDo_mux_2_reg[0]_3 ;
  wire \slaveRegDo_mux_2_reg[0]_4 ;
  wire \slaveRegDo_mux_2_reg[1] ;
  wire [0:0]\slaveRegDo_mux_2_reg[1]_0 ;
  wire \slaveRegDo_mux_2_reg[1]_1 ;
  wire \slaveRegDo_mux_2_reg[1]_2 ;
  wire \slaveRegDo_mux_2_reg[1]_3 ;
  wire [1:0]\xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg_n_0_[0] ;
  wire \xsdb_reg_reg_n_0_[1] ;

  LUT6 #(
    .INIT(64'hFFFFFFFFBABBBABA)) 
    \slaveRegDo_mux_2[0]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[0]_1 ),
        .I1(\slaveRegDo_mux_2_reg[0]_0 ),
        .I2(\slaveRegDo_mux_2[0]_i_3_n_0 ),
        .I3(\slaveRegDo_mux_2_reg[0] ),
        .I4(s_do_o[0]),
        .I5(\slaveRegDo_mux_2_reg[0]_2 ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'h00000000F0CCAAFF)) 
    \slaveRegDo_mux_2[0]_i_3 
       (.I0(\xsdb_reg_reg_n_0_[0] ),
        .I1(\slaveRegDo_mux_2_reg[0]_3 ),
        .I2(\slaveRegDo_mux_2_reg[0]_4 ),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(\slaveRegDo_mux_2_reg[1]_1 ),
        .O(\slaveRegDo_mux_2[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h88888888FFFF88F8)) 
    \slaveRegDo_mux_2[1]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[1] ),
        .I1(\slaveRegDo_mux_2_reg[1]_0 ),
        .I2(s_do_o[1]),
        .I3(\slaveRegDo_mux_2_reg[0] ),
        .I4(\slaveRegDo_mux_2[1]_i_2_n_0 ),
        .I5(\slaveRegDo_mux_2_reg[0]_0 ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h00000000F8C83808)) 
    \slaveRegDo_mux_2[1]_i_2 
       (.I0(\xsdb_reg_reg_n_0_[1] ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\slaveRegDo_mux_2_reg[1]_2 ),
        .I4(\slaveRegDo_mux_2_reg[1]_3 ),
        .I5(\slaveRegDo_mux_2_reg[1]_1 ),
        .O(\slaveRegDo_mux_2[1]_i_2_n_0 ));
  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[1]_0 [0]),
        .Q(\xsdb_reg_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\xsdb_reg_reg[1]_0 [1]),
        .Q(\xsdb_reg_reg_n_0_[1] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_235
   (\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
    s_den_o,
    out,
    s_dclk_o,
    \slaveRegDo_mux_2_reg[3] ,
    s_daddr_o,
    s_do_o,
    \slaveRegDo_mux_2_reg[3]_0 ,
    \slaveRegDo_mux_2_reg[3]_1 );
  output \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  input s_den_o;
  input out;
  input s_dclk_o;
  input \slaveRegDo_mux_2_reg[3] ;
  input [4:0]s_daddr_o;
  input [0:0]s_do_o;
  input \slaveRegDo_mux_2_reg[3]_0 ;
  input \slaveRegDo_mux_2_reg[3]_1 ;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
  wire out;
  wire [4:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire [0:0]s_do_o;
  wire \slaveRegDo_mux_2[3]_i_3_n_0 ;
  wire \slaveRegDo_mux_2_reg[3] ;
  wire \slaveRegDo_mux_2_reg[3]_0 ;
  wire \slaveRegDo_mux_2_reg[3]_1 ;
  wire \xsdb_reg_reg_n_0_[3] ;

  LUT6 #(
    .INIT(64'h000000FF10100000)) 
    \slaveRegDo_mux_2[3]_i_1 
       (.I0(\slaveRegDo_mux_2_reg[3] ),
        .I1(s_daddr_o[3]),
        .I2(s_do_o),
        .I3(\slaveRegDo_mux_2[3]_i_3_n_0 ),
        .I4(s_daddr_o[4]),
        .I5(s_daddr_o[2]),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[3] ));
  LUT6 #(
    .INIT(64'h333FFF3F77FF77FF)) 
    \slaveRegDo_mux_2[3]_i_3 
       (.I0(\xsdb_reg_reg_n_0_[3] ),
        .I1(s_daddr_o[1]),
        .I2(\slaveRegDo_mux_2_reg[3]_0 ),
        .I3(s_daddr_o[0]),
        .I4(\slaveRegDo_mux_2_reg[3]_1 ),
        .I5(s_daddr_o[3]),
        .O(\slaveRegDo_mux_2[3]_i_3_n_0 ));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(out),
        .Q(\xsdb_reg_reg_n_0_[3] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_241
   (\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \xsdb_reg_reg[2]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ,
    \xsdb_reg_reg[1]_0 ,
    s_daddr_o,
    Q,
    \slaveRegDo_mux_0[0]_i_2 ,
    \slaveRegDo_mux_0[3]_i_3 ,
    \slaveRegDo_mux_0[2]_i_2 ,
    \slaveRegDo_mux_0[6]_i_3 ,
    \slaveRegDo_mux_0[0]_i_2_0 ,
    s_den_o,
    D,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \xsdb_reg_reg[2]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  output [0:0]\xsdb_reg_reg[1]_0 ;
  input [1:0]s_daddr_o;
  input [3:0]Q;
  input \slaveRegDo_mux_0[0]_i_2 ;
  input \slaveRegDo_mux_0[3]_i_3 ;
  input \slaveRegDo_mux_0[2]_i_2 ;
  input \slaveRegDo_mux_0[6]_i_3 ;
  input \slaveRegDo_mux_0[0]_i_2_0 ;
  input s_den_o;
  input [4:0]D;
  input s_dclk_o;

  wire [4:0]D;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  wire [3:0]Q;
  wire [1:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire \slaveRegDo_mux_0[0]_i_2 ;
  wire \slaveRegDo_mux_0[0]_i_2_0 ;
  wire \slaveRegDo_mux_0[2]_i_2 ;
  wire \slaveRegDo_mux_0[3]_i_3 ;
  wire \slaveRegDo_mux_0[6]_i_3 ;
  wire [0:0]\xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg_n_0_[0] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[3] ;
  wire \xsdb_reg_reg_n_0_[6] ;

  LUT6 #(
    .INIT(64'h00000000FFFFABFB)) 
    \slaveRegDo_mux_0[0]_i_6 
       (.I0(s_daddr_o[1]),
        .I1(\xsdb_reg_reg_n_0_[0] ),
        .I2(s_daddr_o[0]),
        .I3(Q[0]),
        .I4(\slaveRegDo_mux_0[0]_i_2 ),
        .I5(\slaveRegDo_mux_0[0]_i_2_0 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h00000000FCFDFFFD)) 
    \slaveRegDo_mux_0[2]_i_6 
       (.I0(\xsdb_reg_reg_n_0_[2] ),
        .I1(\slaveRegDo_mux_0[0]_i_2 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[0]),
        .I4(Q[1]),
        .I5(\slaveRegDo_mux_0[2]_i_2 ),
        .O(\xsdb_reg_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFABFB)) 
    \slaveRegDo_mux_0[3]_i_7 
       (.I0(s_daddr_o[1]),
        .I1(\xsdb_reg_reg_n_0_[3] ),
        .I2(s_daddr_o[0]),
        .I3(Q[2]),
        .I4(\slaveRegDo_mux_0[0]_i_2 ),
        .I5(\slaveRegDo_mux_0[3]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1] ));
  LUT6 #(
    .INIT(64'h00000000FFFFABFB)) 
    \slaveRegDo_mux_0[6]_i_7 
       (.I0(s_daddr_o[1]),
        .I1(\xsdb_reg_reg_n_0_[6] ),
        .I2(s_daddr_o[0]),
        .I3(Q[3]),
        .I4(\slaveRegDo_mux_0[0]_i_2 ),
        .I5(\slaveRegDo_mux_0[6]_i_3 ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ));
  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(D[0]),
        .Q(\xsdb_reg_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(D[1]),
        .Q(\xsdb_reg_reg[1]_0 ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(D[2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(D[3]),
        .Q(\xsdb_reg_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(D[4]),
        .Q(\xsdb_reg_reg_n_0_[6] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_248
   (\xsdb_reg_reg[0]_0 ,
    \slaveRegDo_ff9_reg[2] ,
    \slaveRegDo_ff9_reg[2]_0 ,
    \slaveRegDo_ffa_reg[11] ,
    \slaveRegDo_ffa_reg[11]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[11]_0 ,
    Q,
    slaveRegDo_ff9,
    D,
    slaveRegDo_ffa,
    \slaveRegDo_mux_3_reg[4] ,
    \slaveRegDo_mux_3_reg[14] ,
    \slaveRegDo_mux_3_reg[13] ,
    \slaveRegDo_mux_3_reg[12] ,
    \slaveRegDo_mux_3_reg[11] ,
    \slaveRegDo_mux_3_reg[11]_0 ,
    \slaveRegDo_mux_3_reg[5] ,
    \slaveRegDo_mux_3_reg[6] ,
    \slaveRegDo_mux_3_reg[8] ,
    \slaveRegDo_mux_3_reg[9] ,
    \slaveRegDo_mux_3_reg[11]_1 ,
    E,
    \xsdb_reg_reg[15]_0 ,
    s_dclk_o);
  output \xsdb_reg_reg[0]_0 ;
  output \slaveRegDo_ff9_reg[2] ;
  output \slaveRegDo_ff9_reg[2]_0 ;
  output \slaveRegDo_ffa_reg[11] ;
  output \slaveRegDo_ffa_reg[11]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  output \xsdb_reg_reg[5]_0 ;
  output \xsdb_reg_reg[6]_0 ;
  output \xsdb_reg_reg[8]_0 ;
  output \xsdb_reg_reg[9]_0 ;
  output \xsdb_reg_reg[11]_0 ;
  output [2:0]Q;
  input [0:0]slaveRegDo_ff9;
  input [3:0]D;
  input [0:0]slaveRegDo_ffa;
  input \slaveRegDo_mux_3_reg[4] ;
  input \slaveRegDo_mux_3_reg[14] ;
  input \slaveRegDo_mux_3_reg[13] ;
  input \slaveRegDo_mux_3_reg[12] ;
  input \slaveRegDo_mux_3_reg[11] ;
  input \slaveRegDo_mux_3_reg[11]_0 ;
  input \slaveRegDo_mux_3_reg[5] ;
  input \slaveRegDo_mux_3_reg[6] ;
  input \slaveRegDo_mux_3_reg[8] ;
  input \slaveRegDo_mux_3_reg[9] ;
  input \slaveRegDo_mux_3_reg[11]_1 ;
  input [0:0]E;
  input [15:0]\xsdb_reg_reg[15]_0 ;
  input s_dclk_o;

  wire [3:0]D;
  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  wire [2:0]Q;
  wire s_dclk_o;
  wire [0:0]slaveRegDo_ff9;
  wire \slaveRegDo_ff9_reg[2] ;
  wire \slaveRegDo_ff9_reg[2]_0 ;
  wire [0:0]slaveRegDo_ffa;
  wire \slaveRegDo_ffa_reg[11] ;
  wire \slaveRegDo_ffa_reg[11]_0 ;
  wire \slaveRegDo_mux_3_reg[11] ;
  wire \slaveRegDo_mux_3_reg[11]_0 ;
  wire \slaveRegDo_mux_3_reg[11]_1 ;
  wire \slaveRegDo_mux_3_reg[12] ;
  wire \slaveRegDo_mux_3_reg[13] ;
  wire \slaveRegDo_mux_3_reg[14] ;
  wire \slaveRegDo_mux_3_reg[4] ;
  wire \slaveRegDo_mux_3_reg[5] ;
  wire \slaveRegDo_mux_3_reg[6] ;
  wire \slaveRegDo_mux_3_reg[8] ;
  wire \slaveRegDo_mux_3_reg[9] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[11]_0 ;
  wire [15:0]\xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9]_0 ;
  wire \xsdb_reg_reg_n_0_[0] ;
  wire \xsdb_reg_reg_n_0_[11] ;
  wire \xsdb_reg_reg_n_0_[12] ;
  wire \xsdb_reg_reg_n_0_[13] ;
  wire \xsdb_reg_reg_n_0_[14] ;
  wire \xsdb_reg_reg_n_0_[1] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[3] ;
  wire \xsdb_reg_reg_n_0_[4] ;
  wire \xsdb_reg_reg_n_0_[5] ;
  wire \xsdb_reg_reg_n_0_[6] ;
  wire \xsdb_reg_reg_n_0_[8] ;
  wire \xsdb_reg_reg_n_0_[9] ;

  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \slaveRegDo_mux_3[0]_i_3 
       (.I0(\xsdb_reg_reg_n_0_[0] ),
        .I1(slaveRegDo_ff9),
        .I2(D[0]),
        .I3(D[1]),
        .I4(slaveRegDo_ffa),
        .O(\xsdb_reg_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFBA000000BA0000)) 
    \slaveRegDo_mux_3[11]_i_1 
       (.I0(\slaveRegDo_mux_3_reg[11] ),
        .I1(\slaveRegDo_mux_3_reg[11]_0 ),
        .I2(\xsdb_reg_reg_n_0_[11] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[11]_1 ),
        .O(\xsdb_reg_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hFF80000000800000)) 
    \slaveRegDo_mux_3[12]_i_1 
       (.I0(D[1]),
        .I1(D[0]),
        .I2(\xsdb_reg_reg_n_0_[12] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[12] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hFF80000000800000)) 
    \slaveRegDo_mux_3[13]_i_1 
       (.I0(D[1]),
        .I1(D[0]),
        .I2(\xsdb_reg_reg_n_0_[13] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[13] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFF80000000800000)) 
    \slaveRegDo_mux_3[14]_i_1 
       (.I0(D[1]),
        .I1(D[0]),
        .I2(\xsdb_reg_reg_n_0_[14] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[14] ),
        .O(\G_1PIPE_IFACE.s_daddr_r_reg[1] ));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \slaveRegDo_mux_3[1]_i_3 
       (.I0(slaveRegDo_ff9),
        .I1(\slaveRegDo_mux_3_reg[4] ),
        .I2(\xsdb_reg_reg_n_0_[1] ),
        .I3(D[0]),
        .I4(D[1]),
        .I5(slaveRegDo_ffa),
        .O(\slaveRegDo_ff9_reg[2] ));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \slaveRegDo_mux_3[2]_i_3 
       (.I0(slaveRegDo_ff9),
        .I1(\slaveRegDo_mux_3_reg[4] ),
        .I2(\xsdb_reg_reg_n_0_[2] ),
        .I3(D[0]),
        .I4(D[1]),
        .I5(slaveRegDo_ffa),
        .O(\slaveRegDo_ff9_reg[2]_0 ));
  LUT5 #(
    .INIT(32'hCA0FCA00)) 
    \slaveRegDo_mux_3[3]_i_3 
       (.I0(slaveRegDo_ffa),
        .I1(\xsdb_reg_reg_n_0_[3] ),
        .I2(D[0]),
        .I3(D[1]),
        .I4(\slaveRegDo_mux_3_reg[4] ),
        .O(\slaveRegDo_ffa_reg[11] ));
  LUT5 #(
    .INIT(32'hFA0C0A0C)) 
    \slaveRegDo_mux_3[4]_i_3 
       (.I0(slaveRegDo_ffa),
        .I1(\slaveRegDo_mux_3_reg[4] ),
        .I2(D[0]),
        .I3(D[1]),
        .I4(\xsdb_reg_reg_n_0_[4] ),
        .O(\slaveRegDo_ffa_reg[11]_0 ));
  LUT6 #(
    .INIT(64'hFFBA000000BA0000)) 
    \slaveRegDo_mux_3[5]_i_1 
       (.I0(\slaveRegDo_mux_3_reg[11] ),
        .I1(\slaveRegDo_mux_3_reg[11]_0 ),
        .I2(\xsdb_reg_reg_n_0_[5] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[5] ),
        .O(\xsdb_reg_reg[5]_0 ));
  LUT6 #(
    .INIT(64'hFFBA000000BA0000)) 
    \slaveRegDo_mux_3[6]_i_1 
       (.I0(\slaveRegDo_mux_3_reg[11] ),
        .I1(\slaveRegDo_mux_3_reg[11]_0 ),
        .I2(\xsdb_reg_reg_n_0_[6] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[6] ),
        .O(\xsdb_reg_reg[6]_0 ));
  LUT6 #(
    .INIT(64'hFFBA000000BA0000)) 
    \slaveRegDo_mux_3[8]_i_1 
       (.I0(\slaveRegDo_mux_3_reg[11] ),
        .I1(\slaveRegDo_mux_3_reg[11]_0 ),
        .I2(\xsdb_reg_reg_n_0_[8] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[8] ),
        .O(\xsdb_reg_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hFFBA000000BA0000)) 
    \slaveRegDo_mux_3[9]_i_1 
       (.I0(\slaveRegDo_mux_3_reg[11] ),
        .I1(\slaveRegDo_mux_3_reg[11]_0 ),
        .I2(\xsdb_reg_reg_n_0_[9] ),
        .I3(D[2]),
        .I4(D[3]),
        .I5(\slaveRegDo_mux_3_reg[9] ),
        .O(\xsdb_reg_reg[9]_0 ));
  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [0]),
        .Q(\xsdb_reg_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [10]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [11]),
        .Q(\xsdb_reg_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [12]),
        .Q(\xsdb_reg_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [13]),
        .Q(\xsdb_reg_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [14]),
        .Q(\xsdb_reg_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[15] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [15]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [1]),
        .Q(\xsdb_reg_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [3]),
        .Q(\xsdb_reg_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [5]),
        .Q(\xsdb_reg_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [6]),
        .Q(\xsdb_reg_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [7]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [8]),
        .Q(\xsdb_reg_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(E),
        .D(\xsdb_reg_reg[15]_0 [9]),
        .Q(\xsdb_reg_reg_n_0_[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stat" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_250
   (s_do_o,
    s_den_i,
    din_i,
    s_dclk_i);
  output [15:0]s_do_o;
  input s_den_i;
  input [15:0]din_i;
  input s_dclk_i;

  wire [15:0]din_i;
  wire s_dclk_i;
  wire s_den_i;
  wire [15:0]s_do_o;

  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[0]),
        .Q(s_do_o[0]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[10] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[10]),
        .Q(s_do_o[10]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[11] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[11]),
        .Q(s_do_o[11]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[12] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[12]),
        .Q(s_do_o[12]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[13] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[13]),
        .Q(s_do_o[13]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[14] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[14]),
        .Q(s_do_o[14]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[15] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[15]),
        .Q(s_do_o[15]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[1]),
        .Q(s_do_o[1]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[2]),
        .Q(s_do_o[2]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[3]),
        .Q(s_do_o[3]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[4]),
        .Q(s_do_o[4]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[5]),
        .Q(s_do_o[5]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[6]),
        .Q(s_do_o[6]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[7]),
        .Q(s_do_o[7]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[8]),
        .Q(s_do_o[8]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_i),
        .CE(s_den_i),
        .D(din_i[9]),
        .Q(s_do_o[9]),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream
   (\xsdb_reg_reg[0] ,
    \slaveRegDo_ff9_reg[2] ,
    \slaveRegDo_ff9_reg[2]_0 ,
    \slaveRegDo_ffa_reg[11] ,
    \slaveRegDo_ffa_reg[11]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
    \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[11] ,
    Q,
    slaveRegDo_ff9,
    D,
    slaveRegDo_ffa,
    \slaveRegDo_mux_3_reg[4] ,
    \slaveRegDo_mux_3_reg[14] ,
    \slaveRegDo_mux_3_reg[13] ,
    \slaveRegDo_mux_3_reg[12] ,
    \slaveRegDo_mux_3_reg[11] ,
    \slaveRegDo_mux_3_reg[11]_0 ,
    \slaveRegDo_mux_3_reg[5] ,
    \slaveRegDo_mux_3_reg[6] ,
    \slaveRegDo_mux_3_reg[8] ,
    \slaveRegDo_mux_3_reg[9] ,
    \slaveRegDo_mux_3_reg[11]_1 ,
    E,
    \xsdb_reg_reg[15] ,
    s_dclk_o);
  output \xsdb_reg_reg[0] ;
  output \slaveRegDo_ff9_reg[2] ;
  output \slaveRegDo_ff9_reg[2]_0 ;
  output \slaveRegDo_ffa_reg[11] ;
  output \slaveRegDo_ffa_reg[11]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[11] ;
  output [2:0]Q;
  input [0:0]slaveRegDo_ff9;
  input [3:0]D;
  input [0:0]slaveRegDo_ffa;
  input \slaveRegDo_mux_3_reg[4] ;
  input \slaveRegDo_mux_3_reg[14] ;
  input \slaveRegDo_mux_3_reg[13] ;
  input \slaveRegDo_mux_3_reg[12] ;
  input \slaveRegDo_mux_3_reg[11] ;
  input \slaveRegDo_mux_3_reg[11]_0 ;
  input \slaveRegDo_mux_3_reg[5] ;
  input \slaveRegDo_mux_3_reg[6] ;
  input \slaveRegDo_mux_3_reg[8] ;
  input \slaveRegDo_mux_3_reg[9] ;
  input \slaveRegDo_mux_3_reg[11]_1 ;
  input [0:0]E;
  input [15:0]\xsdb_reg_reg[15] ;
  input s_dclk_o;

  wire [3:0]D;
  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ;
  wire [2:0]Q;
  wire s_dclk_o;
  wire [0:0]slaveRegDo_ff9;
  wire \slaveRegDo_ff9_reg[2] ;
  wire \slaveRegDo_ff9_reg[2]_0 ;
  wire [0:0]slaveRegDo_ffa;
  wire \slaveRegDo_ffa_reg[11] ;
  wire \slaveRegDo_ffa_reg[11]_0 ;
  wire \slaveRegDo_mux_3_reg[11] ;
  wire \slaveRegDo_mux_3_reg[11]_0 ;
  wire \slaveRegDo_mux_3_reg[11]_1 ;
  wire \slaveRegDo_mux_3_reg[12] ;
  wire \slaveRegDo_mux_3_reg[13] ;
  wire \slaveRegDo_mux_3_reg[14] ;
  wire \slaveRegDo_mux_3_reg[4] ;
  wire \slaveRegDo_mux_3_reg[5] ;
  wire \slaveRegDo_mux_3_reg[6] ;
  wire \slaveRegDo_mux_3_reg[8] ;
  wire \slaveRegDo_mux_3_reg[9] ;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[11] ;
  wire [15:0]\xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[9] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_248 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_1 ),
        .Q(Q),
        .s_dclk_o(s_dclk_o),
        .slaveRegDo_ff9(slaveRegDo_ff9),
        .\slaveRegDo_ff9_reg[2] (\slaveRegDo_ff9_reg[2] ),
        .\slaveRegDo_ff9_reg[2]_0 (\slaveRegDo_ff9_reg[2]_0 ),
        .slaveRegDo_ffa(slaveRegDo_ffa),
        .\slaveRegDo_ffa_reg[11] (\slaveRegDo_ffa_reg[11] ),
        .\slaveRegDo_ffa_reg[11]_0 (\slaveRegDo_ffa_reg[11]_0 ),
        .\slaveRegDo_mux_3_reg[11] (\slaveRegDo_mux_3_reg[11] ),
        .\slaveRegDo_mux_3_reg[11]_0 (\slaveRegDo_mux_3_reg[11]_0 ),
        .\slaveRegDo_mux_3_reg[11]_1 (\slaveRegDo_mux_3_reg[11]_1 ),
        .\slaveRegDo_mux_3_reg[12] (\slaveRegDo_mux_3_reg[12] ),
        .\slaveRegDo_mux_3_reg[13] (\slaveRegDo_mux_3_reg[13] ),
        .\slaveRegDo_mux_3_reg[14] (\slaveRegDo_mux_3_reg[14] ),
        .\slaveRegDo_mux_3_reg[4] (\slaveRegDo_mux_3_reg[4] ),
        .\slaveRegDo_mux_3_reg[5] (\slaveRegDo_mux_3_reg[5] ),
        .\slaveRegDo_mux_3_reg[6] (\slaveRegDo_mux_3_reg[6] ),
        .\slaveRegDo_mux_3_reg[8] (\slaveRegDo_mux_3_reg[8] ),
        .\slaveRegDo_mux_3_reg[9] (\slaveRegDo_mux_3_reg[9] ),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stream" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized0
   (toggle_reg,
    bram_en,
    \G_1PIPE_IFACE.s_daddr_r_reg[11] ,
    \xsdb_reg_reg[15] ,
    s_dclk_o,
    E,
    bram_en_reg,
    bram_en_reg_0,
    Q,
    bram_en_reg_1,
    config_fsm_we,
    \I_EN_CTL_EQ1.temp_en_reg_0 ,
    D,
    \I_EN_CTL_EQ1.temp_en_reg_1 ,
    s_dwe_o,
    \I_EN_CTL_EQ1.temp_en_reg_2 ,
    s_di_o);
  output toggle_reg;
  output bram_en;
  output \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
  output [15:0]\xsdb_reg_reg[15] ;
  input s_dclk_o;
  input [0:0]E;
  input bram_en_reg;
  input bram_en_reg_0;
  input [0:0]Q;
  input bram_en_reg_1;
  input config_fsm_we;
  input \I_EN_CTL_EQ1.temp_en_reg_0 ;
  input [5:0]D;
  input [0:0]\I_EN_CTL_EQ1.temp_en_reg_1 ;
  input s_dwe_o;
  input \I_EN_CTL_EQ1.temp_en_reg_2 ;
  input [15:0]s_di_o;

  wire [5:0]D;
  wire [0:0]E;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
  wire \I_EN_CTL_EQ1.temp_en_reg_0 ;
  wire [0:0]\I_EN_CTL_EQ1.temp_en_reg_1 ;
  wire \I_EN_CTL_EQ1.temp_en_reg_2 ;
  wire [0:0]Q;
  wire bram_en;
  wire bram_en_reg;
  wire bram_en_reg_0;
  wire bram_en_reg_1;
  wire config_fsm_en;
  wire config_fsm_we;
  wire reg_ce;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire s_dwe_o;
  wire toggle_reg;
  wire [15:0]\xsdb_reg_reg[15] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_249 \I_EN_CTL_EQ1.U_CTL 
       (.D(D),
        .\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
        .\I_EN_CTL_EQ1.temp_en_reg (\I_EN_CTL_EQ1.temp_en_reg_2 ),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .s_dwe_o(s_dwe_o),
        .\xsdb_reg_reg[0]_0 (\I_EN_CTL_EQ1.temp_en_reg_1 ),
        .\xsdb_reg_reg[0]_1 (\I_EN_CTL_EQ1.temp_en_reg_0 ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    \I_EN_CTL_EQ1.temp_en_i_1 
       (.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
        .I1(\I_EN_CTL_EQ1.temp_en_reg_0 ),
        .I2(D[0]),
        .I3(\I_EN_CTL_EQ1.temp_en_reg_1 ),
        .I4(D[5]),
        .I5(D[1]),
        .O(reg_ce));
  FDRE \I_EN_CTL_EQ1.temp_en_reg 
       (.C(s_dclk_o),
        .CE(1'b1),
        .D(reg_ce),
        .Q(config_fsm_en),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    bram_en_i_1
       (.I0(bram_en_reg),
        .I1(bram_en_reg_0),
        .I2(Q),
        .I3(bram_en_reg_1),
        .I4(config_fsm_we),
        .I5(config_fsm_en),
        .O(bram_en));
  LUT2 #(
    .INIT(4'h6)) 
    toggle_i_1
       (.I0(bram_en),
        .I1(E),
        .O(toggle_reg));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stream" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized1
   (\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
    \G_1PIPE_IFACE.s_daddr_r_reg[6] ,
    \xsdb_reg_reg[15] ,
    s_daddr_o,
    \xsdb_reg_reg[0] ,
    s_di_o,
    s_dclk_o);
  output \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
  output \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  output [15:0]\xsdb_reg_reg[15] ;
  input [12:0]s_daddr_o;
  input \xsdb_reg_reg[0] ;
  input [15:0]s_di_o;
  input s_dclk_o;

  wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
  wire \G_1PIPE_IFACE.s_daddr_r_reg[6] ;
  wire [12:0]s_daddr_o;
  wire s_dclk_o;
  wire [15:0]s_di_o;
  wire \xsdb_reg_reg[0] ;
  wire [15:0]\xsdb_reg_reg[15] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl \I_EN_CTL_EQ1.U_CTL 
       (.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
        .\G_1PIPE_IFACE.s_daddr_r_reg[6] (\G_1PIPE_IFACE.s_daddr_r_reg[6] ),
        .s_daddr_o(s_daddr_o),
        .s_dclk_o(s_dclk_o),
        .s_di_o(s_di_o),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_2_reg_stream" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized2
   (\xsdb_reg_reg[15] ,
    \xsdb_reg_reg[14] ,
    \xsdb_reg_reg[13] ,
    \xsdb_reg_reg[12] ,
    \xsdb_reg_reg[11] ,
    \xsdb_reg_reg[10] ,
    \xsdb_reg_reg[9] ,
    \xsdb_reg_reg[8] ,
    \xsdb_reg_reg[7] ,
    \xsdb_reg_reg[6] ,
    \xsdb_reg_reg[5] ,
    \xsdb_reg_reg[4] ,
    \xsdb_reg_reg[3] ,
    \xsdb_reg_reg[2] ,
    \xsdb_reg_reg[1] ,
    \xsdb_reg_reg[0] ,
    \xsdb_reg_reg[15]_0 ,
    data_out_en,
    \xsdb_reg_reg[15]_1 ,
    s_dclk_o,
    \xsdb_reg_reg[14]_0 ,
    \xsdb_reg_reg[13]_0 ,
    \xsdb_reg_reg[12]_0 ,
    \xsdb_reg_reg[11]_0 ,
    \xsdb_reg_reg[10]_0 ,
    \xsdb_reg_reg[9]_0 ,
    \xsdb_reg_reg[8]_0 ,
    \xsdb_reg_reg[7]_0 ,
    \xsdb_reg_reg[6]_0 ,
    \xsdb_reg_reg[5]_0 ,
    \xsdb_reg_reg[4]_0 ,
    \xsdb_reg_reg[3]_0 ,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[1]_0 ,
    \xsdb_reg_reg[0]_0 );
  output \xsdb_reg_reg[15] ;
  output \xsdb_reg_reg[14] ;
  output \xsdb_reg_reg[13] ;
  output \xsdb_reg_reg[12] ;
  output \xsdb_reg_reg[11] ;
  output \xsdb_reg_reg[10] ;
  output \xsdb_reg_reg[9] ;
  output \xsdb_reg_reg[8] ;
  output \xsdb_reg_reg[7] ;
  output \xsdb_reg_reg[6] ;
  output \xsdb_reg_reg[5] ;
  output \xsdb_reg_reg[4] ;
  output \xsdb_reg_reg[3] ;
  output \xsdb_reg_reg[2] ;
  output \xsdb_reg_reg[1] ;
  output \xsdb_reg_reg[0] ;
  input \xsdb_reg_reg[15]_0 ;
  input data_out_en;
  input \xsdb_reg_reg[15]_1 ;
  input s_dclk_o;
  input \xsdb_reg_reg[14]_0 ;
  input \xsdb_reg_reg[13]_0 ;
  input \xsdb_reg_reg[12]_0 ;
  input \xsdb_reg_reg[11]_0 ;
  input \xsdb_reg_reg[10]_0 ;
  input \xsdb_reg_reg[9]_0 ;
  input \xsdb_reg_reg[8]_0 ;
  input \xsdb_reg_reg[7]_0 ;
  input \xsdb_reg_reg[6]_0 ;
  input \xsdb_reg_reg[5]_0 ;
  input \xsdb_reg_reg[4]_0 ;
  input \xsdb_reg_reg[3]_0 ;
  input \xsdb_reg_reg[2]_0 ;
  input \xsdb_reg_reg[1]_0 ;
  input \xsdb_reg_reg[0]_0 ;

  wire data_out_en;
  wire s_dclk_o;
  wire \xsdb_reg_reg[0] ;
  wire \xsdb_reg_reg[0]_0 ;
  wire \xsdb_reg_reg[10] ;
  wire \xsdb_reg_reg[10]_0 ;
  wire \xsdb_reg_reg[11] ;
  wire \xsdb_reg_reg[11]_0 ;
  wire \xsdb_reg_reg[12] ;
  wire \xsdb_reg_reg[12]_0 ;
  wire \xsdb_reg_reg[13] ;
  wire \xsdb_reg_reg[13]_0 ;
  wire \xsdb_reg_reg[14] ;
  wire \xsdb_reg_reg[14]_0 ;
  wire \xsdb_reg_reg[15] ;
  wire \xsdb_reg_reg[15]_0 ;
  wire \xsdb_reg_reg[15]_1 ;
  wire \xsdb_reg_reg[1] ;
  wire \xsdb_reg_reg[1]_0 ;
  wire \xsdb_reg_reg[2] ;
  wire \xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[3] ;
  wire \xsdb_reg_reg[3]_0 ;
  wire \xsdb_reg_reg[4] ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg[5] ;
  wire \xsdb_reg_reg[5]_0 ;
  wire \xsdb_reg_reg[6] ;
  wire \xsdb_reg_reg[6]_0 ;
  wire \xsdb_reg_reg[7] ;
  wire \xsdb_reg_reg[7]_0 ;
  wire \xsdb_reg_reg[8] ;
  wire \xsdb_reg_reg[8]_0 ;
  wire \xsdb_reg_reg[9] ;
  wire \xsdb_reg_reg[9]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat \I_EN_STAT_EQ1.U_STAT 
       (.data_out_en(data_out_en),
        .s_dclk_o(s_dclk_o),
        .\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
        .\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
        .\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
        .\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
        .\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
        .\xsdb_reg_reg[11]_1 (\xsdb_reg_reg[11]_0 ),
        .\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
        .\xsdb_reg_reg[12]_1 (\xsdb_reg_reg[12]_0 ),
        .\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
        .\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
        .\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
        .\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
        .\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
        .\xsdb_reg_reg[15]_1 (\xsdb_reg_reg[15]_0 ),
        .\xsdb_reg_reg[15]_2 (\xsdb_reg_reg[15]_1 ),
        .\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
        .\xsdb_reg_reg[1]_1 (\xsdb_reg_reg[1]_0 ),
        .\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
        .\xsdb_reg_reg[2]_1 (\xsdb_reg_reg[2]_0 ),
        .\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
        .\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ),
        .\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
        .\xsdb_reg_reg[4]_1 (\xsdb_reg_reg[4]_0 ),
        .\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
        .\xsdb_reg_reg[5]_1 (\xsdb_reg_reg[5]_0 ),
        .\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
        .\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
        .\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
        .\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
        .\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
        .\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
        .\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
        .\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule

(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_CORE_MAJOR_VER = "6" *) (* C_CORE_MINOR_VER = "2" *) (* C_CORE_TYPE = "1" *) 
(* C_CSE_DRV_VER = "2" *) (* C_MAJOR_VERSION = "2018" *) (* C_MINOR_VERSION = "3" *) 
(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "1" *) (* C_USE_TEST_REG = "1" *) 
(* C_XDEVICEFAMILY = "zynq" *) (* C_XSDB_SLAVE_TYPE = "17" *) (* dont_touch = "true" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
   (s_rst_o,
    s_dclk_o,
    s_den_o,
    s_dwe_o,
    s_daddr_o,
    s_di_o,
    sl_oport_o,
    s_do_i,
    sl_iport_i,
    s_drdy_i);
  output s_rst_o;
  output s_dclk_o;
  output s_den_o;
  output s_dwe_o;
  output [16:0]s_daddr_o;
  output [15:0]s_di_o;
  output [16:0]sl_oport_o;
  input [15:0]s_do_i;
  input [36:0]sl_iport_i;
  input s_drdy_i;

  wire \G_1PIPE_IFACE.s_den_r0 ;
  wire \G_1PIPE_IFACE.s_den_r_i_2_n_0 ;
  wire \G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ;
  wire [15:0]p_0_in;
  wire [15:0]reg_do;
  wire \reg_do[0]_i_2_n_0 ;
  wire \reg_do[0]_i_3_n_0 ;
  wire \reg_do[0]_i_4_n_0 ;
  wire \reg_do[0]_i_5_n_0 ;
  wire \reg_do[10]_i_2_n_0 ;
  wire \reg_do[10]_i_3_n_0 ;
  wire \reg_do[10]_i_4_n_0 ;
  wire \reg_do[10]_i_5_n_0 ;
  wire \reg_do[11]_i_2_n_0 ;
  wire \reg_do[11]_i_3_n_0 ;
  wire \reg_do[12]_i_2_n_0 ;
  wire \reg_do[12]_i_3_n_0 ;
  wire \reg_do[13]_i_2_n_0 ;
  wire \reg_do[13]_i_3_n_0 ;
  wire \reg_do[14]_i_2_n_0 ;
  wire \reg_do[14]_i_3_n_0 ;
  wire \reg_do[15]_i_2_n_0 ;
  wire \reg_do[15]_i_3_n_0 ;
  wire \reg_do[15]_i_4_n_0 ;
  wire \reg_do[15]_i_5_n_0 ;
  wire \reg_do[15]_i_6_n_0 ;
  wire \reg_do[1]_i_2_n_0 ;
  wire \reg_do[1]_i_3_n_0 ;
  wire \reg_do[1]_i_4_n_0 ;
  wire \reg_do[2]_i_2_n_0 ;
  wire \reg_do[2]_i_3_n_0 ;
  wire \reg_do[3]_i_2_n_0 ;
  wire \reg_do[3]_i_3_n_0 ;
  wire \reg_do[4]_i_2_n_0 ;
  wire \reg_do[4]_i_3_n_0 ;
  wire \reg_do[4]_i_4_n_0 ;
  wire \reg_do[4]_i_5_n_0 ;
  wire \reg_do[4]_i_6_n_0 ;
  wire \reg_do[4]_i_7_n_0 ;
  wire \reg_do[4]_i_8_n_0 ;
  wire \reg_do[4]_i_9_n_0 ;
  wire \reg_do[5]_i_2_n_0 ;
  wire \reg_do[5]_i_3_n_0 ;
  wire \reg_do[5]_i_4_n_0 ;
  wire \reg_do[6]_i_2_n_0 ;
  wire \reg_do[6]_i_3_n_0 ;
  wire \reg_do[6]_i_4_n_0 ;
  wire \reg_do[7]_i_2_n_0 ;
  wire \reg_do[7]_i_3_n_0 ;
  wire \reg_do[7]_i_4_n_0 ;
  wire \reg_do[8]_i_2_n_0 ;
  wire \reg_do[8]_i_3_n_0 ;
  wire \reg_do[8]_i_4_n_0 ;
  wire \reg_do[8]_i_5_n_0 ;
  wire \reg_do[9]_i_2_n_0 ;
  wire \reg_do[9]_i_3_n_0 ;
  wire \reg_do[9]_i_4_n_0 ;
  wire \reg_do_reg_n_0_[0] ;
  wire \reg_do_reg_n_0_[10] ;
  wire \reg_do_reg_n_0_[11] ;
  wire \reg_do_reg_n_0_[12] ;
  wire \reg_do_reg_n_0_[13] ;
  wire \reg_do_reg_n_0_[14] ;
  wire \reg_do_reg_n_0_[15] ;
  wire \reg_do_reg_n_0_[1] ;
  wire \reg_do_reg_n_0_[2] ;
  wire \reg_do_reg_n_0_[3] ;
  wire \reg_do_reg_n_0_[4] ;
  wire \reg_do_reg_n_0_[5] ;
  wire \reg_do_reg_n_0_[6] ;
  wire \reg_do_reg_n_0_[7] ;
  wire \reg_do_reg_n_0_[8] ;
  wire \reg_do_reg_n_0_[9] ;
  wire reg_drdy;
  wire reg_drdy0;
  wire [15:0]reg_test;
  wire reg_test0;
  wire [16:0]s_daddr_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_i;
  wire s_drdy_i;
  wire s_dwe_o;
  wire [36:0]sl_iport_i;
  wire [16:0]sl_oport_o;
  (* DONT_TOUCH *) (* UUID = "1" *) wire [127:0]uuid_stamp;

  assign s_dclk_o = sl_iport_i[1];
  assign s_rst_o = sl_iport_i[0];
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[4]),
        .Q(s_daddr_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[14]),
        .Q(s_daddr_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[15]),
        .Q(s_daddr_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[16]),
        .Q(s_daddr_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[17]),
        .Q(s_daddr_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[18]),
        .Q(s_daddr_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[19]),
        .Q(s_daddr_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[20]),
        .Q(s_daddr_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[5]),
        .Q(s_daddr_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[6]),
        .Q(s_daddr_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[7]),
        .Q(s_daddr_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[8]),
        .Q(s_daddr_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[9]),
        .Q(s_daddr_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[10]),
        .Q(s_daddr_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[11]),
        .Q(s_daddr_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[12]),
        .Q(s_daddr_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[13]),
        .Q(s_daddr_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h7FFF0000)) 
    \G_1PIPE_IFACE.s_den_r_i_1 
       (.I0(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I1(sl_iport_i[12]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[14]),
        .I4(sl_iport_i[2]),
        .O(\G_1PIPE_IFACE.s_den_r0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \G_1PIPE_IFACE.s_den_r_i_2 
       (.I0(sl_iport_i[15]),
        .I1(sl_iport_i[16]),
        .I2(sl_iport_i[17]),
        .I3(sl_iport_i[18]),
        .I4(sl_iport_i[20]),
        .I5(sl_iport_i[19]),
        .O(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_den_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\G_1PIPE_IFACE.s_den_r0 ),
        .Q(s_den_o),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[21]),
        .Q(s_di_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[31]),
        .Q(s_di_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[32]),
        .Q(s_di_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[33]),
        .Q(s_di_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[34]),
        .Q(s_di_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[35]),
        .Q(s_di_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[36]),
        .Q(s_di_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[22]),
        .Q(s_di_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[23]),
        .Q(s_di_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[24]),
        .Q(s_di_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[25]),
        .Q(s_di_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[26]),
        .Q(s_di_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[27]),
        .Q(s_di_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[28]),
        .Q(s_di_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[29]),
        .Q(s_di_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[30]),
        .Q(s_di_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[0]_i_1 
       (.I0(\reg_do_reg_n_0_[0] ),
        .I1(s_do_i[0]),
        .I2(reg_drdy),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[10]_i_1 
       (.I0(\reg_do_reg_n_0_[10] ),
        .I1(s_do_i[10]),
        .I2(reg_drdy),
        .O(p_0_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[11]_i_1 
       (.I0(\reg_do_reg_n_0_[11] ),
        .I1(s_do_i[11]),
        .I2(reg_drdy),
        .O(p_0_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[12]_i_1 
       (.I0(\reg_do_reg_n_0_[12] ),
        .I1(s_do_i[12]),
        .I2(reg_drdy),
        .O(p_0_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[13]_i_1 
       (.I0(\reg_do_reg_n_0_[13] ),
        .I1(s_do_i[13]),
        .I2(reg_drdy),
        .O(p_0_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[14]_i_1 
       (.I0(\reg_do_reg_n_0_[14] ),
        .I1(s_do_i[14]),
        .I2(reg_drdy),
        .O(p_0_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[15]_i_1 
       (.I0(\reg_do_reg_n_0_[15] ),
        .I1(s_do_i[15]),
        .I2(reg_drdy),
        .O(p_0_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[1]_i_1 
       (.I0(\reg_do_reg_n_0_[1] ),
        .I1(s_do_i[1]),
        .I2(reg_drdy),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[2]_i_1 
       (.I0(\reg_do_reg_n_0_[2] ),
        .I1(s_do_i[2]),
        .I2(reg_drdy),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[3]_i_1 
       (.I0(\reg_do_reg_n_0_[3] ),
        .I1(s_do_i[3]),
        .I2(reg_drdy),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[4]_i_1 
       (.I0(\reg_do_reg_n_0_[4] ),
        .I1(s_do_i[4]),
        .I2(reg_drdy),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[5]_i_1 
       (.I0(\reg_do_reg_n_0_[5] ),
        .I1(s_do_i[5]),
        .I2(reg_drdy),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[6]_i_1 
       (.I0(\reg_do_reg_n_0_[6] ),
        .I1(s_do_i[6]),
        .I2(reg_drdy),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[7]_i_1 
       (.I0(\reg_do_reg_n_0_[7] ),
        .I1(s_do_i[7]),
        .I2(reg_drdy),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[8]_i_1 
       (.I0(\reg_do_reg_n_0_[8] ),
        .I1(s_do_i[8]),
        .I2(reg_drdy),
        .O(p_0_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[9]_i_1 
       (.I0(\reg_do_reg_n_0_[9] ),
        .I1(s_do_i[9]),
        .I2(reg_drdy),
        .O(p_0_in[9]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(sl_oport_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[10]),
        .Q(sl_oport_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[11]),
        .Q(sl_oport_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[12]),
        .Q(sl_oport_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[13]),
        .Q(sl_oport_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[14]),
        .Q(sl_oport_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[15]),
        .Q(sl_oport_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(sl_oport_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(sl_oport_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(sl_oport_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(sl_oport_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(sl_oport_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[6]),
        .Q(sl_oport_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[7]),
        .Q(sl_oport_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[8]),
        .Q(sl_oport_o[9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[9]),
        .Q(sl_oport_o[10]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \G_1PIPE_IFACE.s_drdy_r_i_1 
       (.I0(s_drdy_i),
        .I1(reg_drdy),
        .O(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_drdy_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ),
        .Q(sl_oport_o[0]),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_dwe_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[3]),
        .Q(s_dwe_o),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'hFFFFFDFCFEFEFDFC)) 
    \reg_do[0]_i_2 
       (.I0(\reg_do[4]_i_4_n_0 ),
        .I1(sl_iport_i[9]),
        .I2(sl_iport_i[10]),
        .I3(\reg_do[0]_i_4_n_0 ),
        .I4(\reg_do[4]_i_6_n_0 ),
        .I5(\reg_do[0]_i_5_n_0 ),
        .O(\reg_do[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF0F0FBFF)) 
    \reg_do[0]_i_3 
       (.I0(reg_test[0]),
        .I1(\reg_do[4]_i_9_n_0 ),
        .I2(\reg_do[4]_i_8_n_0 ),
        .I3(sl_iport_i[5]),
        .I4(sl_iport_i[4]),
        .O(\reg_do[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[0]_i_4 
       (.I0(uuid_stamp[16]),
        .I1(uuid_stamp[48]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[0]),
        .I5(uuid_stamp[32]),
        .O(\reg_do[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[0]_i_5 
       (.I0(uuid_stamp[80]),
        .I1(uuid_stamp[112]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[64]),
        .I5(uuid_stamp[96]),
        .O(\reg_do[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[10]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[10]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[10]_i_3_n_0 ),
        .I4(\reg_do[10]_i_4_n_0 ),
        .I5(\reg_do[10]_i_5_n_0 ),
        .O(reg_do[10]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[10]_i_2 
       (.I0(uuid_stamp[26]),
        .I1(uuid_stamp[58]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[10]),
        .I5(uuid_stamp[42]),
        .O(\reg_do[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[10]_i_3 
       (.I0(uuid_stamp[90]),
        .I1(uuid_stamp[122]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[74]),
        .I5(uuid_stamp[106]),
        .O(\reg_do[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hC02CC02C2C2CC02C)) 
    \reg_do[10]_i_4 
       (.I0(reg_test[10]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[5]),
        .I3(sl_iport_i[8]),
        .I4(sl_iport_i[6]),
        .I5(sl_iport_i[7]),
        .O(\reg_do[10]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \reg_do[10]_i_5 
       (.I0(sl_iport_i[11]),
        .I1(sl_iport_i[10]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[9]),
        .O(\reg_do[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[11]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[11]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[11]_i_3_n_0 ),
        .I4(reg_test[11]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[11]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[11]_i_2 
       (.I0(uuid_stamp[27]),
        .I1(uuid_stamp[59]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[11]),
        .I5(uuid_stamp[43]),
        .O(\reg_do[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[11]_i_3 
       (.I0(uuid_stamp[91]),
        .I1(uuid_stamp[123]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[75]),
        .I5(uuid_stamp[107]),
        .O(\reg_do[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[12]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[12]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[12]_i_3_n_0 ),
        .I4(reg_test[12]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[12]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[12]_i_2 
       (.I0(uuid_stamp[28]),
        .I1(uuid_stamp[60]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[12]),
        .I5(uuid_stamp[44]),
        .O(\reg_do[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[12]_i_3 
       (.I0(uuid_stamp[92]),
        .I1(uuid_stamp[124]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[76]),
        .I5(uuid_stamp[108]),
        .O(\reg_do[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[13]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[13]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[13]_i_3_n_0 ),
        .I4(reg_test[13]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[13]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[13]_i_2 
       (.I0(uuid_stamp[29]),
        .I1(uuid_stamp[61]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[13]),
        .I5(uuid_stamp[45]),
        .O(\reg_do[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[13]_i_3 
       (.I0(uuid_stamp[93]),
        .I1(uuid_stamp[125]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[77]),
        .I5(uuid_stamp[109]),
        .O(\reg_do[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[14]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[14]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[14]_i_3_n_0 ),
        .I4(reg_test[14]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[14]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[14]_i_2 
       (.I0(uuid_stamp[30]),
        .I1(uuid_stamp[62]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[14]),
        .I5(uuid_stamp[46]),
        .O(\reg_do[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[14]_i_3 
       (.I0(uuid_stamp[94]),
        .I1(uuid_stamp[126]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[78]),
        .I5(uuid_stamp[110]),
        .O(\reg_do[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[15]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[15]_i_3_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[15]_i_5_n_0 ),
        .I4(reg_test[15]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[15]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \reg_do[15]_i_2 
       (.I0(sl_iport_i[10]),
        .I1(sl_iport_i[9]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[8]),
        .I4(sl_iport_i[6]),
        .I5(sl_iport_i[7]),
        .O(\reg_do[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[15]_i_3 
       (.I0(uuid_stamp[31]),
        .I1(uuid_stamp[63]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[15]),
        .I5(uuid_stamp[47]),
        .O(\reg_do[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \reg_do[15]_i_4 
       (.I0(sl_iport_i[10]),
        .I1(sl_iport_i[9]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[8]),
        .I4(sl_iport_i[6]),
        .I5(sl_iport_i[7]),
        .O(\reg_do[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[15]_i_5 
       (.I0(uuid_stamp[95]),
        .I1(uuid_stamp[127]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[79]),
        .I5(uuid_stamp[111]),
        .O(\reg_do[15]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \reg_do[15]_i_6 
       (.I0(\reg_do[8]_i_2_n_0 ),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[5]),
        .O(\reg_do[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[1]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[1]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[1]_i_3_n_0 ),
        .I4(\reg_do[1]_i_4_n_0 ),
        .I5(\reg_do[10]_i_5_n_0 ),
        .O(reg_do[1]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[1]_i_2 
       (.I0(uuid_stamp[17]),
        .I1(uuid_stamp[49]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[1]),
        .I5(uuid_stamp[33]),
        .O(\reg_do[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[1]_i_3 
       (.I0(uuid_stamp[81]),
        .I1(uuid_stamp[113]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[65]),
        .I5(uuid_stamp[97]),
        .O(\reg_do[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hDF55DF5530FF1055)) 
    \reg_do[1]_i_4 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[7]),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[8]),
        .I4(reg_test[1]),
        .I5(sl_iport_i[4]),
        .O(\reg_do[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[2]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[2]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[2]_i_3_n_0 ),
        .I4(reg_test[2]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[2]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[2]_i_2 
       (.I0(uuid_stamp[18]),
        .I1(uuid_stamp[50]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[2]),
        .I5(uuid_stamp[34]),
        .O(\reg_do[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[2]_i_3 
       (.I0(uuid_stamp[82]),
        .I1(uuid_stamp[114]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[66]),
        .I5(uuid_stamp[98]),
        .O(\reg_do[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[3]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[3]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[3]_i_3_n_0 ),
        .I4(reg_test[3]),
        .I5(\reg_do[15]_i_6_n_0 ),
        .O(reg_do[3]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[3]_i_2 
       (.I0(uuid_stamp[19]),
        .I1(uuid_stamp[51]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[3]),
        .I5(uuid_stamp[35]),
        .O(\reg_do[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[3]_i_3 
       (.I0(uuid_stamp[83]),
        .I1(uuid_stamp[115]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[67]),
        .I5(uuid_stamp[99]),
        .O(\reg_do[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFDFCFEFEFDFC)) 
    \reg_do[4]_i_2 
       (.I0(\reg_do[4]_i_4_n_0 ),
        .I1(sl_iport_i[9]),
        .I2(sl_iport_i[10]),
        .I3(\reg_do[4]_i_5_n_0 ),
        .I4(\reg_do[4]_i_6_n_0 ),
        .I5(\reg_do[4]_i_7_n_0 ),
        .O(\reg_do[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAEABAAAB)) 
    \reg_do[4]_i_3 
       (.I0(\reg_do[4]_i_8_n_0 ),
        .I1(\reg_do[4]_i_9_n_0 ),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(reg_test[4]),
        .O(\reg_do[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \reg_do[4]_i_4 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[8]),
        .O(\reg_do[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[4]_i_5 
       (.I0(uuid_stamp[20]),
        .I1(uuid_stamp[52]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[4]),
        .I5(uuid_stamp[36]),
        .O(\reg_do[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \reg_do[4]_i_6 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[6]),
        .I2(sl_iport_i[8]),
        .O(\reg_do[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[4]_i_7 
       (.I0(uuid_stamp[84]),
        .I1(uuid_stamp[116]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[68]),
        .I5(uuid_stamp[100]),
        .O(\reg_do[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'hDFFF)) 
    \reg_do[4]_i_8 
       (.I0(sl_iport_i[9]),
        .I1(sl_iport_i[7]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[10]),
        .O(\reg_do[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \reg_do[4]_i_9 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[6]),
        .I2(sl_iport_i[8]),
        .O(\reg_do[4]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'hFFFF6040)) 
    \reg_do[5]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[8]_i_2_n_0 ),
        .I3(reg_test[5]),
        .I4(\reg_do[5]_i_2_n_0 ),
        .O(reg_do[5]));
  LUT4 #(
    .INIT(16'hF888)) 
    \reg_do[5]_i_2 
       (.I0(\reg_do[5]_i_3_n_0 ),
        .I1(\reg_do[15]_i_4_n_0 ),
        .I2(\reg_do[5]_i_4_n_0 ),
        .I3(\reg_do[15]_i_2_n_0 ),
        .O(\reg_do[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[5]_i_3 
       (.I0(uuid_stamp[85]),
        .I1(uuid_stamp[117]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[69]),
        .I5(uuid_stamp[101]),
        .O(\reg_do[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[5]_i_4 
       (.I0(uuid_stamp[21]),
        .I1(uuid_stamp[53]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[5]),
        .I5(uuid_stamp[37]),
        .O(\reg_do[5]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6040)) 
    \reg_do[6]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[8]_i_2_n_0 ),
        .I3(reg_test[6]),
        .I4(\reg_do[6]_i_2_n_0 ),
        .O(reg_do[6]));
  LUT4 #(
    .INIT(16'hF888)) 
    \reg_do[6]_i_2 
       (.I0(\reg_do[6]_i_3_n_0 ),
        .I1(\reg_do[15]_i_4_n_0 ),
        .I2(\reg_do[6]_i_4_n_0 ),
        .I3(\reg_do[15]_i_2_n_0 ),
        .O(\reg_do[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[6]_i_3 
       (.I0(uuid_stamp[86]),
        .I1(uuid_stamp[118]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[70]),
        .I5(uuid_stamp[102]),
        .O(\reg_do[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[6]_i_4 
       (.I0(uuid_stamp[22]),
        .I1(uuid_stamp[54]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[6]),
        .I5(uuid_stamp[38]),
        .O(\reg_do[6]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6040)) 
    \reg_do[7]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[8]_i_2_n_0 ),
        .I3(reg_test[7]),
        .I4(\reg_do[7]_i_2_n_0 ),
        .O(reg_do[7]));
  LUT4 #(
    .INIT(16'hF888)) 
    \reg_do[7]_i_2 
       (.I0(\reg_do[7]_i_3_n_0 ),
        .I1(\reg_do[15]_i_4_n_0 ),
        .I2(\reg_do[7]_i_4_n_0 ),
        .I3(\reg_do[15]_i_2_n_0 ),
        .O(\reg_do[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[7]_i_3 
       (.I0(uuid_stamp[87]),
        .I1(uuid_stamp[119]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[71]),
        .I5(uuid_stamp[103]),
        .O(\reg_do[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[7]_i_4 
       (.I0(uuid_stamp[23]),
        .I1(uuid_stamp[55]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[7]),
        .I5(uuid_stamp[39]),
        .O(\reg_do[7]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF2A22)) 
    \reg_do[8]_i_1 
       (.I0(\reg_do[8]_i_2_n_0 ),
        .I1(sl_iport_i[5]),
        .I2(sl_iport_i[4]),
        .I3(reg_test[8]),
        .I4(\reg_do[8]_i_3_n_0 ),
        .O(reg_do[8]));
  LUT6 #(
    .INIT(64'h0000000080000000)) 
    \reg_do[8]_i_2 
       (.I0(sl_iport_i[9]),
        .I1(sl_iport_i[10]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[8]),
        .I4(sl_iport_i[6]),
        .I5(sl_iport_i[7]),
        .O(\reg_do[8]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \reg_do[8]_i_3 
       (.I0(\reg_do[8]_i_4_n_0 ),
        .I1(\reg_do[15]_i_4_n_0 ),
        .I2(\reg_do[8]_i_5_n_0 ),
        .I3(\reg_do[15]_i_2_n_0 ),
        .O(\reg_do[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[8]_i_4 
       (.I0(uuid_stamp[88]),
        .I1(uuid_stamp[120]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[72]),
        .I5(uuid_stamp[104]),
        .O(\reg_do[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[8]_i_5 
       (.I0(uuid_stamp[24]),
        .I1(uuid_stamp[56]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[8]),
        .I5(uuid_stamp[40]),
        .O(\reg_do[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \reg_do[9]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[9]_i_2_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[9]_i_3_n_0 ),
        .I4(\reg_do[9]_i_4_n_0 ),
        .I5(\reg_do[10]_i_5_n_0 ),
        .O(reg_do[9]));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[9]_i_2 
       (.I0(uuid_stamp[25]),
        .I1(uuid_stamp[57]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[9]),
        .I5(uuid_stamp[41]),
        .O(\reg_do[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \reg_do[9]_i_3 
       (.I0(uuid_stamp[89]),
        .I1(uuid_stamp[121]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[5]),
        .I4(uuid_stamp[73]),
        .I5(uuid_stamp[105]),
        .O(\reg_do[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hC02CC02C2C2CC02C)) 
    \reg_do[9]_i_4 
       (.I0(reg_test[9]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[5]),
        .I3(sl_iport_i[8]),
        .I4(sl_iport_i[6]),
        .I5(sl_iport_i[7]),
        .O(\reg_do[9]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[0]),
        .Q(\reg_do_reg_n_0_[0] ),
        .R(1'b0));
  MUXF7 \reg_do_reg[0]_i_1 
       (.I0(\reg_do[0]_i_2_n_0 ),
        .I1(\reg_do[0]_i_3_n_0 ),
        .O(reg_do[0]),
        .S(sl_iport_i[11]));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[10]),
        .Q(\reg_do_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[11]),
        .Q(\reg_do_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[12]),
        .Q(\reg_do_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[13]),
        .Q(\reg_do_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[14]),
        .Q(\reg_do_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[15]),
        .Q(\reg_do_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[1]),
        .Q(\reg_do_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[2]),
        .Q(\reg_do_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[3]),
        .Q(\reg_do_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[4]),
        .Q(\reg_do_reg_n_0_[4] ),
        .R(1'b0));
  MUXF7 \reg_do_reg[4]_i_1 
       (.I0(\reg_do[4]_i_2_n_0 ),
        .I1(\reg_do[4]_i_3_n_0 ),
        .O(reg_do[4]),
        .S(sl_iport_i[11]));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[5]),
        .Q(\reg_do_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[6]),
        .Q(\reg_do_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[7]),
        .Q(\reg_do_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[8]),
        .Q(\reg_do_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[9]),
        .Q(\reg_do_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    reg_drdy_i_1
       (.I0(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I1(sl_iport_i[12]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[14]),
        .I4(sl_iport_i[2]),
        .O(reg_drdy0));
  FDRE #(
    .INIT(1'b0)) 
    reg_drdy_reg
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_drdy0),
        .Q(reg_drdy),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \reg_test[15]_i_1 
       (.I0(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I1(sl_iport_i[12]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[14]),
        .I4(sl_iport_i[3]),
        .I5(sl_iport_i[2]),
        .O(reg_test0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[21]),
        .Q(reg_test[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[31]),
        .Q(reg_test[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[32]),
        .Q(reg_test[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[33]),
        .Q(reg_test[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[34]),
        .Q(reg_test[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[35]),
        .Q(reg_test[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[36]),
        .Q(reg_test[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[22]),
        .Q(reg_test[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[23]),
        .Q(reg_test[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[24]),
        .Q(reg_test[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[25]),
        .Q(reg_test[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[26]),
        .Q(reg_test[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[27]),
        .Q(reg_test[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[28]),
        .Q(reg_test[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[29]),
        .Q(reg_test[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[30]),
        .Q(reg_test[9]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[0]),
        .Q(uuid_stamp[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[100] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[100]),
        .Q(uuid_stamp[100]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[101] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[101]),
        .Q(uuid_stamp[101]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[102] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[102]),
        .Q(uuid_stamp[102]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[103] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[103]),
        .Q(uuid_stamp[103]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[104] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[104]),
        .Q(uuid_stamp[104]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[105] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[105]),
        .Q(uuid_stamp[105]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[106] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[106]),
        .Q(uuid_stamp[106]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[107] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[107]),
        .Q(uuid_stamp[107]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[108] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[108]),
        .Q(uuid_stamp[108]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[109] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[109]),
        .Q(uuid_stamp[109]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[10]),
        .Q(uuid_stamp[10]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[110] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[110]),
        .Q(uuid_stamp[110]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[111] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[111]),
        .Q(uuid_stamp[111]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[112] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[112]),
        .Q(uuid_stamp[112]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[113] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[113]),
        .Q(uuid_stamp[113]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[114] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[114]),
        .Q(uuid_stamp[114]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[115] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[115]),
        .Q(uuid_stamp[115]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[116] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[116]),
        .Q(uuid_stamp[116]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[117] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[117]),
        .Q(uuid_stamp[117]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[118] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[118]),
        .Q(uuid_stamp[118]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[119] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[119]),
        .Q(uuid_stamp[119]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[11]),
        .Q(uuid_stamp[11]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[120] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[120]),
        .Q(uuid_stamp[120]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[121] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[121]),
        .Q(uuid_stamp[121]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[122] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[122]),
        .Q(uuid_stamp[122]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[123] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[123]),
        .Q(uuid_stamp[123]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[124] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[124]),
        .Q(uuid_stamp[124]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[125] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[125]),
        .Q(uuid_stamp[125]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[126] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[126]),
        .Q(uuid_stamp[126]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[127] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[127]),
        .Q(uuid_stamp[127]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[12]),
        .Q(uuid_stamp[12]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[13]),
        .Q(uuid_stamp[13]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[14]),
        .Q(uuid_stamp[14]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[15]),
        .Q(uuid_stamp[15]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[16]),
        .Q(uuid_stamp[16]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[17] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[17]),
        .Q(uuid_stamp[17]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[18] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[18]),
        .Q(uuid_stamp[18]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[19] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[19]),
        .Q(uuid_stamp[19]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[1]),
        .Q(uuid_stamp[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[20] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[20]),
        .Q(uuid_stamp[20]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[21] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[21]),
        .Q(uuid_stamp[21]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[22] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[22]),
        .Q(uuid_stamp[22]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[23] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[23]),
        .Q(uuid_stamp[23]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[24] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[24]),
        .Q(uuid_stamp[24]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[25] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[25]),
        .Q(uuid_stamp[25]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[26] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[26]),
        .Q(uuid_stamp[26]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[27] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[27]),
        .Q(uuid_stamp[27]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[28] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[28]),
        .Q(uuid_stamp[28]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[29] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[29]),
        .Q(uuid_stamp[29]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[2]),
        .Q(uuid_stamp[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[30] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[30]),
        .Q(uuid_stamp[30]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[31] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[31]),
        .Q(uuid_stamp[31]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[32] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[32]),
        .Q(uuid_stamp[32]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[33] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[33]),
        .Q(uuid_stamp[33]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[34] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[34]),
        .Q(uuid_stamp[34]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[35] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[35]),
        .Q(uuid_stamp[35]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[36] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[36]),
        .Q(uuid_stamp[36]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[37] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[37]),
        .Q(uuid_stamp[37]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[38] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[38]),
        .Q(uuid_stamp[38]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[39] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[39]),
        .Q(uuid_stamp[39]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[3]),
        .Q(uuid_stamp[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[40] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[40]),
        .Q(uuid_stamp[40]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[41] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[41]),
        .Q(uuid_stamp[41]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[42] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[42]),
        .Q(uuid_stamp[42]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[43] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[43]),
        .Q(uuid_stamp[43]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[44] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[44]),
        .Q(uuid_stamp[44]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[45] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[45]),
        .Q(uuid_stamp[45]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[46] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[46]),
        .Q(uuid_stamp[46]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[47] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[47]),
        .Q(uuid_stamp[47]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[48] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[48]),
        .Q(uuid_stamp[48]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[49] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[49]),
        .Q(uuid_stamp[49]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[4]),
        .Q(uuid_stamp[4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[50] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[50]),
        .Q(uuid_stamp[50]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[51] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[51]),
        .Q(uuid_stamp[51]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[52] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[52]),
        .Q(uuid_stamp[52]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[53] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[53]),
        .Q(uuid_stamp[53]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[54] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[54]),
        .Q(uuid_stamp[54]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[55] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[55]),
        .Q(uuid_stamp[55]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[56] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[56]),
        .Q(uuid_stamp[56]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[57] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[57]),
        .Q(uuid_stamp[57]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[58] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[58]),
        .Q(uuid_stamp[58]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[59] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[59]),
        .Q(uuid_stamp[59]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[5]),
        .Q(uuid_stamp[5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[60] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[60]),
        .Q(uuid_stamp[60]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[61] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[61]),
        .Q(uuid_stamp[61]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[62] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[62]),
        .Q(uuid_stamp[62]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[63] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[63]),
        .Q(uuid_stamp[63]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[64] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[64]),
        .Q(uuid_stamp[64]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[65] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[65]),
        .Q(uuid_stamp[65]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[66] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[66]),
        .Q(uuid_stamp[66]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[67] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[67]),
        .Q(uuid_stamp[67]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[68] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[68]),
        .Q(uuid_stamp[68]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[69] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[69]),
        .Q(uuid_stamp[69]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[6]),
        .Q(uuid_stamp[6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[70] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[70]),
        .Q(uuid_stamp[70]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[71] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[71]),
        .Q(uuid_stamp[71]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[72] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[72]),
        .Q(uuid_stamp[72]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[73] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[73]),
        .Q(uuid_stamp[73]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[74] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[74]),
        .Q(uuid_stamp[74]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[75] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[75]),
        .Q(uuid_stamp[75]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[76] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[76]),
        .Q(uuid_stamp[76]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[77] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[77]),
        .Q(uuid_stamp[77]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[78] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[78]),
        .Q(uuid_stamp[78]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[79] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[79]),
        .Q(uuid_stamp[79]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[7]),
        .Q(uuid_stamp[7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[80] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[80]),
        .Q(uuid_stamp[80]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[81] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[81]),
        .Q(uuid_stamp[81]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[82] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[82]),
        .Q(uuid_stamp[82]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[83] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[83]),
        .Q(uuid_stamp[83]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[84] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[84]),
        .Q(uuid_stamp[84]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[85] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[85]),
        .Q(uuid_stamp[85]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[86] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[86]),
        .Q(uuid_stamp[86]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[87] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[87]),
        .Q(uuid_stamp[87]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[88] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[88]),
        .Q(uuid_stamp[88]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[89] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[89]),
        .Q(uuid_stamp[89]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[8]),
        .Q(uuid_stamp[8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[90] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[90]),
        .Q(uuid_stamp[90]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[91] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[91]),
        .Q(uuid_stamp[91]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[92] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[92]),
        .Q(uuid_stamp[92]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[93] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[93]),
        .Q(uuid_stamp[93]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[94] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[94]),
        .Q(uuid_stamp[94]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[95] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[95]),
        .Q(uuid_stamp[95]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[96] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[96]),
        .Q(uuid_stamp[96]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[97] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[97]),
        .Q(uuid_stamp[97]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[98] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[98]),
        .Q(uuid_stamp[98]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[99] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[99]),
        .Q(uuid_stamp[99]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[9]),
        .Q(uuid_stamp[9]),
        .R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
