### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2405991
date_generated | Wed Jan 14 14:35:05 2026 | os_platform | WIN64
product_version | Vivado v2018.3 (64-bit) | project_id | 27d4b1aff65f45b4909d3408c700e807
project_iteration | 10 | random_id | be329748881e536099b628c5a0978378
registration_id | be329748881e536099b628c5a0978378 | route_design | TRUE
target_device | xc7z035 | target_family | zynq
target_package | ffg676 | target_speed | -2
tool_flow | Vivado

user_environment
cpu_name | Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz | cpu_speed | 3096 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 68.000 GB | total_processors | 1

vivado_usage

gui_handlers
addedconstraintswithouttargetdialog_create_new_file=1 | applyrsbmultiautomationdialog_checkbox_tree=3 | basedialog_apply=3 | basedialog_cancel=2
basedialog_ok=165 | basedialog_yes=1 | cfgmempartchooser_density_chooser=5 | cfgmempartchooser_manufacturer_chooser=5
cfgmempartchooser_table=4 | cfgmempartchooser_type_chooser=4 | cfgmempartchooser_width_chooser=4 | clkconfigtreetablepanel_clk_config_tree_table=22
cmdmsgdialog_ok=21 | constraintschooserpanel_create_file=1 | coretreetablepanel_core_tree_table=3 | createconstraintsfilepanel_file_name=2
createnewdiagramdialog_design_name=1 | ddrconfigtreetablepanel_ddr_config_tree_table=18 | debugwizard_advanced_trigger=3 | debugwizard_capture_control=3
debugwizard_find_nets_to_add=1 | filesetpanel_file_set_panel_tree=206 | flownavigatortreepanel_flow_navigator_tree=128 | fpgachooser_family=1
fpgachooser_fpga_table=1 | fpgachooser_speed=1 | hardwareilawaveformview_run_trigger_for_this_ila_core=5 | hardwaretreepanel_hardware_tree_table=77
mainmenumgr_checkpoint=57 | mainmenumgr_constraints=2 | mainmenumgr_edit=14 | mainmenumgr_export=74
mainmenumgr_file=132 | mainmenumgr_flow=14 | mainmenumgr_help=2 | mainmenumgr_import=24
mainmenumgr_ip=57 | mainmenumgr_project=62 | mainmenumgr_reports=14 | mainmenumgr_text_editor=45
mainmenumgr_tools=32 | mainmenumgr_view=14 | mainmenumgr_window=14 | maintoolbarmgr_run=4
mainwinmenumgr_layout=20 | mainwinmenumgr_load=1 | mioconfigtreetablepanel_mio_config_tree_table=137 | netlisttreeview_netlist_tree=126
newexporthardwaredialog_include_bitstream=18 | packagetreepanel_package_tree_panel=1 | pacommandnames_add_sources=4 | pacommandnames_auto_connect_ports=1
pacommandnames_auto_connect_target=12 | pacommandnames_auto_update_hier=35 | pacommandnames_boot_device=11 | pacommandnames_close_hardware_design=1
pacommandnames_create_top_hdl=4 | pacommandnames_export_hardware=24 | pacommandnames_generate_composite_file=6 | pacommandnames_goto_netlist_design=3
pacommandnames_goto_source=1 | pacommandnames_launch_hardware=35 | pacommandnames_mark_debug_net=41 | pacommandnames_new_project=1
pacommandnames_open_target_wizard=1 | pacommandnames_program_config_memory=2 | pacommandnames_program_fpga=9 | pacommandnames_refresh_device=13
pacommandnames_run_bitgen=10 | pacommandnames_run_synthesis=4 | pacommandnames_stop_trigger=1 | pacommandnames_unmark_debug_net=1
paviews_address_editor=3 | paviews_code=12 | paviews_dashboard=15 | paviews_device=2
paviews_ip_catalog=4 | paviews_package=1 | paviews_project_summary=25 | paviews_system=1
planaheadtab_refresh_changed_modules=1 | programcfgmemdialog_contents_of_configuration_file=4 | programcfgmemdialog_specify_elf_file=4 | programdebugtab_available_targets_on_server=2
programdebugtab_open_target=9 | programdebugtab_program_device=4 | programdebugtab_refresh_device=15 | programfpgadialog_program=9
projectnamechooser_project_name=1 | projecttab_close_design=2 | projecttab_reload=1 | rdicommands_custom_commands=8
rdicommands_delete=2 | rdicommands_properties=4 | rdicommands_settings=1 | rdiviews_waveform_viewer=4
rsbaddmoduledialog_module_list=1 | rsbapplyautomationbar_run_block_automation=1 | rsbapplyautomationbar_run_connection_automation=2 | rsbexternalinterfaceproppanels_name=1
saveprojectutils_save=1 | selectmenu_highlight=12 | selectmenu_mark=2 | signaltreepanel_signal_tree_table=17
simpleoutputproductdialog_generate_output_products_immediately=6 | simpleoutputproductdialog_synthesize_design_globally=1 | srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 | srcmenu_ip_hierarchy=23
srcmenu_refresh_hierarchy=23 | syntheticagettingstartedview_recent_projects=7 | systembuildermenu_add_ip=1 | systembuildermenu_add_module=3
systembuilderview_expand_collapse=7 | systembuilderview_orientation=5 | systembuilderview_pinning=10 | taskbanner_close=5
tclconsoleview_tcl_console_code_editor=1 | waveformnametree_waveform_name_tree=8

java_command_handlers
addcfgmem=8 | addsources=5 | autoconnectport=1 | autoconnecttarget=12
bootdevice=11 | closedesign=1 | createblockdesign=1 | createtophdl=4
customizersbblock=11 | debugwizardcmdhandler=5 | editdelete=2 | editproperties=4
editundo=4 | launchopentarget=1 | launchprogramfpga=11 | managecompositetargets=6
markdebug=41 | newexporthardware=24 | newhardwaredashboard=1 | newlaunchhardware=35
newproject=1 | openblockdesign=18 | openhardwaremanager=20 | openrecenttarget=12
programcfgmem=6 | programdevice=5 | refreshdevice=28 | runbitgen=10
runimplementation=11 | runsynthesis=13 | runtrigger=5 | savedesign=4
saversbdesign=4 | showsource=1 | stoptrigger=1 | toolssettings=2
unmarkdebug=1 | viewlayoutcmd=2 | viewtasksynthesis=4

other_data
guimode=35

project_data
constraintsetcount=2 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=5 | export_simulation_ies=5
export_simulation_modelsim=5 | export_simulation_questa=5 | export_simulation_riviera=5 | export_simulation_vcs=5
export_simulation_xsim=5 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=5 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation

post_unisim_transformation
bibuf=130 | bscane2=1 | bufg=1 | carry4=18
dna_port=1 | fdce=66 | fdpe=40 | fdre=690
fdse=20 | gnd=28 | ibuf=33 | ldce=57
lut1=112 | lut2=35 | lut3=242 | lut4=69
lut5=65 | lut6=154 | muxf7=761 | muxf8=308
obuft=33 | ps7=1 | ramb18e1=1 | ramb36e1=2
ramd32=36 | ramd64e=128 | rams32=12 | srl16e=19
srlc16e=2 | srlc32e=47 | vcc=31

pre_unisim_transformation
bibuf=130 | bscane2=1 | bufg=1 | carry4=18
cfglut5=6404 | dna_port=1 | fdce=66 | fdpe=40
fdre=690 | fdse=20 | gnd=28 | iobuf=33
ldce=57 | lut1=112 | lut2=35 | lut3=242
lut4=69 | lut5=65 | lut6=154 | muxf7=761
muxf8=308 | ps7=1 | ram32m=6 | ram64m=32
ramb18e1=1 | ramb36e1=2 | srl16e=19 | srlc16e=2
srlc32e=47 | vcc=31

power_opt_design

command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]

usage
bram_ports_augmented=3 | bram_ports_newly_gated=0 | bram_ports_total=6 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=18795 | srls_augmented=0
srls_newly_gated=0 | srls_total=13320

ip_statistics

IP_Integrator/1
bdsource=USER | core_container=NA | da_axi4_cnt=2 | da_clkrst_cnt=2
da_ps7_cnt=1 | iptotal=1 | maxhierdepth=0 | numblks=7
numhdlrefblks=2 | numhierblks=2 | numhlsblks=0 | numnonxlnxblks=0
numpkgbdblks=0 | numreposblks=5 | numsysgenblks=0 | synth_mode=Global
x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=system | x_ipvendor=xilinx.com
x_ipversion=1.00.a

axi_protocol_converter_v2_1_18_axi_protocol_converter/1
c_axi_addr_width=32 | c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1
c_axi_data_width=32 | c_axi_id_width=12 | c_axi_ruser_width=1 | c_axi_supports_read=1
c_axi_supports_user_signals=0 | c_axi_supports_write=1 | c_axi_wuser_width=1 | c_family=zynq
c_ignore_id=0 | c_m_axi_protocol=2 | c_s_axi_protocol=1 | c_translation_mode=2
core_container=NA | iptotal=1 | x_ipcorerevision=18 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=axi_protocol_converter | x_ipproduct=Vivado 2018.3 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=2.1

dna_port_read/1
core_container=NA | iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG
x_iplibrary=module_ref | x_ipname=dna_port_read | x_ipproduct=Vivado 2018.3 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0

labtools_ila_v6_00_a/1
all_probe_same_mu=true | all_probe_same_mu_cnt=4 | c_adv_trigger=true | c_data_depth=1024
c_en_strg_qual=true | c_input_pipe_stages=0 | c_num_of_probes=77 | c_probe0_type=0
c_probe0_width=1 | c_probe10_type=0 | c_probe10_width=1 | c_probe11_type=0
c_probe11_width=1 | c_probe12_type=0 | c_probe12_width=1 | c_probe13_type=0
c_probe13_width=1 | c_probe14_type=0 | c_probe14_width=1 | c_probe15_type=0
c_probe15_width=1 | c_probe16_type=0 | c_probe16_width=1 | c_probe17_type=0
c_probe17_width=1 | c_probe18_type=0 | c_probe18_width=1 | c_probe19_type=0
c_probe19_width=1 | c_probe1_type=0 | c_probe1_width=1 | c_probe20_type=0
c_probe20_width=1 | c_probe21_type=0 | c_probe21_width=1 | c_probe22_type=0
c_probe22_width=1 | c_probe23_type=0 | c_probe23_width=1 | c_probe24_type=0
c_probe24_width=1 | c_probe25_type=0 | c_probe25_width=1 | c_probe26_type=0
c_probe26_width=1 | c_probe27_type=0 | c_probe27_width=1 | c_probe28_type=0
c_probe28_width=1 | c_probe29_type=0 | c_probe29_width=1 | c_probe2_type=0
c_probe2_width=1 | c_probe30_type=0 | c_probe30_width=1 | c_probe31_type=0
c_probe31_width=1 | c_probe32_type=0 | c_probe32_width=1 | c_probe33_type=0
c_probe33_width=1 | c_probe34_type=0 | c_probe34_width=1 | c_probe35_type=0
c_probe35_width=1 | c_probe36_type=0 | c_probe36_width=1 | c_probe37_type=0
c_probe37_width=1 | c_probe38_type=0 | c_probe38_width=1 | c_probe39_type=0
c_probe39_width=1 | c_probe3_type=0 | c_probe3_width=1 | c_probe40_type=0
c_probe40_width=1 | c_probe41_type=0 | c_probe41_width=1 | c_probe42_type=0
c_probe42_width=1 | c_probe43_type=0 | c_probe43_width=1 | c_probe44_type=0
c_probe44_width=1 | c_probe45_type=0 | c_probe45_width=1 | c_probe46_type=0
c_probe46_width=1 | c_probe47_type=0 | c_probe47_width=1 | c_probe48_type=0
c_probe48_width=1 | c_probe49_type=0 | c_probe49_width=1 | c_probe4_type=0
c_probe4_width=1 | c_probe50_type=0 | c_probe50_width=1 | c_probe51_type=0
c_probe51_width=1 | c_probe52_type=0 | c_probe52_width=1 | c_probe53_type=0
c_probe53_width=1 | c_probe54_type=0 | c_probe54_width=1 | c_probe55_type=0
c_probe55_width=1 | c_probe56_type=0 | c_probe56_width=1 | c_probe57_type=0
c_probe57_width=1 | c_probe58_type=0 | c_probe58_width=1 | c_probe59_type=0
c_probe59_width=1 | c_probe5_type=0 | c_probe5_width=1 | c_probe60_type=0
c_probe60_width=1 | c_probe61_type=0 | c_probe61_width=1 | c_probe62_type=0
c_probe62_width=1 | c_probe63_type=0 | c_probe63_width=1 | c_probe64_type=0
c_probe64_width=1 | c_probe65_type=0 | c_probe65_width=1 | c_probe66_type=0
c_probe66_width=1 | c_probe67_type=0 | c_probe67_width=1 | c_probe68_type=0
c_probe68_width=1 | c_probe69_type=0 | c_probe69_width=1 | c_probe6_type=0
c_probe6_width=1 | c_probe70_type=0 | c_probe70_width=1 | c_probe71_type=0
c_probe71_width=1 | c_probe72_type=0 | c_probe72_width=1 | c_probe73_type=0
c_probe73_width=1 | c_probe74_type=0 | c_probe74_width=1 | c_probe75_type=0
c_probe75_width=1 | c_probe76_type=0 | c_probe76_width=1 | c_probe7_type=0
c_probe7_width=1 | c_probe8_type=0 | c_probe8_width=1 | c_probe9_type=0
c_probe9_width=1 | c_trigin_en=0 | c_trigout_en=0 | component_name=u_ila_0
core_container=NA | iptotal=1

labtools_xsdbm_v3_00_a/1
c_bscan_mode=false | c_bscan_mode_with_core=false | c_clk_input_freq_hz=300000000 | c_en_bscanid_vec=false
c_enable_clk_divider=false | c_num_bscan_master_ports=0 | c_two_prim_mode=false | c_use_ext_bscan=false
c_user_scan_chain=1 | c_xsdb_num_slaves=1 | component_name=dbg_hub_CV | core_container=NA
iptotal=1

mydna_read_v1_0/1
c_s00_axi_addr_width=4 | c_s00_axi_data_width=32 | core_container=NA | iptotal=1
x_ipcorerevision=1 | x_iplanguage=VERILOG | x_iplibrary=module_ref | x_ipname=mydna_read_v1_0
x_ipproduct=Vivado 2018.3 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=1.0

proc_sys_reset/1
c_aux_reset_high=0 | c_aux_rst_width=4 | c_ext_reset_high=0 | c_ext_rst_width=4
c_family=zynq | c_num_bus_rst=1 | c_num_interconnect_aresetn=1 | c_num_perp_aresetn=1
c_num_perp_rst=1 | core_container=NA | iptotal=1 | x_ipcorerevision=13
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=proc_sys_reset | x_ipproduct=Vivado 2018.3
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=5.0

processing_system7_v5.5_user_configuration/1
core_container=NA | iptotal=1 | pcw_apu_clk_ratio_enable=6:2:1 | pcw_apu_peripheral_freqmhz=666.666666
pcw_armpll_ctrl_fbdiv=40 | pcw_can0_grp_clk_enable=0 | pcw_can0_peripheral_clksrc=External | pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 | pcw_can1_grp_clk_enable=0 | pcw_can1_peripheral_clksrc=External | pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 | pcw_can_peripheral_clksrc=IO PLL | pcw_can_peripheral_freqmhz=100 | pcw_cpu_cpu_pll_freqmhz=1333.333
pcw_cpu_peripheral_clksrc=ARM PLL | pcw_crystal_peripheral_freqmhz=33.333333 | pcw_dci_peripheral_clksrc=DDR PLL | pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1066.667 | pcw_ddr_hpr_to_critical_priority_level=15 | pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) | pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL | pcw_ddr_port0_hpr_enable=0 | pcw_ddr_port1_hpr_enable=0 | pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 | pcw_ddr_write_to_critical_priority_level=2 | pcw_ddrpll_ctrl_fbdiv=32 | pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 | pcw_enet0_peripheral_clksrc=IO PLL | pcw_enet0_peripheral_enable=1 | pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=0 | pcw_enet1_grp_mdio_enable=0 | pcw_enet1_peripheral_clksrc=IO PLL | pcw_enet1_peripheral_enable=0
pcw_enet1_peripheral_freqmhz=1000 Mbps | pcw_enet1_reset_enable=0 | pcw_enet_reset_polarity=Active Low | pcw_fclk0_peripheral_clksrc=IO PLL
pcw_fclk1_peripheral_clksrc=IO PLL | pcw_fclk2_peripheral_clksrc=IO PLL | pcw_fclk3_peripheral_clksrc=IO PLL | pcw_fpga0_peripheral_freqmhz=100
pcw_fpga1_peripheral_freqmhz=50 | pcw_fpga2_peripheral_freqmhz=50 | pcw_fpga3_peripheral_freqmhz=50 | pcw_fpga_fclk0_enable=1
pcw_fpga_fclk1_enable=0 | pcw_fpga_fclk2_enable=0 | pcw_fpga_fclk3_enable=0 | pcw_ftm_cti_in0=DISABLED
pcw_ftm_cti_in1=DISABLED | pcw_ftm_cti_in2=DISABLED | pcw_ftm_cti_in3=DISABLED | pcw_ftm_cti_out0=DISABLED
pcw_ftm_cti_out1=DISABLED | pcw_ftm_cti_out2=DISABLED | pcw_ftm_cti_out3=DISABLED | pcw_gpio_emio_gpio_enable=1
pcw_gpio_emio_gpio_io=33 | pcw_gpio_mio_gpio_enable=0 | pcw_gpio_peripheral_enable=0 | pcw_i2c0_grp_int_enable=0
pcw_i2c0_peripheral_enable=0 | pcw_i2c0_reset_enable=0 | pcw_i2c1_grp_int_enable=0 | pcw_i2c1_peripheral_enable=0
pcw_i2c1_reset_enable=0 | pcw_i2c_reset_polarity=Active Low | pcw_io_io_pll_freqmhz=1000.000 | pcw_iopll_ctrl_fbdiv=30
pcw_irq_f2p_mode=DIRECT | pcw_m_axi_gp0_freqmhz=100 | pcw_m_axi_gp1_freqmhz=10 | pcw_nand_cycles_t_ar=1
pcw_nand_cycles_t_clr=1 | pcw_nand_cycles_t_rc=11 | pcw_nand_cycles_t_rea=1 | pcw_nand_cycles_t_rr=1
pcw_nand_cycles_t_wc=11 | pcw_nand_cycles_t_wp=1 | pcw_nand_grp_d8_enable=0 | pcw_nand_peripheral_enable=0
pcw_nor_cs0_t_ceoe=1 | pcw_nor_cs0_t_pc=1 | pcw_nor_cs0_t_rc=11 | pcw_nor_cs0_t_tr=1
pcw_nor_cs0_t_wc=11 | pcw_nor_cs0_t_wp=1 | pcw_nor_cs0_we_time=0 | pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_pc=1 | pcw_nor_cs1_t_rc=11 | pcw_nor_cs1_t_tr=1 | pcw_nor_cs1_t_wc=11
pcw_nor_cs1_t_wp=1 | pcw_nor_cs1_we_time=0 | pcw_nor_grp_a25_enable=0 | pcw_nor_grp_cs0_enable=0
pcw_nor_grp_cs1_enable=0 | pcw_nor_grp_sram_cs0_enable=0 | pcw_nor_grp_sram_cs1_enable=0 | pcw_nor_grp_sram_int_enable=0
pcw_nor_peripheral_enable=0 | pcw_nor_sram_cs0_t_ceoe=1 | pcw_nor_sram_cs0_t_pc=1 | pcw_nor_sram_cs0_t_rc=11
pcw_nor_sram_cs0_t_tr=1 | pcw_nor_sram_cs0_t_wc=11 | pcw_nor_sram_cs0_t_wp=1 | pcw_nor_sram_cs0_we_time=0
pcw_nor_sram_cs1_t_ceoe=1 | pcw_nor_sram_cs1_t_pc=1 | pcw_nor_sram_cs1_t_rc=11 | pcw_nor_sram_cs1_t_tr=1
pcw_nor_sram_cs1_t_wc=11 | pcw_nor_sram_cs1_t_wp=1 | pcw_nor_sram_cs1_we_time=0 | pcw_override_basic_clock=0
pcw_pcap_peripheral_clksrc=IO PLL | pcw_pcap_peripheral_freqmhz=200 | pcw_pjtag_peripheral_enable=0 | pcw_preset_bank0_voltage=LVCMOS 3.3V
pcw_preset_bank1_voltage=LVCMOS 1.8V | pcw_qspi_grp_fbclk_enable=1 | pcw_qspi_grp_fbclk_io=MIO 8 | pcw_qspi_grp_io1_enable=0
pcw_qspi_grp_single_ss_enable=1 | pcw_qspi_grp_single_ss_io=MIO 1 .. 6 | pcw_qspi_grp_ss1_enable=0 | pcw_qspi_internal_highaddress=0xFCFFFFFF
pcw_qspi_peripheral_clksrc=IO PLL | pcw_qspi_peripheral_enable=1 | pcw_qspi_peripheral_freqmhz=150 | pcw_qspi_qspi_io=MIO 1 .. 6
pcw_s_axi_acp_freqmhz=10 | pcw_s_axi_gp0_freqmhz=10 | pcw_s_axi_gp1_freqmhz=10 | pcw_s_axi_hp0_data_width=64
pcw_s_axi_hp0_freqmhz=10 | pcw_s_axi_hp1_data_width=64 | pcw_s_axi_hp1_freqmhz=10 | pcw_s_axi_hp2_data_width=64
pcw_s_axi_hp2_freqmhz=10 | pcw_s_axi_hp3_data_width=64 | pcw_s_axi_hp3_freqmhz=10 | pcw_sd0_grp_cd_enable=1
pcw_sd0_grp_cd_io=MIO 47 | pcw_sd0_grp_pow_enable=0 | pcw_sd0_grp_wp_enable=1 | pcw_sd0_grp_wp_io=MIO 46
pcw_sd0_peripheral_enable=1 | pcw_sd0_sd0_io=MIO 40 .. 45 | pcw_sd1_grp_cd_enable=0 | pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 | pcw_sd1_peripheral_enable=0 | pcw_sdio_peripheral_clksrc=IO PLL | pcw_sdio_peripheral_freqmhz=50
pcw_single_qspi_data_mode=x4 | pcw_smc_peripheral_clksrc=IO PLL | pcw_smc_peripheral_freqmhz=100 | pcw_spi0_grp_ss0_enable=0
pcw_spi0_grp_ss1_enable=0 | pcw_spi0_grp_ss2_enable=0 | pcw_spi0_peripheral_enable=0 | pcw_spi1_grp_ss0_enable=0
pcw_spi1_grp_ss1_enable=0 | pcw_spi1_grp_ss2_enable=0 | pcw_spi1_peripheral_enable=0 | pcw_spi_peripheral_clksrc=IO PLL
pcw_spi_peripheral_freqmhz=166.666666 | pcw_tpiu_peripheral_clksrc=External | pcw_tpiu_peripheral_freqmhz=200 | pcw_trace_grp_16bit_enable=0
pcw_trace_grp_2bit_enable=0 | pcw_trace_grp_32bit_enable=0 | pcw_trace_grp_4bit_enable=0 | pcw_trace_grp_8bit_enable=0
pcw_trace_peripheral_enable=0 | pcw_ttc0_clk0_peripheral_clksrc=CPU_1X | pcw_ttc0_clk0_peripheral_freqmhz=133.333333 | pcw_ttc0_clk1_peripheral_clksrc=CPU_1X
pcw_ttc0_clk1_peripheral_freqmhz=133.333333 | pcw_ttc0_clk2_peripheral_clksrc=CPU_1X | pcw_ttc0_clk2_peripheral_freqmhz=133.333333 | pcw_ttc0_peripheral_enable=0
pcw_ttc1_clk0_peripheral_clksrc=CPU_1X | pcw_ttc1_clk0_peripheral_freqmhz=133.333333 | pcw_ttc1_clk1_peripheral_clksrc=CPU_1X | pcw_ttc1_clk1_peripheral_freqmhz=133.333333
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X | pcw_ttc1_clk2_peripheral_freqmhz=133.333333 | pcw_ttc1_peripheral_enable=0 | pcw_ttc_peripheral_freqmhz=50
pcw_uart0_baud_rate=115200 | pcw_uart0_grp_full_enable=0 | pcw_uart0_peripheral_enable=0 | pcw_uart1_baud_rate=115200
pcw_uart1_grp_full_enable=0 | pcw_uart1_peripheral_enable=1 | pcw_uart1_uart1_io=MIO 48 .. 49 | pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=100 | pcw_uiparam_ddr_adv_enable=0 | pcw_uiparam_ddr_al=0 | pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 | pcw_uiparam_ddr_board_delay0=0.25 | pcw_uiparam_ddr_board_delay1=0.25 | pcw_uiparam_ddr_board_delay2=0.25
pcw_uiparam_ddr_board_delay3=0.25 | pcw_uiparam_ddr_bus_width=32 Bit | pcw_uiparam_ddr_cl=7 | pcw_uiparam_ddr_clock_0_length_mm=0
pcw_uiparam_ddr_clock_0_package_length=139.2255 | pcw_uiparam_ddr_clock_0_propogation_delay=160 | pcw_uiparam_ddr_clock_1_length_mm=0 | pcw_uiparam_ddr_clock_1_package_length=139.2255
pcw_uiparam_ddr_clock_1_propogation_delay=160 | pcw_uiparam_ddr_clock_2_length_mm=0 | pcw_uiparam_ddr_clock_2_package_length=139.2255 | pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 | pcw_uiparam_ddr_clock_3_package_length=139.2255 | pcw_uiparam_ddr_clock_3_propogation_delay=160 | pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 | pcw_uiparam_ddr_cwl=6 | pcw_uiparam_ddr_device_capacity=4096 MBits | pcw_uiparam_ddr_dq_0_length_mm=0
pcw_uiparam_ddr_dq_0_package_length=105.3065 | pcw_uiparam_ddr_dq_0_propogation_delay=160 | pcw_uiparam_ddr_dq_1_length_mm=0 | pcw_uiparam_ddr_dq_1_package_length=126.177
pcw_uiparam_ddr_dq_1_propogation_delay=160 | pcw_uiparam_ddr_dq_2_length_mm=0 | pcw_uiparam_ddr_dq_2_package_length=129.083 | pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 | pcw_uiparam_ddr_dq_3_package_length=148.0365 | pcw_uiparam_ddr_dq_3_propogation_delay=160 | pcw_uiparam_ddr_dqs_0_length_mm=0
pcw_uiparam_ddr_dqs_0_package_length=101.3165 | pcw_uiparam_ddr_dqs_0_propogation_delay=160 | pcw_uiparam_ddr_dqs_1_length_mm=0 | pcw_uiparam_ddr_dqs_1_package_length=120.42
pcw_uiparam_ddr_dqs_1_propogation_delay=160 | pcw_uiparam_ddr_dqs_2_length_mm=0 | pcw_uiparam_ddr_dqs_2_package_length=121.0875 | pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 | pcw_uiparam_ddr_dqs_3_package_length=142.1405 | pcw_uiparam_ddr_dqs_3_propogation_delay=160 | pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0
pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0 | pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0 | pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0 | pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled | pcw_uiparam_ddr_enable=1 | pcw_uiparam_ddr_freq_mhz=533.333333 | pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 | pcw_uiparam_ddr_partno=MT41K256M16 RE-125 | pcw_uiparam_ddr_row_addr_count=15 | pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=40.0 | pcw_uiparam_ddr_t_ras_min=35.0 | pcw_uiparam_ddr_t_rc=48.75 | pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 | pcw_uiparam_ddr_train_data_eye=1 | pcw_uiparam_ddr_train_read_gate=1 | pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=0 | pcw_usb0_peripheral_enable=0 | pcw_usb0_peripheral_freqmhz=60 | pcw_usb0_reset_enable=0
pcw_usb1_peripheral_enable=0 | pcw_usb1_peripheral_freqmhz=60 | pcw_usb1_reset_enable=0 | pcw_usb_reset_polarity=Active Low
pcw_use_cross_trigger=0 | pcw_use_m_axi_gp0=1 | pcw_use_m_axi_gp1=0 | pcw_use_s_axi_acp=0
pcw_use_s_axi_gp0=0 | pcw_use_s_axi_gp1=0 | pcw_use_s_axi_hp0=0 | pcw_use_s_axi_hp1=0
pcw_use_s_axi_hp2=0 | pcw_use_s_axi_hp3=0 | pcw_wdt_peripheral_clksrc=CPU_1X | pcw_wdt_peripheral_enable=0
pcw_wdt_peripheral_freqmhz=133.333333

processing_system7_v5_5_processing_system7/1
c_dm_width=4 | c_dq_width=32 | c_dqs_width=4 | c_emio_gpio_width=33
c_en_emio_enet0=0 | c_en_emio_enet1=0 | c_en_emio_pjtag=0 | c_en_emio_trace=0
c_fclk_clk0_buf=TRUE | c_fclk_clk1_buf=FALSE | c_fclk_clk2_buf=FALSE | c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 | c_gp1_en_modifiable_txn=1 | c_include_acp_trans_check=0 | c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT | c_m_axi_gp0_enable_static_remap=0 | c_m_axi_gp0_id_width=12 | c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 | c_m_axi_gp1_id_width=12 | c_m_axi_gp1_thread_id_width=12 | c_mio_primitive=54
c_num_f2p_intr_inputs=1 | c_package_name=ffg676 | c_ps7_si_rev=PRODUCTION | c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 | c_s_axi_acp_id_width=3 | c_s_axi_gp0_id_width=6 | c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 | c_s_axi_hp0_id_width=6 | c_s_axi_hp1_data_width=64 | c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 | c_s_axi_hp2_id_width=6 | c_s_axi_hp3_data_width=64 | c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 | c_trace_buffer_fifo_size=128 | c_trace_internal_width=2 | c_trace_pipeline_width=8
c_use_axi_nonsecure=0 | c_use_default_acp_user_val=0 | c_use_m_axi_gp0=1 | c_use_m_axi_gp1=0
c_use_s_axi_acp=0 | c_use_s_axi_gp0=0 | c_use_s_axi_gp1=0 | c_use_s_axi_hp0=0
c_use_s_axi_hp1=0 | c_use_s_axi_hp2=0 | c_use_s_axi_hp3=0 | core_container=NA
iptotal=1 | use_trace_data_edge_detector=0 | x_ipcorerevision=6 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=processing_system7 | x_ipproduct=Vivado 2018.3 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=5.5

report_drc

command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]

report_utilization

clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=2 | bufgctrl_util_percentage=6.25
bufhce_available=168 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=32 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=16 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=32 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=8 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=8 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00

dsp
dsps_available=900 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00

io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_i_dci=0
diff_hstl_i_dci_18=0 | diff_hstl_ii=0 | diff_hstl_ii_18=0 | diff_hstl_ii_dci=0
diff_hstl_ii_dci_18=0 | diff_hstl_ii_t_dci=0 | diff_hstl_ii_t_dci_18=0 | diff_hsul_12=0
diff_hsul_12_dci=0 | diff_mobile_ddr=0 | diff_sstl12=0 | diff_sstl12_dci=0
diff_sstl12_t_dci=0 | diff_sstl135=0 | diff_sstl135_dci=0 | diff_sstl135_r=0
diff_sstl135_t_dci=0 | diff_sstl15=1 | diff_sstl15_dci=0 | diff_sstl15_r=0
diff_sstl15_t_dci=1 | diff_sstl18_i=0 | diff_sstl18_i_dci=0 | diff_sstl18_ii=0
diff_sstl18_ii_dci=0 | diff_sstl18_ii_t_dci=0 | hslvdci_15=0 | hslvdci_18=0
hstl_i=0 | hstl_i_12=0 | hstl_i_18=0 | hstl_i_dci=0
hstl_i_dci_18=0 | hstl_ii=0 | hstl_ii_18=0 | hstl_ii_dci=0
hstl_ii_dci_18=0 | hstl_ii_t_dci=0 | hstl_ii_t_dci_18=0 | hsul_12=0
hsul_12_dci=0 | lvcmos12=0 | lvcmos15=0 | lvcmos18=1
lvcmos25=0 | lvcmos33=1 | lvdci_15=0 | lvdci_18=0
lvdci_dv2_15=0 | lvdci_dv2_18=0 | lvds=0 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl12=0 | sstl12_dci=0
sstl12_t_dci=0 | sstl135=0 | sstl135_dci=0 | sstl135_r=0
sstl135_t_dci=0 | sstl15=1 | sstl15_dci=0 | sstl15_r=0
sstl15_t_dci=1 | sstl18_i=0 | sstl18_i_dci=0 | sstl18_ii=0
sstl18_ii_dci=0 | sstl18_ii_t_dci=0 | tmds_33=0

memory
block_ram_tile_available=500 | block_ram_tile_fixed=0 | block_ram_tile_used=2.5 | block_ram_tile_util_percentage=0.50
ramb18_available=1000 | ramb18_fixed=0 | ramb18_used=1 | ramb18_util_percentage=0.10
ramb18e1_only_used=1 | ramb36_fifo_available=500 | ramb36_fifo_fixed=0 | ramb36_fifo_used=2
ramb36_fifo_util_percentage=0.40 | ramb36e1_only_used=2

primitives
bibuf_functional_category=IO | bibuf_used=130 | bscane2_functional_category=Others | bscane2_used=1
bufg_functional_category=Clock | bufg_used=2 | carry4_functional_category=CarryLogic | carry4_used=1979
dna_port_functional_category=Others | dna_port_used=1 | fdce_functional_category=Flop & Latch | fdce_used=237
fdpe_functional_category=Flop & Latch | fdpe_used=40 | fdre_functional_category=Flop & Latch | fdre_used=18455
fdse_functional_category=Flop & Latch | fdse_used=63 | ibuf_functional_category=IO | ibuf_used=33
ldce_functional_category=Flop & Latch | ldce_used=57 | lut1_functional_category=LUT | lut1_used=425
lut2_functional_category=LUT | lut2_used=543 | lut3_functional_category=LUT | lut3_used=1271
lut4_functional_category=LUT | lut4_used=3281 | lut5_functional_category=LUT | lut5_used=539
lut6_functional_category=LUT | lut6_used=8385 | muxf7_functional_category=MuxFx | muxf7_used=761
muxf8_functional_category=MuxFx | muxf8_used=308 | obuft_functional_category=IO | obuft_used=33
ps7_functional_category=Specialized Resource | ps7_used=1 | ramb18e1_functional_category=Block Memory | ramb18e1_used=1
ramb36e1_functional_category=Block Memory | ramb36e1_used=2 | ramd32_functional_category=Distributed Memory | ramd32_used=36
ramd64e_functional_category=Distributed Memory | ramd64e_used=128 | rams32_functional_category=Distributed Memory | rams32_used=12
srl16e_functional_category=Distributed Memory | srl16e_used=6508 | srlc16e_functional_category=Distributed Memory | srlc16e_used=2
srlc32e_functional_category=Distributed Memory | srlc32e_used=6810

slice_logic
f7_muxes_available=109300 | f7_muxes_fixed=0 | f7_muxes_used=761 | f7_muxes_util_percentage=0.70
f8_muxes_available=54650 | f8_muxes_fixed=0 | f8_muxes_used=308 | f8_muxes_util_percentage=0.56
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=152 | lut_as_logic_available=171900 | lut_as_logic_fixed=0
lut_as_logic_used=13155 | lut_as_logic_util_percentage=7.65 | lut_as_memory_available=70400 | lut_as_memory_fixed=0
lut_as_memory_used=7027 | lut_as_memory_util_percentage=9.98 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=6875
register_as_flip_flop_available=343800 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=18795 | register_as_flip_flop_util_percentage=5.47
register_as_latch_available=343800 | register_as_latch_fixed=0 | register_as_latch_used=57 | register_as_latch_util_percentage=0.02
slice_luts_available=171900 | slice_luts_fixed=0 | slice_luts_used=20182 | slice_luts_util_percentage=11.74
slice_registers_available=343800 | slice_registers_fixed=0 | slice_registers_used=18852 | slice_registers_util_percentage=5.48
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=152 | lut_as_logic_available=171900 | lut_as_logic_fixed=0
lut_as_logic_used=13155 | lut_as_logic_util_percentage=7.65 | lut_as_memory_available=70400 | lut_as_memory_fixed=0
lut_as_memory_used=7027 | lut_as_memory_util_percentage=9.98 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=6875
lut_in_front_of_the_register_is_unused_fixed=6875 | lut_in_front_of_the_register_is_unused_used=5789 | lut_in_front_of_the_register_is_used_fixed=5789 | lut_in_front_of_the_register_is_used_used=1471
register_driven_from_outside_the_slice_fixed=1471 | register_driven_from_outside_the_slice_used=7260 | register_driven_from_within_the_slice_fixed=7260 | register_driven_from_within_the_slice_used=11592
slice_available=54650 | slice_fixed=0 | slice_registers_available=343800 | slice_registers_fixed=0
slice_registers_used=18852 | slice_registers_util_percentage=5.48 | slice_used=7753 | slice_util_percentage=14.19
slicel_fixed=0 | slicel_used=4775 | slicem_fixed=0 | slicem_used=2978
unique_control_sets_available=54650 | unique_control_sets_fixed=54650 | unique_control_sets_used=858 | unique_control_sets_util_percentage=1.57
using_o5_and_o6_fixed=1.57 | using_o5_and_o6_used=6445 | using_o5_output_only_fixed=6445 | using_o5_output_only_used=7
using_o6_output_only_fixed=7 | using_o6_output_only_used=423

specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=1 | bscane2_util_percentage=25.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=1 | dna_port_util_percentage=100.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis

command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z035ffg676-2
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=system_wrapper | -verilog_define=default::[not_specified]

usage
elapsed=00:00:58s | hls_ip=0 | memory_gain=782.723MB | memory_peak=1152.969MB