+* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 11/02/17 Added processor specific sleep routines +* function prototypes. +* 7.7 sk 01/10/22 Typecast sleep declaration argument from unsigned int to +* u32 to fix misra_c_2012_directive_4_6 violation. +* 7.7 sk 01/10/22 Modify the return type of sleep_R5 and usleep_R5 from +* unsigned to void to fix misra_c_2012_rule_17_7 violation. +* 8.0 sk 03/02/22 Update usleep_R5 and usleep parameter types to fix misra_ +* c_2012_directive_4_6 violation. +* 8.0 sk 03/17/22 Modify the return type of usleep_MB from int to void and +* sleep_MB from unsigned to void to fix misra_c_2012_rule_ +* 17_7 violation. +* 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to +* u32 and usleep_MB parameter type from unsigned long to +* ULONG to fix misra_c_2012_rule_4_6 violation. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +*+* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +/************************** Function Prototypes ******************************/ +void usleep(ULONG useconds); +void sleep(u32 seconds); +void usleep_R5(ULONG useconds); +void sleep_R5(u32 seconds); +void usleep_MB(ULONG useconds); +void sleep_MB(u32 seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +/*****************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/smc.h new file mode 100644 index 0000000..b4fa9d3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/smc.h @@ -0,0 +1,97 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file smc.h +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 1.00a sdm 11/03/09 Initial release. +* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit +* as smc.c is removed +*+* +* @note None. +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef SMC_H /* prevent circular inclusions */ +#define SMC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory controller configuration register offset */ +#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */ +#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */ +#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */ +#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */ +#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */ +#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */ +#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */ +#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */ +#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */ + +/* Chip select configuration register offset */ +#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */ +#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */ +#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */ +#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */ +#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */ +#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */ +#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */ +#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */ + +/* User configuration register offset */ +#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */ +#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */ + +/* Integration test register offset */ +#define XSMCPSS_IT_OFFSET 0xE00U + +/* ID configuration register offset */ +#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U +#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U +#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U +#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU +#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U +#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U +#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U +#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SMC_H */ + +/** + *@endcond + */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/vectors.h new file mode 100644 index 0000000..f9747c7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/vectors.h @@ -0,0 +1,64 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A9 core. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 1.00a ecm 10/20/10 Initial version, moved over from bsp area +* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors +* 8.0 sk 03/02/22 Update _VECTORS_H_ with VECTORS_H_ to fix misra_c_ +* 2012_rule_21_1 violation. +*+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef VECTORS_H_ +#define VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void FIQInterrupt(void); +void IRQInterrupt(void); +#if !defined (__aarch64__) +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); +void UndefinedException(void); +#else +void SynchronousInterrupt(void); +void SErrorInterrupt(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xadcps.h new file mode 100644 index 0000000..f73ff96 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xadcps.h @@ -0,0 +1,582 @@ +/****************************************************************************** +* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xadcps.h +* @addtogroup Overview +* @{ +* @details +* +* The XAdcPs driver supports the Xilinx XADC/ADC device. +* +* The XADC/ADC device has the following features: +* - 10-bit, 200-KSPS (kilo samples per second) +* Analog-to-Digital Converter (ADC) +* - Monitoring of on-chip supply voltages and temperature +* - 1 dedicated differential analog-input pair and +* 16 auxiliary differential analog-input pairs +* - Automatic alarms based on user defined limits for the on-chip +* supply voltages and temperature +* - Automatic Channel Sequencer, programmable averaging, programmable +* acquisition time for the external inputs, unipolar or differential +* input selection for the external inputs +* - Inbuilt Calibration +* - Optional interrupt request generation +* +* +* The user should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the XADC/ADC device. +* +* +* XADC Channel Sequencer Modes +* +* The XADC Channel Sequencer supports the following operating modes: +* +* - Default : This is the default mode after power up. +* In this mode of operation the XADC operates in +* a sequence mode, monitoring the on chip sensors: +* Temperature, VCCINT, and VCCAUX. +* - One pass through sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers for a single pass and then stops. +* - Continuous cycling of sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers continuously. +* - Single channel mode: In this mode the XADC Channel +* Sequencer is disabled and the XADC operates in a +* Single Channel Mode. +* The XADC can operate either in a Continuous or Event +* driven sampling mode in the single channel mode. +* - Simultaneous Sampling Mode: In this mode the XADC Channel +* Sequencer will automatically sequence through eight fixed pairs +* of auxiliary analog input channels for simulataneous conversion. +* - Independent ADC mode: In this mode the first ADC (A) is used to +* is used to implement a fixed monitoring mode similar to the +* default mode but the alarm fucntions ar eenabled. +* The second ADC (B) is available to be used with external analog +* input channels only. +* +* Read the XADC spec for more information about the sequencer modes. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the XADC/ADC device. +* +* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC +* device. The user needs to first call the XAdcPs_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAdcPs_CfgInitialize() API. +* +* +* Interrupts +* +* The XADC/ADC device supports interrupt driven mode and the default +* operation mode is polling mode. +* +* The interrupt mode is available only if hardware is configured to support +* interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* device in interrupt mode. +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAdcPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* XADC/ADC device can be accessed through the JTAG port and the PLB +* interface. The driver implementation does not support the simultaneous access +* of the device by both these interfaces. The user has to care of this situation +* in the user application code. +* +*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver +* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables +* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs +* in xadcps.c to fix CR #693371 +* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets +* CR#749687 +* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent, +* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode, +* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode +* functions. +* Modified Assert for XAdcPs_SetSingleChParams in +* xadcps.c to fix CR #807563. +* 2.2 bss 04/27/14 Modified to use correct Device Config base address in +* xadcps.c (CR#854437). +* ms 01/23/17 Added xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of xadcps +* examples to recognize it as documentation block +* for doxygen generation. +* 2.3 mn 07/09/18 Fix Doxygen warning +* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors. +* aad 12/17/20 Added missing function declarations and removed +* functions with no definitions. +* 2.7 cog 07/24/23 Added support for SDT flow +* +* +*+* +*****************************************************************************/ +#ifndef XADCPS_H /* Prevent circular inclusions */ +#define XADCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xadcps_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Indexes for the different channels. + * @{ + */ +#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */ +#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */ +#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */ +#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */ +#define XADCPS_CH_VREFP 0x4U /**< VREFP */ +#define XADCPS_CH_VREFN 0x5U /**< VREFN */ +#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */ +#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */ +#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */ +#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */ +#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */ +#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */ +#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */ +#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */ +#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */ + +/*@}*/ + + +/** + * @name Indexes for reading the Calibration Coefficient Data. + * @{ + */ +#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */ +#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */ +#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/ +/*@}*/ + + +/** + * @name Indexes for reading the Minimum/Maximum Measurement Data. + * @{ + */ +#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */ +#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */ +#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */ +#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */ +#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */ +#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */ +#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */ +#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */ +#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */ +#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */ +#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */ +#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */ +#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */ +#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */ + +/*@}*/ + + +/** + * @name Alarm Threshold(Limit) Register (ATR) indexes. + * @{ + */ +#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */ +#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */ +#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */ +#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */ +#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */ + +/*@}*/ + + +/** + * @name Averaging to be done for the channels. + * @{ + */ +#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */ +#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */ +#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */ +#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */ + +/*@}*/ + + +/** + * @name Channel Sequencer Modes of operation + * @{ + */ +#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */ +#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */ +#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */ +#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */ +#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */ +#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */ + +/*@}*/ + + + +/** + * @name Power Down Modes + * @{ + */ +#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */ +#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */ +#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */ +/*@}*/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the XADC/ADC + * device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif + u32 BaseAddress; /**< Device base address */ +} XAdcPs_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every XADC/ADC device in the system. A pointer to + * a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAdcPs_Config Config; /**< XAdcPs_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + +} XAdcPs; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in Event Sampling mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in Event Sampling Mode. +* - FALSE if the device is in Continuous Sampling Mode. +* +* @note C-Style signature: +* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \ + TRUE : FALSE)) + + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in External Mux mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in External Mux Mode. +* - FALSE if the device is NOT in External Mux Mode. +* +* @note C-Style signature: +* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \ + TRUE : FALSE)) + +/****************************************************************************/ +/** +* +* This macro converts XADC Raw Data to Temperature(centigrades). +* +* @param AdcData is the Raw ADC Data from XADC. +* +* @return The Temperature in centigrades. +* +* @note C-Style signature: +* float XAdcPs_RawToTemperature(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToTemperature(AdcData) \ + ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) + +/****************************************************************************/ +/** +* +* This macro converts XADC/ADC Raw Data to Voltage(volts). +* +* @param AdcData is the XADC/ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XAdcPs_RawToVoltage(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToVoltage(AdcData) \ + ((((float)(AdcData))* (3.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts Temperature in centigrades to XADC/ADC Raw Data. +* +* @param Temperature is the Temperature in centigrades to be +* converted to XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_TemperatureToRaw(float Temperature); +* +*****************************************************************************/ +#define XAdcPs_TemperatureToRaw(Temperature) \ + ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) + +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to XADC/ADC Raw Data. +* +* @param Voltage is the Voltage in volts to be converted to +* XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_VoltageToRaw(float Voltage); +* +*****************************************************************************/ +#define XAdcPs_VoltageToRaw(Voltage) \ + ((int)((Voltage)*65536.0f/3.0f)) + + +/****************************************************************************/ +/** +* +* This macro is used for writing to the XADC Registers using the +* command FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* @param Data is the value to be written to XADC register. +* +* @return None. +* +* @note C-Style signature: +* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data); +* +*****************************************************************************/ +#define XAdcPs_WriteFifo(InstancePtr, Data) \ + XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_CMDFIFO_OFFSET, Data); + + +/****************************************************************************/ +/** +* +* This macro is used for reading from the XADC Registers using the +* data FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return Data read from the FIFO +* +* @note C-Style signature: +* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_ReadFifo(InstancePtr) \ + XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_RDFIFO_OFFSET); + + +/************************** Function Prototypes *****************************/ + + + +/** + * Functions in xadcps_sinit.c + */ +#ifndef SDT +XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); +#else +XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress); +#endif + +/** + * Functions in xadcps.c + */ +int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, + XAdcPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data); +u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr); + +u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr); + +void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data); +u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr); + +void XAdcPs_Reset(XAdcPs *InstancePtr); + +u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel); + +u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType); + +u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType); + +void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average); +u8 XAdcPs_GetAvg(XAdcPs *InstancePtr); + +int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, + u8 Channel, + int IncreaseAcqCycles, + int IsEventMode, + int IsDifferentialMode); + + +void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask); +u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration); +u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode); +u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr); + +void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor); +u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask); +u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask); +u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask); +u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask); +u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr); + +void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value); +u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg); + +void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr); +void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode); + +int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr); + +void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel); + +void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode); + +u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_selftest.c + */ +int XAdcPs_SelfTest(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_intr.c + */ +void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask); +void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask); +u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr); + +u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr); +void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask); + + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xadcps_hw.h new file mode 100644 index 0000000..1477617 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xadcps_hw.h @@ -0,0 +1,478 @@ +/****************************************************************************** +* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xadcps_hw.h +* @addtogroup Overview +* @{ +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the XADC device through the Device +* Config Interface of the Zynq. +* +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* +*
+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------------- +* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver +* 1.03a bss 11/01/13 Modified macros to use correct Register offsets +* CR#749687 +* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors. +* +*+* +*****************************************************************************/ +#ifndef XADCPS_HW_H /* Prevent circular inclusions */ +#define XADCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of XADC in the Device Config + * + * The following constants provide access to each of the registers of the + * XADC device. + * @{ + */ + +#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */ +#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */ +#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */ +#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */ +#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */ +#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */ +#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */ + +/* @} */ + + + + + +/** @name XADC Config Register Bit definitions + * @{ + */ +#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */ +#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */ +#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */ +#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */ +#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */ +#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */ +#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between + * successive commands */ +/* @} */ + + +/** @name XADC Interrupt Status/Mask Register Bit definitions + * + * The definitions are same for the Interrupt Status Register and + * Interrupt Mask Register. They are defined only once. + * @{ + */ +#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */ +#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */ +#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */ +#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */ +#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */ +#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */ +#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */ +#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */ +#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */ +#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */ +#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */ +#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */ + +/* @} */ + + +/** @name XADC Miscellaneous Register Bit definitions + * @{ + */ +#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */ +#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */ +#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */ +#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */ +#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */ +#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */ +#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */ +#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */ +/* @} */ + + +/** @name XADC Miscellaneous Control Register Bit definitions + * @{ + */ +#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */ +#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */ +/* @} */ + + +/**@name Internal Register offsets of the XADC + * + * The following constants provide access to each of the internal registers of + * the XADC device. + * @{ + */ + +/* + * XADC Internal Channel Registers + */ +#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */ +#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */ +#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */ +#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */ +#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */ +#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */ +#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */ +#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */ +#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */ +#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */ +#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */ +#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */ +#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */ + +/* + * XADC External Channel Registers + */ +#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */ +#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */ +#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */ +#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */ +#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */ +#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */ +#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */ +#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */ +#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */ +#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */ +#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */ +#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */ +#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */ +#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */ +#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */ +#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */ + +/* + * XADC Registers for Maximum/Minimum data captured for the + * on chip Temperature/VCCINT/VCCAUX data. + */ +#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */ +#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */ +#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */ +#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */ +#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */ +#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */ +#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */ +#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */ +#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */ +#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */ +#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */ +#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */ +#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */ +#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */ + /* Undefined 0x2F to 0x3E */ +#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */ + +/* + * XADC Configuration Registers + */ +#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */ +#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */ +#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */ + +/* Test Registers 0x43 to 0x47 */ + +/* + * XADC Sequence Registers + */ +#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */ +#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */ +#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */ +#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */ +#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */ +#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */ +#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */ +#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */ + +/* + * XADC Alarm Threshold/Limit Registers (ATR) + */ +#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */ +#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */ +#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */ +#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */ +#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */ +#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */ +#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */ +#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */ +#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */ +#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */ + +/* Undefined 0x60 to 0x7F */ + +/*@}*/ + + + +/** + * @name Configuration Register 0 (CFR0) mask(s) + * @{ + */ +#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */ +#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */ +#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */ +#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */ +#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */ +#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */ +#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */ +#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */ +#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */ +#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/ + * Continuous mode selection + */ +#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */ +#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */ + +/*@}*/ + +/** + * @name Configuration Register 1 (CFR1) mask(s) + * @{ + */ +#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */ +#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */ +#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */ +#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */ +#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */ +#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */ +#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */ +#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */ +#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */ +#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */ +#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */ +#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */ +#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */ +#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power + Supply Gain/Offset + Enable */ +#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power + Supply Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain + Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset + Enable */ +#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */ +#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */ +#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */ +#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */ +#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */ +#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */ + +/*@}*/ + +/** + * @name Configuration Register 2 (CFR2) mask(s) + * @{ + */ +#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ----- -------- ----------------------------------------------- +* 1.00 kvn 02/14/15 First release +* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP. +* kvn 08/18/15 Modified Makefile according to compiler changes. +* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile +* for MB BSPs. Instead it throws up a warning. This +* fixes the CR#953056. +* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101. +* +*+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */ +#define XCORESIGHTPSDCC_H /* by using protection macros */ +#ifndef __MICROBLAZE__ +#include
+ * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ----------------------------------------------- + * 1.0 nsk 08/06/15 First Release + * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl + * to support PBD Designs (CR #876857) + * + *+ * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdebug.h new file mode 100644 index 0000000..74bfdb0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdebug.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#ifndef XDEBUG +#define XDEBUG + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_printf.h" + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */ +#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */ +#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */ +#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */ + +#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */ +#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */ +#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */ +#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */ + +#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */ +#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */ +#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */ +#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */ +#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */ + + +#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG) + +#define xdbg_stmnt(x) x + +/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for + * macros that accept variable number of arguments + */ +#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) +#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0) +#else /* ANSI Syntax */ +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) +#endif + +#define xdbg_exception_printf(type, ...) (((type) & xdbg_current_types) ? xil_printf (__VA_ARGS__) : 0) + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) /**< Debug statement */ + +/* See VxWorks comments above */ +#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) +#define xdbg_printf(type, args...) +#else /* ANSI Syntax */ +#define xdbg_printf(...) /**< Debug printf */ +#endif +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#ifdef __cplusplus +} +#endif + +#endif /* XDEBUG */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdevcfg.h new file mode 100644 index 0000000..694e3b3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdevcfg.h @@ -0,0 +1,393 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* @addtogroup devcfg Overview +* @{ +* @details +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for +* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer +* APIs is words (32 bit) and not bytes. +* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs +* to add information that 2 LSBs of the Source/Destination +* address when equal to 2�b01 indicate the last DMA command +* of an overall transfer. +* Destination Address passed to this API for secure transfers +* instead of using 0xFFFFFFFF for CR 662197. This issue was +* resulting in the failure of secure transfers of +* non-bitstream images. +* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly +* set the mask instead of oring it with the +* value read from the interrupt status register +* Added defines for the PS Version bits, +* removed the FIFO Flush bits from the +* Miscellaneous Control Reg. +* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface +* and XDcfg_SelectPcapInterface APIs for CR 643295 +* The user has to call the XDcfg_SelectIcapInterface API +* for the PL reconfiguration using AXI HwIcap. +* Updated the XDcfg_Transfer API to clear the +* QUARTER_PCAP_RATE_EN bit in the control register for +* non secure writes for CR 675543. +* 2.02a nm 01/31/13 Fixed CR# 679335. +* Added Setting and Clearing the internal PCAP loopback. +* Removed code for enabling/disabling AES engine as BootROM +* locks down this setting. +* Fixed CR# 681976. +* Skip Checking the PCFG_INIT in case of non-secure DMA +* loopback. +* Fixed CR# 699558. +* XDcfg_Transfer fails to transfer data in loopback mode. +* Fixed CR# 701348. +* Peripheral test fails with Running +* DcfgSelfTestExample() in SECURE bootmode. +* 2.03a nm 04/19/13 Fixed CR# 703728. +* Updated the register definitions as per the latest TRM +* version UG585 (v1.4) November 16, 2012. +* 3.0 adk 10/12/13 Updated as per the New Tcl API's +* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister +* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function +* updated driver code with != instead of ==, +* while checking for Interrupt Status with DMA and +* PCAP Done Mask +* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, +* XDCFG_INT_STS_OFFSET) & +* XDCFG_IXR_D_P_DONE_MASK) != +* XDCFG_IXR_D_P_DONE_MASK); +* A new example has been added to read back the +* configuration registers from the PL region. +* xdevcfg_reg_readback_example.c +* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in interrupt and polled examples +* to include them in doxygen examples. +* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros +* definitions of devcfg in xparameters.h +* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c +* 3.8 Nava 06/21/23 Added support for system device-tree flow. +*+* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif + u32 BaseAddr; /**< Base address of the device */ +#ifdef SDT + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +#ifndef SDT +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); +#else +XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress); +#endif + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdevcfg_hw.h new file mode 100644 index 0000000..3db7835 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdevcfg_hw.h @@ -0,0 +1,371 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* @addtogroup devcfg Overview +* @{ +* +* This file contains the hardware interface to the Device Config Interface. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a hvm 02/07/11 First release +* 2.01a nm 08/01/12 Added defines for the PS Version bits, +* removed the FIFO Flush bits from the +* Miscellaneous Control Reg +* 2.03a nm 04/19/13 Fixed CR# 703728. +* Updated the register definitions as per the latest TRM +* version UG585 (v1.4) November 16, 2012. +* 2.04a kpc 10/07/13 Added function prototype. +* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value. +* 3.8 Nava 06/21/23 Added support for system device-tree flow. +*+* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 +/**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdmaps.h new file mode 100644 index 0000000..4b98640 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdmaps.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xdmaps.h +* @addtogroup dmaps Overview +* @{ +* @details +* +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ---------------------------------------------- +* 1.00 hbm 08/19/10 First Release +* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies +* the maximum number of channels. +* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV +* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h. +* Added the tcl file to automatically generate the +* xparameters.h +* 1.02a sg 05/16/12 Made changes for doxygen and moved some function +* header from the xdmaps.h file to xdmaps.c file +* Other cleanup for coding guidelines and CR 657109 +* and CR 657898 +* The xdmaps_example_no_intr.c example is removed +* as it is using interrupts and is similar to +* the interrupt example - CR 652477 +* 1.03a sg 07/16/2012 changed inline to __inline for CR665681 +* 1.04a nm 10/22/2012 Fixed CR# 681671. +* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled +* with -Wall and -Wextra option in bsp. +* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg() +* function description. +* Fixed CR# 704396. Removed unused variables +* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg() +* function. +* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc. +* Removed the PDBG prints. By default they were always +* defined out and never used. The PDBG is non-standard for +* Xilinx drivers and no other driver does something similar. +* Since there is no easy way to fix compilation issues with +* the IARCC compiler around PDBG, it is better to remove it. +* Users can always use xil_printfs if they want to debug. +* 2.0 adk 10/12/13 Updated as per the New Tcl API's +* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors +* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid +* linker error for IAR compiler +* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310. +* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline +* to static inline to avoid the linkage conflict for IAR compiler. +* 2.9 aj 11/07/23 Added support for system device tree +*+* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif + u32 BaseAddress; /**< Base address of device (IPIF) */ + +#ifdef SDT + u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); +int XDmaPs_Instr_DMARMB(char *DmaProg); +int XDmaPs_Instr_DMAWMB(char *DmaProg); + +/** + * To avoid linkage error,modify all inline functions from extern + * inline to static inline for IAR compiler + */ +#ifdef __ICCARM__ +static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); +static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); +static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns); +static INLINE int XDmaPs_Instr_DMALD(char *DmaProg); +static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations); +static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); +static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); +static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); +static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber); +static INLINE int XDmaPs_Instr_DMAST(char *DmaProg); +static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize); +static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize); +#endif + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +#ifndef SDT +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); +#else +XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress); +u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress); +#endif + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdmaps_hw.h new file mode 100644 index 0000000..32c2c91 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xdmaps_hw.h @@ -0,0 +1,268 @@ +/****************************************************************************** +* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* @addtogroup dmaps Overview +* @{ +* +* This header file contains the hardware interface of an XDmaPs device. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ---------------------------------------------- +* 1.00a hbm 08/18/10 First Release +* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies +* the maximum number of channels. +* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV +* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h +* 1.02a sg 05/16/12 Made changes for doxygen +* 1.06a kpc 07/10/13 Added function prototype +*+* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps.h new file mode 100644 index 0000000..a7db38d --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps.h @@ -0,0 +1,857 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** + * + * @file xemacps.h +* @addtogroup emacps Overview +* @{ +* @details + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not supported from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + *
+ * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 1.00a wsy 01/10/10 First release + * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file + * xemacps_bdring.c is modified. Earlier it was checking for + * "BdLimit"(passed argument) number of BDs for finding out + * which BDs are successfully processed. Now one more check + * is added. It looks for BDs till the current BD pointer + * reaches HwTail. By doing this processing time is saved. + * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file + * xemacps_bdring.c is modified. Now start of packet is + * searched for returning the number of BDs processed. + * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH + * registers. Added a new API to set the bust length. + * Added some new hash-defines. + * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for + * Rx errors. Under heavy Rx traffic, there will be a large + * number of errors related to receive buffer not available. + * Because of a HW bug (SI #692601), under such heavy errors, + * the Rx data path can become unresponsive. To reduce the + * probabilities for hitting this HW bug, the SW writes to + * bit 18 to flush a packet from Rx DPRAM immediately. The + * changes for it are done in the function + * XEmacPs_IntrHandler. + * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence + * removed. It is expected that all BDs are allocated in + * from uncached area. + * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff + * to 0x1fff. This fixes the CR#744902. + * Made changes in example file xemacps_example.h to fix compilation + * issues with iarcc compiler. + * 2.0 adk 10/12/13 Updated as per the New Tcl API's + * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file. + * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy + * address in xparameters.h when GMII to RGMII converter + * is present in hw. + * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit + * changes. + * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with + * 1000BASE-X mode export proper values to the xparameters.h + * file. Changes are made in the driver tcl file. + * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is + * configured with PCS/PMA Core. Changes are made in the + * test app tcl(CR:827686). + * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. + * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst. + * Disable extended mode. Perform all 64 bit changes under + * check for arch64. + * Remove "used bit set" from TX error interrupt masks. + * 3.1 hk 07/27/15 Do not call error handler with '0' error code when + * there is no error. CR# 869403 + * 08/10/15 Update upper 32 bit tx and rx queue ptr registers. + * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC. + * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all + * examples to ensure that "Successfully ran" and "Failed" + * strings are available in all examples. This is a fix + * for CR-965028. + * ms 03/17/17 Modified text file in examples folder for doxygen + * generation. + * ms 04/05/17 Added tabspace for return statements in functions of + * xemacps_ieee1588_example.c for proper documentation + * while generating doxygen. + * 3.5 hk 08/14/17 Update cache coherency information of the interface in + * its config structure. + * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is + * changed to volatile. + * Add API XEmacPs_BdRingPtrReset() to reset pointers + * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327 + * hk 09/17/18 Fix PTP interrupt masks and cleanup comments. + * 3.9 hk 01/23/19 Add RX watermark support + * 3.11 sd 02/14/20 Add clock support + * 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names. + * + *+ * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U +#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * parameter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { +#ifdef SDT + char *Name; /**< Unique name of the device */ +#else + u16 DeviceId; /**< Unique ID of device */ +#endif + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ +#ifdef SDT + u16 IntrId; + UINTPTR IntrParent; +#endif +#if defined (XCLOCKING) + u32 RefClk; /**< Input clock */ +#endif + u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */ + u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */ + u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */ + u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */ + u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */ + u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/****************************************************************************/ +/** +* +* This macro sets RX watermark register. +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* @param High is the non-zero RX high watermark value. When SRAM fill level +* is above this, a pause frame will be sent. +* @param Low is the non-zero RX low watermark value. When SRAM fill level +* is below this, a zero length pause frame will be sent IF the last +* pause frame sent was non-zero. +* +* @return None +* +* @note +* +* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High, +* u16 Low) +* +*****************************************************************************/ +#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_RXWATERMARK_OFFSET, \ + (High & XEMACPS_RXWM_HIGH_MASK) | \ + ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |) + +/****************************************************************************/ +/** +* +* This macro gets RX watermark register. +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return RX watermark register value +* +* @note +* +* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRXWatermark(InstancePtr) \ + XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_RXWATERMARK_OFFSET) +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ + +#ifndef SDT +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); +#else +XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress); +#endif + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps_bd.h new file mode 100644 index 0000000..264dfb7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps_bd.h @@ -0,0 +1,763 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h +* @addtogroup emacps Overview +* @{ + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + *
+ * MODIFICATION HISTORY: + * + * Ver Who Date Changes + * ----- ---- -------- ------------------------------------------------------- + * 1.00a wsy 01/10/10 First release + * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification + * and 64-bit changes. + * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. + * 3.0 hk 02/20/15 Added support for jumbo frames. + * Disable extended mode. Perform all 64 bit changes under + * check for arch64. + * 3.2 hk 11/18/15 Change BD typedef and number of words. + * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength + * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform. + * + *+ * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a wsy 01/10/10 First release +* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. +* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is +* changed to volatile. +* +*+* +******************************************************************************/ + +#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ +#define XEMACPS_BDRING_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/**************************** Type Definitions *******************************/ + +/** This is an internal structure used to maintain the DMA list */ +typedef struct { + UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */ + UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */ + UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */ + u32 Length; /**< Total size of ring in bytes */ + u32 RunState; /**< Flag to indicate DMA is started */ + u32 Separation; /**< Number of bytes between the starting address + of adjacent BDs */ + XEmacPs_Bd *FreeHead; + /**< First BD in the free group */ + XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ + XEmacPs_Bd *HwHead; /**< First BD in the work group */ + XEmacPs_Bd *HwTail; /**< Last BD in the work group */ + XEmacPs_Bd *PostHead; + /**< First BD in the post-work group */ + XEmacPs_Bd *BdaRestart; + /**< BDA to load when channel is started */ + + volatile u32 HwCnt; /**< Number of BDs in work group */ + u32 PreCnt; /**< Number of BDs in pre-work group */ + u32 FreeCnt; /**< Number of allocatable BDs in the free group */ + u32 PostCnt; /**< Number of BDs in post-work group */ + u32 AllCnt; /**< Total Number of BDs for channel */ +} XEmacPs_BdRing; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many BDs will fit +* in a BD list within the given memory constraints. +* +* The results of this macro can be provided to XEmacPs_BdRingCreate(). +* +* @param Alignment specifies what byte alignment the BDs must fall on and +* must be a power of 2 to get an accurate calculation (32, 64, 128,...) +* @param Bytes is the number of bytes to be used to store BDs. +* +* @return Number of BDs that can fit in the given memory area +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) +* +******************************************************************************/ +#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ + (u32)((Bytes) / (sizeof(XEmacPs_Bd))) + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many bytes of memory +* is required to contain a given number of BDs at a given alignment. +* +* @param Alignment specifies what byte alignment the BDs must fall on. This +* parameter must be a power of 2 to get an accurate calculation (32, 64, +* 128,...) +* @param NumBd is the number of BDs to calculate memory size requirements for +* +* @return The number of bytes of memory required to create a BD list with the +* given memory constraints. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) +* +******************************************************************************/ +#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ + (u32)(sizeof(XEmacPs_Bd) * (NumBd)) + +/****************************************************************************/ +/** +* Return the total number of BDs allocated by this channel with +* XEmacPs_BdRingCreate(). +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The total number of BDs allocated for this channel. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) + +/****************************************************************************/ +/** +* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- +* processing. +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The number of BDs currently allocatable. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) + +/****************************************************************************/ +/** +* Return the next BD from BdPtr in a list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on. +* +* @return The next BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ + (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \ + (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \ + (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation)) + +/****************************************************************************/ +/** +* Return the previous BD from BdPtr in the list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on +* +* @return The previous BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ + (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ + (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ + (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation)) + +/************************** Function Prototypes ******************************/ + +/* + * Scatter gather DMA related functions in xemacps_bdring.c + */ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount); +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction); +LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); + +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc); + +#ifdef __cplusplus +} +#endif + + +#endif /* end of protection macros */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps_hw.h new file mode 100644 index 0000000..765411d --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xemacps_hw.h @@ -0,0 +1,664 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xemacps_hw.h +* @addtogroup emacps Overview +* @{ +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. +* High-level driver functions are defined in xemacps.h. +* +* @note +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a wsy 01/10/10 First release. +* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration. +* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype +* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff +* to 0x1fff. This fixes the CR#744902. +* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification. +* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to +* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters. +* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values. +* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.0 hk 03/18/15 Added support for jumbo frames. +* Remove "used bit set" from TX error interrupt masks. +* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets. +* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC. +* 3.8 hk 09/17/18 Fix PTP interrupt masks. +* 3.9 hk 01/23/19 Add RX watermark support +* 3.10 hk 05/16/19 Clear status registers properly in reset +* 3.18 sne 01/11/23 Add PCS control and status registers information. +*+* +******************************************************************************/ + +#ifndef XEMACPS_HW_H /* prevent circular inclusions */ +#define XEMACPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address + supported */ +#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */ + +#ifdef __aarch64__ +#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment + on the local bus */ +#else + +#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment + on the local bus */ +#endif +#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using + options that impose alignment + restrictions on the buffer data on + the local bus */ + +/** @name Direction identifiers + * + * These are used by several functions and callbacks that need + * to specify whether an operation specifies a send or receive channel. + * @{ + */ +#define XEMACPS_SEND 1U /**< send direction */ +#define XEMACPS_RECV 2U /**< receive direction */ +/*@}*/ + +/** @name MDC clock division + * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. + * @{ + */ +typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, + MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 +} XEmacPs_MdcDiv; + +/*@}*/ + +#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in + bytes, 64, 128, ... 10240 */ +#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U + +#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a + unit, this is HW setup */ + +#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */ +#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */ + +#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */ + +/* Register offset definitions. Unless otherwise noted, register access is + * 32 bit. Names are self explained here. + */ + +#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */ +#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */ +#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */ + +#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */ +#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */ +#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */ +#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */ +#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */ + +#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */ +#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */ +#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */ +#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */ + +#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */ +#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */ +#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */ + +#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */ + +#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */ + +#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */ +#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */ + +#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */ +#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */ +#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */ +#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */ +#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */ +#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */ +#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */ +#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */ + +#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */ +#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */ +#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */ +#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */ + +#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */ + +#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low + reg */ +#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High + reg */ + +#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes + transmitted counter */ +#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast + Frames counter*/ +#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast + Frame counter */ +#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted + Counter */ +#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames + Transmitted counter */ +#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte + Frames Transmitted + counter */ +#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte + Frames Transmitted + counter*/ +#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte + Frames transmitted + counter */ +#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte + Frames transmitted + counter */ +#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte + Frames transmitted + counter */ +#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than + 1519 byte Frames + transmitted counter */ +#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error + counter */ + +#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame + Counter */ +#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame + Counter */ +#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame + Counter */ +#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame + Counter */ +#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission + Frame Counter */ +#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense + Error Counter */ + +#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register + Low */ +#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register + High */ + +#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames + Received Counter */ +#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast + Frames Received Counter */ +#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast + Frames Received Counter */ +#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames + Received Counter */ +#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames + Received Counter */ +#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte + Frames Received Counter */ +#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte + Frames Received Counter */ +#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte + Frames Received Counter */ +#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte + Frames Received Counter */ +#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte + Frames Received Counter */ +#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte + Frames Received Counter */ +#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received + Counter */ +#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received + Counter */ +#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received + Counter */ +#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence + Error Counter */ +#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error + Counter */ +#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */ +#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */ +#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error + Counter */ +#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */ +#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error + Counter */ +#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error + Counter */ +#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error + Counter */ +#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter + offset, for clearing */ + +#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */ +#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */ +#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond + adjustment counter */ +#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond + increment counter */ +#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second + counter */ +#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit + nanosecond counter */ +#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second + counter */ +#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive + nanosecond counter */ +#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit + second counter */ +#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit + nanosecond counter */ +#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive + second counter */ +#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive + nanosecond counter */ +#define XEMACPS_PCS_CONTROL_OFFSET 0x00000200U /** PCS control register */ +#define XEMACPS_PCS_STATUS_OFFSET 0x00000204U /** PCS status register */ + +#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status + reg */ +#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address + reg */ +#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address + reg */ +#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base + reg */ +#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base + reg */ +#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable + reg */ +#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable + reg */ +#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask + reg */ + +/* Define some bit positions for registers. */ + +/** @name network control register bit definitions + * @{ + */ +#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from + Rx SRAM */ +#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum + pause frame */ +#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */ +#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission + after current frame */ +#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */ + +#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to + stat counters */ +#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic + registers */ +#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic + registers */ +#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */ +#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */ +#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */ +#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */ +/*@}*/ + +/** @name network configuration register bit definitions + * @{ + */ +#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of + non-standard preamble */ +#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */ +#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */ +#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of + FCS error */ +#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */ +#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum + offload */ +#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause + Frames to memory */ +#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */ +#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */ +#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */ +#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from + received frames */ +#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U +/**< RX length error discard */ +#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */ +#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */ +#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */ +#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U +/**< External address match enable */ +#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */ +#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */ +#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte + frames reception */ +#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash + frames */ +#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash + frames */ +#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive + broadcast frames */ +#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */ +#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */ +#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN + frames */ +#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */ +#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */ +#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */ +/*@}*/ + +/** @name network status register bit definitaions + * @{ + */ +#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */ +#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */ +/*@}*/ + + +/** @name MAC address register word 1 mask + * @{ + */ +#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32] + bit[31:0] are in BOTTOM */ +/*@}*/ + + +/** @name DMA control register bit definitions + * @{ + */ +#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */ +#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */ +#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */ +#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer + size */ +#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer + size */ +#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX + checksum offload */ +#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */ +#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */ +#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */ +#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */ +#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */ +#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */ +/*@}*/ + +/** @name transmit status register bit definitions + * @{ + */ +#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */ +#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */ +#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */ +#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted + mid frame */ +#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */ +#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */ +#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */ +#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */ + +#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_TXSR_URUN_MASK | \ + (u32)XEMACPS_TXSR_BUFEXH_MASK | \ + (u32)XEMACPS_TXSR_RXOVR_MASK | \ + (u32)XEMACPS_TXSR_FRAMERX_MASK | \ + (u32)XEMACPS_TXSR_USEDREAD_MASK) +/*@}*/ + +/** + * @name receive status register bit definitions + * @{ + */ +#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */ +#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */ +#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */ +#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */ + +#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_RXSR_RXOVR_MASK | \ + (u32)XEMACPS_RXSR_BUFFNA_MASK) + +#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */ + +/*@}*/ + +/** + * @name PCS control register bit definitions + * @{ + */ +#define XEMACPS_PCS_CON_AUTO_NEG_MASK 0x00001000U /**< Auto-negotiation */ +/*@}*/ + +/** + * @name PCS status register bit definitions + * @{ + */ +#define XEMACPS_PCS_STATUS_LINK_STATUS_MASK 0x00000004U /**< Link status */ +/*@}*/ + +/** + * @name Interrupt Q1 status register bit definitions + * @{ + */ +#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */ +#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */ + +#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \ + (u32)XEMACPS_INTQ1SR_TXERR_MASK) + +/*@}*/ + +/** + * @name interrupts bit definitions + * Bits definitions are same in XEMACPS_ISR_OFFSET, + * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET + * @{ + */ +#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */ +#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */ +#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */ +#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */ + +#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */ +#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */ +#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */ +#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */ + +#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */ +#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached + zero */ +#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */ +#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */ +#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */ +#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */ +#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or + no buffers*/ +#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */ +#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */ +#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */ +#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */ +#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */ +#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */ +#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */ + +#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \ + (u32)XEMACPS_IXR_RETRY_MASK | \ + (u32)XEMACPS_IXR_URUN_MASK) + + +#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \ + (u32)XEMACPS_IXR_RXUSED_MASK | \ + (u32)XEMACPS_IXR_RXOVR_MASK) + +/*@}*/ + +/** @name PHY Maintenance bit definitions + * @{ + */ +#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */ +#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */ +#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */ +#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */ +#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */ +#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */ +#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */ +#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */ +/*@}*/ + +/** @name RX watermark bit definitions + * @{ + */ +#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */ +#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */ +#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */ +/*@}*/ + +/* Transmit buffer descriptor status words offset + * @{ + */ +#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */ +#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */ +#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */ + +/* + * @} + */ + +/* Transmit buffer descriptor status words bit positions. + * Transmit buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit address pointing to the location of + * the transmit data. + * The following register - word1, consists of various information to control + * the XEmacPs transmit process. After transmit, this is updated with status + * information, whether the frame was transmitted OK or why it had failed. + * @{ + */ +#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */ +#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */ +#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */ +#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */ +#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */ +#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */ +#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */ +#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */ +#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */ +/* + * @} + */ + +/* Receive buffer descriptor status words bit positions. + * Receive buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit word aligned address pointing to the + * address of the buffer. The lower two bits make up the wrap bit indicating + * the last descriptor and the ownership bit to indicate it has been used by + * the XEmacPs. + * The following register - word1, contains status information regarding why + * the frame was received (the filter match condition) as well as other + * useful info. + * @{ + */ +#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */ +#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */ +#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */ +#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */ +#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address + matched */ +#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */ +#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */ +#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */ +#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */ +#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */ +#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */ +#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */ +#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */ +#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */ +#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */ + +#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */ +#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */ +#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */ +/* + * @} + */ + +/* + * Define appropriate I/O access method to memory mapped I/O or other + * interface if necessary. + */ + +#define XEmacPs_In32 Xil_In32 +#define XEmacPs_Out32 Xil_Out32 + + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ + XEmacPs_In32((BaseAddress) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ + XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the emacps interface + */ +void XEmacPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus + } +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xenv.h new file mode 100644 index 0000000..d8aef59 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xenv.h @@ -0,0 +1,169 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00b ch 10/24/02 Added XENV_LINUX +* 1.00a rmm 04/17/02 First release +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + +/** + *@endcond + */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xenv_standalone.h new file mode 100644 index 0000000..9794da0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xenv_standalone.h @@ -0,0 +1,350 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a wgr 02/28/07 Added cache handling macros. +* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. +* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being +* used under Xilinx standalone BSP. +* 1.00a xd 11/03/04 Improved support for doxygen. +* 1.00a rmm 03/21/02 First release +* 1.00a wgr 03/22/07 Converted to new coding style. +* 1.00a rpm 06/29/07 Added udelay macro for standalone +* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred +* to in MICROBLAZE section +* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality +* +*+* +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a sv 01/15/10 First Release +* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin +* XGpioPs_GetMode, XGpioPs_GetModePin as they are not +* relevant to Zynq device.The interrupts are disabled +* for output pins on all banks during initialization. +* 1.02a hk 08/22/13 Added low level reset API +* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667. +* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number +* passed to APIs. CR# 822636 +* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Added tabspace for return statements in functions of +* gpiops examples for proper documentation while +* generating doxygen. +* 3.3 ms 04/17/17 Added notes about gpio input and output pin description +* for zcu102 and zc702 boards in polled and interrupt +* example, configured Interrupt pin to input pin for +* proper functioning of interrupt example. +* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751 +* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012 +* in safety mode and modified the code such as +* Use of mixed mode arithmetic,Declared the pointer param +* as Pointer to const,Casting operation to a pointer, +* Literal value requires a U suffix. +* 3.5 sne 03/14/19 Added Versal support. +* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in +* sync with standalone BSP +* 3.6 sne 06/12/19 Fixed IAR compiler warning. +* 3.6 sne 08/14/19 Added interrupt handler support on versal. +* 3.7 sne 12/04/19 Reverted versal examples support. +* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution. +* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins. +* 3.9 sne 03/15/21 Fixed MISRA-C violations. +* 3.11 sg 02/23/23 Update bank and pin mapping information. +* 3.12 gm 07/11/23 Added SDT support. +* +*+* +******************************************************************************/ +#ifndef XGPIOPS_H /* prevent circular inclusions */ +#define XGPIOPS_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xgpiops_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types + * @{ + * The following constants define the interrupt types that can be set for each + * GPIO pin. + */ +#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */ +#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */ +#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */ +/** @}*/ + +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ +#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */ +#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */ +#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */ +#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */ +#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */ +#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */ + +#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a + * Zynq Ultrascale+ MP GPIO device + */ +#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the + * Zynq Ultrascale+ MP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + +/**************************** Type Definitions *******************************/ + +/****************************************************************************/ +/** + * This handler data type allows the user to define a callback function to + * handle the interrupts for the GPIO device. The application using this + * driver is expected to define a handler of this type, to support interrupt + * driven mode. The handler executes in an interrupt context such that minimal + * processing should be performed. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions for a GPIO bank. It is + * passed back to the upper layer when the callback is invoked. Its + * type is not important to the driver component, so it is a void + * pointer. + * @param Bank is the bank for which the interrupt status has changed. + * @param Status is the Interrupt status of the GPIO bank. + * + *****************************************************************************/ +typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif + UINTPTR BaseAddr; /**< Register base address */ +#ifdef SDT + u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif +} XGpioPs_Config; + +/** + * The XGpioPs driver instance data. The user is required to allocate a + * variable of this type for the GPIO device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XGpioPs_Config GpioConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + XGpioPs_Handler Handler; /**< Status handlers for all banks */ + void *CallBackRef; /**< Callback ref for bank handlers */ + u32 Platform; /**< Platform data */ + u32 MaxPinNum; /**< Max pins in the GPIO device */ + u8 MaxBanks; /**< Max banks in a GPIO device */ + u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/ +} XGpioPs; + +/************************** Variable Definitions *****************************/ +extern XGpioPs_Config XGpioPs_ConfigTable[]; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* Functions in xgpiops.c */ +s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr); + +/* Bank APIs in xgpiops.c */ +u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data); +void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction); +u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable); +u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank); +#ifdef versal +void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank); +#else +void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank); +#endif + +/* Pin APIs in xgpiops.c */ +u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data); +void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction); +u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable); +u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin); + +/* Diagnostic functions in xgpiops_selftest.c */ +s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr); + +/* Functions in xgpiops_intr.c */ +/* Bank APIs in xgpiops_intr.c */ +void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank); +u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny); +void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny); +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPointer); +void XGpioPs_IntrHandler(const XGpioPs *InstancePtr); + +/* Pin APIs in xgpiops_intr.c */ +void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType); +u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin); + +void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin); + +/* Functions in xgpiops_sinit.c */ +#ifndef SDT +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); +#else +XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xgpiops_hw.h new file mode 100644 index 0000000..3248dc2 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xgpiops_hw.h @@ -0,0 +1,147 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.h +* @addtogroup gpiops Overview +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xgpiops.h. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------- +* 1.00a sv 01/15/10 First Release +* 1.02a hk 08/22/13 Added low level reset API function prototype and +* related constant definitions +* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/13/15 Corrected reset values of banks. +* 3.5 sne 03/14/19 Added versal support. +*+* +******************************************************************************/ +#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ +#define XGPIOPS_HW_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the GPIO. Each register is 32 bits. + * @{ + */ +#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */ +#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */ +#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */ +#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */ +#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */ +#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */ +#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */ +#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */ +#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/ +#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */ +#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */ +#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */ +#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */ +/** @} */ + +/** @name Register offsets for each Bank. + * @{ + */ +#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */ +#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */ +#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */ +/** @} */ + +/* For backwards compatibility */ +#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */ + +/** @name Interrupt type reset values for each bank + * @{ + */ +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */ +#else +#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */ +#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */ +#endif + +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */ +#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */ +/** @} */ +#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */ +#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */ +#define XGPIOPS_ONE 1U /**< Flag for 1 Value */ +#define XGPIOPS_TWO 2U /**< Flag for 2 Value */ +#define XGPIOPS_THREE 3U /**< Flag for 3 Value */ +#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */ +#define XGPIOPS_SIX 6U /**< Flag for 6 Value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes to the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the offset of the register to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ + +void XGpioPs_ResetHw(UINTPTR BaseAddress); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XGPIOPS_HW_H */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_assert.h new file mode 100644 index 0000000..e8b87b5 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_assert.h @@ -0,0 +1,176 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* @addtogroup common_assert_apis Assert APIs and Macros +* +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern s32 Xil_AssertWait; +extern void Xil_Assert(const char8 *File, s32 Line); +/** + *@endcond + */ +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accommodate tests so that asserts which fail allow execution to +* continue. +* +* @param Expression: expression to be evaluated. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accommodate tests so that asserts which fail allow execution +* to continue. +* +* @param Expression: expression to be evaluated. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache.h new file mode 100644 index 0000000..7c94568 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache.h @@ -0,0 +1,107 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a ecm 01/29/10 First release +* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance +* APIs. +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* 9.0 ml 03/03/23 Updated function prototypes. +*+* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __GNUC__ + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#elif defined (__ICCARM__) + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#endif + +/** +*@endcond +*/ + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache_l.h new file mode 100644 index 0000000..21c8ced --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache_l.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache_l.h +* +* Contains L1 and L2 specific functions for the ARM cache functionality +* used by xcache.c. This functionality is being made available here for +* more sophisticated users. +* +* @addtogroup a9_cache_apis +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a ecm 01/24/10 First release +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +*+* +******************************************************************************/ +#ifndef XIL_CACHE_MACH_H +#define XIL_CACHE_MACH_H + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_DCacheInvalidateLine(u32 adr); +void Xil_DCacheFlushLine(u32 adr); +void Xil_DCacheStoreLine(u32 adr); +void Xil_ICacheInvalidateLine(u32 adr); + +void Xil_L1DCacheEnable(void); +void Xil_L1DCacheDisable(void); +void Xil_L1DCacheInvalidate(void); +void Xil_L1DCacheInvalidateLine(u32 adr); +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len); +void Xil_L1DCacheFlush(void); +void Xil_L1DCacheFlushLine(u32 adr); +void Xil_L1DCacheFlushRange(u32 adr, u32 len); +void Xil_L1DCacheStoreLine(u32 adr); + +void Xil_L1ICacheEnable(void); +void Xil_L1ICacheDisable(void); +void Xil_L1ICacheInvalidate(void); +void Xil_L1ICacheInvalidateLine(u32 adr); +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len); + +void Xil_L2CacheEnable(void); +void Xil_L2CacheDisable(void); +void Xil_L2CacheInvalidate(void); +void Xil_L2CacheInvalidateLine(u32 adr); +void Xil_L2CacheInvalidateRange(u32 adr, u32 len); +void Xil_L2CacheFlush(void); +void Xil_L2CacheFlushLine(u32 adr); +void Xil_L2CacheFlushRange(u32 adr, u32 len); +void Xil_L2CacheStoreLine(u32 adr); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache_vxworks.h new file mode 100644 index 0000000..64079e7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cache_vxworks.h @@ -0,0 +1,75 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 12/11/09 Initial release +* +*+* +* @note +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif +/** + *@endcond + */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_clocking.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_clocking.h new file mode 100644 index 0000000..d40a6f7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_clocking.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.h +* +* The xil_clocking.h file contains clocking related functions and macros. +* certain conditions. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 7.2 sd 12/11/19 First release +* 7.2 sd 03/20/20 Added checking for isolation case +* 7.7 sk 01/10/22 Add function prototype for Xil_ClockGetRate to fix +* misra_c_2012_rule_8_4 violation. +* 9.0 ml 03/03/23 Added description to fix doxygen warnings. +*+* +******************************************************************************/ + +#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */ +#define XIL_CLOCKING_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xdebug.h" +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xparameters.h" +#include "xstatus.h" +#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR) +#include "xclockps.h" +#else +typedef u32 XClock_OutputClks; +typedef u64 XClockRate; +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + + +XStatus Xil_ClockDisable(XClock_OutputClks ClockId); +XStatus Xil_ClockEnable(XClock_OutputClks ClockId); +XStatus Xil_ClockInit(void); +XStatus Xil_ClockGet(void); +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate); +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cryptoalginfo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cryptoalginfo.h new file mode 100644 index 0000000..df95b88 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_cryptoalginfo.h @@ -0,0 +1,50 @@ +/******************************************************************************/ +/** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_cryptoalginfo.h +* @{ +* @details +* +* Crypto algotithm information structure declaration. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 9.0 mmd 07/04/23 First release. +*+* +*****************************************************************************/ +#ifndef XIL_CRYPTOALGINFO_H +#define XIL_CRYPTOALGINFO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/**************************** Type Definitions *******************************/ +typedef enum _Xil_CryptoAlgNistStatus { + NOT_APPLICABLE = 0x00, + NIST_COMPLIANT = 0x11, + NIST_NON_COMPLIANT = 0xFE, +} Xil_CryptoAlgNistStatus; + +typedef struct _Xil_CryptoAlgInfo { + u32 Version; + Xil_CryptoAlgNistStatus NistStatus; +} Xil_CryptoAlgInfo; + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_CRYPTOALGINFO_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_errata.h new file mode 100644 index 0000000..5923f44 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_errata.h @@ -0,0 +1,101 @@ +/****************************************************************************** +* Copyright (c) 2013 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_errata.h +* +* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support +* @{ +* Various ARM errata are handled in the standalone BSP. The implementation for +* errata handling follows ARM guidelines and is based on the open source Linux +* support for these errata. +* +* @note The errata handling is enabled by default. To disable handling of all the +* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To +* disable errata on a per-erratum basis, un-define relevant macros in +* xil_errata.h. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a srt 04/18/13 First release +* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132 +* 7.7 asa 01/06/22 Removed errata 742230 and 743622. These are +* already fixed in Cortex-A9 r3p0, the revision +* that is being used in Zynq platforms. +*+* +******************************************************************************/ +#ifndef XIL_ERRATA_H +#define XIL_ERRATA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + *@cond nocomments + */ +/** + * @name errata_definitions + * + * The errata conditions handled in the standalone BSP are listed below + * @{ + */ + +#define ENABLE_ARM_ERRATA 1 + +/** + *@endcond + */ + +#ifdef ENABLE_ARM_ERRATA + +/** + * Errata No: 775420 + * Description: A data cache maintenance operation which aborts, + * might lead to deadlock + */ +#define CONFIG_ARM_ERRATA_775420 1 + +/** + * Errata No: 794073 + * Description: Speculative instruction fetches with MMU disabled + * might not comply with architectural requirements + */ +#define CONFIG_ARM_ERRATA_794073 1 + + +/** PL310 L2 Cache Errata */ + +/** + * Errata No: 588369 + * Description: Clean & Invalidate maintenance operations do not + * invalidate clean lines + */ +#define CONFIG_PL310_ERRATA_588369 1 + +/** + * Errata No: 727915 + * Description: Background Clean and Invalidate by Way operation + * can cause data corruption + */ +#define CONFIG_PL310_ERRATA_727915 1 + +/*@}*/ +#endif /* ENABLE_ARM_ERRATA */ + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_ERRATA_H */ +/** +* @} End of "addtogroup a9_errata". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_exception.h new file mode 100644 index 0000000..b517983 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_exception.h @@ -0,0 +1,532 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.2 pkp 28/05/15 First release +* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors +* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler. +* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler. +* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and +* Xil_ExceptionDisableMask macros to support legacy +* examples for Cortexa72 EL3 exception level. +* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and +* Xil_DisableNestedInterrupts macros for ARMv8. +* For Cortexa72, these macro's would not be supported +* at EL3, as Cortexa72 is using GIC-500(GICv3), which +* triggeres only FIQ at EL3. Fix for CR#1062506 +* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with +* -Wundef compiler option CR#1110261 +* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated +* in different way based on "versal" flag. In existing +* flow, this flag is defined only in xparameters.h and +* BSP compiler flags, it is not defined in application +* compiler flags. So, including xil_exception.h in +* application source file, without including +* xparameters.h results in incorrect behavior. +* Including xparameters.h in xil_exception.h to avoid +* such issues. It fixes CR#1120498. +* 8.0 mus 02/24/22 Updated few macros to support legacy driver examples +* for CortexR52. This is needed, as by default scugic +* driver configures interrupts as group0 and CortexR52 +* GIC triggers FIQ for group0 interrupts. +* 8.0 sk 03/02/22 Define XExc_VectorTableEntry structure to fix +* misra_c_2012_rule_5_6 violation. +* 8.0 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_ +* rule_8_4 violation. +* 8.1 asa 02/12/23 Updated data abort and prefetch abort fault +* status reporting for ARMv7. +* Updated Sync and SError fault status reporting +* for ARMv8. +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#include "xdebug.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +#ifdef DEBUG + +#if defined (__aarch64__) +#define ARMV8_SYNC_ERROR 0x01U +#define ARMV8_SERROR 0x02U + +#define ARMV8_FAR_VALUE_VALID 0x01U + +#define ARMV8_ESR_EC_SHIFT 26U +#define ARMV8_ESR_EC_MASK ((0x3FU) << ARMV8_ESR_EC_SHIFT) +#define ARMV8_EXTRACT_ESR_EC(Val) \ + (((Val) & ARMV8_ESR_EC_MASK) >> ARMV8_ESR_EC_SHIFT) + +#define ARMV8_ESR_IL_SHIFT (25U) +#define ARMV8_ESR_IL_MASK ((1U) << ARMV8_ESR_IL_SHIFT) +#define ARMV8_EXTRACT_ESR_IL(Val) \ + (((Val) & ARMV8_ESR_IL_MASK) >> ARMV8_ESR_IL_SHIFT) + +#define ARMV8_ESR_ISS_MASK (ARMV8_ESR_IL_MASK - 1U) +#define ARMV8_EXTRACT_ESR_ISS(Val) ((Val) & ARMV8_ESR_ISS_MASK) + + +#define ARMV8_ESR_EC_UNKNOWN_ERR 0x00U +#define ARMV8_ESR_EC_FP_ASIMD 0x07U +#define ARMV8_ESR_ILL_EXECUTION_STATE 0x0EU +#define ARMV8_ESR_EC_DATA_ABORT_LOWER 0x24U +#define ARMV8_ESR_EC_DATA_ABORT 0x25U +#define ARMV8_ESR_EC_INS_ABORT_LOWER 0x20U +#define ARMV8_ESR_EC_INS_ABORT 0x21U +#define ARMV8_ESR_EC_PC_ALIGNMENT_FAULT 0x22U +#define ARMV8_ESR_EC_SP_ALIGNMENT_FAULT 0x26U +#define ARMV8_ESR_EC_SERROR 0x2FU + + +/* ISS field definitions shared by different classes */ +#define ARMV8_ESR_ISS_WNR_SHIFT (6U) +#define ARMV8_ESR_ISS_WNR_MASK ((1U) << ARMV8_ESR_ISS_WNR_SHIFT) + +/* Asynchronous Error Type */ + +#define ARMV8_ESR_ISS_AET_SHIFT (10U) +#define ARMV8_ESR_ISS_AET_MASK ((0x7U) << ARMV8_ESR_ISS_AET_SHIFT) +#define ARMV8_ESR_ISS_AET_UC ((0U) << ARMV8_ESR_ISS_AET_SHIFT) +#define ARMV8_ESR_ISS_AET_UEU ((1U) << ARMV8_ESR_ISS_AET_SHIFT) +#define ARMV8_ESR_ISS_AET_UEO ((2U) << ARMV8_ESR_ISS_AET_SHIFT) +#define ARMV8_ESR_ISS_AET_UER ((3U) << ARMV8_ESR_ISS_AET_SHIFT) +#define ARMV8_ESR_ISS_AET_CE ((6U) << ARMV8_ESR_ISS_AET_SHIFT) + + +/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ +#define ARMV8_ESR_ISS_FSC (0x3FU) +#define ARMV8_ESR_ISS_CM_SHIFT (8U) +#define ARMV8_ESR_ISS_CM_MASK ((1U) << ARMV8_ESR_ISS_CM_SHIFT) + +#define ARMV8_LEVEL_0_ADDR_FAULT 0x00U +#define ARMV8_LEVEL_1_ADDR_FAULT 0x01U +#define ARMV8_LEVEL_2_ADDR_FAULT 0x02U +#define ARMV8_LEVEL_3_ADDR_FAULT 0x03U +#define ARMV8_LEVEL_0_TRANS_FAULT 0x04U +#define ARMV8_LEVEL_1_TRANS_FAULT 0x05U +#define ARMV8_LEVEL_2_TRANS_FAULT 0x06U +#define ARMV8_LEVEL_3_TRANS_FAULT 0x07U +#define ARMV8_LEVEL_0_ACCS_FLAG_FAULT 0x08U +#define ARMV8_LEVEL_1_ACCS_FLAG_FAULT 0x09U +#define ARMV8_LEVEL_2_ACCS_FLAG_FAULT 0x0AU +#define ARMV8_LEVEL_3_ACCS_FLAG_FAULT 0x0BU +#define ARMV8_LEVEL_0_PERMISSION_FAULT 0x0CU +#define ARMV8_LEVEL_1_PERMISSION_FAULT 0x0DU +#define ARMV8_LEVEL_2_PERMISSION_FAULT 0x0EU +#define ARMV8_LEVEL_3_PERMISSION_FAULT 0x0FU + +#define ARMV8_SYNC_EXT_ABORT_NOT_ON_TTW 0x10U +#define ARMV8_LEVEL_0_SYNC_EXT_ABORT 0x14U +#define ARMV8_LEVEL_1_SYNC_EXT_ABORT 0x15U +#define ARMV8_LEVEL_2_SYNC_EXT_ABORT 0x16U +#define ARMV8_LEVEL_3_SYNC_EXT_ABORT 0x17U + +#define ARMV8_SYNC_PAR_OR_ECC_ERROR_NOT_ON_TTW 0x18U +#define ARMV8_LEVEL_0_SYNC_PAR_OR_ECC_ERROR 0x1CU +#define ARMV8_LEVEL_1_SYNC_PAR_OR_ECC_ERROR 0x1DU +#define ARMV8_LEVEL_2_SYNC_PAR_OR_ECC_ERROR 0x1EU +#define ARMV8_LEVEL_3_SYNC_PAR_OR_ECC_ERROR 0x1FU + +#define ARMV8_ALIGNMENT_FAULT 0x21U +#define ARMV8_TLB_CONFLICT_ABORT 0x30U + +#define ARMV8_ASYNC_SEEROR_INTERRUPT 0x11U + +#else /* #if defined (__aarch64__) */ + +#define DATA_ABORT 0x00U +#define INS_PREFETCH_ABORT 0x01U +#define ARMV7_FAULT_STATUS_MASK_BIT3_0 0x0FU +#define ARMV7_DFAR_VALUE_VALID 0x01U +#define ARMV7_FAULT_STATUS_BIT10_MASK 0x400U + +#define ARMV7_BACKGROUND_FAULT 0x00U +#define ARMV7_ALIGNMENT_FAULT 0x01U +#define ARMV7_DEBUG_EVENT 0x02U +#define ARMV7_ACCESS_FLAG_FAULT 0x03U +#define ARMV7_ICACHE_MAINTENANCE_FAULT 0x04U +#define ARMV7_TRANSLATION_FAULT 0x05U +#define ARMV7_SYNC_EXT_ABORT 0x08U +#define ARMV7_DOMAIN_FAULT 0x09U +#define ARMV7_SYNC_ABORT_TRANSTAB_WALK 0x0CU +#define ARMV7_PERMISSION_FAULT 0x0DU +#define ARMV7_TLB_CONFLICT_ABORT 0x10U +#define ARMV7_ASYNC_EXT_ABORT 0x16U +#define ARMV7_MEM_ACS_ASYNC_PAR_ERR 0x18U +#define ARMV7_MEM_ACS_SYNC_PAR_ERR 0x19U +#define ARMV7_SYNCPAR_ERR_TRANSTAB_WALK 0x1CU + +#define EXTRACT_BITS_10_AND_3_TO_0(Val) \ + ((Val & (ARMV7_FAULT_STATUS_BIT10_MASK)) >> 6) | \ + (Val & ARMV7_FAULT_STATUS_MASK_BIT3_0) + +#endif /* #if defined (__aarch64__) */ +#endif /* #ifdef DEBUG */ + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#if (defined (versal) && !defined(ARMR5) && EL3) +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT +#else +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT +#endif + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +typedef struct { + Xil_ExceptionHandler Handler; + void *Data; +} XExc_VectorTableEntry; + +extern XExc_VectorTableEntry XExc_VectorTable[]; + +/** +*@endcond +*/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if (defined (versal) && !defined(ARMR5) && EL3) +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionEnableMask(Mask) \ + (void)Mask; \ + mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#if (defined (versal) && !defined(ARMR5) && EL3) +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ) +#else +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) +#endif + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if (defined (versal) && !defined(ARMR5) && EL3) +/* + * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports + * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ + * ignoring argument passed by user. + */ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL)) +#elif defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) ) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3.. However,it is not defined for Versal Cortex-A72 BSP +* configured to run at EL3. Reason is, Cortex-A72 is coupled +* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL3"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode BSP configured to run +* at EL3. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL3, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL3, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I bit in DAIF.This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I bit +* is set as 1). To allow nesting of interrupts, this macro should be +* used. It clears the I bit. Once that bit is cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I +* bit, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs X1, ELR_EL1"); \ + __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \ + __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I bit in DAIF. This +* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit +* BSP configured to run at EL1 NON SECURE +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ mode and +* hence sets back the I bit. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \ + __asm__ __volatile__ ("msr ELR_EL1, X1"); \ + __asm__ __volatile__ ("msr SPSR_EL1, X2"); \ + __asm__ __volatile__ ("mrs X1, DAIF"); \ + __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \ + __asm__ __volatile__ ("msr DAIF, X1"); \ + +#elif (!defined (__aarch64__) && !defined (ARMA53_32)) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); +extern void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, void **Data); + +extern void Xil_ExceptionInit(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_hal.h new file mode 100644 index 0000000..4b289a7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_hal.h @@ -0,0 +1,43 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/28/09 Initial release +* +*+* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_io.h new file mode 100644 index 0000000..382bc87 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_io.h @@ -0,0 +1,433 @@ +/****************************************************************************** +* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/29/14 First release +* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for +* ARM processors +* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for +* CR-1049218 +* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to +* xil_io.h and made them as static inline +* am 10/13/20 Changed the return type of Xil_SecureOut32 function +* from u32 to int +* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur +* when -Werror=conversion compiler flag is enabled +* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739. +* 9.0 ml 03/03/23 Add description and remove comments to fix doxygen warnings. +*+******************************************************************************/ + +#ifndef XIL_IO_H /**< prevent circular inclusions */ +#define XIL_IO_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" +#include "xstatus.h" + +#if defined (__MICROBLAZE__) +#include "mb_interface.h" +#else +#include "xpseudo_asm.h" +#endif + +/************************** Function Prototypes ******************************/ +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined __GNUC__ +#if defined (__MICROBLAZE__) +# define INST_SYNC mbar(0) /**< Instruction Synchronization Barrier */ +# define DATA_SYNC mbar(1) /**< Data Synchronization Barrier */ +# else +# define SYNCHRONIZE_IO dmb() /**< Data Memory Barrier */ +# define INST_SYNC isb() /**< Instruction Synchronization Barrier */ +# define DATA_SYNC dsb() /**< Data Synchronization Barrier */ +# endif +#else +# define SYNCHRONIZE_IO /**< Data Memory Barrier */ +# define INST_SYNC /**< Instruction Synchronization Barrier */ +# define DATA_SYNC /**< Data Synchronization Barrier */ +# define INST_SYNC /**< Instruction Synchronization Barrier */ +# define DATA_SYNC /**< Data Synchronization Barrier */ +#endif + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline /**< static inline keyword */ +#else +#define INLINE __inline /**
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.1 nsk 11/07/16 First release. +* 7.0 mus 01/07/19 Add cpp extern macro +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +*+* +*****************************************************************************/ +#ifndef XIL_MEM_H /**< prevent circular inclusions */ +#define XIL_MEM_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes *****************************/ + +void Xil_MemCpy(void* dst, const void* src, u32 cnt); + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MEM_H */ +/** +* @} End of "addtogroup common_mem_operation_api". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_misc_psreset_api.h new file mode 100644 index 0000000..de0ff25 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_misc_psreset_api.h @@ -0,0 +1,263 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xil_misc_psreset_api.h +* +* This file contains the various register definitions and function prototypes for +* implementing the reset functionality of zynq ps devices +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b kpc 03/07/13 First release. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* +* +******************************************************************************/ + +#ifndef XIL_MISC_RESET_H /**< prevent circular inclusions */ +#define XIL_MISC_RESET_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** + *@cond nocomments + */ + +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U +/**< OCM configuration register */ +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) +/**< SLCR unlock register */ +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) +/**< SLCR GEM0 rx clock control register */ +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) +/**< SLCR GEM1 rx clock control register */ +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) +/**< SLCR GEM0 clock control register */ +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) +/**< SLCR GEM1 clock control register */ +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) +/**< SLCR SMC clock control register */ +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) +/**< SLCR GEM reset control register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) +/**< SLCR USB0 clock control register */ +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) +/**< SLCR USB1 clock control register */ +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) +/**< SLCR USB1 reset control register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) +/**< SLCR SMC reset control register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) +/**< SLCR Level shifter enable register */ +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) +/**< SLCR ARM pll control register */ +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) +/**< SLCR DDR pll control register */ +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) +/**< SLCR IO pll control register */ +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) +/**< SLCR ARM pll configuration register */ +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) +/**< SLCR DDR pll configuration register */ +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) +/**< SLCR IO pll configuration register */ +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) +/**< SLCR ARM clock control register */ +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) +/**< SLCR DDR clock control register */ +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) +/**< SLCR MIO pin address register */ +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) +/**< SLCR DMAC reset control address register */ +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) +/**< SLCR USB reset control address register */ +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ +/**< SLCR GEM reset control address register */ +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ +/**< SLCR SDIO reset control address register */ +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) +/**< SLCR SPI reset control address register */ +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) +/**< SLCR CAN reset control address register */ +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) +/**< SLCR I2C reset control address register */ +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) +/**< SLCR UART reset control address register */ +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) +/**< SLCR GPIO reset control address register */ +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) +/**< SLCR LQSPI reset control address register */ +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) +/**< SLCR SMC reset control address register */ +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ +/**< SLCR OCM reset control address register */ +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) + +/**< SMC mem controller clear config register */ +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU +/**< SMC idlecount configuration register */ +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U +/**< SMC ECC configuration register */ +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U +/**< SMC ECC command 1 register */ +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U +/**< SMC ECC command 2 register */ +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U + +/**< SLCR unlock code */ +#define XSLCR_UNLOCK_CODE 0x0000DF0DU + +/**< SMC mem clear configuration mask */ +#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU +/**< SMC ECC memconfig 1 reset value */ +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U +/**< SMC ECC memcommand 1 reset value */ +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U +/**< SMC ECC memcommand 2 reset value */ +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U + +/**< DDR controller reset bit mask */ +#define XDDRPS_CTRL_RESET_MASK 0x00000001U +/**< SLCR OCM configuration reset value*/ +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U +/**< SLCR OCM bank selection mask*/ +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU +/**< SLCR level shifter enable mask*/ +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU + +/**< SLCR PLL register reset values */ +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U + +/**< SLCR MIO register default values */ +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U + +/**< SLCR Reset control registers default values */ +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U + +/** + *@endcond + */ + +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +/* + * Performs reset operation to the ddr interface + */ +void XDdr_ResetHw(void); +/* + * Map the ocm region to post bootrom state + */ +void XOcm_Remap(void); +/* + * Performs the smc interface reset + */ +void XSmc_ResetHw(u32 BaseAddress); +/* + * updates the MIO registers with reset values + */ +void XSlcr_MioWriteResetValues(void); +/* + * updates the PLL and clock registers with reset values + */ +void XSlcr_PllWriteResetValues(void); +/* + * Disables the level shifters + */ +void XSlcr_DisableLevelShifters(void); +/* + * provides softreset to the GPIO interface + */ +void XSlcr_GpioPsReset(void); +/* + * provides softreset to the DMA interface + */ +void XSlcr_DmaPsReset(void); +/* + * provides softreset to the SMC interface + */ +void XSlcr_SmcPsReset(void); +/* + * provides softreset to the CAN interface + */ +void XSlcr_CanPsReset(void); +/* + * provides softreset to the Uart interface + */ +void XSlcr_UartPsReset(void); +/* + * provides softreset to the I2C interface + */ +void XSlcr_I2cPsReset(void); +/* + * provides softreset to the SPI interface + */ +void XSlcr_SpiPsReset(void); +/* + * provides softreset to the QSPI interface + */ +void XSlcr_QspiPsReset(void); +/* + * provides softreset to the USB interface + */ +void XSlcr_UsbPsReset(void); +/* + * provides softreset to the GEM interface + */ +void XSlcr_EmacPsReset(void); +/* + * provides softreset to the OCM interface + */ +void XSlcr_OcmReset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MISC_RESET_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_mmu.h new file mode 100644 index 0000000..d21e13a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_mmu.h @@ -0,0 +1,92 @@ +/****************************************************************************** +* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions +* +* MMU functions equip users to enable MMU, disable MMU and modify default +* memory attributes of MMU table as per the need. +* +* @{ +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 1.00a sdm 01/12/12 Initial version +* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for +* u32 which resolves issue of CR#805869 +* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +*+* +* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory type */ +#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */ +#define STRONG_ORDERED 0xC02 /* Strongly ordered */ +#define DEVICE_MEMORY 0xC06 /* Device memory */ +#define RESERVED 0x0 /* reserved memory */ + +/* Normal write-through cacheable shareable */ +#define NORM_WT_CACHE 0x16DEA + +/* Normal write back cacheable shareable */ +#define NORM_WB_CACHE 0x15DE6 + +/* shareability attribute */ +#define SHAREABLE (0x1 << 16) +#define NON_SHAREABLE (~(0x1 << 16)) + +/* Execution type */ +#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0)) + +/** +*@endcond +*/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMMU(void); +void Xil_DisableMMU(void); +void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ +/** +* @} End of "addtogroup a9_mmu_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_printf.h new file mode 100644 index 0000000..c69af0f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_printf.h @@ -0,0 +1,57 @@ +/****************************************************************************** +* Copyright (C) 1995 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include
+* MODIFICATION HISTORY : +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 6.6 srm 10/18/17 First Release. +* 7.0 mus 01/07/19 Add cpp extern macro +* 7.7 sk 01/10/22 Add explicit parentheses for EL3==1 to fix +* misra_c_2012_rule_12_1 violation. +* 7.7 sk 01/10/22 Add void to XTime_StartTTCTimer function declaration +* to fix misra_c_2012_rule_8_2 violation. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +*+*****************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && (EL3==1)) || defined (ARMA53_32) +#if defined (versal) +#define CRL_TTC_RST 0xFF5E0344U +#define CRL_TTC_BASE_RST_MASK 0x1U +#else +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ +/** + *@endcond + */ +/************************** Function Prototypes ******************************/ + +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ +void Xil_SleepTTCCommon(u32 delay, u64 frequency); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_SLEEPTIMER_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_spinlock.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_spinlock.h new file mode 100644 index 0000000..b61d7d3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_spinlock.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_spinlock.h +* +* This header file contains function prototypes to be used while using Xilinx +* spinlocking mechanism. +* Please refer to file header contents of xil_spinlock.c to understand in +* detail the spinlocking mechanism. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 7.5 asa 02/16/21 First release +* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled +* if condition to fix misrac violations. +* 7.7 sk 01/10/22 Update XIL_SPINLOCK_ENABLED from signed to unsigned to +* fix misra_c_2012_rule_10_4 violation. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +*+* +******************************************************************************/ + +#ifndef XIL_SPINLOCK_H /**< prevent circular inclusions */ +#define XIL_SPINLOCK_H /**< by using protection macros */ + +/***************************** Include Files ********************************/ +#include "xil_types.h" +#include "xstatus.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) +/************************** Function Prototypes *****************************/ +u32 Xil_SpinLock(void); +u32 Xil_SpinUnlock(void); +u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr, + u32 lockflag); +void Xil_ReleaseSpinLock(void); +u32 Xil_IsSpinLockEnabled(void); + +/************************** MACRO Definitions ****************************/ +#define XIL_SPINLOCK_LOCKVAL 0x10203040 +#define XIL_SPINLOCK_RESETVAL 0x40302010 +#define XIL_SPINLOCK_ENABLE 0x17273747 +#define XIL_SPINLOCK_ENABLED 0x17273747U +/***************** Macros (Inline Functions) Definitions ********************/ + +#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ +/***************************************************************************/ +#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) +#define XIL_SPINLOCK() \ + if(Xil_IsSpinLockEnabled()!=(u32)0) { \ + Xil_SpinLock(); } +#else +#define XIL_SPINLOCK() /**< protect multiple applications running at separate + * CPUs to write to the same register */ +#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ + +#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) +#define XIL_SPINUNLOCK() \ + if(Xil_IsSpinLockEnabled()!=(u32)0) { \ + Xil_SpinUnlock(); } +#else +#define XIL_SPINUNLOCK() /**< Release the lock previously taken */ +#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_SPINLOCK_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testcache.h new file mode 100644 index 0000000..5798c21 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testcache.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* @addtogroup common_test_utils +*
+* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 07/29/09 First release +*+* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + +/** + *@endcond + */ + +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testio.h new file mode 100644 index 0000000..5a1bda3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testio.h @@ -0,0 +1,76 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testio.h +* +* @addtogroup common_test_utils Test Utilities for Memory and Caches +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00 hbm 08/05/09 First release +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/** + *@endcond + */ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testmem.h new file mode 100644 index 0000000..9fddbc5 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_testmem.h @@ -0,0 +1,169 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* @addtogroup common_test_utils Test Utilities for Memory and Caches +* +* - Cache test: xil_testcache.h contains utility functions to test cache. +* +* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A +* subset of the memory tests can be selected or all of the tests can be run in order. +* If there is an error detected by a subtest, the test stops and the failure code is +* returned. Further tests are not run even if all of the tests are selected. +* +* - Memory test: The xil_testmem.h file contains utility functions to test memory. +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests are selected. +* +* +* Following list describes the supported memory tests: +* +* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests. +* +* - XIL_TESTMEM_INCREMENT: This test +* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the +* test value for memory. +* +* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test +* uses a walking '1' as the test value for memory. +* @code +* location 1 = 0x00000001 +* location 2 = 0x00000002 +* ... +* @endcode +* +* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test. +* This test uses the inverse value of the walking ones test +* as the test value for memory. +* @code +* location 1 = 0xFFFFFFFE +* location 2 = 0xFFFFFFFD +* ... +*@endcode +* +* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test. +* This test uses the inverse of the address of the location under test +* as the test value for memory. +* +* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test. +* This test uses the provided patters as the test value for memory. +* If zero is provided as the pattern the test uses '0xDEADBEEF". +* +* @warning +* The tests are DESTRUCTIVE. Run before any initialized memory spaces +* have been set up. +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 08/25/09 First release +* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and +* Xil_TestMem8 APIs to support memory test for memory +* regions mapped at extended addresses +* (addresses > 4 GB). These new set of APIs would be +* compiled only for 32 bit Microblaze processor, if +* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32. +* It fixes CR#1089129. +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1U + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +#if !defined(__aarch64__) && !defined(__arch64__) +#define NUM_OF_BITS_IN_BYTE 8U +#define NUM_OF_BYTES_IN_HW 2U +#define NUM_OF_BITS_IN_HW 16U +#define NUM_OF_BYTES_IN_WORD 4U +#define NUM_OF_BITS_IN_WORD 32U +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/** + *@endcond + */ + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ +#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32) +extern s32 Xil_TestMem32(u32 AddrLow, u32 AddrHigh, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u32 AddrLow, u32 AddrHigh, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u32 AddrLow, u32 AddrHigh, u32 Words, u8 Pattern, u8 Subtest); +#else +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_types.h new file mode 100644 index 0000000..4c37fbc --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xil_types.h @@ -0,0 +1,230 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values +* 7.00 mus 01/07/19 Add cpp extern macro +* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it +* is 64-bit processor +* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types +* incase of microblaze 32-bit with extended address enabled +* 9.0 ml 14/04/23 Add parenthesis on sub-expression to fix misra-c violation. +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 6.4 mmd 04/21/19 First release. +* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API +* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API +* rpo 08/19/20 Added function for read, modify and write +* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add +* redundancy in security critical functions, to avoid +* glitches from altering the return values of security +* critical functions. The macro requires a label to be +* passed to "go to" in case of error. +* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy +* kal 09/22/20 Changed the param type from const char to const char* +* to avoid copying key onto stack +* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and +* Xil_MemCmp functions +* am 10/13/20 Resolved Coverity warning +* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and +* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3 +* 7.4 am 11/26/20 Added Xil_StrCpyRange function +* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function +* 7.7 kpt 11/09/21 Added Xil_SMemCmp, Xil_SMemCmp_CT, Xil_SMemCpy, +* Xil_SMemSet, Xil_SStrCat, Xil_SStrCmp, Xil_SStrCmp_CT +* Xil_SStrCpy functions +* 7.7 sk 01/10/22 Update functions return type to fix misra_c_2012_ +* directive_4_6 violations. +* mmd 02/28/22 Added Xil_SMemMove function prototype +* 8.0 adk 04/18/22 Added Xil_WaitForEventSet function prototype. +* ssc 08/25/22 Added Xil_SecureRMW32 prototype +* 8.1 sa 09/29/22 Change the type of first argument passed to Xil_WaitForEvent +* API from u32 to UINTPTR for supporting 64 bit addressing. +* 8.1 sa 10/20/22 Change the type of first argument passed to Xil_WaitForEvents +* API from u32 to UINTPTR for supporting 64 bit addressing. +* 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs. +* bm 03/14/23 Added XSECURE_REDUNDANT_CALL and XSECURE_REDUNDANT_IMPL macros +* sk 03/14/23 Added Status Check Glitch detect Macro +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +* mmd 07/09/23 Added macro to build version +* ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to +* fix MISRA-C violations for Rule 4.6 +*+* +*****************************************************************************/ + +#ifndef XIL_UTIL_H_ +#define XIL_UTIL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************* Include Files ********************************/ +#include "xil_types.h" +#include "xil_io.h" +#include "xstatus.h" + +/*************************** Constant Definitions *****************************/ +#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U /**< size of nibble in bits */ +#define XIL_SIZE_OF_BYTE_IN_BITS 8U /**< size of byte in bits */ + +#define XIL_MAX_HEX_STR_LEN 512U /**< Maximum string length handled by + Xil_ValidateHexStr function */ + +/****************** Macros (Inline Functions) Definitions *********************/ + +/******************************************************************************/ +/** + * + * Builds version number by concatenates 16-bit Major version and Minor version. + * + * @param Major is the 16-bit major version number + * @param Minor is the 16-bit minor version number + * + * @return 32-bit version number + * + ******************************************************************************/ +#define XIL_BUILD_VERSION(Major, Minor) (((Major) << 16U) | (Minor)) + +#ifdef __GNUC__ +/******************************************************************************/ +/** + * + * Updates the return value of the called function into Var and VarTmp variables + * for redundancy. This is to avoid glitches from altering the return values of + * security critical functions. + * + * @param Var is the variable which holds the return value of function + * executed + * @param VarTmp is the variable which holds the value stored in Var + * @param Function is the function to be executed + * @param Other params are arguments to the called function + * + * @return None + * + ******************************************************************************/ +#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \ + { \ + Var = XST_FAILURE; \ + VarTmp = XST_FAILURE; \ + Var = Function(__VA_ARGS__); \ + VarTmp = Var; \ + } + +/******************************************************************************/ +/** + * + * Adds redundancy while checking the status of the called function. + * This is to avoid glitches from altering the return values of security + * critical functions. The macro requires a label to be passed to "go to" + * in case of error. + * + * @param Label is the label defined in function and the control + * will jump to the label in case of XST_FAILURE + * @param Status is the variable which holds the return value of + * function executed + * @param Function is the function to be executed + * @param Other params are arguments to the called function + * + * @return None + * + ******************************************************************************/ +#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \ + { \ + volatile int StatusTmp; \ + XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \ + if ((Status != XST_SUCCESS) || \ + (StatusTmp != XST_SUCCESS)) { \ + if (((Status) != (StatusTmp)) || \ + (Status == XST_SUCCESS)) { \ + Status = XST_GLITCH_ERROR; \ + }\ + goto Label; \ + } \ + } + +/******************************************************************************/ +/** + * + * Adds redundancy to the function call. This is to avoid glitches which can skip + * a function call and cause altering of the code flow in security critical + * functions. + * + * @param Status is the variable which holds the return value of + * function executed + * @param StatusTmp is the variable which holds the return value of + * redundant function call executed + * @param Function is the function to be executed + * @param Other params are arguments to the called function + * + * @return None + * + ******************************************************************************/ +#define XSECURE_REDUNDANT_CALL(Status, StatusTmp, Function, ...) \ + { \ + Status = Function(__VA_ARGS__); \ + StatusTmp = Function(__VA_ARGS__); \ + } + +/******************************************************************************/ +/** + * + * Adds redundancy to the function call. This is to avoid glitches which can skip + * a function call and cause altering of the code flow in security critical + * functions. + * + * @param Function is the function to be executed + * @param Other params are arguments to the called function + * + * @return None + * + ******************************************************************************/ +#define XSECURE_REDUNDANT_IMPL(Function, ...) \ + { \ + Function(__VA_ARGS__); \ + Function(__VA_ARGS__); \ + } + +/******************************************************************************/ +/** + * + * This Macro helps to detect glitches skipping the Status check + * in case of error. + * + * @param None + * + * @return None + * + ******************************************************************************/ +#define XSECURE_STATUS_CHK_GLITCH_DETECT(Status) \ + { \ + if (Status == XST_SUCCESS) { \ + Status = (int)XST_GLITCH_ERROR; \ + } \ + } + +#endif +/*************************** Function Prototypes ******************************/ +/**< Ceils the provided float value */ +s32 Xil_Ceil(float Value); + +/**< Converts input character to nibble */ +u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num); + +/**< Convert input hex string to array of 32-bits integers */ +u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len); + +#ifdef VERSAL_PLM +/**< Register PLM handler */ +void Xil_RegisterPlmHandler(void (*PlmAlive) (void)); + +/**< Call PLM handler */ +void Xil_PlmStubHandler(void); +#endif + +/**< Waits for specified event */ +u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout); + +/**< Waits for specified events */ +u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, + u32 Timeout, u32 *Events); + +/**< Validate input hex character */ +u32 Xil_IsValidHexChar(const char *Ch); + +/**< Validate the input string contains only hexadecimal characters */ +u32 Xil_ValidateHexStr(const char *HexStr); + +/**< Convert string to hex numbers in little enidian format */ +u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len); + +/**< Returns length of the input string */ +u32 Xil_Strnlen(const char *Str, u32 MaxLen); + +/**< Convert string to hex numbers in big endian format */ +u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len); + +/**< Read, Modify and Write to an address*/ +void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value); + +/**< Copies source string to destination string */ +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size); + +/**< Copies specified range from source string to destination string */ +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen); + +/**< Appends string2 to string1 */ +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size); + +/**< Copies Len bytes from source memory to destination memory */ +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len); + +/**< Compares Len bytes from memory1 and memory2 */ +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len); + +/**< Zeroizes the memory of given length */ +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length); + +/**< Copies Len bytes from source memory to destination memory */ +s32 Xil_SMemCpy (void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); + +/**< Copies Len bytes from source memory to destination memory, allows + overlapped memory between source and destination */ +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen); + +/**< Compares Len bytes between source and destination memory */ +s32 Xil_SMemCmp (const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen); + +/**< Compares Len bytes between source and destination memory with constant time */ +s32 Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen); + +/**< Sets the destination memory of given length with given data */ +s32 Xil_SMemSet (void *Dest, const u32 DestSize, + const u8 Data, const u32 Len); + +/**< Copies source string to destination string */ +s32 Xil_SStrCpy (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize); + +/**< Compares source string with destination string */ +s32 Xil_SStrCmp (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size); + +/**< Compares source string with destination string with constant time */ +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size); + +/**< Concatenates source string to destination string */ +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize); + +/**< Waits for event timeout */ +u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...); + +/**< Implements Read Modify Writes securely */ +s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value); + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_UTIL_H_ */ +/** +* @} End of "addtogroup common_utilities". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xinterrupt_wrap.h new file mode 100644 index 0000000..423aa0e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xinterrupt_wrap.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xinterrupt_wrap.h +* +* The xinterrupt_wrap.h file contains interrupt related functions and macros. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 7.2 mus 22/11/21 First release of xil interrupt support +* 8.0 sk 03/17/22 Update XINTC_BASEADDR_MASK macro to unsigned to +* fix misra_c_2012_rule_7_2 violation. +* 9.0 ml 03/03/23 Add description to fix doxygen warnings. +*+* +******************************************************************************/ + +#ifndef XINTERRUPT_WRAP_H /**< prevent circular inclusions */ +#define XINTERRUPT_WRAP_H /**< by using protection macros */ + +#include "xil_types.h" +#include "xstatus.h" + +#ifdef XIL_INTERRUPT +#ifdef SDT +#include "xcommon_drv_config.h" +#else +#include "xparameters.h" +#endif +#include "xil_exception.h" + +#if defined(XPAR_AXI_INTC) +#include "xintc.h" +#endif + +#if defined(XPAR_SCUGIC) +#include "xscugic.h" +#define XSPI_INTR_OFFSET 32U +#endif + +#define XINTERRUPT_DEFAULT_PRIORITY 0xA0U /* AXI INTC doesnt support priority setting, it is default priority for GIC interrupts */ +#define XINTC_TYPE_IS_SCUGIC 0U +#define XINTC_TYPE_IS_INTC 1U +#define XINTR_IS_EDGE_TRIGGERED 3U +#define XINTR_IS_LEVEL_TRIGGERED 1U + +#define XINTC_TYPE_MASK 0x1 +#define XINTC_INTR_TYPE_MASK 0x100000 +#define XINTC_BASEADDR_MASK 0xFFFFFFFFFFFFFFFEU +#define XINTC_INTRID_MASK 0xFFF +#define XINTC_TRIGGER_MASK 0xF000 +#define XINTC_TRIGGER_SHIFT 12 +#define XINTC_INTR_TYPE_SHIFT 20U +#define XGet_IntcType(IntParent) (IntParent & XINTC_TYPE_MASK) +#define XGet_IntrType(IntId) ((IntId & XINTC_INTR_TYPE_MASK) >> XINTC_INTR_TYPE_SHIFT) +#define XGet_BaseAddr(IntParent) (IntParent & XINTC_BASEADDR_MASK) +#define XGet_IntrId(IntId) (IntId & XINTC_INTRID_MASK) +#define XGet_TriggerType(IntId) ((IntId & XINTC_TRIGGER_MASK) >> XINTC_TRIGGER_SHIFT) +#define XGet_IntrOffset(IntId) (( XGet_IntrType(IntId) == 1) ? 16 : 32) /* For PPI offset is 16 and for SPI it is 32 */ + +extern int XConfigInterruptCntrl(UINTPTR IntcParent); +extern int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent); +extern int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent); +extern int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent); +extern void XEnableIntrId( u32 IntrId, UINTPTR IntcParent); +extern void XDisableIntrId( u32 IntrId, UINTPTR IntcParent); +extern void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent); +extern void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent); +extern void XStopInterruptCntrl( UINTPTR IntcParent); +extern void XRegisterInterruptHandler( void *IntrHandler, UINTPTR IntcParent); +extern int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent, + u16 Priority); +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xl2cc.h new file mode 100644 index 0000000..4df6d87 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xl2cc.h @@ -0,0 +1,155 @@ +/****************************************************************************** +* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xl2cc.h +* +* This file contains the address definitions for the PL310 Level-2 Cache +* Controller. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------- +* 1.00a sdm 02/01/10 Initial version +* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file +* 'xil_errata.h' for errata description +*+* +* @note +* +* None. +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef _XL2CC_H_ +#define _XL2CC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* L2CC Register Offsets */ +#define XPS_L2CC_ID_OFFSET 0x0000U +#define XPS_L2CC_TYPE_OFFSET 0x0004U +#define XPS_L2CC_CNTRL_OFFSET 0x0100U +#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U +#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U +#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU + +#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U +#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U +#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U +#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU +#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U + +#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */ +#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */ +#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */ +#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */ + +#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */ +#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */ +#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */ +#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */ +#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */ +#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */ +#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */ +#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */ +#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */ +#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */ + +#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */ + +#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */ +#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */ + +#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */ + +#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */ + +/* XPS_L2CC_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */ + +/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */ +#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */ +#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */ +#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */ +#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */ +#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */ +#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */ +#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */ +#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */ +#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */ +#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */ +#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */ +#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */ +#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */ +#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */ +#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */ +#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */ + +#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */ + /* Cache replacement policy, Parity enable, */ + /* Event monitor bus enable and Way Size (64 KB) */ +#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */ + +#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */ +#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */ + +/* Interrupt bit masks */ +#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */ +#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */ +#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */ +#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */ +#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */ + +/* Address filtering mask and enable bit */ +#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/ +#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/ + +/* Debug control bits */ +#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */ +#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */ +#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */ + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ + +/** + *@endcond + */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xl2cc_counter.h new file mode 100644 index 0000000..31156ee --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xl2cc_counter.h @@ -0,0 +1,96 @@ +/****************************************************************************** +* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.h +* +* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions +* +* xl2cc_counter.h contains APIs for configuring and controlling the event +* counters in PL310 L2 cache controller. +* PL310 has two event counters which can be used to count variety of events +* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions +* for different configurations which can be used for the event counters to +* count a set of events. +* +* +* @{ +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a sdm 07/11/11 First release +* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address +* inside the APIs +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +*+* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ +#define L2CCCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* + * The following constants define the event codes for the event counters. + */ +#define XL2CC_CO 0x1 +#define XL2CC_DRHIT 0x2 +#define XL2CC_DRREQ 0x3 +#define XL2CC_DWHIT 0x4 +#define XL2CC_DWREQ 0x5 +#define XL2CC_DWTREQ 0x6 +#define XL2CC_IRHIT 0x7 +#define XL2CC_IRREQ 0x8 +#define XL2CC_WA 0x9 +#define XL2CC_IPFALLOC 0xa +#define XL2CC_EPFHIT 0xb +#define XL2CC_EPFALLOC 0xc +#define XL2CC_SRRCVD 0xd +#define XL2CC_SRCONF 0xe +#define XL2CC_EPFRCVD 0xf + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/** +*@endcond +*/ + +/************************** Function Prototypes *****************************/ + +void XL2cc_EventCtrInit(s32 Event0, s32 Event1); +void XL2cc_EventCtrStart(void); +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* L2CCCOUNTER_H */ +/** +* @} End of "addtogroup l2_event_counter_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xlwipconfig.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xlwipconfig.h new file mode 100644 index 0000000..acec86b --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xlwipconfig.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * Copyright (C) 2007 - 2022 Xilinx, Inc. + * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------- -------- --------------------------------------------------- +* 1.00a ecm/sdm 02/01/10 Initial version +* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through +* driver tcl +* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP +* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9 +* +*+* +* @note +* +* None. +* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files *******************************/ + + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID + + +#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR +#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR + + + +/* Canonical definitions for DMAC */ + + +/* Canonical definitions for WDT */ + +/* Canonical definitions for SLCR */ +#define XPAR_XSLCR_NUM_INSTANCES 1U +#define XPAR_XSLCR_0_DEVICE_ID 0U +#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +/* Canonical definitions for Global Timer */ +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U +#define XPAR_GLOBAL_TMR_DEVICE_ID 0U +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) +#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID + + +/* Xilinx Parallel Flash Library (XilFlash) User Settings */ +#define XPAR_AXI_EMC + + +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibility + */ + +#define XPS_PERIPHERAL_BASEADDR 0xE0000000U +#define XPS_UART0_BASEADDR 0xE0000000U +#define XPS_UART1_BASEADDR 0xE0001000U +#define XPS_USB0_BASEADDR 0xE0002000U +#define XPS_USB1_BASEADDR 0xE0003000U +#define XPS_I2C0_BASEADDR 0xE0004000U +#define XPS_I2C1_BASEADDR 0xE0005000U +#define XPS_SPI0_BASEADDR 0xE0006000U +#define XPS_SPI1_BASEADDR 0xE0007000U +#define XPS_CAN0_BASEADDR 0xE0008000U +#define XPS_CAN1_BASEADDR 0xE0009000U +#define XPS_GPIO_BASEADDR 0xE000A000U +#define XPS_GEM0_BASEADDR 0xE000B000U +#define XPS_GEM1_BASEADDR 0xE000C000U +#define XPS_QSPI_BASEADDR 0xE000D000U +#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U +#define XPS_SDIO0_BASEADDR 0xE0100000U +#define XPS_SDIO1_BASEADDR 0xE0101000U +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U +#define XPS_NAND_BASEADDR 0xE1000000U +#define XPS_PARPORT0_BASEADDR 0xE2000000U +#define XPS_PARPORT1_BASEADDR 0xE4000000U +#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U +#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */ +#define XPS_TTC0_BASEADDR 0xF8001000U +#define XPS_TTC1_BASEADDR 0xF8002000U +#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U +#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U +#define XPS_WDT_BASEADDR 0xF8005000U +#define XPS_DDR_CTRL_BASEADDR 0xF8006000U +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U +#define XPS_AFI0_BASEADDR 0xF8008000U +#define XPS_AFI1_BASEADDR 0xF8009000U +#define XPS_AFI2_BASEADDR 0xF800A000U +#define XPS_AFI3_BASEADDR 0xF800B000U +#define XPS_OCM_BASEADDR 0xF800C000U +#define XPS_EFUSE_BASEADDR 0xF800D000U +#define XPS_CORESIGHT_BASEADDR 0xF8800000U +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U +#define XPS_SCU_PERIPH_BASE 0xF8F00000U +#define XPS_L2CC_BASEADDR 0xF8F02000U +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U +#define XPS_PERIPH_APB_BASEADDR 0xF8000000U + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_CORE_PARITY0_INT_ID 32U +#define XPS_CORE_PARITY1_INT_ID 33U +#define XPS_L2CC_INT_ID 34U +#define XPS_OCMINTR_INT_ID 35U +#define XPS_ECC_INT_ID 36U +#define XPS_PMU0_INT_ID 37U +#define XPS_PMU1_INT_ID 38U +#define XPS_SYSMON_INT_ID 39U +#define XPS_DVC_INT_ID 40U +#define XPS_WDT_INT_ID 41U +#define XPS_TTC0_0_INT_ID 42U +#define XPS_TTC0_1_INT_ID 43U +#define XPS_TTC0_2_INT_ID 44U +#define XPS_DMA0_ABORT_INT_ID 45U +#define XPS_DMA0_INT_ID 46U +#define XPS_DMA1_INT_ID 47U +#define XPS_DMA2_INT_ID 48U +#define XPS_DMA3_INT_ID 49U +#define XPS_SMC_INT_ID 50U +#define XPS_QSPI_INT_ID 51U +#define XPS_GPIO_INT_ID 52U +#define XPS_USB0_INT_ID 53U +#define XPS_GEM0_INT_ID 54U +#define XPS_GEM0_WAKE_INT_ID 55U +#define XPS_SDIO0_INT_ID 56U +#define XPS_I2C0_INT_ID 57U +#define XPS_SPI0_INT_ID 58U +#define XPS_UART0_INT_ID 59U +#define XPS_CAN0_INT_ID 60U +#define XPS_FPGA0_INT_ID 61U +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_TTC1_0_INT_ID 69U +#define XPS_TTC1_1_INT_ID 70U +#define XPS_TTC1_2_INT_ID 71U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_USB1_INT_ID 76U +#define XPS_GEM1_INT_ID 77U +#define XPS_GEM1_WAKE_INT_ID 78U +#define XPS_SDIO1_INT_ID 79U +#define XPS_I2C1_INT_ID 80U +#define XPS_SPI1_INT_ID 81U +#define XPS_UART1_INT_ID 82U +#define XPS_CAN1_INT_ID 83U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Private Peripheral Interrupts (PPI) */ +#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */ +#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */ +#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */ +#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */ +#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */ + + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID +#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID + +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibility */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + +/* + * Defines for interrupt wrapper API + * For more details about usage please refer xinterrupt_wrap.h + * Here Bits[11:0] represents interrupt id + * Bits[15:12] represents interrupt trigger type and level flags + */ +#define XPAR_PS7_SCUTIMER_0_INTERRUPT_ID 0x10000D +#define XPAR_PS7_TTC_0_INTERRUPT_ID 0x400A +#define XPAR_PS7_TTC_1_INTERRUPT_ID 0x400B +#define XPAR_PS7_TTC_2_INTERRUPT_ID 0x400C +#define XPAR_PS7_TTC_3_INTERRUPT_ID 0x4025 +#define XPAR_PS7_TTC_4_INTERRUPT_ID 0x4026 +#define XPAR_PS7_TTC_5_INTERRUPT_ID 0x4027 + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ + +/** + *@endcond + */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xplatform_info.h new file mode 100644 index 0000000..251a697 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xplatform_info.h @@ -0,0 +1,159 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xplatform_info.h +* +* +* @addtogroup common_platform_info APIs to Get Platform Information +* +* +* The xplatform_info.h file contains definitions for various available Xilinx® +* platforms. Also, it contains prototype of APIs, which can be used to get the +* platform information. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- --------- ------------------------------------------------------- +* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info +* function for PMUFW. +* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function. +* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any +* arguments with void keyword. This has been done to fix +* compilation warnings with "-Wstrict-prototypes" flag. +* It fixes CR#1108601. +* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings +* reported with "-Wundef" flag. +* 7.7 sk 01/10/22 Update XPLAT_INFO_MASK from signed to unsigned to fix +* misra_c_2012_rule_10_4 violation. +* 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now +* they are supported only for VERSAL_NET APU and RPU. +* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be +* used to identify type of boot (cold/warm). +* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor +* 9.0 ml 09/14/23 Added U to numerical to fix MISRA-C violation for Rule +* 10.1 and 10.4 +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +#if defined (versal) +#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U +#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U +#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \ + XPAR_PMC_TAP_VERSION_OFFSET) +#else +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U +#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \ + XPAR_CSU_VER_OFFSET) +#endif +#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 +#define XPLAT_VERSAL 0x6U + +#define XPS_VERSION_1 0x0 +#define XPS_VERSION_2 0x1 +#define XPLAT_INFO_MASK (0xFU) + +#if defined (versal) +#define XPS_VERSION_INFO_MASK 0xFF00U +#define XPS_VERSION_INFO_SHIFT 0x8U +#define XPLAT_INFO_SHIFT 0x18U +#else +#define XPS_VERSION_INFO_MASK 0xFU +#define XPS_VERSION_INFO_SHIFT 0x0U +#define XPLAT_INFO_SHIFT 0xCU +#endif + +#if defined (VERSAL_NET) +#if defined (ARMR52) +#define XPS_NUM_OF_CORES_PER_CLUSTER 2U +#define XPS_RPU_PCIL_A0_PWRDWN 0xEB4200C0U +/* + * Offset between RPU_PCIL_X_PWRDWN registers of consecutive + * CPU cores in given cluster + */ +#define XPS_RPU_PCIL_CORE_OFFSET 0x100U + +/* + * Offset between RPU_PCIL_A0_PWRDWN registers of 2 clusters + */ +#define XPS_RPU_PCIL_CLUSTER_OFFSET 0x1000U +#define XPS_RPU_PCIL_X_PWRDWN_EN_MASK 1U +#else +#define XPS_NUM_OF_CORES_PER_CLUSTER 4U +#define XPS_CORE_X_PWRDWN_BASEADDR 0xECB10000U +/* + * Offset between CORE_X_PWRDWN registers of consecutive + * CPU cores + */ +#define XPS_CORE_X_PWRDWN_OFFSET 48U +#define XPS_CORE_X_PWRDWN_EN_MASK 1U +#endif +#endif +/**************************** Type Definitions *******************************/ +/** + *@endcond + */ +/***************** Macros (Inline Functions) Definitions *********************/ + + +u32 XGetPlatform_Info(void); +#if ! defined(__microblaze__) && ! defined(__riscv) +u8 XGetCoreId(void); +#endif + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal) +u32 XGetPSVersion_Info(void); +#endif + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(void); +#endif + +#if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) +u8 XGetClusterId(void); +u8 XGetCoreId(void); +u8 XGetBootStatus(void); +#endif + +/************************** Function Prototypes ******************************/ + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_platform_info". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpm_counter.h new file mode 100644 index 0000000..8b09ef5 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpm_counter.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* Copyright (c) 2011 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions +* +* Cortex A9 event counter functions can be utilized to configure and control +* the Cortex-A9 performance monitor events. +* +* Cortex-A9 performance monitor has six event counters which can be used to +* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines +* configurations XPM_CNTRCFGx which can be used to program the event counters +* to count a set of events. +* +* @note +* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is +* being used for time keeping. +* +* @{ +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a sdm 07/11/11 First release +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* 8.0 mus 07/07/22 Added prototype for new APIs as per consolidated +* xpm_counter.c. +*+* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 1.0 gm 14/06/23 Initial release. +*+******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpseudo_asm.h new file mode 100644 index 0000000..6d07851 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpseudo_asm.h @@ -0,0 +1,60 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a9_specific Cortex A9 Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h. +* +* The xreg_cortexa9.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers, +* co-processor registers and Debug registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a ecm 10/18/09 First release +* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction. +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +*+* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xreg_cortexa9.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#elif defined (__ICCARM__) + #include "xpseudo_asm_iccarm.h" +#else + #include "xpseudo_asm_rvct.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a9_specific". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpseudo_asm_gcc.h new file mode 100644 index 0000000..b8517d3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xpseudo_asm_gcc.h @@ -0,0 +1,285 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 5.00 pkp 05/21/14 First release +* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors +* 7.2 asa 04/03/20 Renamed the str macro to strw. +* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors +* 8.0 mus 02/24/22 Added macro mfcpnotoken and mtcpnotoken. +* 8.1 asa 02/13/23 Create macros to read ESR, FAR and ELR registers. +*+* +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "bspconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +#if defined (__aarch64__) +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#if (EL3 == 1) +#define mfelrel3() ({u64 rval = 0U; \ + asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ + rval;\ + }) +#define mfesrel3() ({u64 rval = 0U; \ + asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\ + rval;\ + }) + +#define mffarel3() ({u64 rval = 0U; \ + asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\ + rval;\ + }) + +#else +#define mfelrel1() ({u64 rval = 0U; \ + asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\ + rval;\ + }) + +#define mfesrel1() ({u64 rval = 0U; \ + asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\ + rval;\ + }) + +#define mffarel1() ({u64 rval = 0U; \ + asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\ + rval;\ + }) + + +#endif + +#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v)) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v) : "cc" \ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#endif + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define strw(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mfcpnotoken(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) +#define mtcpnotoken(reg,val) __asm__ __volatile__("msr " reg ",%0" : : "r" (val)) + +#else +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcp2(rn, v) __asm__ __volatile__(\ + "mcrr " rn "\n"\ + : : "r" (v), "r" (0)\ + ); + +#endif + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/** + *@endcond + */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xqspips.h new file mode 100644 index 0000000..23ccb52 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xqspips.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xqspips.h +* @addtogroup qspips Overview +* @{ +* @details +* +* This file contains the implementation of the XQspiPs driver. It supports only +* master mode. User documentation for the driver functions is contained in this +* file in the form of comment blocks at the front of each function. +* +* A QSPI device connects to an QSPI bus through a 4-wire serial interface. +* The QSPI bus is a full-duplex, synchronous bus that facilitates communication +* between one master and one slave. The device is always full-duplex, +* which means that for every byte sent, one is received, and vice-versa. +* The master controls the clock, so it can regulate when it wants to +* send or receive data. The slave is under control of the master, it must +* respond quickly since it has no control of the clock and must send/receive +* data as fast or as slow as the master does. +* +* Linear Mode +* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s +* functionality by adding a linear addressing scheme that allows the SPI flash +* memory subsystem to behave like a typical ROM device. The new feature hides +* the normal SPI protocol from a master reading from the SPI flash memory. The +* feature improves both the user friendliness and the overall read memory +* throughput over that of the current Quad-SPI Controller by lessening the +* amount of software overheads required and by the use of the faster AXI +* interface. +* +* Initialization & Configuration +* +* The XQspiPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find +* static configuration structure defined in xqspips_g.c. This is setup +* by the tools. For some operating systems the config structure will be +* initialized by the software and this call is not needed. +* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the provided virtual memory base address +* replaces the physical address present in the configuration structure. +* +* Multiple Masters +* +* More than one master can exist, but arbitration is the responsibility of +* the higher layer software. The device driver does not perform any type of +* arbitration. +* +* Modes of Operation +* +* There are four modes to perform a data transfer and the selection of a mode +* is based on Chip Select(CS) and Start. These two options individually, can +* be controlled either by software(Manual) or hardware(Auto). +* - Auto CS: Chip select is automatically asserted as soon as the first word +* is written into the TXFIFO and de asserted when the TXFIFO becomes +* empty +* - Manual CS: Software must assert and de assert CS. +* - Auto Start: Data transmission starts as soon as there is data in the +* TXFIFO and stalls when the TXFIFO is empty +* - Manual Start: Software must start data transmission at the beginning of +* the transaction or whenever the TXFIFO has become empty +* +* The preferred combination is Manual CS and Auto Start. +* In this combination, the software asserts CS before loading any data into +* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it +* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the +* data is available. If no further data, software disables CS. +* +* Risks/challenges of other combinations: +* - Manual CS and Manual Start: Manual Start bit should be set after each +* TXFIFO write otherwise there could be a race condition where the TXFIFO +* becomes empty before the new word is written. In that case the +* transmission stops. +* - Auto CS with Manual or Auto Start: It is very difficult for software to +* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted. +* This results in a single transaction to be split into multiple pieces each +* with its own chip select. This will result in garbage data to be sent. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XQspiPs_InterruptHandler, to an interrupt system such that it will be +* called when an interrupt occurs. This function does not save and restore +* the processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Data Transmit Register/FIFO Underflow +* - Data Receive Register/FIFO Not Empty +* - Data Transmit Register/FIFO Overwater +* - Data Receive Register/FIFO Overrun +* +* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the +* QSPI device has transmitted the data available to transmit, and now its data +* register and FIFO is ready to accept more data. The driver uses this +* interrupt to indicate progress while sending data. The driver may have +* more data to send, in which case the data transmit register and FIFO is +* filled for subsequent transmission. When this interrupt arrives and all +* the data has been sent, the driver invokes the status callback with a +* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that +* all data has been sent. +* +* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, +* as slave, the QSPI device was required to transmit but there was no data +* available to transmit in the transmit register (or FIFO). This may not +* be an error if the master is not expecting data. But in the case where +* the master is expecting data, this serves as a notification of such a +* condition. The driver reports this condition to the upper layer +* software through the status handler. +* +* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI +* device received data and subsequently dropped the data because the data +* receive register and FIFO was full. The driver reports this condition to the +* upper layer software through the status handler. This likely indicates a +* problem with the higher layer protocol, or a problem with the slave +* performance. +* +* +* Polled Operation +* +* Transfer in polled mode is supported through a separate interface function +* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, +* this function blocks until all data has been sent/received. +* +* Device Busy +* +* Some operations are disallowed when the device is busy. The driver tracks +* whether a device is busy. The device is considered busy when a data transfer +* request is outstanding, and is considered not busy only when that transfer +* completes (or is aborted with a mode fault error). +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xqspips_g.c file or +* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry +* contains configuration information for an QSPI device, including the base +* address for the device. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied +* by the layer above this driver. +* +* NOTE: This driver was always tested with endianness set to little-endian. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 1.00a sdm 11/25/10 First release, based on the PS SPI driver... +* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters +* in xparameters.h +* 2.00a kka 07/25/12 Added a few register defines for CR 670297 +* Removed code related to mode fault for CR 671468 +* The XQspiPs_SetSlaveSelect has been modified to remove +* the argument of the slave select as the QSPI controller +* only supports one slave. +* XQspiPs_GetSlaveSelect API has been removed +* Added a flag ShiftReadData to the instance structure +*. and is used in the XQspiPs_GetReadData API. +* The ShiftReadData Flag indicates whether the data +* read from the Rx FIFO needs to be shifted +* in cases where the data is less than 4 bytes +* Removed the selection for the following options: +* Master mode (XQSPIPS_MASTER_OPTION) and +* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option +* as the QSPI driver supports the Master mode +* and Flash Interface mode and doesnot support +* Slave mode or the legacy mode. +* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer +* APIs so that the last argument (IsInst) specifying whether +* it is instruction or data has been removed. The first byte +* in the SendBufPtr argument of these APIs specify the +* instruction to be sent to the Flash Device. +* This version of the driver fixes CRs 670197/663787/ +* 670297/671468. +* Added the option for setting the Holdb_dr bit in the +* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION +* is the option to be used for setting this bit in the +* configuration register. +* The XQspiPs_PolledTransfer function has been updated +* to fill the data to fifo depth. +* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ. +* Added macros for Set/Get Rx Watermark. Changed QSPI +* Enable/Disable macro argument from BaseAddress to +* Instance Pointer. Added DelayNss argument to SetDelays +* and GetDelays API's. +* Created macros XQspiPs_IsManualStart and +* XQspiPs_IsManualChipSelect. +* Changed QSPI transfer logic for polled and interrupt +* modes to be based on filled tx fifo count and receive +* based on it. RXNEMPTY interrupt is not used. +* Added assertions to XQspiPs_LqspiRead function. +* SetDelays and GetDelays API's include DelayNss parameter. +* Added defines for DelayNss,Rx Watermark,Interrupts +* which need write to clear. Removed Read zeros mask from +* LQSPI Config register. Renamed Fixed burst error to +* data FSM error in LQSPI Status register. +* +* 2.02a hk 05/07/13 Added ConnectionMode to config structure. +* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel +* Added enable and disable to the XQspiPs_LqspiRead() function +* Removed XQspi_Reset() in Set_Options() function when +* LQSPI_MODE_OPTION is set. +* Added instructions for bank selection, die erase and +* flag status register to the flash instruction table +* Handling for instructions not in flash instruction +* table added. Checking for Tx FIFO empty when switching from +* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with +* byte count 3 (spansion), instruction size and TXD register +* changed accordingly. CR# 712502 and 703869. +* Added prefix to constant definitions for ConnectionMode +* Added (\#ifdef linear base address) in the Linear read function. +* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to +* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in +* XQspiPs_LqspiRead function. Fix for CR#718141. +* +* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of +* thresholds. This is to improve performance. +* Added API's for QSPI reset and +* linear mode initialization for boot. +* Added RX and TX threshold reset to one in XQspiPs_Abort. +* Added RX threshold reset(1) after transfer in polled and +* interrupt transfers. Made changes to make sure threshold +* change is done only when no transfer is in progress. +* Updated linear init API for parallel and stacked modes. +* CR#737760. +* 3.1 hk 08/13/14 When writing to the configuration register, set/reset +* required bits leaving reserved bits untouched. CR# 796813. +* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because +* controller does not update FIFO status flags as expected +* when thresholds are used. +* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards +* to remove compilation warnings. CR# 868893. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of qspips +* examples to recognize it as documentation block +* and modified filename tag in +* xqspips_dual_flash_stack_lqspi_example.c to include it in +* doxygen examples. +* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file +* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC. +* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts. +* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357) +* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs, +* to wait for the on going operation to complete before +* performing the next operation. +* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve +* configuration register values of both the Flashes in dual +* parellel connection. +* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer() +* and XQspiPs_Transfer() APIs. +* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and +* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid +* data when RX buffer is not NULL. +* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution. +* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow. +* +*+* +******************************************************************************/ +#ifndef XQSPIPS_H /* prevent circular inclusions */ +#define XQSPIPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspips_hw.h" +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 1.00 sdm 11/25/10 First release +* 2.00a ka 07/25/12 Added a few register defines for CR 670297 +* and removed some defines of reserved fields for +* CR 671468 +* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr +* bit in Configuration register. +* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts +* which need write to clear. Removed Read zeros mask from +* LQSPI Config register. +* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and +* linear mode initialization for boot. Added related +* constant definitions. +* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset +* required bits leaving reserved bits untouched. CR# 796813. +* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because +* controller does not update FIFO status flags as expected +* when thresholds are used. +* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357) +* +*+* +******************************************************************************/ +#ifndef XQSPIPS_HW_H /* prevent circular inclusions */ +#define XQSPIPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an QSPI device. + * @{ + */ +#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */ +#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */ +#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */ +#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */ +#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */ +#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */ +#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */ +#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */ +#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */ +#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */ +#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */ +#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */ +#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */ +#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */ +#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */ +#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */ +#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */ +#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */ +#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */ +#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */ + +/* @} */ + +/** @name Configuration Register + * + * This register contains various control bits that + * affect the operation of the QSPI device. Read/Write. + * @{ + */ + +#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */ +#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */ +#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */ +#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start + Enable */ +#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */ +#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */ +#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */ +#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be + transferred */ +#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */ +#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */ +#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */ + +#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */ +#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */ + +#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */ + +#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ + +#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */ + +/* Deselect the Slave select line and set the transfer size to 32 at reset */ +#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \ + XQSPIPS_CR_SSCTRL_MASK | \ + XQSPIPS_CR_DATA_SZ_MASK | \ + XQSPIPS_CR_MSTREN_MASK | \ + XQSPIPS_CR_SSFORCE_MASK | \ + XQSPIPS_CR_HOLD_B_MASK +#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \ + XQSPIPS_CR_CPHA_MASK | \ + XQSPIPS_CR_PRESC_MASK | \ + XQSPIPS_CR_MANSTRTEN_MASK | \ + XQSPIPS_CR_MANSTRT_MASK | \ + XQSPIPS_CR_ENDIAN_MASK | \ + XQSPIPS_CR_REF_CLK_MASK +/* @} */ + + +/** @name QSPI Interrupt Registers + * + * QSPI Status Register + * + * This register holds the interrupt status flags for an QSPI device. Some + * of the flags are level triggered, which means that they are set as long + * as the interrupt condition exists. Other flags are edge triggered, + * which means they are set once the interrupt condition occurs and remain + * set until they are cleared by software. The interrupts are cleared by + * writing a '1' to the interrupt bit position in the Status Register. + * Read/Write. + * + * QSPI Interrupt Enable Register + * + * This register is used to enable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Disable Register + * + * This register is used to disable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Mask Register + * + * This register shows the enabled/disabled interrupts of an QSPI device. + * Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Channel Interrupt Status Register + * @{ + */ + +#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */ +#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */ +#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */ +#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */ +#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */ +#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */ +#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts + mask */ +#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which + need write to clear */ +#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */ +#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */ +/* @} */ + + +/** @name Enable Register + * + * This register is used to enable or disable an QSPI device. + * Read/Write + * @{ + */ +#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */ +/* @} */ + + +/** @name Delay Register + * + * This register is used to program timing delays in + * slave mode. Read/Write + * @{ + */ +#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select + between two words mask */ +#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select + between two words shift */ +#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers + mask */ +#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */ +#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */ +#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */ +#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */ +/* @} */ + +/** @name Slave Idle Count Registers + * + * This register defines the number of pclk cycles the slave waits for a the + * QSPI clock to become stable in quiescent state before it can detect the start + * of the next transfer in CPHA = 1 mode. + * Read/Write + * + * @{ + */ +#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */ +/* @} */ + + +/** @name Transmit FIFO Watermark Register + * + * This register defines the watermark setting for the Transmit FIFO. + * + * @{ + */ +#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */ +#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark + * register reset value */ + +/* @} */ + +/** @name Receive FIFO Watermark Register + * + * This register defines the watermark setting for the Receive FIFO. + * + * @{ + */ +#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */ +#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark + * register reset value */ + +/* @} */ + +/** @name FIFO Depth + * + * This macro provides the depth of transmit FIFO and receive FIFO. + * + * @{ + */ +#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */ +/* @} */ + + +/** @name Linear QSPI Configuration Register + * + * This register contains various control bits that + * affect the operation of the Linear QSPI controller. Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */ +#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */ +#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */ +#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */ +#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */ +#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */ +#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O + or quad I/O */ +#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes + between addr and return + read data */ +#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ +#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */ +/* @} */ + +/** @name Linear QSPI Status Register + * + * This register contains various status bits of the Linear QSPI controller. + * Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error + received */ +#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command + received */ +/* @} */ + + +/** @name Loopback Delay Adjust Register + * + * This register contains various bit masks of Loopback Delay Adjust Register. + * + * @{ + */ + +#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */ + +/* @} */ + + +/** @name SLCR Register + * + * Register offsets from SLCR base address. + * + * @{ + */ + +#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */ +#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */ +#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */ +#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */ + +/* @} */ + + +/** @name SLCR Register + * + * Bit Masks of above SLCR Registers . + * + * @{ + */ + +#ifndef XPAR_XSLCR_0_BASEADDR +#define XPAR_XSLCR_0_BASEADDR 0xF8000000 +#endif +#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/ +#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */ +#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */ + +/* @} */ + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPs_In32 Xil_In32 +#define XQspiPs_Out32 Xil_Out32 +#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XQspiPs_ReadReg(BaseAddress, RegOffset) \ + XQspiPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/************************** Function Prototypes ******************************/ + +/* + * Functions implemented in xqspips_hw.c + */ +void XQspiPs_ResetHw(u32 BaseAddress); +void XQspiPs_LinearInit(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xreg_cortexa9.h new file mode 100644 index 0000000..0d2c7b1 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xreg_cortexa9.h @@ -0,0 +1,578 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xreg_cortexa9.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, ARMCC compiler. +* +* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- -------- -------- ----------------------------------------------- +* 1.00a ecm/sdm 10/20/09 First release +* 9.0 mus 07/29/23 Added definitions for processor affinity register. +*+* +******************************************************************************/ +#ifndef XREG_CORTEXA9_H +#define XREG_CORTEXA9_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + *@cond nocomments + */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ +#if defined (__GNUC__) || defined (__ICCARM__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" +#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" +#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + +#if defined (__GNUC__) || defined (__ICCARM__) +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +#else +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" +#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" +#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" + +#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" +#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" +#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" +#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" +#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" +#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" +#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" +#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" +#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" + +#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" +#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" + +#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" +#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" +#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" + +#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" +#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" + +#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" + +#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" + +#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" +#endif + +/* Affinity register bits */ +#define XREG_MPIDR_MASK 0xFFFFFFFFU +#define XREG_MPIDR_AFFINITY0_MASK 0x3U +#define XREG_MPIDR_AFFINITY0_SHIFT 0x0U +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +/** + *@endcond + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA9_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscugic.h new file mode 100644 index 0000000..1230208 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscugic.h @@ -0,0 +1,725 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xscugic.h +* @addtogroup scugic Overview +* @{ +* @details +* +* The generic interrupt controller driver component. +* +* The interrupt controller driver uses the idea of priority for the various +* handlers. Priority is an integer within the range of 1 and 31 inclusive with +* default of 1 being the highest priority interrupt source. The priorities +* of the various sources can be dynamically altered as needed through +* hardware configuration. +* +* The generic interrupt controller supports the following +* features: +* +* - specific individual interrupt enabling/disabling +* - specific individual interrupt acknowledging +* - attaching specific callback function to handle interrupt source +* - assigning desired priority to interrupt source if default is not +* acceptable. +* +* Details about connecting the interrupt handler of the driver are contained +* in the source file specific to interrupt processing, xscugic_intr.c. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* Interrupt Vector Tables +* +* The device ID of the interrupt controller device is used by the driver as a +* direct index into the configuration data table. The user should populate the +* vector table with handlers and callbacks at run-time using the +* XScuGic_Connect() and XScuGic_Disconnect() functions. +* +* Each vector table entry corresponds to a device that can generate an +* interrupt. Each entry contains an interrupt handler function and an +* argument to be passed to the handler when an interrupt occurs. The +* user must use XScuGic_Connect() when the interrupt handler takes an +* argument other than the base address. +* +* Nested Interrupts Processing +* +* Nested interrupts are not supported by this driver. +* +* NOTE: +* The generic interrupt controller is not a part of the snoop control unit +* as indicated by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 1.00a drg 01/19/00 First release +* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed. +* The HandlerTable (of type XScuGic_VectorTableEntry) is +* moved to XScuGic_Config structure from XScuGic structure. +* +* The "Config" entry in XScuGic structure is made as +* pointer for better efficiency. +* +* A new file named as xscugic_hw.c is now added. It is +* to implement low level driver routines without using +* any xscugic instance pointer. They are useful when the +* user wants to use xscugic through device id or +* base address. The driver routines provided are explained +* below. +* XScuGic_DeviceInitialize that takes device id as +* argument and initializes the device (without calling +* XScuGic_CfgInitialize). +* XScuGic_DeviceInterruptHandler that takes device id +* as argument and calls appropriate handlers from the +* HandlerTable. +* XScuGic_RegisterHandler that registers a new handler +* by taking xscugic hardware base address as argument. +* LookupConfigByBaseAddress is used to return the +* corresponding config structure from XScuGic_ConfigTable +* based on the scugic base address passed. +* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config +* structure. +* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to +* *_hw.h +* Added APIs +* - XScuGic_SetPriTrigTypeByDistAddr() +* - XScuGic_GetPriTrigTypeByDistAddr() +* (CR 702687) +* Added support to direct interrupts to the appropriate CPU. Earlier +* interrupts were directed to CPU1 (hard coded). Now depending +* upon the CPU selected by the user (xparameters.h), interrupts +* will be directed to the relevant CPU. This fixes CR 699688. +* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in +* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings. +* Moved functions XScuGic_SetPriTrigTypeByDistAddr and +* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c. +* This is fix for CR#705621. +* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to +* xparameters.h. Fix for CR's 690505, 708928 & 719359. +* 2.0 adk 12/10/13 Updated as per the New Tcl API's +* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file. +* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The +* distributor is left uninitialized for Zynq AMP. It is assumed +* that the distributor will be initialized by Linux master. However +* for CortexR5 case, the earlier code is left unchanged where the +* the interrupt processor target registers in the distributor is +* initialized with the corresponding CPU ID on which the application +* built over the scugic driver runs. +* These changes fix CR#937243. +* +* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify +* the flow and avoid code duplication. Changes are made for +* USE_AMP use case for R5. In a scenario (in R5 split mode) when +* one R5 is operating with A53 in open amp config and other +* R5 running baremetal app, the existing code +* had the potential to stop the whole AMP solution to work (if +* for some reason the R5 running the baremetal app tasked to +* initialize the Distributor hangs or crashes before initializing). +* Changes are made so that the R5 under AMP first checks if +* the distributor is enabled or not and if not, it does the +* standard Distributor initialization. +* This fixes the CR#952962. +* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro +* definitions of scugic in xparameters.h +* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected +* through util_reduced_vector IP(OR gate) +* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize +* the HandlerTable in XScuGic_ConfigTable to 0, it removes +* the compilation warning in xscugic_g.c. Fix for CR#978736. +* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical +* definitions for pl to ps interrupts.Fix for CR#980534 +* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and +* XScuGic_InterruptUnmapFromCpu, These API's can be used +* by applications to unmap specific/all interrupts from +* target CPU. +* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations +* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through +* XScuGic_SoftwareIntr API +* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all +* available CPUs by default. This was breaking AMP +* behavior. Instead every time an interrupt enable +* request is received, the interrupt was mapped to +* the respective CPU. There were several other changes +* made to implement this. This set of changes was to +* fix CR-1024716. +* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and +* XScuGic_MarkCoreAwake to mark processor core as +* asleep or awake. Fix for CR#1027220. +* 4.5 asa 03/07/21 Included a header file xil_spinlock.h to ensure that +* GIC driver can use newly introduced spinlock +* functionality. +* 4.6 sk 08/05/21 Fix scugic misrac violations. +* 4.7 dp 11/22/21 Added new API XScuGic_IsInitialized() to check and return +* the GIC initialization status. +* 5.0 mus 22/02/22 Add support for VERSAL NET +* adk 04/18/22 Replace infinite while loops in the examples with +* Xil_WaitForEventSet() API. +* dp 04/25/22 Correct Trigger index calculation in macro +* XScuGic_Get_Rdist_Int_Trigger_Index +* 5.0 dp 11/07/22 Add macros for accessing the GIC Binary Point and +* Running Priority registers of Cortex-R52. +* 5.1 mus 02/13/23 Updated XScuGic_CfgInitialize, XScuGic_Enable and +* XScuGic_Disable to support interrupts on each core +* of all CortexA78/CortexR52 clusters in VERSAL NET SoC. +* While at it, modified interrupt routing logic to make +* use of CPU affinity register instead of XPAR_CPU_ID macro. +* Also, XScuGic_CfgInitialize has been updated to find +* redistributor base address of core on which API is +* executed, redistributor address will be stored in newly +* added member of XScuGic data structure "RedistBaseAddr". +* It fixes CR#1150432. +* 5.2 ml 03/02/23 Add description to fix Doxygen warnings. +* 5.2 adk 04/14/23 Added support for system device-tree flow. +*+* +******************************************************************************/ + +#ifndef XSCUGIC_H /**< prevent circular inclusions */ +#define XSCUGIC_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_io.h" +#include "xscugic_hw.h" +#include "xil_exception.h" +#include "xil_spinlock.h" + +/************************** Constant Definitions *****************************/ + +/** + * @name EFUSE status Register information + * EFUSE Status Register + * @{ + */ +#define EFUSE_STATUS_OFFSET 0x10 +#define EFUSE_STATUS_CPU_MASK 0x80 + +#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) +#define ARMA9 /**< ARMA9 macro to identify cortexA9 */ +#endif + +/** + * @name GICD_CTLR Register information + * GICD_CTLR Status Register + * @{ + */ +#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20 +#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10 + +#if defined (VERSAL_NET) +#define XSCUGIC_CLUSTERID_MASK 0xF0U +#define XSCUGIC_COREID_MASK 0xFU +#define XSCUGIC_CLUSTERID_SHIFT 4U +#define XSCUGIC_COREID_SHIFT 0U + +#define XSCUGIC_SGI1R_AFFINITY1_SHIFT 16U +#define XSCUGIC_SGI1R_AFFINITY2_SHIFT 32U + +#define XSCUGIC_IROUTER_AFFINITY1_SHIFT 8U +#define XSCUGIC_IROUTER_AFFINITY2_SHIFT 16U + +#define XSCUGIC_IROUTER_IRM_MASK 0x80000000U +#endif + +/**************************** Type Definitions *******************************/ + +/* The following data type defines each entry in an interrupt vector table. + * The callback reference is the base address of the interrupting device + * for the low level driver and an instance pointer for the high level driver. + */ +typedef struct +{ + Xil_InterruptHandler Handler; /**< Interrupt Handler */ + void *CallBackRef; /**< CallBackRef is the callback reference passed in + by the upper layer when setting the Interrupt + handler for specific interrupt ID, and it will + passed back to Interrupt handler when it is + invoked. */ +} XScuGic_VectorTableEntry; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct +{ +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ + u32 DistBaseAddress; /**< Distributor Register base address */ +#else + char *Name; /**< Compatible string */ + u32 DistBaseAddress; /**< Distributor Register base address */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ +#endif + XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< + Vector table of interrupt handlers */ +} XScuGic_Config; + +/** + * The XScuGic driver instance data. The user is required to allocate a + * variable of this type for every intc device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct +{ + XScuGic_Config *Config; /**< Configuration table entry */ +#if defined (GICv3) + UINTPTR RedistBaseAddr; +#endif + u32 IsReady; /**< Device is initialized and ready */ + u32 UnhandledInterrupts; /**< Intc Statistics */ +} XScuGic; + +/************************** Variable Definitions *****************************/ + +extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ + (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) + +#if defined (GICv3) +/****************************************************************************/ +/** +* +* Write the given ReDistributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(InstancePtr->RedistBaseAddr, RegOffset, (u32)Data)) + +/****************************************************************************/ +/** +* +* Read the given ReDistributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(InstancePtr->RedistBaseAddr, RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given ReDistributor SGI PPI Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(InstancePtr->RedistBaseAddr + \ + XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given ReDistributor SGI PPI Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(InstancePtr->RedistBaseAddr + XSCUGIC_RDIST_SGI_PPI_OFFSET, \ + RegOffset)) + +#if defined(ARMR52) +#define XREG_ICC_SRE_EL1 "p15, 0, %0, c12, c12, 5" +#define XREG_ICC_IGRPEN0_EL1 "p15, 0, %0, c12, c12, 6" +#define XREG_ICC_IGRPEN1_EL1 "p15, 0, %0, c12, c12, 7" +#define XREG_ICC_SGI0R_EL1 "p15, 2, %0, %1, c12" +#define XREG_ICC_SGI1R_EL1 "p15, 0, %0, %1, c12" +#define XREG_ICC_PMR_EL1 "p15, 0, %0, c4, c6, 0" +#define XREG_ICC_IAR0_EL1 "p15, 0, %0, c12, c8, 0" +#define XREG_ICC_IAR1_EL1 "p15, 0, %0, c12, c12, 0" +#define XREG_ICC_EOIR0_EL1 "p15, 0, %0, c12, c8, 1" +#define XREG_ICC_EOIR1_EL1 "p15, 0, %0, c12, c12, 1" +#define XREG_IMP_CBAR "p15, 1, %0, c15, c3, 0" +#define XREG_ICC_BPR0_EL1 "p15, 0, %0, c12, c8, 3" +#define XREG_ICC_BPR1_EL1 "p15, 0, %0, c12, c12, 3" +#define XREG_ICC_RPR_EL1 "p15, 0, %0, c12, c11, 3" +#else +#define XREG_ICC_SRE_EL1 "S3_0_C12_C12_5" +#define XREG_ICC_SRE_EL3 "S3_6_C12_C12_5" +#define XREG_ICC_IGRPEN0_EL1 "S3_0_C12_C12_6" +#define XREG_ICC_IGRPEN1_EL1 "S3_0_C12_C12_7" +#define XREG_ICC_IGRPEN1_EL3 "S3_6_C12_C12_7" +#define XREG_ICC_SGI0R_EL1 "S3_0_C12_C11_7" +#define XREG_ICC_SGI1R_EL1 "S3_0_C12_C11_5" +#define XREG_ICC_PMR_EL1 "S3_0_C4_C6_0" +#define XREG_ICC_IAR0_EL1 "S3_0_C12_C8_0" +#define XREG_ICC_IAR1_EL1 "S3_0_C12_C12_0" +#define XREG_ICC_EOIR0_EL1 "S3_0_C12_C8_1" +#define XREG_ICC_EOIR1_EL1 "S3_0_C12_C12_1" +#endif +/****************************************************************************/ +/** +* This function enables system register interface for GIC CPU Interface +* +* @param value to be written +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined (__aarch64__) +#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcpnotoken(XREG_ICC_SRE_EL3, 0xF); +#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcpnotoken(XREG_ICC_SRE_EL1, 0xF); +#elif defined (ARMR52) +#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(XREG_ICC_SRE_EL1, 0xF); +#endif +/****************************************************************************/ +/** +* This function enables Grou0 interrupts +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined(ARMR52) +#define XScuGic_Enable_Group0_Interrupts() mtcp(XREG_ICC_IGRPEN0_EL1,0x1); +#else +#define XScuGic_Enable_Group0_Interrupts() mtcpnotoken(XREG_ICC_IGRPEN0_EL1,0x1); +#endif +/****************************************************************************/ +/** +* This function enables Group1 interrupts +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined (ARMR52) + +#define XScuGic_Enable_Group1_Interrupts() \ + mtcp (XREG_ICC_IGRPEN1_EL1, 0x1 | mfcp(XREG_ICC_IGRPEN1_EL1) ); +#elif EL1_NONSECURE +#define XScuGic_Enable_Group1_Interrupts() \ + mtcpnotoken(XREG_ICC_IGRPEN1_EL1, 0x1 | mfcpnotoken(XREG_ICC_IGRPEN1_EL1) ); +#else +#define XScuGic_Enable_Group1_Interrupts() \ + mtcpnotoken(XREG_ICC_IGRPEN1_EL3, 0x1 | mfcpnotoken(XREG_ICC_IGRPEN1_EL3) ); +#endif +/****************************************************************************/ +/** +* This function writes to ICC_SGI0R_EL1 +* +* @param value to be written +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined(ARMR52) +#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp2(XREG_ICC_SGI0R_EL1,val) +#else +#define XScuGic_WriteICC_SGI0R_EL1(val) mtcpnotoken(XREG_ICC_SGI0R_EL1,val) +#endif + +/****************************************************************************/ +/** +* This function writes to ICC_SGI1R_EL1 +* +* @param value to be written +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined(ARMR52) +#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp2(XREG_ICC_SGI1R_EL1,val) +#else +#define XScuGic_WriteICC_SGI1R_EL1(val) mtcpnotoken(XREG_ICC_SGI1R_EL1,val) +#endif + +/****************************************************************************/ +/** +* This function reads ICC_SGI1R_EL1 register +* +* @param None +* +* @return Value of ICC_SGI1R_EL1 register +* +* @note None. +* +*****************************************************************************/ +#if defined (ARMR52) +#define XScuGic_ReadICC_SGI1R_EL1() mfcp(XREG_ICC_SGI1R_EL1) +#else +#define XScuGic_ReadICC_SGI1R_EL1() mfcpnotoken(XREG_ICC_SGI1R_EL1) +#endif +/****************************************************************************/ +/** +* This function sets interrupt priority filter +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined (ARMR52) +#define XScuGic_set_priority_filter(val) mtcp(XREG_ICC_PMR_EL1, val) +#else +#define XScuGic_set_priority_filter(val) mtcpnotoken(XREG_ICC_PMR_EL1, val) +#endif +/****************************************************************************/ +/** +* This function returns interrupt id of highest priority pending interrupt +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined(ARMR52) +#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR1_EL1) +#elif EL3 +#define XScuGic_get_IntID() mfcpnotoken(XREG_ICC_IAR0_EL1) +#else +#define XScuGic_get_IntID() mfcpnotoken(XREG_ICC_IAR1_EL1) +#endif +/****************************************************************************/ +/** +* This function acks the interrupt +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#if defined(ARMR52) +#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR1_EL1,val) +#elif EL3 +#define XScuGic_ack_Int(val) mtcpnotoken(XREG_ICC_EOIR0_EL1,val) +#else +#define XScuGic_ack_Int(val) mtcpnotoken(XREG_ICC_EOIR1_EL1,val) +#endif +/****************************************************************************/ +/** +* This macro returns bit position for the specific interrupt's trigger type +* configuration within GICR_ICFGR0/GICR_ICFGR1 register +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) ((Int_Id%16) * 2U) +#endif +/************************** Function Prototypes ******************************/ + +/* + * Required functions in xscugic.c + */ + +s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); + +void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); +void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); + +s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier); + +void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); +#ifndef SDT +u8 XScuGic_IsInitialized(u32 DeviceId); +#else +u8 XScuGic_IsInitialized(u32 BaseAddress); +#endif +#ifndef SDT +/* + * Lookup configuration by using DeviceId + */ +XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); +/* + * Lookup configuration by using BaseAddress + */ +XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress); +#else +XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddr); +#endif + +/* + * Interrupt functions in xscugic_intr.c + */ +void XScuGic_InterruptHandler(XScuGic *InstancePtr); + +/* + * Self-test functions in xscugic_selftest.c + */ +s32 XScuGic_SelfTest(XScuGic *InstancePtr); + +#if defined (GICv3) +void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr); +void XScuGic_MarkCoreAwake(XScuGic *InstancePtr); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscugic_hw.h new file mode 100644 index 0000000..139bf8a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscugic_hw.h @@ -0,0 +1,762 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xscugic_hw.h +* @addtogroup scugic Overview +* @{ +* +* This header file contains identifiers and HW access functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The driver functions/APIs are defined in xscugic.h. +* +* This GIC device has two parts, a distributor and CPU interface(s). Each part +* has separate register definition sections. +* +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------------- +* 1.00a drg 01/19/10 First release +* 1.01a sdm 11/09/11 "xil_exception.h" added as include. +* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are +* added to enable or disable interrupts based on +* Distributor Register base address. Normally users use +* XScuGic instance and call XScuGic_Enable or +* XScuGic_Disable to enable/disable interrupts. These +* new macros are provided when user does not want to +* use an instance pointer but still wants to enable or +* disable interrupts. +* Function prototypes for functions (present in newly +* added file xscugic_hw.c) are added. +* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR +* 702687). +* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes +* XScuGic_SetPriTrigTypeByDistAddr and +* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h +* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for +* Zynq Ultrascale Mp +* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance. +* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value +* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK +* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr +* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These +* API's can be used by applications to unmap specific/all +* interrupts from target CPU. It fixes CR#992490. +* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations +* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and +* XScuGic_DisableIntr. These are now C functions. This +* change was to fix CR-1024716. +* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal. +* 4.6 sk 06/07/21 Delete the commented macro code to fix the MISRA-C warning. +* 4.6 sk 08/05/21 Fix Scugic Misrac violations. +* 4.7 sk 12/10/21 Update XSCUGIC_SPI_INT_ID_START macro from signed to unsigned +* to fix misrac violation. +* 4.7 mus 03/17/22 GICv3 coupled with A72 has different redistributor for +* each core, and each redistributor has different address, +* Updated #define for re-distributor address to have correct +* value based on the cpu number. It fixes CR#1126156. +* 5.0 mus 22/02/22 Added support for VERSAL NET +* 5.1 mus 02/13/23 Added #defines required for logic to find redistributor +* based address for specific CPU core. Also, added new macro +* XScuGic_ReadReg64 to read 64 bit value from specific address. +* 5.1 mus 02/15/23 Added support for VERSAL_NET APU and RPU GIC. +* 5.2 ml 03/02/23 Add description to fix Doxygen warnings. +* 5.2 mus 03/26/23 Fixed calculation for XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC. +*+* +******************************************************************************/ + +#ifndef XSCUGIC_HW_H /**< prevent circular inclusions */ +#define XSCUGIC_HW_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ +#if (defined (versal) && !defined(ARMR5)) || defined (ARMR52) +#define GICv3 +#endif + +#if defined (VERSAL_NET) && ! defined (ARMR52) +#define GIC600 +#endif + +#if defined (VERSAL_NET) +#if defined (ARMR52) +#define XSCUGIC_NUM_OF_CORES_PER_CLUSTER 2U +#else +#define XSCUGIC_NUM_OF_CORES_PER_CLUSTER 4U +#endif +#endif + +/* + * The maximum number of interrupts supported by the hardware. + */ +#ifdef PLATFORM_ZYNQ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /**< Maximum number of + interrupt defined by + Zynq */ +#elif defined (VERSAL_NET) +#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /**< Maximum number of + interrupt sources in + VERSAL NET */ +#elif defined (versal) +#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U /**< Maximum number of + interrupt sources in + VERSAL */ +#else +#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /**< Maximum number of + interrupt defined by + Zynq Ultrascale Mp */ +#endif + +#define XSCUGIC_SPI_INT_ID_START 0x20U /**< First Interrupt Id for + SPI interrupts. */ + +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U /**< The maximum priority value + that can be used in + the GIC. */ +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U /**< The Interrupt + priority mask value */ + +/** @name Distributor Interface Register Map + * + * Define the offsets from the base address for all Distributor registers of + * the interrupt controller, some registers may be reserved in the hardware + * device. + * @{ + */ +#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable + Register */ +#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller + Type Register */ +#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID + Register */ +#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security + Register */ +#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set + Register */ +#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */ +#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set + Register */ +#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear + Register */ +#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */ +#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */ +#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target + Register 0x800-0x8FB */ +#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */ +#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register + 0xd04-0xd7C */ +#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration + Register */ +#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered + Interrupt Register */ +#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */ +#if defined (GICv3) +#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */ +#else +#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */ +#endif +/* @} */ + +/** @name Distributor Enable Register + * Controls if the distributor response to external interrupt inputs. + * @{ + */ +#if defined (GICv3) +#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */ +#else +#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */ +#endif +/* @} */ + +/** @name Interrupt Controller Type Register + * @{ + */ +#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable + Shared Peripheral + Interrupts*/ +#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/ +#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */ +#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */ +/* @} */ + +/** @name Implementor ID Register + * Implementor and revision information. + * @{ + */ +#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */ +#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */ +/* @} */ + +/** @name Interrupt Security Registers + * Each bit controls the security level of an interrupt, either secure or non + * secure. These registers can only be accessed using secure read and write. + * There are registers for each of the CPU interfaces at offset 0x080. A + * register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x084. + * @{ + */ +#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Set Register + * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a + * bit to 0. + * There are registers for each of the CPU interfaces at offset 0x100. With up + * to 8 registers aliased to the same address. A register set for the SPI + * interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x104. + * @{ + */ +#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Clear Register + * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and + * sets the corresponding bit to 0. + * There are registers for each of the CPU interfaces at offset 0x180. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x184. + * @{ + */ +#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Set Register + * Each bit controls the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets + * an interrupt to the pending state. + * There are registers for each of the CPU interfaces at offset 0x200. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x204. + * @{ + */ +#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Clear Register + * Each bit can clear the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 + * clears the pending state of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x280. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x284. + * @{ + */ +#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Active Status Register + * Each bit provides the Active status of an interrupt, a + * 0 is not Active, a 1 is Active. This is a read only register. + * There are registers for each of the CPU interfaces at offset 0x300. With up + * to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x380. + * @{ + */ +#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Priority Level Register + * Each byte in a Priority Level Register sets the priority level of an + * interrupt. Reading the register provides the priority level of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x400 through + * 0x41C. With up to 8 registers aliased to each address. + * 0 is highest priority, 0xFF is lowest. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x420. + * @{ + */ +#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an + INT_ID */ +#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority + actually the lowest priority*/ +/* @} */ + +/** @name SPI Target Register 0x800-0x8FB + * Each byte references a separate SPI and programs which of the up to 8 CPU + * interfaces are sent a Pending interrupt. + * There are registers for each of the CPU interfaces at offset 0x800 through + * 0x81C. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x820. + * + * This driver does not support multiple CPU interfaces. These are included + * for complete documentation. + * @{ + */ +#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/ +#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/ +#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/ +#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/ +#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/ +#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/ +#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/ +#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/ +/* @} */ + +/** @name Interrupt Configuration Register 0xC00-0xCFC + * The interrupt configuration registers program an SFI to be active HIGH level + * sensitive or rising edge sensitive. + * Each bit pair describes the configuration for an INT_ID. + * SFI Read Only b10 always + * PPI Read Only depending on how the PPIs are configured. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive + * SPI LSB is read only. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive/ + * There are registers for each of the CPU interfaces at offset 0xC00 through + * 0xC04. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0xC08. + * @{ + */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< Interrupt configuration Mask */ +/* @} */ + +/** @name PPI Status Register + * Enables an external AMBA master to access the status of the PPI inputs. + * A CPU can only read the status of its local PPI signals and cannot read the + * status for other CPUs. + * This register is aliased for each CPU interface. + * @{ + */ +#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */ +#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */ +#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */ +#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */ +#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */ +#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */ +#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */ +#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */ +#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */ +#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */ +#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */ +#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */ +#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */ +#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */ +#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */ +#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */ +/* @} */ + +/** @name SPI Status Register 0xd04-0xd7C + * Enables an external AMBA master to access the status of the SPI inputs. + * There are up to 63 registers if the maximum number of SPI inputs are + * configured. + * @{ + */ +#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI + input */ +/* @} */ + +/** @name AHB Configuration Register + * Provides the status of the CFGBIGEND input signal and allows the endianness + * of the GIC to be set. + * @{ + */ +#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, + 1-GIC uses Big Endian */ +#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, + 1-use the AHB_END bit */ +#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */ + +/* @} */ + +/** @name Software Triggered Interrupt Register + * Controls issuing of software interrupts. + * @{ + */ +#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U +#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter + b00-Use the target List + b01-All CPUs except requester + b10-To Requester + b11-reserved */ +#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */ +#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */ +#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID + signaled to the CPU*/ +/* @} */ + +/** @name CPU Interface Register Map + * + * Define the offsets from the base address for all CPU registers of the + * interrupt controller, some registers may be reserved in the hardware device. + * @{ + */ +#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control + Register */ +#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */ +#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */ +#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */ +#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */ +#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */ +#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt + Register */ +#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure + Binary Point Register */ + +/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written + * to. */ +/* @} */ + + +/** @name Control Register + * CPU Interface Control register definitions + * All bits are defined here although some are not available in the non-secure + * mode. + * @{ + */ +#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, + 0=separate registers, + 1=both use bin_pt_s */ +#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure + interrupts, + 0= use IRQ for both, + 1=Use FIQ for secure, IRQ for non*/ +#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */ +#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */ +#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */ +/* @} */ + + +/** @name Binary Point Register + * Binary Point register definitions + * @{ + */ + +#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value + Value Secure Non-secure + b000 0xFE 0xFF + b001 0xFC 0xFE + b010 0xF8 0xFC + b011 0xF0 0xF8 + b100 0xE0 0xF0 + b101 0xC0 0xE0 + b110 0x80 0xC0 + b111 0x00 0x80 + */ +/*@}*/ + +/** @name Interrupt Acknowledge Register + * Interrupt Acknowledge register definitions + * Identifies the current Pending interrupt, and the CPU ID for software + * interrupts. + */ +#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */ +/* @} */ + +/** @name End of Interrupt Register + * End of Interrupt register definitions + * Allows the CPU to signal the GIC when it completes an interrupt service + * routine. + */ +#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */ + +/* @} */ + +/** @name Running Priority Register + * Running Priority register definitions + * Identifies the interrupt priority level of the highest priority active + * interrupt. + */ +#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */ +/* @} */ + +#if defined (GICv3) +#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U +#endif +/* + * Highest Pending Interrupt register definitions + * Identifies the interrupt priority of the highest priority pending interrupt + */ +#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */ +/* @} */ +#if defined (GICv3) +/** @name ReDistributor Interface Register Map + * + * @{ + */ +#if defined (VERSAL_NET) && ! defined (ARMR52) +#define XSCUGIC_RDIST_START_ADDR 0xE2060000U +#define XSCUGIC_RDIST_END_ADDR 0xE2260000U +#elif defined (ARMR52) +#define XSCUGIC_RDIST_START_ADDR 0xE2100000U +#define XSCUGIC_RDIST_END_ADDR 0xE2130000U +#else +#define XSCUGIC_RDIST_START_ADDR 0xF9080000U +#define XSCUGIC_RDIST_END_ADDR 0xF90B0000U +#endif +#define XSCUGIC_RDIST_OFFSET 0x20000U /* offset between consecutive redistributors */ +#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x10000U /* offset between control redistributor and SGI/PPI redistributor */ +#define XSCUGIC_GICR_TYPER_AFFINITY_SHIFT 32U +#define XSCUGIC_GICR_TYPER_AFFINITY_MASK 0xFFFFFFFF00000000UL + +#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U +#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U +#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U + +#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U +#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U +#define XSCUGIC_RDIST_TYPER_OFFSET 0x8U +#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U +#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U + +#if defined (GIC600) +#define XSCUGIC_RDIST_PWRR_OFFSET 0x24U +#endif +/* + * GICR_IGROUPR register definitions + */ +#if EL3 +#define XSCUGIC_DEFAULT_SECURITY 0x0U +#else +#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU +#endif +/* + * GICR_WAKER register definitions + */ +#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7 +#define XSCUGIC_RDIST_PWRR_RDPD_MASK 0x1U +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the Interrupt Configuration Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Priority Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Routing Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8)) + +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U)) +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U)) + +/****************************************************************************/ +/** +* +* Read the Re-distributor Interrupt configuration register offset +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4)) + +/****************************************************************************/ +/** +* +* Read the Re-distributor Interrupt Priority register offset +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + ((InterruptID/4) * 4)) +/****************************************************************************/ +/** +* +* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* +* @param Register is the register offset for the clear/enable bank. +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ + ((Register) + (((InterruptID)/32U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + +/****************************************************************************/ +/** +* +* Read the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be read +* +* @return The 64-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReadReg64(BaseAddress, RegOffset) \ + (Xil_In64((BaseAddress) + (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data)))) + + +/************************** Function Prototypes ******************************/ + +void XScuGic_DeviceInterruptHandler(void *DeviceId); +s32 XScuGic_DeviceInitialize(u32 DeviceId); +void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, + Xil_InterruptHandler IntrHandler, void *CallBackRef); +void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id); +void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id); +void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id); +#if defined(GICv3) +UINTPTR XScuGic_GetRedistBaseAddr(void); +#endif +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscutimer.h new file mode 100644 index 0000000..008b900 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscutimer.h @@ -0,0 +1,360 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xscutimer.h +* @addtogroup scutimer Overview +* @{ +* @details +* +* The timer driver supports the Cortex A9 private timer. +* +* The timer driver supports the following features: +* - Normal mode and Auto reload mode +* - Interrupts (Interrupt handler is not provided in this driver. Application +* has to register it's own handler) +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Timer. +* +* XScuTimer_CfgInitialize() API is used to initialize the Timer. The +* user needs to first call the XScuTimer_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuTimer_CfgInitialize() API. +* +* Interrupts +* +* The Timer hardware supports interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuTimer driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a nm 03/10/10 First release +* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue +* when the xstatus.h in the common driver overwrites +* the xstatus.h of the standalone BSP during the +* libgen. +* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 2.3 mus 08/31/20 Updated makefile to support parallel make and +* incremental builds, it would help to reduce compilation +* time. +* 2.5 dp 07/11/23 Add support for system device tree flow +*+* +******************************************************************************/ +#ifndef XSCUTIMER_H /* prevent circular inclusions */ +#define XSCUTIMER_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscutimer_hw.h" +#include "bspconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif + u32 BaseAddr; /**< Base address of the device */ +#ifdef XIL_INTERRUPT + u32 IntrId; + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */ +#endif +} XScuTimer_Config; + +/** + * The XScuTimer driver instance data. The user is required to allocate a + * variable of this type for every timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuTimer_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device timer is running */ +} XScuTimer; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Check if the timer has expired. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return +* - TRUE if the timer has expired. +* - FALSE if the timer has not expired. +* +* @note C-style signature: +* int XScuTimer_IsExpired(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_IsExpired(InstancePtr) \ + ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) & \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the timer. This macro will read the timer load register +* and writes the same value to load register to update the counter register. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_RestartTimer(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_RestartTimer(InstancePtr) \ + XScuTimer_LoadTimer((InstancePtr), \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET)) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_LoadTimer(InstancePtr, Value) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. It can be called at any +* time. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetCounterValue(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) + +/****************************************************************************/ +/** +* +* Disable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) + +/****************************************************************************/ +/** +* +* Enable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) + +/****************************************************************************/ +/** +* +* Disable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetInterruptStatus(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_ClearInterruptStatus(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscutimer_sinit.c + */ +#ifndef SDT +XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); +#else +XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr); +#endif + +/* + * Selftest function in xscutimer_selftest.c + */ +s32 XScuTimer_SelfTest(XScuTimer *InstancePtr); + +/* + * Interface functions in xscutimer.c + */ +s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr, + XScuTimer_Config *ConfigPtr, u32 EffectiveAddress); +void XScuTimer_Start(XScuTimer *InstancePtr); +void XScuTimer_Stop(XScuTimer *InstancePtr); +void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue); +u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscutimer_hw.h new file mode 100644 index 0000000..8eb1875 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscutimer_hw.h @@ -0,0 +1,262 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xscutimer_hw.h +* @addtogroup scutimer Overview +* @{ +* +* This file contains the hardware interface to the Timer. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a nm 03/10/10 First release +* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control +* and interrupt registers +* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue +* when the xstatus.h in the common driver overwrites +* the xstatus.h of the standalone BSP during the +* libgen. +* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +*+* +******************************************************************************/ +#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */ +#define XSCUTIMER_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */ +#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */ +#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */ +#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt + Status Register */ +/* @} */ + +/** @name Timer Control register + * This register bits control the prescaler, Intr enable, + * auto-reload and timer enable. + * @{ + */ + +#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */ +#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U +#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */ +#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */ +#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Timer counter register has reached zero. + * @{ + */ + +#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetLoadReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: +* u32 XScuTimer_GetLoadReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetLoadReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetCounterReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetCounterReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetControlReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: + u32 XScuTimer_GetControlReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetControlReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetIntrReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetIntrReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetIntrReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET) + +/****************************************************************************/ +/** +* +* Read from the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuTimer_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscuwdt.h new file mode 100644 index 0000000..9130e4d --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscuwdt.h @@ -0,0 +1,382 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xscuwdt.h +* @addtogroup Overview +* @{ +* @details +* +* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private +* watchdog timer hardware. +* +* The XScuWdt driver supports the following features: +* - Watchdog mode +* - Timer mode +* - Auto reload (timer mode only) +* +* The watchdog counter register is a down counter and starts decrementing when +* the watchdog is started. +* In watchdog mode, when the counter reaches 0, the Reset flag is set in the +* Reset status register and the WDRESETREQ pin is asserted, causing a system +* reset. The Reset flag is not reset by normal processor reset and is cleared +* when written with a value of 1. This enables the user to differentiate a +* normal reset and a reset caused by watchdog time-out. The user needs to call +* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out. +* +* The IsWdtExpired function can be used to check if the watchdog was the cause +* of the last reset. In this situation, call Initialize then call IsWdtExpired. +* If the result is true, watchdog timeout caused the last system reset. The +* application then needs to clear the Reset flag. +* +* In timer mode, when the counter reaches 0, the Event flag is set in the +* Interrupt status register and if interrupts are enabled, interrupt ID 30 is +* set as pending in the interrupt distributor. The IsTimerExpired function +* is used to check if the watchdog counter has decremented to 0 in timer mode. +* If auto-reload mode is enabled, the Counter register is automatically reloaded +* from the Load register. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Watchdog Timer. +* +* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The +* user needs to first call the XScuWdt_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuWdt_CfgInitialize() API. +* +* Interrupts +* +* The SCU Watchdog Timer supports interrupts in Timer mode. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuWdt driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a sdm 01/15/10 First release +* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue +* when the xstatus.h in the common driver overwrites +* the xstatus.h of the standalone BSP during the +* libgen. +* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 2.3 mus 08/31/20 Updated makefile to support parallel make and +* incremental builds. It would help to reduce compilaton +* time. +* 2.3 sne 09/16/20 Fixed MISRA-C violations. +* 2.4 sne 02/04/21 Fixed Doxygen warnings. +* 2.5 asa 07/18/23 Added support for system device tree based workflow +* decoupling flow. +*+* +******************************************************************************/ +#ifndef XSCUWDT_H /**< prevent circular inclusions */ +#define XSCUWDT_H /**< by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscuwdt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; /**< Unique name of the device */ +#endif + UINTPTR BaseAddr; /**< Register base address */ +#ifdef SDT + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif +} XScuWdt_Config; + +/** + * The XScuWdt driver instance data. The user is required to allocate a + * variable of this type for every watchdog/timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuWdt_Config Config;/**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device watchdog timer is running */ +} XScuWdt; + +/************************** Variable Definitions *****************************/ +extern XScuWdt_Config XScuWdt_ConfigTable[]; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog has timed-out and the last +* reset was caused by the watchdog reset. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsWdtExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_RST_STS_OFFSET) & \ + XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) + +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog counter has reached 0 in timer +* mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsTimerExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_ISR_OFFSET) & \ + XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the watchdog timer. This macro will read the watchdog load register +* and write the same value to load register to update the counter register. +* An application needs to call this function periodically to keep the watchdog +* from asserting the WDRESETREQ reset request output pin. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_RestartWdt(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_RestartWdt(InstancePtr) \ + XScuWdt_LoadWdt((InstancePtr), \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET))) + +/****************************************************************************/ +/** +* +* Write to the watchdog timer load register. This will also update the +* watchdog counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param Value is the value to be written to the Watchdog Load register. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuWdt_LoadWdt(InstancePtr, Value) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the +* Watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetWdMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetWdMode(InstancePtr) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) | \ + (XSCUWDT_CONTROL_WD_MODE_MASK))) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321 +* successively to the Watchdog Disable Register. +* The software must write 0x12345678 and 0x87654321 successively to the +* Watchdog Disable Register so that the watchdog mode bit in the Watchdog +* Control Register is set to zero. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetTimerMode(InstancePtr) \ + { \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE1); \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE2); \ + } + +/****************************************************************************/ +/** +* +* Get the contents of the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return Contents of the watchdog control register. +* +* @note C-style signature: + u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_GetControlReg(InstancePtr) \ + XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param ControlReg is the value to be written to the watchdog control +* register. +* +* @return None. +* +* @note C-style signature: + void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg) +* +******************************************************************************/ +#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, (ControlReg)) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_EnableAutoReload(InstancePtr) \ + XScuWdt_SetControlReg((InstancePtr), \ + (XScuWdt_GetControlReg(InstancePtr) | \ + XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscuwdt_sinit.c. + */ +#ifndef SDT +XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); +#else +XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress); +#endif + +/* + * Selftest function in xscuwdt_selftest.c + */ +s32 XScuWdt_SelfTest(XScuWdt *InstancePtr); + +/* + * Interface functions in xscuwdt.c + */ +s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr, + XScuWdt_Config *ConfigPtr, u32 EffectiveAddress); + +void XScuWdt_Start(XScuWdt *InstancePtr); + +void XScuWdt_Stop(XScuWdt *InstancePtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscuwdt_hw.h new file mode 100644 index 0000000..3c401ec --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xscuwdt_hw.h @@ -0,0 +1,157 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xscuwdt_hw.h +* @addtogroup Overview +* @{ +* +* This file contains the hardware interface to the Xilinx SCU private Watch Dog +* Timer (XSCUWDT). +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- --------------------------------------------- +* 1.00a sdm 01/15/10 First release +* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead +* of 0x20 as the base address obtained from the tools +* starts at 0x20. +* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue +* when the xstatus.h in the common driver overwrites +* the xstatus.h of the standalone BSP during the +* libgen. +* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +*+* +******************************************************************************/ +#ifndef XSCUWDT_HW_H /**< prevent circular inclusions */ +#define XSCUWDT_HW_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device. The WDT registers start at + * an offset 0x20 + * @{ + */ + +#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */ +#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */ +#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */ +#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */ +#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */ +#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */ +/* @} */ + +/** @name Watchdog Control register + * This register bits control the prescaler, WD/Timer mode, Intr enable, + * auto-reload, watchdog enable. + * @{ + */ + +#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */ +#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U +#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */ +#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in + timer mode) */ +#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in + timer mode) */ +#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Counter register has reached zero in Counter + * mode. + * @{ + */ + +#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */ +/*@}*/ + +/** @name Reset Status register + * This register indicates the Counter register has reached zero in Watchdog + * mode and a reset request is sent. + * @{ + */ + +#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */ +/*@}*/ + +/** @name Disable register + * This register is used to switch from watchdog mode to timer mode. + * The software must write 0x12345678 and 0x87654321 successively to the + * Watchdog Disable Register so that the watchdog mode bit in the Watchdog + * Control Register is set to zero. + * @{ + */ +#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable + value 1 */ +#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable + value 2 */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuWdt_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + ((u32)RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xsdps.h new file mode 100644 index 0000000..6278d69 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xsdps.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps.h +* @addtogroup sdps Overview +* @{ +* @details +* +* This section explains the implementation of the XSdPs driver. +* See xsdps.h for a detailed description of the device and driver. +* +* This driver is used initialize read from and write to the SD card. +* Features such as switching bus width to 4-bit and switching to high speed, +* changing clock frequency, block size etc. are supported. +* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however +* is done using 1-bit bus width and 400KHz clock frequency. +* SD commands are classified as broadcast and addressed. Commands can be +* those with response only (using only command line) or +* response + data (using command and data lines). +* Only one command can be sent at a time. During a data transfer however, +* when dsta lines are in use, certain commands (which use only the command +* line) can be sent, most often to obtain status. +* This driver does not support multi card slots at present. +* +* Initialization & Configuration +* +* This includes initialization on the host controller side to select +* clock frequency, bus power and default transfer related parameters. +* The default voltage is 3.3V. +* On the SD card side, the initialization and identification state diagram is +* implemented. This resets the card, gives it a unique address/ID and +* identifies key card related specifications. +* +* Data transfer +* +* The SD card is put in transfer state to read from or write to it. +* The default block size is 512 bytes and if supported, +* default bus width is 4-bit and bus speed is High speed. +* The read and write functions are implemented in polled mode using ADMA2. +* +* At any point, when key parameters such as block size or +* clock/speed or bus width are modified, this driver takes care of +* maintaining the same selection on host and card. +* All error bits in host controller are monitored by the driver and in the +* event one of them is set, driver will clear the interrupt status and +* communicate failure to the upper layer. +* +* File system use +* +* This driver can be used with xilffs library to read and write files to SD. +* (Please refer to procedure in diskio.c). The file system read/write example +* in polled mode can used for reference. +* +* There is no example for using SD driver without file system at present. +* However, the driver can be used without the file system. The glue layer +* in filesystem can be used as reference for the same. The block count +* passed to the read/write function in one call is limited by the ADMA2 +* descriptor table and hence care will have to be taken to call read/write +* API's in a loop for large file sizes. +* +* Interrupt mode is not supported because it offers no improvement when used +* with file system. +* +* eMMC support +* +* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. +* The features of eMMC supported by the driver will depend on those supported +* by the host controller. The current driver supports read/write on eMMC card +* using 4-bit and high speed mode currently. +* +* Features not supported include - card write protect, password setting, +* lock/unlock, interrupts, SDMA mode, programmed I/O mode and +* 64-bit addressed ADMA2, erase/pre-erase commands. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 1.00a hk/sg 10/17/13 Initial release +* 2.0 hk 03/07/14 Version number revised. +* 2.1 hk 04/18/14 Increase sleep for eMMC switch command. +* Add sleep for microblaze designs. CR# 781117. +* 2.2 hk 07/28/14 Make changes to enable use of data cache. +* 2.3 sk 09/23/14 Send command for relative card address +* when re-initialization is done.CR# 819614. +* Use XSdPs_Change_ClkFreq API whenever changing +* clock.CR# 816586. +* 2.4 sk 12/04/14 Added support for micro SD without +* WP/CD. CR# 810655. +* Checked for DAT Inhibit mask instead of CMD +* Inhibit mask in Cmd Transfer API. +* Added Support for SD Card v1.0 +* 2.5 sg 07/09/15 Added SD 3.0 features +* kvn 07/15/15 Modified the code according to MISRAC-2012. +* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601. +* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins. +* sk 12/10/15 Added support for MMC cards. +* 01/08/16 Added workaround for issue in auto tuning mode +* of SDR50, SDR104 and HS200. +* sk 02/16/16 Corrected the Tuning logic. +* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311. +* 2.8 sk 04/20/16 Added new workaround for auto tuning. +* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024 +* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. +* sk 07/16/16 Added support for UHS modes. +* sk 07/07/16 Used usleep API for both arm and microblaze. +* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC +* operating modes. +* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for +* CR#956899. +* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. +* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec +* sk 10/19/16 Used emmc_hwreset pin to reset eMMC. +* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency +* information. +* mn 09/06/17 Resolved compilation errors with IAR toolchain +* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor +* 3.7 mn 02/01/19 Add support for idling of SDIO +* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal +* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses +* 3.9 mn 03/03/20 Restructured the code for more readability and modularity +* mn 03/16/20 Move XSdPs_Select_Card API to User APIs +* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and +* XSdPs_Write APIs +* mn 06/05/20 Modified code for SD Non-Blocking Read support +* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN +* always, write zero to tap register for zero tap value. +* sk 12/07/20 Fix eMMC DDR52 mode write/read issue. +* sk 12/17/20 Removed checking platform specific SD macros and used +* Baseaddress instead. +* 3.12 sk 01/28/21 Added support for non-blocking write. +* sk 02/12/21 Fix the issue in reading CID and CSD. +* sk 04/08/21 Fixed doxygen warnings in all source files. +* sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by +* removing the DLL reset logic (Dead code for Versal). +* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal. +* 3.14 sk 10/22/21 Add support for Erase feature. +* sk 11/29/21 Fix compilation warnings reported with "-Wundef" flag. +* sk 01/10/22 Add support to read slot_type parameter. +* 4.0 sk 02/25/22 Add support for eMMC5.1. +* sk 04/07/22 Add support to read custom tap delay values from design +* for SD/eMMC. +* sk 06/03/22 Fix issue in internal clock divider calculation logic. +* 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net. +* 4.1 sa 01/03/23 Report error if Transfer size is greater than 2MB. +* 4.1 sa 12/19/22 Enable eMMC HS400 mode for Versal Net. +* sa 01/25/23 Use instance structure to store DMA descriptor tables. +* 4.2 ro 06/12/23 Added support for system device-tree flow. +* 4.2 ap 08/09/23 Reordered XSdPs_FrameCmd XSdPs_Identify_UhsMode functions +* +*+* +******************************************************************************/ + + +#ifndef SDPS_H_ +#define SDPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_printf.h" +#include "xil_cache.h" +#include "xstatus.h" +#include "xsdps_hw.h" +#include "xplatform_info.h" +#include "sleep.h" +#include
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 3.9 mn 03/03/20 Restructured the code for more readability and modularity +* mn 03/16/20 Move XSdPs_Select_Card API to User APIs +* 3.12 sk 01/28/21 Added support for non-blocking write. +* 3.14 sk 10/22/21 Add support for Erase feature. +* mn 11/28/21 Fix MISRA-C violations. +* 4.0 sk 02/25/22 Add support for eMMC5.1. +* 4.1 sa 01/06/23 Include xil_util.h in this file. +* 4.2 ap 08/09/23 Add XSdPs_SetTapDelay APIs. +*+* +******************************************************************************/ + +/** @cond INTERNAL */ +#ifndef SDPS_INCLUDE_H_ +#define SDPS_INCLUDE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xsdps.h" +#if defined (__aarch64__) +#include "xil_smc.h" +#endif + +#include "xil_util.h" + +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); +s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); +s32 XSdPs_SetupTransfer(XSdPs *InstancePtr); +s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +s32 XSdPs_CheckTransferComplete(XSdPs *InstancePtr); +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_DllReset(XSdPs *InstancePtr); +s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); +void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt); +void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); +void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst); +void XSdPs_ConfigTapDelay(XSdPs *InstancePtr); +s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); +void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); +void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); +u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd); +void XSdPs_SetTapDelay(XSdPs *InstancePtr); +s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value); +s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr); +s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt); +void XSdPs_SetExecTuning(XSdPs *InstancePtr); +s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr); +s32 XSdPs_CardReset(XSdPs *InstancePtr); +s32 XSdPs_CardIfCond(XSdPs *InstancePtr); +s32 XSdPs_CardOpCond(XSdPs *InstancePtr); +s32 XSdPs_GetCardId(XSdPs *InstancePtr); +s32 XSdPs_GetCsd(XSdPs *InstancePtr); +s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr); +s32 XSdPs_SdModeInit(XSdPs *InstancePtr); +s32 XSdPs_SdCardEnum(XSdPs *InstancePtr); +s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr); +s32 XSdPs_MmcModeInit(XSdPs *InstancePtr); +s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr); +s32 XSdPs_ResetConfig(XSdPs *InstancePtr); +void XSdPs_HostConfig(XSdPs *InstancePtr); +s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value); +void XSdPs_DisableBusPower(XSdPs *InstancePtr); +void XSdPs_EnableBusPower(XSdPs *InstancePtr); +s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value); +s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr); +s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr); +s32 XSdPs_AutoTuning(XSdPs *InstancePtr); +s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq); +u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq); +s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg); +s32 XSdps_CheckTransferDone(XSdPs *InstancePtr); +s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr); +s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr); +s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg); +void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff); +void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff); +s32 XSdPs_SetVoltage18(XSdPs *InstancePtr); +s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd); +void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd); +s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd); +void XSdPs_ConfigPower(XSdPs *InstancePtr); +void XSdPs_ConfigDma(XSdPs *InstancePtr); +void XSdPs_ConfigInterrupt(XSdPs *InstancePtr); +s32 XSdPs_SendErase(XSdPs *InstancePtr); +s32 XSdPs_SetEndAddr(XSdPs *InstancePtr, u32 EndAddr); +s32 XSdPs_SetStartAddr(XSdPs *InstancePtr, u32 StartAddr); +void XSdPs_SetTapDelay_SDR104(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_SDR50(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_DDR50(XSdPs *InstancePtr); +void XSdPs_SetTapDelay_SDR25(XSdPs *InstancePtr); +#ifdef VERSAL_NET +u32 XSdPs_Select_HS400(XSdPs *InstancePtr); +#endif + +#if defined (__aarch64__) && (EL1_NONSECURE == 1) +void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val); +#endif + +#ifdef __cplusplus +} +#endif + +#endif +/** @endcond */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xsdps_hw.h new file mode 100644 index 0000000..d7c4e9d --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xsdps_hw.h @@ -0,0 +1,1508 @@ +/****************************************************************************** +* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xsdps_hw.h +* @addtogroup sdps Overview +* @{{ +* +* The xsdps_hw.h header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- --- -------- ----------------------------------------------- +* 1.00a hk/sg 10/17/13 Initial release +* 2.5 sg 07/09/15 Added SD 3.0 features +* kvn 07/15/15 Modified the code according to MISRAC-2012. +* 2.7 sk 12/10/15 Added support for MMC cards. +* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode. +* 2.8 sk 04/20/16 Added new workaround for auto tuning. +* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. +* sk 07/16/16 Added support for UHS modes. +* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC +* operating modes. +* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Added support for ARMCC toolchain +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines +* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver +* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal +* mn 05/21/19 Set correct tap delays for Versal +* mn 05/21/19 Disable DLL Reset code for Versal +* mn 07/03/19 Update Input Tap Delays for Versal +* 3.9 mn 03/03/20 Restructured the code for more readability and modularity +* 3.14 mn 11/28/21 Fix MISRA-C violations. +* 4.0 sk 02/25/22 Add support for eMMC5.1. +* sk 04/07/22 Fix typo in 'XSDPS_MMC_1_BIT_BUS_ARG' macro definition. +* 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net. +* 4.2 ro 06/12/23 Added support for system device-tree flow. +* +*+* +******************************************************************************/ + +/** @cond INTERNAL */ +#ifndef SD_HW_H_ +#define SD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "bspconfig.h" +#include "xparameters.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SD device. + * @{ + */ + +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address + Register */ +#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET +/**< SDMA System Address + Low Register */ +#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ +#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address + High Register */ +#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */ + +#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ +#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET +/**< Argument1 Register */ +#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ + +#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt + Status Register */ +#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt + Status Register */ +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt + Status Enable Register */ +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt + Status Enable Register */ +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt + Signal Enable Register */ +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt + Signal Enable Register */ + +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status + Register */ +#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current + Capabilities Register */ +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current + Capabilities Ext Register */ +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for + Error Interrupt Status */ +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt + Status Register */ +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status + Register */ +#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address + Register */ +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address + Extended Register */ +#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */ +#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control + register */ + +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control + Register */ +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status + Register */ +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version + Register */ +#ifdef VERSAL_NET +#define XSDPS_PHYCTRLREG1_OFFSET 0x270U /**< PHY Control register2 */ +#define XSDPS_PHYCTRLREG2_OFFSET 0x274U /**< PHY Control register2 */ +#endif + +/** @} */ + +/** @name Control Register - Host control, Power control, + * Block Gap control and Wakeup control + * + * This register contains bits for various configuration options of + * the SD host controller. Read/Write apart from the reserved bits. + * @{ + */ + +#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */ +#define XSDPS_HC_BUS_WIDTH_4 0x00000002U +#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */ + +#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */ +#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */ + +#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */ + +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */ + +/** @} */ + +/** @name Control Register - Clock control, Timeout control & Software reset + * + * This register contains bits for configuration options of clock, timeout and + * software reset. + * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits. + * @{ + */ + +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U /**< INT clk enable */ +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U /**< INT clk stable */ +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U /**< SD clk enable */ +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U /**< SD clk gen selection */ +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U /**< SD clk freq sel upper */ +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU /**< SD clk freq sel */ +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U /**< Divider 256 */ +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U /**< Divider 128 */ +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U /**< Divider 64 */ +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U /**< Divider 32 */ +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U /**< Divider 16 */ +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U /**< Divider 8 */ +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U /**< Divider 4 */ +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U /**< Divider 2 */ +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U /**< Base clock */ +#define XSDPS_CC_MAX_DIV_CNT 256U /**< Max divider count */ +#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U /**< Max extended divider count */ +#define XSDPS_CC_EXT_DIV_SHIFT 6U /**< Ext divider shift */ + +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU /**< Data timeout counter */ + +#define XSDPS_SWRST_ALL_MASK 0x00000001U /**< Software Reset All */ +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U /**< Software reset for CMD line */ +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U /**< Software reset for DAT line */ + +#define XSDPS_CC_MAX_NUM_OF_DIV 9U /**< Max number of Clock dividers */ +#define XSDPS_CC_DIV_SHIFT 8U /**< Clock Divider shift */ + +/** @} */ + +/** @name SD Interrupt Registers + * + * Normal and Error Interrupt Status Register + * This register shows the normal and error interrupt status. + * Status enable register affects reads of this register. + * If Signal enable register is set and the corresponding status bit is set, + * interrupt is generated. + * Write to clear except + * Error_interrupt and Card_Interrupt bits - Read only + * + * Normal and Error Interrupt Status Enable Register + * Setting this register bits enables Interrupt status. + * Read/Write except Fixed_to_0 bit (Read only) + * + * Normal and Error Interrupt Signal Enable Register + * This register is used to select which interrupt status is + * indicated to the Host System as the interrupt. + * Read/Write except Fixed_to_0 bit (Read only) + * + * All three registers have same bit definitions + * @{ + */ + +#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv + Interrupt */ +#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate + Interrupt */ +#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU + +#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout + Error */ +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit + Error */ +#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific + Error */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */ +/** @} */ + +/** @name Block Size and Block Count Register + * + * This register contains the block count for current transfer, + * block size and SDMA buffer size. + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_SIZE_1024 0x400U +#define XSDPS_BLK_SIZE_2048 0x800U +#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for + Current Transfer */ + +/** @} */ + +/** @name Transfer Mode and Command Register + * + * The Transfer Mode register is used to control the data transfers and + * Command register is used for command generation + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer + Direction Select */ +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single + Block Select */ + +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type + Select */ +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 & + check busy after + response */ +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check + Enable */ +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check + Enable */ +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask - + Set to CMD0-63, + AMCD0-63 */ + +/** @} */ + +/** @name Auto CMD Error Status Register + * + * This register is read only register which contains + * information about the error status of Auto CMD 12 and 23. + * Read Only + * @{ + */ +#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/** @} */ + +/** @name Host Control2 Register + * + * This register contains extended configuration bits. + * Read Write + * @{ + */ +#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */ +#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */ +#define XSDPS_HC2_HS400_MASK 0x0005U /**< HS400 Mode */ +#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */ +#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength + Selection */ +#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */ +#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */ +#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */ +#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */ +#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */ +#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock + Selection */ +#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt + Enable */ +#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */ + +/** @} */ + +/** @name Capabilities Register + * + * Capabilities register is a read only register which contains + * information about the host controller. + * Sufficient if read once after power on. + * Read Only + * @{ + */ +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq + select */ +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit - + MHz/KHz */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */ +#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */ +#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */ +#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */ + +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume + support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */ + +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus + support */ +/* Spec 2.0 */ +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode + support */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */ + + +/* Spec 3.0 */ +#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt + support */ +#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */ +#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */ +#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */ +#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */ + +#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */ +#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */ +#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */ +#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */ +#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */ +#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */ +#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for + Re-tuning */ +#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs + tuning */ +#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes + support */ +#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */ +#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */ +#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */ +#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value + for Programmable clock + mode */ +#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */ +#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */ + +/** @} */ + +/** @name Present State Register + * + * Gives the current status of the host controller + * Read Only + * @{ + */ + +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */ +#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch + pin level */ +#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */ +#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */ +#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */ + +/** @} */ + +/** @name Maximum Current Capabilities Register + * + * This register is read only register which contains + * information about current capabilities at each voltage levels. + * Read Only + * @{ + */ +#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current + Capability at 1.8V */ +#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current + Capability at 3.0V */ +#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current + Capability at 3.3V */ +/** @} */ + + +/** @name Force Event for Auto CMD Error Status Register + * + * This register is write only register which contains + * control bits to generate events for Auto CMD error status. + * Write Only + * @{ + */ +#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/** @} */ + + + +/** @name Force Event for Error Interrupt Status Register + * + * This register is write only register which contains + * control bits to generate events of error interrupt status register. + * Write Only + * @{ + */ +#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout + Error */ +#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */ +#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit + Error */ +#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */ +#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */ +#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */ +#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */ +#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */ +#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */ +#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */ +#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */ +#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific + Error */ + +/** @} */ + +/** @name ADMA Error Status Register + * + * This register is read only register which contains + * status information about ADMA errors. + * Read Only + * @{ + */ +#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch + Error */ +#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */ +#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State + STOP */ +#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State + FDS */ +#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State + TFR */ +/** @} */ + +/** @name Preset Values Register + * + * This register is read only register which contains + * preset values for each of speed modes. + * Read Only + * @{ + */ +#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency + Select Value */ +#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator + Mode Select */ +#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength + Select Value */ + +/** @} */ + +/** @name Slot Interrupt Status Register + * + * This register is read only register which contains + * interrupt slot signal for each slot. + * Read Only + * @{ + */ +#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal + mask */ + +/** @} */ + +/** @name Host Controller Version Register + * + * This register is read only register which contains + * Host Controller and Vendor Specific version. + * Read Only + * @{ + */ +#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor + Specification + version mask */ +#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host + Specification + version mask */ +#define XSDPS_HC_SPEC_V3 0x0002U /**< HC spec version 3 */ +#define XSDPS_HC_SPEC_V2 0x0001U /**< HC spec version 2 */ +#define XSDPS_HC_SPEC_V1 0x0000U /**< HC spec version 1 */ +/** @} */ + +/** @name PHYCTRL Register1 - OTAP, ITAP and SROBE SEL + * + * This register contains bits for input tap, output tap and strobe sel. + * @{ + */ + +#define XSDPS_PHYREG1_STROBE_SEL_MASK 0xFF0000U /**< STROBE Sel Mask */ +#define XSDPS_PHYREG1_STROBE_SEL_SHIFT 16U /**< STROBE Sel Shift */ +#define XSDPS_PHYREG1_ITAP_CHGWIN_MASK 0x40U /**< Input Tap Change Window */ +#define XSDPS_PHYREG1_ITAP_EN_MASK 0x1U /**< Input Tap Enable Mask */ +#define XSDPS_PHYREG1_ITAP_DLY_MASK 0x2EU /**< Input Tap Delay Mask */ +#define XSDPS_PHYREG1_ITAP_DLY_SHIFT 1U /**< Input Tap Delay Shift */ +#define XSDPS_PHYREG1_OTAP_EN_MASK 0x100U /**< Output Tap Enable Mask */ +#define XSDPS_PHYREG1_OTAP_DLY_MASK 0xF000U /**< Output Tap Delay Mask */ +#define XSDPS_PHYREG1_OTAP_DLY_SHIFT 12U /**< Output Tap Delay Shift */ + +/** @} */ + +/** @name PHYCTRL Register2 - DLL enable, FREQ_SEL, Tx and Rx Dly Chain Sel + * + * This register contains bits for cDLL enable, FREQ_SEL, Tx and Rx Dly Chain Sel + * and DLL Ready. + * @{ + */ + +#define XSDPS_PHYREG2_DLL_EN_MASK 0x00000001U /**< DLL enable */ +#define XSDPS_PHYREG2_DLL_RDY_MASK 0x00000002U /**< DLL Ready */ +#define XSDPS_PHYREG2_FREQ_SEL_MASK 0x00000070U /**< Freq selection */ +#define XSDPS_PHYREG2_FREQ_SEL_SHIFT 4U /**< Freq selection shift */ +#define XSDPS_FREQ_SEL_170MHZ_200MHz 0U /**< Macro to select between 170MHz to 200MHz */ +#define XSDPS_FREQ_SEL_140MHZ_169MHz 1U /**< Macro to select between 140MHz to 169MHz */ +#define XSDPS_FREQ_SEL_110MHZ_139MHz 2U /**< Macro to select between 110MHz to 139MHz */ +#define XSDPS_FREQ_SEL_80MHZ_109MHz 3U /**< Macro to select between 80MHz to 109MHz */ +#define XSDPS_FREQ_SEL_50MHZ_79MHz 4U /**< Macro to select between 50MHz to 79MHz */ +#define XSDPS_PHYREG2_TRIM_ICP_MASK 0x00000F00U /**< DLL TRIM ICP */ +#define XSDPS_PHYREG2_TRIM_ICP_DEF_VAL 8U /**< DLL TRIM ICP default value */ +#define XSDPS_PHYREG2_TRIM_ICP_SHIFT 8U /**< DLL TRIM ICP shift */ +#define XSDPS_PHYREG2_DLYTX_SEL_MASK 0x00010000U /**< Delay Chain based Tx Clk */ +#define XSDPS_PHYREG2_DLYRX_SEL_MASK 0x00020000U /**< Delay Chain based Rx Clk */ +/** @} */ + +/** @name Commands + * + * Constant definitions for commands and response related to SD + * @{ + */ +/** + * Command/Response related to SD/eMMC + */ + +#define XSDPS_APP_CMD_PREFIX 0x8000U +#define CMD0 0x0000U +#define CMD1 0x0100U +#define CMD2 0x0200U +#define CMD3 0x0300U +#define CMD4 0x0400U +#define CMD5 0x0500U +#define CMD6 0x0600U +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U) +#define CMD7 0x0700U +#define CMD8 0x0800U +#define CMD9 0x0900U +#define CMD10 0x0A00U +#define CMD11 0x0B00U +#define CMD12 0x0C00U +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U) +#define CMD16 0x1000U +#define CMD17 0x1100U +#define CMD18 0x1200U +#define CMD19 0x1300U +#define CMD21 0x1500U +#define CMD23 0x1700U +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U) +#define CMD24 0x1800U +#define CMD25 0x1900U +#define CMD32 0x2000U +#define CMD33 0x2100U +#define CMD35 0x2300U +#define CMD36 0x2400U +#define CMD38 0x2600U +#define CMD41 0x2900U +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U) +#define CMD52 0x3400U +#define CMD55 0x3700U +#define CMD58 0x3A00U + +#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ + (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK + +#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +/** @} */ + +/** + * @name Card Interface + * @{ + */ +/** + * Card Interface Conditions Definitions + */ +#define XSDPS_CIC_CHK_PATTERN 0xAAU +#define XSDPS_CIC_VOLT_MASK (0xFU<<8) +#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8) +#define XSDPS_CIC_VOLT_LOW (1U<<9) +/** @} */ + +/** + * @name OCR + * @{ + */ +/** + * Operation Conditions Register Definitions + */ +#define XSDPS_OCR_PWRUP_STS (0x00000001U << 31) +#define XSDPS_OCR_CC_STS (0x00000001U << 30) +#define XSDPS_OCR_S18 (0x00000001U << 24) +#define XSDPS_OCR_3V5_3V6 (0x00000001U << 23) +#define XSDPS_OCR_3V4_3V5 (0x00000001U << 22) +#define XSDPS_OCR_3V3_3V4 (0x00000001U << 21) +#define XSDPS_OCR_3V2_3V3 (0x00000001U << 20) +#define XSDPS_OCR_3V1_3V2 (0x00000001U << 19) +#define XSDPS_OCR_3V0_3V1 (0x00000001U << 18) +#define XSDPS_OCR_2V9_3V0 (0x00000001U << 17) +#define XSDPS_OCR_2V8_2V9 (0x00000001U << 16) +#define XSDPS_OCR_2V7_2V8 (0x00000001U << 15) +#define XSDPS_OCR_1V7_1V95 (0x00000001U << 7) +#define XSDPS_OCR_HIGH_VOL 0x00FF8000U +#define XSDPS_OCR_LOW_VOL 0x00000080U +/** @} */ + +/** + * @name Card Configuration + * @{ + */ +/** + * SD Card Configuration Register Definitions + */ +#define XSDPS_SCR_REG_LEN 8U +#define XSDPS_SCR_STRUCT_MASK (0xFU<<28) +#define XSDPS_SCR_SPEC_MASK (0xFU<<24) +#define XSDPS_SCR_SPEC_1V0 0U +#define XSDPS_SCR_SPEC_1V1 (1U<<24) +#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24) +#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23) +#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20) +#define XSDPS_SCR_SEC_SUPP_NONE 0U +#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20) +#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20) +#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20) +#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16) +#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16) +#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16) +#define XSDPS_SCR_SPEC3_MASK (1U<<12) +#define XSDPS_SCR_SPEC3_2V0 0U +#define XSDPS_SCR_SPEC3_3V0 (1U<<12) +#define XSDPS_SCR_CMD_SUPP_MASK 0x3U +#define XSDPS_SCR_CMD23_SUPP (1U<<1) +#define XSDPS_SCR_CMD20_SUPP (1U<<0) +/** @} */ + +/** + * @name Card Status + * @{ + */ +/** + * Card Status Register Definitions + */ +#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31) +#define XSDPS_CD_STS_ADDR_ERR (1U<<30) +#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29) +#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28) +#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27) +#define XSDPS_CD_STS_WP_VIO (1U<<26) +#define XSDPS_CD_STS_IS_LOCKED (1U<<25) +#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24) +#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23) +#define XSDPS_CD_STS_ILGL_CMD (1U<<22) +#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21) +#define XSDPS_CD_STS_CC_ERR (1U<<20) +#define XSDPS_CD_STS_ERR (1U<<19) +#define XSDPS_CD_STS_CSD_OVRWR (1U<<16) +#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15) +#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14) +#define XSDPS_CD_STS_ER_RST (1U<<13) +#define XSDPS_CD_STS_CUR_STATE (0xFU<<9) +#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8) +#define XSDPS_CD_STS_APP_CMD (1U<<5) +#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2) +/** @} */ + +/** + * @name Switch function + * @{ + */ +/** + * Switch Function Definitions CMD6 + */ +#define XSDPS_SWITCH_SD_RESP_LEN 64U + +#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31) +#define XSDPS_SWITCH_FUNC_CHECK 0U +/** @} */ + +/** + * @name Mode Function + * @{ + */ +/** + * Mode function groups definitions. + */ +#define XSDPS_MODE_FUNC_GRP1 1U +#define XSDPS_MODE_FUNC_GRP2 2U +#define XSDPS_MODE_FUNC_GRP3 3U +#define XSDPS_MODE_FUNC_GRP4 4U +#define XSDPS_MODE_FUNC_GRP5 5U +#define XSDPS_MODE_FUNC_GRP6 6U + +#define XSDPS_FUNC_GRP_DEF_VAL 0xFU +#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU +/** @} */ + +/** + * @name Operating modes + * @{ + */ +/** + * SD operating modes in UHS. + */ +#define XSDPS_ACC_MODE_DEF_SDR12 0U +#define XSDPS_ACC_MODE_HS_SDR25 1U +#define XSDPS_ACC_MODE_SDR50 2U +#define XSDPS_ACC_MODE_SDR104 3U +#define XSDPS_ACC_MODE_DDR50 4U +/** @} */ + +/** + * @name General definitions + * @{ + */ +/** + * Definitions related to Driver strength, Current limit and + * CSD specific data. + */ +#define XSDPS_CMD_SYS_ARG_SHIFT 4U +#define XSDPS_CMD_SYS_DEF 0U +#define XSDPS_CMD_SYS_eC 1U +#define XSDPS_CMD_SYS_OTP 3U +#define XSDPS_CMD_SYS_ASSD 4U +#define XSDPS_CMD_SYS_VEND 5U + +#define XSDPS_DRV_TYPE_ARG_SHIFT 8U +#define XSDPS_DRV_TYPE_B 0U +#define XSDPS_DRV_TYPE_A 1U +#define XSDPS_DRV_TYPE_C 2U +#define XSDPS_DRV_TYPE_D 3U + +#define XSDPS_CUR_LIM_ARG_SHIFT 12U +#define XSDPS_CUR_LIM_200 0U +#define XSDPS_CUR_LIM_400 1U +#define XSDPS_CUR_LIM_600 2U +#define XSDPS_CUR_LIM_800 3U + +#define CSD_SPEC_VER_MASK 0x3C0000U +#define READ_BLK_LEN_MASK 0x00000F00U +#define C_SIZE_MULT_MASK 0x00000380U +#define C_SIZE_LOWER_MASK 0xFFC00000U +#define C_SIZE_UPPER_MASK 0x00000003U +#define CSD_STRUCT_MASK 0x00C00000U +#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U +#define CSD_CCC_MASK 0xFFF00000U +#define CSD_CCC_SHIFT 20U +#define CSD_CCC_CLASS5_MASK 0x20U +/** @} */ + +/** + * @name Extended Card Specific Data + * @{ + */ +/** + * EXT_CSD field definitions + */ +#define XSDPS_EXT_CSD_SIZE 512U + +#define EXT_CSD_WR_REL_PARAM_EN (1U<<2) + +#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U) +#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U) + +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U) +#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) +#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) +#define EXT_CSD_PART_CONFIG_BYTE (179U) +#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)(0U) << 8U)) + +#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U)) + +#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \ + | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \ + | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U)) + +#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) + +#define EXT_CSD_CMD_SET_NORMAL (1U<<0) +#define EXT_CSD_CMD_SET_SECURE (1U<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1U<<2) + +#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ +/* DDR mode @1.8V or 3V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ +/* DDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) +#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ +/* SDR mode @1.2V I/O */ +#define EXT_CSD_BUS_WIDTH_BYTE 183U +#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */ + +#define EXT_CSD_HS_TIMING_BYTE 185U +#define EXT_CSD_HS_TIMING_DEF 0U +#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */ +#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */ +#define EXT_CSD_HS_TIMING_HS400 3U /* Card is in HS200 mode */ + +#define EXT_CSD_RST_N_FUN_BYTE 162U +#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */ +#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */ +#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */ + +#define XSDPS_EXT_CSD_CMD_SET 0U +#define XSDPS_EXT_CSD_SET_BITS 1U +#define XSDPS_EXT_CSD_CLR_BITS 2U +#define XSDPS_EXT_CSD_WRITE_BYTE 3U +/** @} */ + +/** + * @name SD/eMMC Bus Speed and Bus Width Arguments + * @{ + */ +/** + * SD/MMC Arguments for Bus Speed and Bus Width. + */ +#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) + +#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) + +#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) + +#define XSDPS_MMC_HS400_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS400 << 8)) + +#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8)) + +#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) + +#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) + +#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) + +#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) + +#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + +#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U + +/** @} */ + +/** + * @name General Delay definitions + * @{ + */ +/** + * @400KHz, in usec + */ +#define XSDPS_74CLK_DELAY 2960U +#define XSDPS_100CLK_DELAY 4000U +#define XSDPS_INIT_DELAY 10000U +/** @} */ + +#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK /**< Default voltage level */ +#define XSDPS_CARD_DEF_ADDR 0x1234U /**< Card Default address */ + +#define XSDPS_CARD_SD 1U /**< SD card */ +#define XSDPS_CARD_MMC 2U /**< MMC card */ +#define XSDPS_CARD_SDIO 3U /**< SDIO card */ +#define XSDPS_CARD_SDCOMBO 4U /**< SDCOMBO card */ +#define XSDPS_CHIP_EMMC 5U /**< EMMC chip */ + + +/** + *@name ADMA2 Descriptor related definitions + * @{ + */ +/** + * ADMA2 Descriptor related definitions + */ +#define XSDPS_DESC_MAX_LENGTH 65536U + +#define XSDPS_DESC_VALID (0x1U << 0) +#define XSDPS_DESC_END (0x1U << 1) +#define XSDPS_DESC_INT (0x1U << 2) +#define XSDPS_DESC_TRAN (0x2U << 4) + +/** @} */ + +/* For changing clock frequencies */ +#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */ +#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */ +#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */ +#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */ +#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */ +#define XSDPS_SCR_BLKCNT 1U /**< SCR Block Count */ +#define XSDPS_SCR_BLKSIZE 8U /**< SCR Block Size */ +#define XSDPS_1_BIT_WIDTH 0x1U /**< Bus Width 1 */ +#define XSDPS_4_BIT_WIDTH 0x2U /**< Bus Width 4 */ +#define XSDPS_8_BIT_WIDTH 0x3U /**< Bus Width 8 */ +#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U /**< SDR12 mode */ +#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U /**< SDR25 mode */ +#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U /**< SDR50 mode */ +#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U /**< SDR104 mode */ +#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U /**< DDR50 mode */ +#define XSDPS_HIGH_SPEED_MODE 0x5U /**< High Speed mode */ +#define XSDPS_DEFAULT_SPEED_MODE 0x6U /**< Default speed mode */ +#define XSDPS_HS200_MODE 0x7U /**< eMMC HS200 mode */ +#define XSDPS_HS400_MODE 0x8U /**< eMMC HS400 mode */ +#define XSDPS_DDR52_MODE 0x4U /**< eMMC DDR52 mode */ +#define XSDPS_SWITCH_CMD_BLKCNT 1U /**< Blk cnt for SWITCH cmd */ +#define XSDPS_SWITCH_CMD_BLKSIZE 64U /**< Blk sz for SWITCH cmd */ +#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U /**< SWITCH cmd to Get HS */ +#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U /**< SWITCH cmd to Set HS */ +#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U /**< SWITCH cmd to Set SDR12 */ +#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U /**< SWITCH cmd to Set SDR25 */ +#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U /**< SWITCH cmd to Set SDR50 */ +#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U /**< SWITCH cmd to Set SDR104 */ +#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U /**< SWITCH cmd to Set DDR50 */ +#define XSDPS_EXT_CSD_CMD_BLKCNT 1U /**< Blk Cnt for EXT CSD */ +#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U /**< Blk Sz for EXT CSD */ +#define XSDPS_TUNING_CMD_BLKCNT 1U /**< Blk Cnt for Tuning cmd */ +#define XSDPS_TUNING_CMD_BLKSIZE 64U /**< Blk Sz for Tuning cmd */ +#define XSDPS_SD_STATUS_BLKCNT 1U /**< Blk Cnt for SD status */ +#define XSDPS_SD_STATUS_BLKSIZE 64U /**< Blk Sz for SD status */ + +#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U /**< Max clk for HS mode */ +#define XSDPS_UHS_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */ +#define XSDPS_UHS_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */ +#define XSDPS_UHS_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */ +#define XSDPS_UHS_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */ +#define XSDPS_UHS_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */ + +#define SD_DRIVER_TYPE_B 0x01U /**< Driver Type B */ +#define SD_DRIVER_TYPE_A 0x02U /**< Driver Type A */ +#define SD_DRIVER_TYPE_C 0x04U /**< Driver Type C */ +#define SD_DRIVER_TYPE_D 0x08U /**< Driver Type D */ +#define SD_SET_CURRENT_LIMIT_200 0U /**< Current limit 200mA */ +#define SD_SET_CURRENT_LIMIT_400 1U /**< Current limit 400mA */ +#define SD_SET_CURRENT_LIMIT_600 2U /**< Current limit 600mA */ +#define SD_SET_CURRENT_LIMIT_800 3U /**< Current limit 800mA */ + +#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) /**< Current limit 200mA Arg */ +#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) /**< Current limit 400mA Arg */ +#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) /**< Current limit 600mA Arg */ +#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) /**< Current limit 800mA Arg */ + +#define XSDPS_SD_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */ +#define XSDPS_SD_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */ +#define XSDPS_SD_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */ +#define XSDPS_SD_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */ +#define XSDPS_SD_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */ +/** + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + +#define XSDPS_MMC_HS200_MAX_CLK 200000000U /**< Max clk for MMC HS200 mode */ +#define XSDPS_MMC_HSD_MAX_CLK 52000000U /**< Max clk for MMC HSD mode */ +#define XSDPS_MMC_DDR_MAX_CLK 52000000U /**< Max clk for MMC DDR52 mode */ + +#define XSDPD_MIN_DLL_MODE_CLK 50000000U /**< Min clk for DLL mode */ + +/** + * @name Card states + * @{ + */ +/** + * Definition for Card state. + */ +#define XSDPS_CARD_STATE_IDLE 0U +#define XSDPS_CARD_STATE_RDY 1U +#define XSDPS_CARD_STATE_IDEN 2U +#define XSDPS_CARD_STATE_STBY 3U +#define XSDPS_CARD_STATE_TRAN 4U +#define XSDPS_CARD_STATE_DATA 5U +#define XSDPS_CARD_STATE_RCV 6U +#define XSDPS_CARD_STATE_PROG 7U +#define XSDPS_CARD_STATE_DIS 8U +#define XSDPS_CARD_STATE_BTST 9U +#define XSDPS_CARD_STATE_SLP 10U +/** @} */ + +#define XSDPS_SLOT_REM 0U /**< Removable slot */ +#define XSDPS_SLOT_EMB 1U /**< Embedded slot */ + +#define XSDPS_WIDTH_8 8U /**< Bus width 8 */ +#define XSDPS_WIDTH_4 4U /**< Bus width 4 */ + +#define XSDPS_SLOTTYPE_SDADIR 4U /**< SD3.0 Auto Direction */ + +/** + * @name Tap delays + * @{ + */ +/** + * SD/eMMC ITAP and OTAP delays for different operating modes + * for both Versal and ZynqMP platforms. + */ +#ifdef VERSAL_NET +#define SD_ITAPDLY_SEL_MASK 0x000000FFU +#define SD_OTAPDLY_SEL_MASK 0x0000003FU +#define SD_ITAPDLY 0x0000F0F8U +#define SD_OTAPDLY 0x0000F0FCU +#define SD0_DLL_CTRL 0x00000448U +#define SD1_DLL_CTRL 0x000004C8U +#define SD_DLL_RST 0x00000004U +#define SD_ITAPCHGWIN 0x00000200U +#define SD_ITAPDLYENA 0x00000100U +#define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_HS200_B0 0x00000007U +#define SD_OTAPDLYSEL_HS200_B2 0x00000007U +#define SD_OTAPDLYSEL_HS400 0x00000004U +#define SD_ITAPDLYSEL_SD50 0x0000000EU +#define SD_OTAPDLYSEL_SD50 0x00000003U +#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U +#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000003U +#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U +#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U +#define SD_ITAPDLYSEL_HSD 0x0000002CU +#define SD_ITAPDLYSEL_EMMC_HSD 0x00000000U +#define SD_OTAPDLYSEL_SD_HSD 0x00000004U +#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U +#define SD_AUTODIR_ITAPDLYSEL_HSD 0x00000025U +#define SD_AUTODIR_ITAPDLYSEL_SDR25 0x00000026U +#define SD_AUTODIR_ITAPDLYSEL_DDR50 0x0000002AU +#define PHY_STRB_SEL_SIG 0x00000077U +#elif defined (versal) +#define SD_ITAPDLY_SEL_MASK 0x000000FFU +#define SD_OTAPDLY_SEL_MASK 0x0000003FU +#define SD_ITAPDLY 0x0000F0F8U +#define SD_OTAPDLY 0x0000F0FCU +#define SD0_DLL_CTRL 0x00000448U +#define SD1_DLL_CTRL 0x000004C8U +#define SD_DLL_RST 0x00000004U +#define SD_ITAPCHGWIN 0x00000200U +#define SD_ITAPDLYENA 0x00000100U +#define SD_OTAPDLYENA 0x00000040U +#define SD_OTAPDLYSEL_HS200_B0 0x00000002U +#define SD_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD_ITAPDLYSEL_SD50 0x0000000EU +#define SD_OTAPDLYSEL_SD50 0x00000003U +#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U +#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU +#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U +#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U +#define SD_ITAPDLYSEL_HSD 0x0000002CU +#define SD_ITAPDLYSEL_EMMC_HSD 0x0000002CU +#define SD_OTAPDLYSEL_SD_HSD 0x00000004U +#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U +#define SD_AUTODIR_ITAPDLYSEL_HSD 0x00000025U +#define SD_AUTODIR_ITAPDLYSEL_SDR25 0x00000026U +#define SD_AUTODIR_ITAPDLYSEL_DDR50 0x0000002AU +#else +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U +#define SD_DLL_CTRL 0x00000358U +#define SD_ITAPDLY 0x00000314U +#define SD_OTAPDLY 0x00000318U +#define SD0_DLL_RST 0x00000004U +#define SD1_DLL_RST 0x00040000U +#define SD0_ITAPCHGWIN 0x00000200U +#define SD0_ITAPDLYENA 0x00000100U +#define SD0_OTAPDLYENA 0x00000040U +#define SD1_ITAPCHGWIN 0x02000000U +#define SD1_ITAPDLYENA 0x01000000U +#define SD1_OTAPDLYENA 0x00400000U +#define SD_OTAPDLYSEL_HS200_B0 0x00000003U +#define SD_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD_ITAPDLYSEL_SD50 0x00000014U +#define SD_OTAPDLYSEL_SD50 0x00000003U +#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU +#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U +#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U +#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U +#define SD_ITAPDLYSEL_HSD 0x00000015U +#define SD_ITAPDLYSEL_EMMC_HSD 0x00000015U +#define SD_OTAPDLYSEL_SD_HSD 0x00000005U +#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U +#define SD_AUTODIR_ITAPDLYSEL_HSD 0x00000028U +#define SD_AUTODIR_ITAPDLYSEL_SDR25 0x0000002CU +#define SD_AUTODIR_ITAPDLYSEL_DDR50 0x00000033U +#endif +/** @} */ + +#ifdef __MICROBLAZE__ +#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */ +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define XSdPs_In64 Xil_In64 /**< Low level 64-bit data read */ +#define XSdPs_Out64 Xil_Out64 /**< Low level 64-bit data write */ + +#define XSdPs_In32 Xil_In32 /**< Low level 32-bit data read */ +#define XSdPs_Out32 Xil_Out32 /**< Low level 32-bit data write */ + +#define XSdPs_In16 Xil_In16 /**< Low level 16-bit data read */ +#define XSdPs_Out16 Xil_Out16 /**< Low level 16-bit data write */ + +#define XSdPs_In8 Xil_In8 /**< Low level 8-bit data read */ +#define XSdPs_Out8 Xil_Out8 /**< Low level 8-bit data write */ + +/****************************************************************************/ +/** +* Read a register. +* +* @param InstancePtr is the pointer to the sdps instance. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg64(InstancePtr, RegOffset) \ + XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param InstancePtr is the pointer to the sdps instance. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, +* u64 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \ + XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \ + (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg(BaseAddress, RegOffset) \ + XSdPs_In32((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out32((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u16 XSdPs_ReadReg16(UINTPTR BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3) * 8); + return (u16)Reg; +#else + return XSdPs_In16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)); +#endif +} + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ + +static INLINE void XSdPs_WriteReg16(UINTPTR BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFFU << ((RegOffset & 0x3) * 8)); + Reg |= RegisterValue << ((RegOffset & 0x3) * 8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)); +#endif +} + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u8 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u8 XSdPs_ReadReg8(UINTPTR BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3) * 8); + return (u8)Reg; +#else + return XSdPs_In8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset)); +#endif +} +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +static INLINE void XSdPs_WriteReg8(UINTPTR BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFU << ((RegOffset & 0x3) * 8)); + Reg |= RegisterValue << ((RegOffset & 0x3) * 8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue)); +#endif +} +/***************************************************************************/ +/** +* Macro to get present status register +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_GetPresentStatusReg(BaseAddress) \ + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_HW_H_ */ +/** @endcond */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xstatus.h new file mode 100644 index 0000000..f534bdf --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xstatus.h @@ -0,0 +1,525 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. * +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx software status codes +* +* The xstatus.h file contains the Xilinx software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +/** + *@cond nocomments + */ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +#define XST_NO_ACCESS 30L /* Generic access error */ +#define XST_TIMEOUT 31L /*!< Event timeout occurred */ +#define XST_GLITCH_ERROR 32L /*!< Used when a glitch occurs*/ + +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be committed */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + +/** + *@endcond + */ + +/** +* @} End of "addtogroup common_status_codes". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xtime_l.h new file mode 100644 index 0000000..9d17f5c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xtime_l.h @@ -0,0 +1,86 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- --------------------------------------------------- +* 1.00a rp/sdm 11/03/09 Initial release. +* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer +* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer. +* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer +* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep +* implementation +* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain. +* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid +* displaying same warnings multiple times. It fixes CR#1090562. +*+* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +#endif +/************************** Variable Definitions *****************************/ + +/** +*@endcond +*/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xuartps.h new file mode 100644 index 0000000..89ed5fd --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xuartps.h @@ -0,0 +1,523 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartps.h +* @addtogroup uartps Overview +* @{ +* @details +* +* This driver supports the following features: +* +* - Dynamic data format (baud rate, data bits, stop bits, parity) +* - Polled mode +* - Interrupt driven mode +* - Transmit and receive FIFOs (32 byte FIFO depth) +* - Access to the external modem control lines +* +* Initialization & Configuration +* +* The XUartPs_Config structure is used by the driver to configure itself. +* Fields inside this structure are properties of XUartPs based on its hardware +* build. +* +* To support multiple runtime loading and initialization strategies employed +* by various operating systems, the driver instance can be initialized in the +* following way: +* +* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the parameter EffectiveAddr should be the +* virtual address. +* +* Baud Rate +* +* The UART has an internal baud rate generator, which furnishes the baud rate +* clock for both the receiver and the transmitter. The input clock frequency +* can be either the master clock or the master clock divided by 8, configured +* through the mode register. +* +* Accompanied with the baud rate divider register, the baud rate is determined +* by: +*
+* baud_rate = input_clock / (bgen * (bdiv + 1) +*+* where bgen is the value of the baud rate generator, and bdiv is the value of +* baud rate divider. +* +* Interrupts +* +* The FIFOs are not flushed when the driver is initialized, but a function is +* provided to allow the user to reset the FIFOs if desired. +* +* The driver defaults to no interrupts at initialization such that interrupts +* must be enabled if desired. An interrupt is generated for one of the +* following conditions. +* +* - A change in the modem signals +* - Data in the receive FIFO for a configuable time without receiver activity +* - A parity error +* - A framing error +* - An overrun error +* - Transmit FIFO is full +* - Transmit FIFO is empty +* - Receive FIFO is full +* - Receive FIFO is empty +* - Data in the receive FIFO equal to the receive threshold +* +* The application can control which interrupts are enabled using the +* XUartPs_SetInterruptMask() function. +* +* In order to use interrupts, it is necessary for the user to connect the +* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt +* system of the application. A separate handler should be provided by the +* application to communicate with the interrupt system, and conduct +* application specific interrupt handling. An application registers its own +* handler through the XUartPs_SetHandler() function. +* +* Data Transfer +* +* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the +* driver to allow data to be sent and received. They can be used in either +* polled or interrupt mode. +* +* @note +* +* The default configuration for the UART after initialization is: +* +* - 9,600 bps or XPAR_DFT_BAUDRATE if defined +* - 8 data bits +* - 1 stop bit +* - no parity +* - FIFO's are enabled with a receive threshold of 8 bytes +* - The RX timeout is enabled with a timeout of 1 (4 char times) +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ---------------------------------------------- +* 1.00a drg/jz 01/12/10 First Release +* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug +* in XUartPs_SetFlowDelay where the value was not +* being written to the register. +* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs +* instance structure and the driver is updated to use +* InputClockHz parameter from the XUartPs_Config config +* structure. +* Added a parameter to XUartPs_Config structure which +* specifies whether the user has selected Modem pins +* to be connected to MIO or FMIO. +* Added the tcl file to generate the xparameters.h +* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix. +* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS +* with the correct values for CR 666724 +* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL +* and XUARTPS_IXR_TTRIG. +* Modified the name of these defines +* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD +* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI +* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR +* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS +* 1.05a hk 08/22/13 Added API for uart reset and related +* constant definitions. +* 2.0 hk 03/07/14 Version number revised. +* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625. +* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing +* baud rate. CR# 804281. +* 3.0 vm 12/09/14 Modified source code according to misrac guideline. +* Support for Zynq Ultrascale Mp added. +* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added +* platform variable in driver instance structure. +* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when +* uart is connected to a valid interrupt controller CR#946803. +* 3.2 rk 07/20/16 Modified the logic for transmission break bit set +* 3.4 ms 01/23/17 Added xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem +* control register. +* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations. +* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro. +* 3.9 sd 02/06/20 Added clock support +* 3.12 gm 11/04/22 Added timeout support using Xil_WaitForEvent +* 3.13 adk 14/04/23 Added support for system device-tree flow. +* +*+* +*****************************************************************************/ + +#ifndef XUARTPS_H /* prevent circular inclusions */ +#define XUARTPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xuartps_hw.h" +#include "xplatform_info.h" +#if defined (XCLOCKING) +#include "xil_clocking.h" +#endif +#include "xil_util.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants indicate the max and min baud rates and these + * numbers are based only on the testing that has been done. The hardware + * is capable of other baud rates. + */ +#define XUARTPS_MAX_RATE 6240000U +#define XUARTPS_MIN_RATE 110U + +#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */ + +/** @name Configuration options + * @{ + */ +/** + * These constants specify the options that may be set or retrieved + * with the driver, each is a unique bit mask such that multiple options + * may be specified. These constants indicate the available options + * in active state. + * + */ + +#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */ +#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */ +#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */ +#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */ +#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */ +#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */ +#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */ +#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */ +/*@}*/ + + +/** @name Channel Operational Mode + * + * The UART can operate in one of four modes: Normal, Local Loopback, Remote + * Loopback, or automatic echo. + * + * @{ + */ + +#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */ +#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */ +#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */ +#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */ + +/* @} */ + +/** @name Data format values + * + * These constants specify the data format that the driver supports. + * The data format includes the number of data bits, the number of stop + * bits and parity. + * + * @{ + */ +#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */ +#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */ +#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */ + +#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */ +#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */ +#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */ +#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */ +#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */ + +#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */ +#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */ +#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that an application can handle + * using its specific handler function. Note that these constants are not bit + * mask, so only one event can be passed to an application at a time. + * + * @{ + */ +#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */ +#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ +#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */ +#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */ +#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */ +#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break + * error detected */ +#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ + +/*@}*/ + +#define TIMEOUT_VAL 1000000U /**< Wait for 1 sec in worst case */ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { +#ifndef SDT + u16 DeviceId; /**< Unique ID of device */ +#else + char *Name; +#endif + u32 BaseAddress; /**< Base address of device (IPIF) */ + u32 InputClockHz;/**< Input clock frequency */ + s32 ModemPinsConnected; /** Specifies whether modem pins are connected + * to MIO or FMIO */ +#if defined (XCLOCKING) || defined(SDT) + u32 RefClk; /**< Input clock frequency */ +#endif +#if defined(SDT) + u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] + * trigger type and level flags */ + UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] + * Parent base address */ +#endif +} XUartPs_Config; + +/* Keep track of state information about a data buffer in the interrupt mode. */ +typedef struct { + u8 *NextBytePtr; + u32 RequestedBytes; + u32 RemainingBytes; +} XUartPsBuffer; + +/** + * Keep track of data format setting of a device. + */ +typedef struct { + u32 BaudRate; /**< In bps, ie 1200 */ + u32 DataBits; /**< Number of data bits */ + u32 Parity; /**< Parity */ + u8 StopBits; /**< Number of stop bits */ +} XUartPsFormat; + +/******************************************************************************/ +/** + * This data type defines a handler that an application defines to communicate + * with interrupt system to retrieve state information about an application. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the handler, and is passed back to the upper layer + * when the handler is called. It is used to find the device driver + * instance. + * @param Event contains one of the event constants indicating events that + * have occurred. + * @param EventData contains the number of bytes sent or received at the + * time of the call for send and receive events and contains the + * modem status for modem events. + * + ******************************************************************************/ +typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, + u32 EventData); + +/** + * The XUartPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XUartPs_Config Config; /* Configuration data structure */ + u32 InputClockHz; /* Input clock frequency */ + u32 IsReady; /* Device is initialized and ready */ + u32 BaudRate; /* Current baud rate */ + + XUartPsBuffer SendBuffer; + XUartPsBuffer ReceiveBuffer; + + XUartPs_Handler Handler; + void *CallBackRef; /* Callback reference for event handler */ + u32 Platform; + u8 is_rxbs_error; +} XUartPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Get the UART Channel Status Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetChannelStatus(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) + +/****************************************************************************/ +/** +* Get the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_GetControl(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetModeControl(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET) + +/****************************************************************************/ +/** +* Set the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \ + (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Enable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_EnableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_EnableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN))) + +/****************************************************************************/ +/** +* Disable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_DisableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_DisableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS))) + +/****************************************************************************/ +/** +* Determine if the transmitter FIFO is empty. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return +* - TRUE if a byte can be sent +* - FALSE if the Transmitter Fifo is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(InstancePtr) \ + ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY) + + +/************************** Function Prototypes *****************************/ + +/* Static lookup function implemented in xuartps_sinit.c */ +#ifndef SDT +XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); +#else +XUartPs_Config *XUartPs_LookupConfig(u32 BaseAddress); +#endif + +/* Interface functions implemented in xuartps.c */ +s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, + XUartPs_Config * Config, u32 EffectiveAddr); + +u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); + +/* Options functions in xuartps_options.c */ +void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); + +u16 XUartPs_GetOptions(XUartPs *InstancePtr); + +void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); + +u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); + +u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); + +u32 XUartPs_IsSending(XUartPs *InstancePtr); + +u8 XUartPs_GetOperMode(XUartPs *InstancePtr); + +void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); + +u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); + +void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); + +u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); + +void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); + +s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +/* interrupt functions in xuartps_intr.c */ +u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); + +void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); + +void XUartPs_InterruptHandler(XUartPs *InstancePtr); + +void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, + void *CallBackRef); + +/* self-test functions in xuartps_selftest.c */ +s32 XUartPs_SelfTest(XUartPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xuartps_hw.h new file mode 100644 index 0000000..144f28c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/bspinclude/include/xuartps_hw.h @@ -0,0 +1,427 @@ +/****************************************************************************** +* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xuartps_hw.h +* @addtogroup uartps Overview +* @{ +* +* This header file contains the hardware interface of an XUartPs device. +* +*
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ------ -------- ---------------------------------------------- +* 1.00 drg/jz 01/12/10 First Release +* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL +* and XUARTPS_IXR_TTRIG. +* Modified the names of these defines +* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD +* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI +* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR +* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS +* 1.05a hk 08/22/13 Added prototype for uart reset and related +* constant definitions. +* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.6 ms 02/16/18 Updates flow control mode offset value in +* modem control register. +* +*+* +******************************************************************************/ +#ifndef XUARTPS_HW_H /* prevent circular inclusions */ +#define XUARTPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the UART. + * @{ + */ +#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */ +#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ +#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */ +#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */ +#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */ +#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/ +#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */ +#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */ +#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */ +#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */ +#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */ +#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ +#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */ +#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */ +#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */ +#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */ +#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */ +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */ +#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */ +#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */ +#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */ +#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */ +#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */ +#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */ +#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */ +#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */ +#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */ +/* @}*/ + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */ +#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */ +#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */ +#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */ +#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */ +#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */ +#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */ +#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */ +#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */ +#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */ +#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */ +#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */ +#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */ +#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */ +#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */ +#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */ +#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */ +#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */ +#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */ +#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */ +#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */ +#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */ +#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */ +#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */ +#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */ +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */ +#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */ +#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */ +#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */ +#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */ +#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */ +#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */ +#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */ +#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */ +#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */ +#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */ +#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */ +#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */ +/* @} */ + + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */ +#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */ +#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */ +#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */ +/* @} */ + + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */ +#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */ +#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Transmit FIFO Trigger Level Register + * + * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at + * which the TX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ +#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ +#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */ +#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */ +#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */ +#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */ +#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */ +#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */ +#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */ +#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */ +#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */ +#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */ +#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */ +#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */ +#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */ +#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */ +#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */ +#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */ +#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */ +#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ +/* @} */ + +/** @name Receiver FIFO Byte Status Register + * + * The Receiver FIFO Status register is used to have a continuous + * monitoring of the raw unmasked byte status information. The register + * contains frame, parity and break status information for the top + * four bytes in the RX FIFO. + * + * Receiver FIFO Byte Status Register Bit Definition + * @{ + */ +#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */ +#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */ +#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */ +#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */ +#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */ +#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */ +#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */ +#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */ +#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */ +#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */ +#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */ +#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */ +#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */ +/* @} */ + + +/* + * Defines for backwards compatibility, will be removed + * in the next version of the driver + */ +#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD +#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI +#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR +#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS + + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* Read a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) +* +******************************************************************************/ +#define XUartPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (u32)(RegOffset)) + +/***************************************************************************/ +/** +* Write a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* u32 XUartPs_IsReceiveData(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsReceiveData(BaseAddress) \ + !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitFull(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitFull(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL) + +/************************** Function Prototypes ******************************/ + +void XUartPs_SendByte(u32 BaseAddress, u8 Data); + +u8 XUartPs_RecvByte(u32 BaseAddress); + +void XUartPs_ResetHw(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/qemu_args.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/qemu_args.txt new file mode 100644 index 0000000..39b5bda --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/qemu_args.txt @@ -0,0 +1,51 @@ +######################################################################## +# This is file which used to generate QEMU(which emulates A9 core) +# commandline(start_qemu.sh script) which used in Zynq HW-EMU. +# This is a template file which is packaged in platform and it gets +# processed by Vitis tool to generate meaningful file. +# +# This file contains flag and value pairs and they must be seperated +# into two lines value followed by flag. Below are the common/mandated +# flag and value pairs used for emulating Zynq. User can add more +# commandline args to this file depends on requirements. +# +# For more details on the QEMU commandline, please refer to +# the QEMU user guide UG1169. +######################################################################## +# +# +# selects emulated machine +-M +arm-generic-fdt-7series +# +# +# redirect the serial port to specified char dev (i.e stdio, tcp port, file etc) +-serial +/dev/null +-serial +mon:stdio +# +# +# Register writes to SLCR block, to set PLL and CLK_CTRL regs (required for linux) +-device +loader,addr=0xf8000008,data=0xDF0D,data-len=4 +-device +loader,addr=0xf8000140,data=0x00500801,data-len=4 +-device +loader,addr=0xf800012c,data=0x1ed044d,data-len=4 +-device +loader,addr=0xf8000108,data=0x0001e008,data-len=4 +-device +loader,addr=0xF800025C,data=0x00000005,data-len=4 +-device +loader,addr=0xF8000240,data=0x00000000,data-len=4 +# +# +# Boot device selection +-boot +mode=5 +# +# +# Guest software to load during boot up +-kernel +