Add dc function (05-18)

2.FW/CPLD1/BUS_Con.v

@@ -152,8 +152,6 @@ module BUS_Con (
 
     // --- 4. Register Control FSM ---
 
-    
-
     always @(posedge i_sys_clk) begin
         if (!i_rst_n) begin
             state         <= IDLE;

2.FW/CPLD1/CPLD_Con.v

@@ -2,16 +2,35 @@ module CPLD_Con (
     input i_sys_clk,
     input i_rst_n,
     input i_con_exec,
+
+// Freq Relay Control
     input [23:0]i_freq_relay1,
     input [23:0]i_freq_relay2,
     input [23:0]i_freq_relay3,
     input [23:0]i_freq_relay4,
-    output o_con_done,
+
+// DC related Control
+    input [23:0]i_DC_Con1,
+    input [23:0]i_DC_Con2,
+    input [23:0]i_DC_Con3,
+    input [23:0]i_DC_Con4,
+
+    //Output RELAYs
     output [3:0]o_OC_x01,
     output [3:0]o_OC_x17,
     output [18:0]o_DMM_EN,
     output o_IO_RC1,
     output [4:0]o_RC_Tx,
+
+//  DMM Mode Sel
+    output o_RC_VSel;           
+    output o_RC_ISel;
+
+// Output RLoad Sel
+    output [17:0]o_RC_RLSel;
+
+//  FLAGs
+    output o_con_done,
     output o_err
 );
 
@@ -23,10 +42,16 @@ module CPLD_Con (
 	reg[4:0]RC_Tx;
     reg io_RC;
 
+    //Condition Tester
+    reg [15:0]en_t ;
+    reg freq_t;
+    reg dc_t;
+
     //Flags
     reg exec_flag;
     reg err_flag;
-    reg [3:0]slot_exec_flag;
+    reg [3:0]freq_slot_flag;
+    reg [3:0]dc_slot_flag ;
     reg done_flag;
 
     //Counter
@@ -46,15 +71,36 @@ module CPLD_Con (
         end
     end
 
+//Function Identify
+    always @(posedge i_sys_clk) begin
+        if (i_rst_n == 1'b0) begin
+            en_t <= 'd0;
+            freq_t <= 'd0;
+            dc_t <= 'd0;
+        end
+        else begin
+            en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
+            freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
+            dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
+        end
+    end
+
+//  Main Controller Function
     always @(posedge i_sys_clk) begin
         if (i_rst_n == 1'b0) begin
             exec_flag <= 1'b0;
             err_flag <= 1'b0;
-            slot_exec_flag <= 'd0;
+
+            freq_slot_flag <= 'd0;
+            dc_slot_flag <= 'd0;
 
             OC_x01              <= 'd0;
             OC_x17              <= 'd0;
             io_RC                  <= 'd0;
+            o_RC_VSel        <='d0;
+            o_RC_ISel         <='d0;
+            o_RC_RLSel     <='d0;
+
             done_flag <= 'd1;
         end
         else begin
@@ -62,20 +108,28 @@ module CPLD_Con (
                 exec_flag <= 1'b1;
                 done_flag <= 1'b0;
                 //To DO: More Sanity Check?
-                if (i_freq_relay1[0] && i_freq_relay2[0] && i_freq_relay3[0] && i_freq_relay4[0]) begin
+                if (en_t > 'd1) begin                                                   //Only ONE Enable bit should be set!
                     err_flag <= 1'b1;
                 end
                 else begin
-                    slot_exec_flag[0] <= i_freq_relay1[0];
+                    freq_slot_flag[0] <= i_freq_relay1[0];
-                    slot_exec_flag[1] <= i_freq_relay2[0];
+                    freq_slot_flag[1] <= i_freq_relay2[0];
-                    slot_exec_flag[2] <= i_freq_relay3[0];
+                    freq_slot_flag[2] <= i_freq_relay3[0];
-                    slot_exec_flag[3] <= i_freq_relay4[0];
+                    freq_slot_flag[3] <= i_freq_relay4[0];
-                    RC_Tx <= i_freq_relay4[14:10];
+                    
+                    RC_Tx <= i_freq_relay4[14:10];                      //Special Relay for slot4
+
+                    dc_slot_flag[0] <= i_DC_Con1[0];
+                    dc_slot_flag[1] <= i_DC_Con2[0];
+                    dc_slot_flag[2] <= i_DC_Con3[0];
+                    dc_slot_flag[3] <= i_DC_Con4[0];
+
                 end
             end
             else if (exec_flag == 1'b1) begin
+                if (freq_t == 1'b1) begin
                     io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
-                case (slot_exec_flag)
+                    case (freq_slot_flag)
                         4'b0001: begin
                             if (i_freq_relay1[9:1] < 9) begin
                                 OC_x01 <= 4'b0001;
@@ -164,12 +218,34 @@ module CPLD_Con (
                                 DMM_en <= 19'b000_1000_0000_0000_0000;
                             end
                         end
-                    default: begin 
+                        default: begin                                                                                  // You Should NOT be HERE
                             OC_x01 <= 4'b0000;
                             OC_x17 <= 4'b0000;
                             DMM_en <= 'd0;
                         end
                     endcase
+                end
+                else if (dc_t == 1'b1) begin
+                    case (dc_slot_flag)
+                        4'b0001: begin
+                            
+                        end
+                        4'b0010: begin
+                            
+                        end
+                        4'b0100:begin
+                            
+                        end
+                        4'b1000:begin
+                            
+                        end
+                        default:begin                           // You Should NOT be HERE
+                            o_RC_VSel        <='d0;
+                            o_RC_ISel         <='d0;
+                            o_RC_RLSel     <='d0;
+                        end
+                    endcase
+                end
                 done_flag <= 1'b1;
             end
         end

2.FW/CPLD1/Reg_file.v

@@ -18,10 +18,18 @@ module Reg_file (
     output o_exec,
     
     // Direct Register Outputs
+    //Freq Regs
     output [23:0] o_freq1,
     output [23:0] o_freq2,
     output [23:0] o_freq3,
-    output [23:0] o_freq4 
+    output [23:0] o_freq4,
+
+    //DC Regs
+    output [23:0] o_DC1,
+    output [23:0] o_DC2,
+    output [23:0] o_DC3,
+    output [23:0] o_DC4
+
 );
 
     // --- Parameters ---
@@ -163,5 +171,9 @@ module Reg_file (
     assign o_freq2  = regtable[3];
     assign o_freq3  = regtable[4];
     assign o_freq4  = regtable[5];
+    assign o_DC1    = regtable[6];
+    assign o_DC2    = regtable[7];
+    assign o_DC3    = regtable[8];
+    assign o_DC4    = regtable[9];
 
 endmodule

2.FW/CPLD1/RelayConTop.v

@@ -49,6 +49,12 @@ module RelayConTop (
 	wire [23:0]freq2_relay ;
 	wire [23:0]freq3_relay ;
 	wire [23:0]freq4_relay ;
+
+	wire [23:0]DC_Con1 ;
+	wire [23:0]DC_Con2 ;
+	wire [23:0]DC_Con3 ;
+	wire [23:0]DC_Con4 ;
+
 	wire con_rvalid;
 
 	wire con_done;
@@ -85,6 +91,10 @@ module RelayConTop (
 		.o_freq2(freq2_relay),                            		//Freq_Slot2
 		.o_freq3(freq3_relay),                            		//Freq_Slot3 
 		.o_freq4(freq4_relay),									//Freq_Slot4
+		.o_DC1(DC_Con1),
+		.o_DC2(DC_Con2),
+		.o_DC3(DC_Con3),
+		.o_DC4(DC_Con4),
 		.o_rvalid(con_rvalid),
 		.o_rdata(r_data),
 		.o_exec(con_exec),                                  	//Exec cmd