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PMU DC Control Output & bug fix

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This commit is contained in:
Jeremy Shen
2026-05-20 18:21:42 +08:00
parent 248a54b777
commit 7096f94f47
8 changed files with 1116 additions and 254 deletions
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2.FW/CPLD1/RelayConTop.v
+71 -19
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@@ -6,7 +6,7 @@ module RelayConTop (
input i_mosi,
input i_cs,
output o_miso,
output o_rvalid,
//output o_rvalid,
input i_rready,
input i_wvalid,
output o_wready,
@@ -19,15 +19,24 @@ module RelayConTop (
output o_RC_T29,
output o_RC_T30,
output o_RC_T31,
output [31:0]o_OC_1,
output [31:0]o_OC_2,
output [31:0]o_OC_3,
output [31:0]o_OC_4
output o_RC_T32,
output [17:0]o_RC_RLSel,
output o_RC_VSel,
output o_RC_ISel,
output [1:0]o_RC_LOF, //Strange DMM_N port relay
output [1:0]o_RC_LOS,
output [31:0]o_PMU_OC_1,
output [31:0]o_PMU_OC_2,
output [31:0]o_PMU_OC_3,
output [31:0]o_PMU_OC_4
);
wire [3:0]OC_x01;
wire [3:0]OC_x17;
wire [4:0]RC_Tx;
wire [5:0]RC_Tx;
wire [18:0]DMM_EN;
wire IO_RC1;
@@ -50,11 +59,26 @@ module RelayConTop (
wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
//PMU OC Control
wire [31:0]PMU_OC_1 ;
wire [31:0]PMU_OC_2 ;
wire [31:0]PMU_OC_3 ;
wire [31:0]PMU_OC_4 ;
//RL Control
wire [17:0]RC_RLSel ;
//DMM V Select
wire RC_VSel;
//DMM I Select
wire RC_ISel;
wire con_rvalid;
wire con_done;
@@ -110,39 +134,67 @@ module RelayConTop (
.i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay),
.i_freq_relay4(freq4_relay),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.o_con_done(con_done),
.o_OC_x01(OC_x01),
.o_OC_x17(OC_x17),
.o_RC_Tx(RC_Tx),
.o_DMM_EN(DMM_EN),
.o_PMU_OC_1(PMU_OC_1),
.o_PMU_OC_2(PMU_OC_2),
.o_PMU_OC_3(PMU_OC_3),
.o_PMU_OC_4(PMU_OC_4),
.o_RC_VSel(RC_VSel),
.o_RC_ISel(RC_ISel),
.o_RC_RLSel(RC_RLSel),
.o_IO_RC1(IO_RC1),
.o_err(cpld_err_flag)
);
assign o_con_done = con_done;
//assign o_OC_x01 = OC_x01;
assign o_OC_1[0] = OC_x01[0];
assign o_OC_2[0] = OC_x01[1];
assign o_OC_3[0] = OC_x01[2];
assign o_OC_4[0] = OC_x01[3];
assign o_PMU_OC_1[0] = OC_x01[0];
assign o_PMU_OC_2[0] = OC_x01[1];
assign o_PMU_OC_3[0] = OC_x01[2];
assign o_PMU_OC_4[0] = OC_x01[3];
//assign o_OC_x17 = OC_x17;
assign o_OC_1[16] = OC_x17[0];
assign o_OC_2[16] = OC_x17[1];
assign o_OC_3[16] = OC_x17[2];
assign o_OC_4[16] = OC_x17[3];
assign o_PMU_OC_1[16] = OC_x17[0];
assign o_PMU_OC_2[16] = OC_x17[1];
assign o_PMU_OC_3[16] = OC_x17[2];
assign o_PMU_OC_4[16] = OC_x17[3];
assign o_PMU_OC_1[15:1] = PMU_OC_1[15:1];
assign o_PMU_OC_1[31:17] = PMU_OC_1[31:17];
assign o_PMU_OC_2[15:1] = PMU_OC_2[15:1];
assign o_PMU_OC_2[31:17] = PMU_OC_2[31:17];
assign o_PMU_OC_3[15:1] = PMU_OC_3[15:1];
assign o_PMU_OC_3[31:17] = PMU_OC_3[31:17];
assign o_PMU_OC_4[15:1] = PMU_OC_4[15:1];
assign o_PMU_OC_4[31:17] = PMU_OC_4[31:17];
assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[4];
assign o_RC_T28 = RC_Tx[3];
assign o_RC_T29 = RC_Tx[2];
assign o_RC_T30 = RC_Tx[1];
assign o_RC_T31 = RC_Tx[0];
assign o_RC_T27 = RC_Tx[5];
assign o_RC_T28 = RC_Tx[4];
assign o_RC_T29 = RC_Tx[3];
assign o_RC_T30 = RC_Tx[2];
assign o_RC_T31 = RC_Tx[1];
assign o_RC_T32 = RC_Tx[0];
assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel;
assign o_RC_ISel = RC_ISel;
assign o_RC_LOF = (RC_VSel == 1'b1)?2'b01:2'b10; //if Measure V then close RC_LOF[0]
assign o_RC_LOS = (RC_VSel == 1'b1)?2'b01:2'b10;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;