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PMU DC Control Output & bug fix

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This commit is contained in:
Jeremy Shen
2026-05-20 18:21:42 +08:00
parent 248a54b777
commit 7096f94f47
8 changed files with 1116 additions and 254 deletions
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2.FW/CPLD1/CPLD_Con.v
+3 -3
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@@ -44,7 +44,7 @@ module CPLD_Con (
reg [3:0]OC_x17 ;
reg [18:0]DMM_en ;
reg[4:0]RC_Tx;
reg[5:0]RC_Tx;
reg io_RC;
reg RC_VISel;
@@ -136,7 +136,7 @@ module CPLD_Con (
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
RC_Tx <= i_freq_relay4[14:10]; //Special Relay for slot4
RC_Tx <= i_freq_relay4[17:12]; //Special Relay for slot4
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
@@ -325,7 +325,7 @@ module CPLD_Con (
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
end