Add testbenches

scripts/sim_cpld3.sh

@@ -0,0 +1,62 @@
+#!/bin/bash
+# CPLD3 RTL Behavioral Simulation Run Script
+# Project: NewCalBoard DIG
+# Tool: Lattice Diamond 3.14 / QuestaSim 2024.2
+# DUT: CPLD3 RelayConTop (PMU_RC[3:0] only)
+#
+# Usage: ./run_cpld3_sim.sh
+# Run inside distrobox container: distrobox enter fpga-tools -- ./run_cpld3_sim.sh
+
+set -e
+
+# Environment setup
+export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:$PATH"
+export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat"
+export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64"
+
+# Project root
+PROJECT_ROOT="/home/ly0kos/work/prj/New_CalBoard"
+CPLD3_DIR="${PROJECT_ROOT}/2.FW/CPLD3"
+TB_FILE="${CPLD3_DIR}/tb_RelayConTop.sv"
+
+# Temp directory
+SIM_DIR="/tmp/cpld3_sim"
+rm -rf "${SIM_DIR}"
+mkdir -p "${SIM_DIR}"
+cd "${SIM_DIR}"
+
+echo "============================================================="
+echo "  CPLD3 RTL Behavioral Simulation"
+echo "  DUT: RelayConTop (PMU_RC[3:0] only)"
+echo "============================================================="
+echo ""
+
+# Create libraries
+echo "[1/4] Creating libraries..."
+vlib work && vmap work work
+echo "  work library created"
+
+# Compile source files
+echo "[2/4] Compiling source files..."
+vlog -work work \
+    "${CPLD3_DIR}/BUS_Con.v" \
+    "${CPLD3_DIR}/Reg_file.v" \
+    "${CPLD3_DIR}/CPLD_Con.v" \
+    "${CPLD3_DIR}/RelayConTop.v"
+echo "  Source files compiled"
+
+# Compile testbench
+echo "[3/4] Compiling testbench..."
+vlog -work work "${TB_FILE}"
+echo "  Testbench compiled"
+
+# Run simulation
+echo "[4/4] Running simulation..."
+echo ""
+vsim -c -work work tb_RelayConTop -t 1ps +access+r \
+    -do "run -all; quit" 2>&1 | tee transcript.log
+
+echo ""
+echo "============================================================="
+echo "  Simulation complete. Results in: ${SIM_DIR}/transcript.log"
+echo "============================================================="