From 4d9b8116488e1996946fbe50350a80199dfb414a Mon Sep 17 00:00:00 2001 From: Jeremy Shen Date: Tue, 26 May 2026 18:32:25 +0800 Subject: [PATCH] Fallback to Vitis Classic --- 2.FW/Zynq/proj_cal/Vitis/.analytics | 11 + 2.FW/Zynq/proj_cal/Vitis/.gitignore | 17 - 2.FW/Zynq/proj_cal/Vitis/.peers.ini | 65 - 2.FW/Zynq/proj_cal/Vitis/.repo.yaml | 436 - 2.FW/Zynq/proj_cal/Vitis/.theia/settings.json | 3 - 2.FW/Zynq/proj_cal/Vitis/.vitisWorkspace.json | 3 - .../proj_cal/Vitis/NewCalBoard_APP/.gitignore | 17 - .../NewCalBoard_APP/_ide/.theia/launch.json | 54 - .../NewCalBoard_APP/compile_commands.json | 62 - .../Vitis/NewCalBoard_APP/src/.clangd | 4 - .../Vitis/NewCalBoard_APP/src/CMakeLists.txt | 64 - .../src/Empty_applicationExample.cmake | 13 - .../Vitis/NewCalBoard_APP/src/README.txt | 1 - .../NewCalBoard_APP/src/UserConfig.cmake | 158 - .../Vitis/NewCalBoard_APP/src/app.yaml | 3 - .../NewCalBoard_APP/src/compile_commands.json | 62 - .../Vitis/NewCalBoard_APP/vitis-comp.json | 18 - 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| 128 - .../gen_bsp/include/include/lwip/udp.h | 209 - .../gen_bsp/include/include/netif/bridgeif.h | 127 - .../include/include/netif/bridgeif_opts.h | 90 - .../gen_bsp/include/include/netif/etharp.h | 3 - .../gen_bsp/include/include/netif/ethernet.h | 77 - .../include/include/netif/ieee802154.h | 112 - .../gen_bsp/include/include/netif/lowpan6.h | 89 - .../include/include/netif/lowpan6_ble.h | 78 - .../include/include/netif/lowpan6_common.h | 82 - .../include/include/netif/lowpan6_opts.h | 122 - .../gen_bsp/include/include/netif/ppp/ccp.h | 164 - .../include/include/netif/ppp/chap-md5.h | 36 - .../include/include/netif/ppp/chap-new.h | 200 - .../include/include/netif/ppp/chap_ms.h | 44 - .../gen_bsp/include/include/netif/ppp/eap.h | 169 - .../gen_bsp/include/include/netif/ppp/ecp.h | 62 - .../gen_bsp/include/include/netif/ppp/eui64.h | 102 - .../gen_bsp/include/include/netif/ppp/fsm.h | 182 - .../gen_bsp/include/include/netif/ppp/ipcp.h | 134 - .../include/include/netif/ppp/ipv6cp.h | 191 - .../gen_bsp/include/include/netif/ppp/lcp.h | 179 - .../gen_bsp/include/include/netif/ppp/magic.h | 130 - .../gen_bsp/include/include/netif/ppp/mppe.h | 181 - .../include/include/netif/ppp/polarssl/arc4.h | 81 - .../include/include/netif/ppp/polarssl/des.h | 92 - .../include/include/netif/ppp/polarssl/md4.h | 97 - .../include/include/netif/ppp/polarssl/md5.h | 96 - .../include/include/netif/ppp/polarssl/sha1.h | 96 - .../gen_bsp/include/include/netif/ppp/ppp.h | 698 -- .../include/include/netif/ppp/ppp_impl.h | 722 -- .../include/include/netif/ppp/ppp_opts.h | 617 - .../include/include/netif/ppp/pppapi.h | 137 - .../include/include/netif/ppp/pppcrypt.h | 144 - .../include/include/netif/ppp/pppdebug.h | 88 - .../gen_bsp/include/include/netif/ppp/pppoe.h | 187 - .../include/include/netif/ppp/pppol2tp.h | 209 - .../gen_bsp/include/include/netif/ppp/pppos.h | 126 - .../gen_bsp/include/include/netif/ppp/upap.h | 131 - .../gen_bsp/include/include/netif/ppp/vj.h | 169 - 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1740 --- .../src/lwip-2.1.3/src/netif/ppp/chap-md5.c | 126 - .../src/lwip-2.1.3/src/netif/ppp/chap-new.c | 677 -- .../src/lwip-2.1.3/src/netif/ppp/chap_ms.c | 962 -- .../src/lwip-2.1.3/src/netif/ppp/demand.c | 465 - .../src/lwip-2.1.3/src/netif/ppp/eap.c | 2423 ---- .../src/lwip-2.1.3/src/netif/ppp/ecp.c | 191 - .../src/lwip-2.1.3/src/netif/ppp/eui64.c | 56 - .../src/lwip-2.1.3/src/netif/ppp/fsm.c | 799 -- .../src/lwip-2.1.3/src/netif/ppp/ipcp.c | 2418 ---- .../src/lwip-2.1.3/src/netif/ppp/ipv6cp.c | 1533 --- .../src/lwip-2.1.3/src/netif/ppp/lcp.c | 2790 ----- .../src/lwip-2.1.3/src/netif/ppp/magic.c | 294 - .../src/lwip-2.1.3/src/netif/ppp/mppe.c | 412 - .../src/lwip-2.1.3/src/netif/ppp/multilink.c | 609 - .../lwip-2.1.3/src/netif/ppp/polarssl/README | 22 - .../lwip-2.1.3/src/netif/ppp/polarssl/arc4.c | 101 - .../lwip-2.1.3/src/netif/ppp/polarssl/des.c | 422 - .../lwip-2.1.3/src/netif/ppp/polarssl/md4.c | 281 - .../lwip-2.1.3/src/netif/ppp/polarssl/md5.c | 300 - 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- .../proj_cal/Vitis/test_app/src/platform.h | 16 - .../proj_cal/Vitis/test_app/vitis-comp.json | 18 - 4566 files changed, 34689 insertions(+), 658043 deletions(-) create mode 100644 2.FW/Zynq/proj_cal/Vitis/.analytics delete mode 100644 2.FW/Zynq/proj_cal/Vitis/.gitignore delete mode 100644 2.FW/Zynq/proj_cal/Vitis/.peers.ini delete mode 100644 2.FW/Zynq/proj_cal/Vitis/.repo.yaml delete mode 100644 2.FW/Zynq/proj_cal/Vitis/.theia/settings.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/.vitisWorkspace.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/.gitignore delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/_ide/.theia/launch.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/compile_commands.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/.clangd delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/CMakeLists.txt delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/Empty_applicationExample.cmake delete mode 100755 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/README.txt delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/UserConfig.cmake delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/app.yaml delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/compile_commands.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/vitis-comp.json create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.cproject create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.gitignore create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.project rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt => NewInstCal_bsp/hw}/ps7_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt => NewInstCal_bsp/hw}/ps7_init.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt => NewInstCal_bsp/hw}/ps7_init_gpl.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt => NewInstCal_bsp/hw}/ps7_init_gpl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewCalBoard_APP/_ide/bitstream => NewInstCal_bsp/hw}/system_wrapper.bit (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp => NewInstCal_bsp}/hw/system_wrapper.xsa (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/platform.spr create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/Makefile create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/dep.mk rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/_profile_timer_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/arch/cc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/arch/cpu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/arch/perf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/arch/sys_arch.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/bspconfig.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/altcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/altcp_tcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/altcp_tls.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/FILES (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/altcp_proxyconnect.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/altcp_tls_mbedtls_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/fs.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/http_client.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/httpd.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/httpd_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/lwiperf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/mdns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/mdns_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/mdns_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/mqtt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/mqtt_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/mqtt_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/netbiosns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/netbiosns_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/smtp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/smtp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_core.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_mib2.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_scalar.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_snmpv2_framework.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_snmpv2_usm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_table.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmp_threadsync.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/snmpv3.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/sntp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/sntp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/tftp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/apps/tftp_server.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/arch.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/autoip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/debug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/def.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/dhcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/dhcp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/dns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/err.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/errno.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/etharp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ethip6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/icmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/icmp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/if_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/igmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/inet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/inet_chksum.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/init.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/init.h.cmake.in (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip4_addr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip4_frag.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip6_addr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip6_frag.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip6_zone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/ip_addr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/memp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/mld6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/nd6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/netbuf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/netdb.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/netif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/netifapi.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/opt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/pbuf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/altcp_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/api_msg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/mem_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/memp_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/memp_std.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/nd6_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/raw_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/sockets_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/tcp_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/priv/tcpip_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/autoip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/dhcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/dhcp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/dns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/etharp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/ethernet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/iana.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/icmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/icmp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/ieee.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/igmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/ip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/ip4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/ip6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/mld6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/nd6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/tcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/prot/udp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/raw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/sio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/snmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/sockets.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/stats.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/sys.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/tcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/tcpbase.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/tcpip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/timeouts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/lwip/udp.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwipopts.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/mblaze_nt_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/bridgeif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/bridgeif_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/etharp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ethernet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ieee802154.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/lowpan6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/lowpan6_ble.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/lowpan6_common.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/lowpan6_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ccp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/chap-md5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/chap-new.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/chap_ms.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/eap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ecp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/eui64.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/fsm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ipcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ipv6cp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/lcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/magic.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/mppe.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/polarssl/arc4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/polarssl/des.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/polarssl/md4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/polarssl/md5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/polarssl/sha1.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ppp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ppp_impl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/ppp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/pppapi.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/pppcrypt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/pppdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/pppoe.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/pppol2tp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/pppos.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/upap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/ppp/vj.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/slipif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xadapter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xaxiemacif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xemacliteif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xemacpsif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xlltemacif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xpqueue.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/xtopology.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/netif/zepif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/pm_api_version.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/profile.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/sleep.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/smc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/vectors.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xadcps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xadcps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xbasic_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xcoresightpsdcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xcortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xcortexa9_config.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xddrps.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xdevcfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xdevcfg_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xdmaps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xdmaps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xemacps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xemacps_bd.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xemacps_bdring.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xemacps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xenv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xenv_standalone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xgpiops.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xgpiops_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_assert.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_cache_vxworks.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_clocking.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_cryptoalginfo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_errata.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_hal.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_io.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_macroback.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_misc_psreset_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_printf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/xil_sleeptimer.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_spinlock.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_testcache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_testio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_testmem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xil_util.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xinterrupt_wrap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xl2cc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xl2cc_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xlwipconfig.h (84%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xplatform_info.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/xpm_init.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xqspips.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xqspips_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xreg_cortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xscugic.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xscugic_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xscutimer.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xscutimer_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xscuwdt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xscuwdt_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xsdps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xsdps_core.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xsdps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xstatus.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include}/xtime_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xuartps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0}/include/xuartps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/xcoresightpsdcc.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src}/xcoresightpsdcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12}/src/Makefile (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2}/src/Makefile (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/Makefile (100%) mode change 100755 => 100644 rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src}/xdevcfg.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src}/xdevcfg_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src}/xdmaps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src}/xdmaps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src}/xemacps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src}/xemacps_bd.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_bdring.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src}/xemacps_bdring.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_control.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src}/xemacps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src}/xgpiops.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src}/xgpiops_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/ChangeLog (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/Filelists.cmake (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/Makefile.adapter (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.config rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/Makefile.lwip (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/arch/cc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/arch/cpu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/arch/perf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/arch/sys_arch.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/lwipopts.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/include/lwipopts.h.in (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xadapter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xaxiemacif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xemacliteif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xemacpsif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xlltemacif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xpqueue.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx}/include/netif/xtopology.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacpsif_hw.h => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/xlwipconfig.h} (80%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/include/xlwipconfig.h.in (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xadapter.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif}/xemac_ieee_reg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xemacliteif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xemacpsif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xemacpsif_dma.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xemacpsif_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif}/xemacpsif_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/netif/xpqueue.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xtopology_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/sys_arch.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/contrib/ports/xilinx/sys_arch_raw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/CHANGELOG (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/COPYING (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/FEATURES (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/FILES (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/README (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip-2.1.3/UPGRADING (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/FILES (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/Filelists.cmake (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/Filelists.mk (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/api_lib.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/api_msg.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/err.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/if_api.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/netbuf.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/netdb.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/netifapi.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/sockets.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/api/tcpip.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/altcp_tls/altcp_tls_mbedtls.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/altcp_tls/altcp_tls_mbedtls_mem.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/altcp_tls/altcp_tls_mbedtls_mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/altcp_tls/altcp_tls_mbedtls_structs.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/altcp_proxyconnect.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/fs.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/fs/img/sics.gif (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/fsdata.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/fsdata.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/http_client.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/httpd.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/httpd_structs.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/makefsdata/makefsdata (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/makefsdata/makefsdata.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/makefsdata/readme.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/http/makefsdata/tinydir.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/lwiperf/lwiperf.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/mdns/mdns.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/mqtt/mqtt.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/netbiosns/netbiosns.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/smtp/smtp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_asn1.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_asn1.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_core.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_core_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_icmp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_interfaces.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_ip.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_snmp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_system.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_tcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_mib2_udp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_msg.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_msg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_netconn.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_pbuf_stream.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_pbuf_stream.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_raw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_scalar.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_snmpv2_framework.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_snmpv2_usm.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_table.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_threadsync.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmp_traps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmpv3.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmpv3_mbedtls.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/snmp/snmpv3_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/sntp/sntp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/apps/tftp/tftp_server.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/altcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/altcp_alloc.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/altcp_tcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/def.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/dns.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/inet_chksum.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ip.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/autoip.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/dhcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/etharp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/icmp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/igmp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/ip4.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/ip4_addr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv4/ip4_frag.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/dhcp6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/ethip6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/icmp6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/inet6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/ip6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/ip6_addr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/ip6_frag.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/mld6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/ipv6/nd6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/mem.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/memp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/netif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/pbuf.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/raw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/stats.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/sys.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/tcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/tcp_in.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/tcp_out.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/timeouts.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/core/udp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src}/include/compat/posix/arpa/inet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src}/include/compat/posix/net/if.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src}/include/compat/posix/netdb.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src}/include/compat/posix/sys/socket.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src}/include/compat/stdc/errno.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/altcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/altcp_tcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/altcp_tls.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/FILES (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/altcp_proxyconnect.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/altcp_tls_mbedtls_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/fs.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/http_client.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/httpd.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/httpd_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/lwiperf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/mdns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/mdns_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/mdns_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/mqtt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/mqtt_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/mqtt_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/netbiosns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/netbiosns_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/smtp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/smtp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_core.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_mib2.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_scalar.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_snmpv2_framework.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_snmpv2_usm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_table.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmp_threadsync.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/snmpv3.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/sntp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/sntp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/tftp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/apps/tftp_server.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/arch.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/autoip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/debug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/def.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/dhcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/dhcp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/dns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/err.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/errno.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/etharp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ethip6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/icmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/icmp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/if_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/igmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/inet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/inet_chksum.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/init.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/init.h.cmake.in (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip4_addr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip4_frag.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip6_addr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip6_frag.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip6_zone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/ip_addr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/memp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/mld6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/nd6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/netbuf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/netdb.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/netif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/netifapi.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/opt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/pbuf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/altcp_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/api_msg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/mem_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/memp_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/memp_std.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/nd6_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/raw_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/sockets_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/tcp_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/priv/tcpip_priv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/autoip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/dhcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/dhcp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/dns.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/etharp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/ethernet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/iana.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/icmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/icmp6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/ieee.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/igmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/ip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/ip4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/ip6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/mld6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/nd6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/tcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/prot/udp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/raw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/sio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/snmp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/sockets.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/stats.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/sys.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/tcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/tcpbase.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/tcpip.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/timeouts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/lwip/udp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/bridgeif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/bridgeif_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/etharp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ethernet.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ieee802154.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/lowpan6.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/lowpan6_ble.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/lowpan6_common.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/lowpan6_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ccp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/chap-md5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/chap-new.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/chap_ms.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/eap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ecp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/eui64.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/fsm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ipcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ipv6cp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/lcp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/magic.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/mppe.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/polarssl/arc4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/polarssl/des.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/polarssl/md4.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/polarssl/md5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/polarssl/sha1.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ppp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ppp_impl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/ppp_opts.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/pppapi.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/pppcrypt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/pppdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/pppoe.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/pppol2tp.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/pppos.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/upap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/ppp/vj.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/slipif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/include/netif/zepif.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/FILES (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/bridgeif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/bridgeif_fdb.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ethernet.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/lowpan6.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/lowpan6_ble.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/lowpan6_common.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/PPPD_FOLLOWUP (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/auth.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/ccp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/chap-md5.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/chap-new.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/chap_ms.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/demand.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/eap.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/ecp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/eui64.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/fsm.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/ipcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/ipv6cp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/lcp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/magic.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/mppe.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/multilink.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/polarssl/README (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/polarssl/arc4.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/polarssl/des.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/polarssl/md4.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/polarssl/md5.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/polarssl/sha1.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/ppp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/pppapi.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/pppcrypt.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/pppoe.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/pppol2tp.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/pppos.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/upap.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/utils.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/ppp/vj.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/slipif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3}/src/netif/zepif.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1}/src/lwip213.cmake (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src}/xqspips.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src}/xqspips_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_options.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src}/xscugic.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src}/xscugic_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src}/xscutimer.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src}/xscutimer_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/CMakeLists.txt (100%) mode change 100755 => 100644 rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src}/xscuwdt.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src}/xscuwdt_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src}/xsdps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_card.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src}/xsdps_core.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_host.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src}/xsdps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_options.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/_open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/_sbrk.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/abort.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/gcc/Makefile (100%) rename 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(100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/ZynqMP/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/versal/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/versal/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/usleep.c (100%) rename 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NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/xarmv8.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/xarmv8_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_iserror.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_istty.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_write.c (100%) rename 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2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/gcc/abort.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/gcc/close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/gcc/cpputest_time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/gcc/errno.c (100%) rename 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2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/gcc/write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc}/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/abort.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/clock.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/low_level_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/lseek.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/remove.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/xpseudo_asm_iccarm.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/xpseudo_asm_iccarm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/putnum.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/vectors.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common}/vectors.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/xil_exception.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common}/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/xil_sleeptimer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/xil_sleeptimer.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/xil_spinlock.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common}/xil_spinlock.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/xpm_counter.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/ARM_argv_veneer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_iserror.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_istty.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/asm_vectors.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/translation_table.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/cpu_init.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/gcc/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/asm_vectors.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/boot.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/translation_table.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/smc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/usleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xcortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xcortexa9_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_errata.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/xil_misc_psreset_api.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_misc_psreset_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/xil_mmu.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xl2cc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/xl2cc_counter.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xl2cc_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xreg_cortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/xtime_l.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/xtime_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/ARM_argv_veneer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/cpu_init.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/xpseudo_asm_armclang.h (100%) rename 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2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xreg_cortexr5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xtime_l.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xtime_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/platform/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/platform/versal_net/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/platform/versal_net/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/boot.S (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/bspconfig.h.in (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/changelog.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/inbyte.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/intr/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/intr/xinterrupt_wrap.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr}/xinterrupt_wrap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/outbyte.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/pm_api_version.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/print.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/sleep.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/versal/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/versal/xil_error_node.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/versal/xil_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/versal_net/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/versal_net/xil_error_node.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/versal_net/xil_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xbasic_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xenv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xenv_standalone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_assert.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_assert.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_cache_vxworks.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_cryptoalginfo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_hal.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_io.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_macroback.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_mem.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_printf.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_printf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_sleepcommon.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_testcache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_testcache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_testio.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_testio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_testmem.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_testmem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xil_util.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_util.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xplatform_info.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xplatform_info.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xpm_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/xpm_init.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xstatus.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/cpputest_time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/cpu_init.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/errno.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/fcntl.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/fstat.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/getentropy.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/getpid.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/intr/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/intr/xinterrupt_wrap.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr}/xinterrupt_wrap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/isatty.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/kill.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/lseek.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/errno.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/fcntl.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/fsl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/hw_exception_handler.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/mb_interface.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_exceptions.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_exceptions.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_exception_handler.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_exceptions_g.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_exceptions_i.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_cache_ext.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_cache_ext_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_init_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_init_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_instructions.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_interrupt_handler.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_interrupts_g.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_interrupts_i.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_cache_ext.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_cache_ext_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_icache_range.S (100%) rename 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(100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_update_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_update_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/pvr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/pvr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_exception.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_misc_psreset_api.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_misc_psreset_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xmicroblaze.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xmicroblaze_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/open.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/print.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_clean.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_timer_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_timer_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/dummy.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/mblaze_nt_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_cg.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_hist.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_mcount_arm.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_mcount_mb.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_mcount_ppc.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/putnum.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/_sbrk.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/errno.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/fcntl.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/fsl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_disable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_enable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_exceptions_g.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_interface.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_interrupt_handler.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_scrub.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/trap_handler.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xil_exception.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xreg_riscv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/sbrk.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/sleep.h (52%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/smc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/unlink.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/usleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/vectors.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/vectors.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/versal/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/versal/xil_error_node.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/versal/xil_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/versal_net/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/versal_net/xil_error_node.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/versal_net/xil_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xbasic_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xcortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xcortexa9_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xenv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xenv_standalone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_assert.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_assert.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache_vxworks.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cryptoalginfo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_errata.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_exception.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_hal.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_io.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_macroback.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_mem.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_misc_psreset_api.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_misc_psreset_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_mmu.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_printf.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_printf.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_sleepcommon.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_sleeptimer.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_spinlock.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_spinlock.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testcache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testcache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testio.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testmem.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testmem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_util.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_util.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/xilstandalone.cmake (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/intr => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xinterrupt_wrap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xl2cc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xl2cc_counter.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xl2cc_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xplatform_info.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xplatform_info.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpm_counter.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpm_init.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xreg_cortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xstatus.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xtime_l.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src}/xuartps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src}/xuartps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_options.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/CMakeLists.txt (100%) mode change 100755 => 100644 rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src}/xadcps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src}/xadcps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw => NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain}/qemu/qemu_args.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/qemu => NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain}/qemu_args.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/CMakeLists.txt (97%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Makefile create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Xilinx.spec create mode 100755 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/fsbl.elf rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/fsbl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/fsbl_debug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/fsbl_handoff.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/fsbl_hooks.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/fsbl_hooks.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/image_mover.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/image_mover.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/lscript.ld (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/main.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/md5.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/md5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/nand.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/nand.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/nor.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/nor.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/pcap.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/pcap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/hw_artifacts => NewInstCal_bsp/zynq_fsbl}/ps7_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/hw_artifacts => NewInstCal_bsp/zynq_fsbl}/ps7_init.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/qspi.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/qspi.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/rsa.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/rsa.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/sd.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp => NewInstCal_bsp}/zynq_fsbl/sd.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/Makefile create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/dep.mk create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/diskio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/ff.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/ffconf.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/pm_api_version.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/sleep.h (52%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/smc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/vectors.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xadcps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xadcps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xbasic_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xcoresightpsdcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xcortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xcortexa9_config.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xdevcfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xdevcfg_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xdmaps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xdmaps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xemacps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xemacps_bd.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xemacps_bdring.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xemacps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xenv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xenv_standalone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xgpiops.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xgpiops_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_assert.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_cache_vxworks.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_clocking.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_cryptoalginfo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_errata.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_hal.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_io.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_macroback.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_mem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_misc_psreset_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_printf.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_spinlock.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_testcache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_testio.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_testmem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xil_util.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xilrsa.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xinterrupt_wrap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xl2cc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xl2cc_counter.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xplatform_info.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xpm_counter.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_init.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xqspips.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xqspips_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9 => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xreg_cortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xscugic.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xscugic_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xscutimer.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xscutimer_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xscuwdt.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xscuwdt_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xsdps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xsdps_core.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xsdps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include}/xstatus.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xuartps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0}/include/xuartps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/xcoresightpsdcc.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9}/src/xcoresightpsdcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12}/src/Makefile (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2}/src/Makefile (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/Makefile (100%) mode change 100755 => 100644 rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8}/src/xdevcfg_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9}/src/xdmaps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_bd.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_bdring.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_bdring.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_control.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19}/src/xemacps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12}/src/xgpiops_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_options.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11}/src/xqspips_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2}/src/xscugic_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/Makefile (73%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5}/src/xscutimer_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/CMakeLists.txt (100%) mode change 100755 => 100644 rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/Makefile (73%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5}/src/xscuwdt_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/CMakeLists.txt (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/Makefile rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_card.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_core.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_host.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_options.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2}/src/xsdps_sinit.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/Makefile create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_exit.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_open.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_sbrk.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/abort.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/gcc/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/gcc/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/gcc/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/gcc/cpu_init.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/gcc/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/ZynqMP/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/versal/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/platform/versal/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/usleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xil_mmu.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xreg_cortexa53.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xtime_l.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/32bit/xtime_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/armclang/ARM_argv_veneer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/armclang/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/armclang/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/armclang/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/armclang/xpseudo_asm_armclang.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/gcc/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/gcc/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/gcc/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/gcc/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/gcc/initialise_monitor_handles.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/gcc/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/ZynqMP/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/ZynqMP/armclang/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/versal/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/versal/armclang/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/versal/gcc/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/versal/gcc/translation_table.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/platform/versal/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_errata.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_mmu.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_smc.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xil_smc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/arm64_ops.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/hypercall.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/hypercall.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/xen.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/xen_console.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/xen_console.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/xen_events.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xpvxenconsole/xen_events.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xreg_cortexa53.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xtime_l.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/64bit/xtime_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slave_xmpu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slcr_secure.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h (100%) rename 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2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/xarmv8.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/ARMv8/xarmv8_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_iserror.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_istty.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/armclang/_sys_write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/gcc/CMakeLists.txt (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_exit.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_open.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_sbrk.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/abort.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/close.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/cpputest_time.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/errno.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fcntl.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fstat.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getentropy.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getpid.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/isatty.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/kill.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/lseek.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/open.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/read.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/sbrk.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/time.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/unlink.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/write.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc}/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/abort.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/clock.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/low_level_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/lseek.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/remove.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/xpseudo_asm_iccarm.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/common/iccarm/xpseudo_asm_iccarm.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/putnum.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/vectors.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common}/vectors.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_exception.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common}/xil_exception.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_spinlock.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common}/xil_spinlock.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xpm_counter.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/ARM_argv_veneer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_close.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_iserror.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_istty.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_open.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_read.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_time.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/_sys_write.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/asm_vectors.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/translation_table.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/Makefile create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/asm_vectors.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/boot.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/cpu_init.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/translation_table.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/xil-crt0.S rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/asm_vectors.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/boot.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexa9/iccarm/translation_table.s (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/sleep.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/smc.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/usleep.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xcortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xcortexa9_config.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_errata.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_misc_psreset_api.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_misc_psreset_api.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_mmu.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xl2cc.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc_counter.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xl2cc_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9}/xreg_cortexa9.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/ARM_argv_veneer.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/cpu_init.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/armclang/xpseudo_asm_armclang.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/gcc/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/gcc/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/gcc/asm_vectors.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/gcc/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/gcc/cpu_init.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/gcc/xil-crt0.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/iccarm/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/iccarm/asm_vectors.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/iccarm/boot.s (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR5/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR5/xcortexr5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR5/xcortexr5_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR5/xil_mpu_r5.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR5/xil_mpu_r5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR52/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR52/xcortexr52.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR52/xcortexr52_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/versal-net/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/versal-net/mpu_r52.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/versal/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/versal/mpu_r5.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/platform/versal/xparameters_ps.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/usleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xil_mmu.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xpm_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xreg_cortexr5.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xtime_l.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/cortexr5/xtime_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/platform/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/platform/versal_net/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/arm/platform/versal_net/xparameters_ps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/asm_vectors.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/boot.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/bspconfig.h.in (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/changelog.txt (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/close.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/inbyte.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/xinterrupt_wrap.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr}/xinterrupt_wrap.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/common/outbyte.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/pm_api_version.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/print.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xiltimer/src => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/sleep.h (52%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_error_node.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_hw.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_error_node.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_hw.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xbasic_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xenv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xenv_standalone.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/xbasic_types.c => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_assert.c} (55%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_assert.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_cache_vxworks.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_cryptoalginfo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_hal.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_io.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_macroback.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_mem.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_printf.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_sleepcommon.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_testcache.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_testio.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_testmem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_types.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xil_util.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xplatform_info.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common}/xstatus.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpputest_time.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpu_init.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/errno.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fcntl.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fstat.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getentropy.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getpid.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/intr/xinterrupt_wrap.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/isatty.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/kill.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/lseek.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/errno.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/fcntl.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/fsl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/hw_exception_handler.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/mb_interface.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_exceptions.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_disable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_exceptions.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_enable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_exception_handler.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_exceptions_g.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_exceptions_i.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_cache_ext.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_cache_ext_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_flush_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_init_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_init_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_instructions.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_interrupt_handler.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_interrupts_g.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_interrupts_i.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_cache_ext.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_cache_ext_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_invalidate_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_scrub.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_selftest.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_sleep.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_sleep.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_update_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/microblaze_update_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/pvr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/pvr.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_cache.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_exception.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_misc_psreset_api.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xil_misc_psreset_api.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xmicroblaze.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/microblaze/xmicroblaze_config.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/open.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/print.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_clean.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_init.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/_profile_timer_hw.c (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_timer_hw.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/dummy.S (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/mblaze_nt_types.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_cg.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_hist.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_mcount_arm.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_mcount_mb.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/profile/profile_mcount_ppc.S (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/putnum.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/read.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/_exit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/_sbrk.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/boot.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/errno.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/fcntl.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/fsl.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_disable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_enable_interrupts.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_exceptions_g.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_flush_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_interface.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_interrupt_handler.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_dcache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_dcache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_icache.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_invalidate_icache_range.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/riscv_scrub.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/trap_handler.S (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xil_exception.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/riscv/xreg_riscv.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sbrk.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/sleep.h (52%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/smc.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/time.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/translation_table.S create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/unlink.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/usleep.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/vectors.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_error_node.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_hw.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/CMakeLists.txt create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_error_node.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_hw.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/write.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xbasic_types.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xcortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xcortexa9_config.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xdebug.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xenv.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xenv_standalone.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil-crt0.S rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/xbasic_types.c => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.c} (55%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_assert.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache_l.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cache_vxworks.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_cryptoalginfo.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_errata.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_exception.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_hal.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_io.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_macroback.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_mem.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_misc_psreset_api.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_mmu.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_printf.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleepcommon.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_spinlock.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testcache.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testio.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_testmem.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_types.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xil_util.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0}/src/xilstandalone.cmake (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xl2cc.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xl2cc_counter.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xparameters_ps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xplatform_info.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpm_counter.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpseudo_asm.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xpseudo_asm_gcc.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xreg_cortexa9.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src}/xstatus.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.c create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/CMakeLists.txt (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/Makefile rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_hw.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_options.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13}/src/xuartps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/CMakeLists.txt (100%) mode change 100755 => 100644 rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps.h (100%) create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_hw.h (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_intr.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_selftest.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7}/src/xadcps_sinit.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1}/src/CMakeLists.txt (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1}/src/Makefile (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1}/src/diskio.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1}/src/ff.c (100%) rename 2.FW/Zynq/proj_cal/Vitis/{NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs => NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1}/src/ffsystem.c (100%) rename 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/compat/posix/net/if.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/compat/posix/netdb.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/compat/posix/sys/socket.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/compat/stdc/errno.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/altcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/altcp_tcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/altcp_tls.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/api.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/FILES delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/altcp_proxyconnect.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/altcp_tls_mbedtls_opts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/fs.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/http_client.h delete mode 100644 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/mqtt.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/mqtt_opts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/mqtt_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/netbiosns.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/netbiosns_opts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/apps/smtp.h delete mode 100644 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/dhcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/dhcp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/dns.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/err.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/errno.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/etharp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ethip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/icmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/icmp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/if_api.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/igmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/inet.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/inet_chksum.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/init.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/init.h.cmake.in delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ip4.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ip4_addr.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ip4_frag.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/ip6_addr.h delete mode 100644 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/netbuf.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/netdb.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/netif.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/netifapi.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/opt.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/pbuf.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/priv/altcp_priv.h delete mode 100644 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100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/igmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/ip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/ip4.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/ip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/mld6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/nd6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/tcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/prot/udp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/raw.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/sio.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/snmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/sockets.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/stats.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/include/lwip/sys.h delete mode 100644 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/err.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/errno.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/etharp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ethip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/icmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/icmp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/if_api.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/igmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/inet.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/inet_chksum.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/init.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/init.h.cmake.in delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip4.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip4_addr.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip4_frag.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip6_addr.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip6_frag.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip6_zone.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/ip_addr.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/mem.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/memp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/mld6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/nd6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/netbuf.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/netdb.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/netif.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/netifapi.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/opt.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/pbuf.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/altcp_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/api_msg.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/mem_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/memp_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/memp_std.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/nd6_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/raw_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/sockets_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/tcp_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/priv/tcpip_priv.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/autoip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/dhcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/dhcp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/dns.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/etharp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/ethernet.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/iana.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/icmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/icmp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/ieee.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/igmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/ip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/ip4.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/ip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/mld6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/nd6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/tcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/prot/udp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/raw.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/sio.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/snmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/sockets.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/stats.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/sys.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/tcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/tcpbase.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/tcpip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/timeouts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/lwip/udp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/bridgeif.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/bridgeif_opts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/etharp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ethernet.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ieee802154.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/lowpan6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/lowpan6_ble.h delete mode 100644 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ppp/eap.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ppp/ecp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ppp/eui64.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ppp/fsm.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ppp/ipcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/src/include/netif/ppp/ipv6cp.h delete mode 100644 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100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/err.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/errno.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/etharp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/ethip6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/icmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/icmp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/if_api.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/igmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/inet.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/inet_chksum.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/init.h delete mode 100644 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delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/ip6_addr.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/ip6_frag.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/ip6_zone.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/ip_addr.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/mem.h delete mode 100644 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100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/sys.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/tcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/tcpbase.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/tcpip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/timeouts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/lwip/udp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/netif/bridgeif.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/netif/bridgeif_opts.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/netif/etharp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/netif/ethernet.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/include/netif/ieee802154.h delete mode 100644 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100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/dhcp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/dhcp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/dns.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/err.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/errno.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/etharp.h delete mode 100644 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delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/prot/icmp6.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/prot/ieee.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/prot/igmp.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/prot/ip.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/lwip-2.1.3/src/include/lwip/prot/ip4.h delete mode 100644 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create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_system/.cproject create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_system/.gitignore create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_system/.project create mode 100644 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_system/NewInstrCalBoard_system.sprj create mode 100644 2.FW/Zynq/proj_cal/Vitis/RemoteSystemsTempFiles/.project delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/.gitignore delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/_ide/.theia/launch.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/_ide/bitstream/system_wrapper.bit delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/_ide/hwspec.checksum delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/compile_commands.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/.clangd delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/CMakeLists.txt delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/Hello_worldExample.cmake delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/UserConfig.cmake delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/app.yaml delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/compile_commands.json delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/helloworld.c delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/lscript.ld delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/platform.c delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/src/platform.h delete mode 100644 2.FW/Zynq/proj_cal/Vitis/test_app/vitis-comp.json diff --git a/2.FW/Zynq/proj_cal/Vitis/.analytics b/2.FW/Zynq/proj_cal/Vitis/.analytics new file mode 100644 index 0000000..7f06cd6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/.analytics @@ -0,0 +1,11 @@ +timestamp=[2026-05-26 10:20:53], mode=WORKBENCH_START, duration=0:00:02.125, duration_ms=2125, data={} +timestamp=[2026-05-26 10:20:53], mode=PLATFORM_REPOSITORY_INIT, duration=0:00:00.015, duration_ms=15, data={} +timestamp=[2026-05-26 10:20:53], mode=WORKBENCH_UI_INIT, duration=0:00:00.173, duration_ms=173, data={editors_count=0, platform_editors_count=0, projects_count=0, platform_projects_count=0, active_platform_editor=false, projects=} +timestamp=[2026-05-26 10:22:06], mode=PLATFORM_CREATION, duration=0:00:03.275, duration_ms=3275, data={platform_source=dsa, os=standalone, processor=ps7_cortexa9, platform=null} +timestamp=[2026-05-26 10:23:03], mode=APP_CREATION, duration=0:00:02.818, duration_ms=2818, data={name=NewInstrCalBoard, project_type=sdk, os=standalone, processor=cortex-a9, runtime=C/C++, platform=NewInstCal_bsp, application_type=application} +timestamp=[2026-05-26 10:24:48], mode=PLATFORM_GENERATION, duration=0:00:08.086, duration_ms=8086, data={name=NewInstCal_bsp} +timestamp=[2026-05-26 10:24:49], mode=BUILD, duration=0:00:00.432, duration_ms=432, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false} +timestamp=[2026-05-26 10:31:30], mode=BUILD, duration=0:00:00.283, duration_ms=283, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false} +timestamp=[2026-05-26 10:31:35], mode=BUILD, duration=0:00:04.585, duration_ms=4585, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false} +timestamp=[2026-05-26 10:31:41], mode=BUILD, duration=0:00:00.130, duration_ms=130, data={name=NewInstrCalBoard, configuration=Debug, clean_build=false} +timestamp=[2026-05-26 10:31:46], mode=BUILD, duration=0:00:04.531, duration_ms=4531, data={name=NewInstrCalBoard_system, configuration=Debug, clean_build=false} diff --git a/2.FW/Zynq/proj_cal/Vitis/.gitignore b/2.FW/Zynq/proj_cal/Vitis/.gitignore deleted file mode 100644 index 9b16e22..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/.gitignore +++ /dev/null @@ -1,17 +0,0 @@ -# Ignore build output directory -/build - - -# Ignore object files and dependent files -.o -.d - -#Ignore logs folder and log files -/logs -.log - -#Ignore lock files -.lock - -.bin -.pdi \ No newline at end of file diff --git a/2.FW/Zynq/proj_cal/Vitis/.peers.ini b/2.FW/Zynq/proj_cal/Vitis/.peers.ini deleted file mode 100644 index 20b1b54..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/.peers.ini +++ /dev/null @@ -1,65 +0,0 @@ -DefaultTarget=true -ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d -TransportName=TCP -AutoSetJtagFrequency=false -PeerTypeId=LINUX_EMULATION -UserName=ly0kos -Port=1440 -Host=127.0.0.1 -OSName=Linux -ID=LinuxEmulation -AgentID=0362f829-e89b-432f-b55e-58f745adaf5d -Name=LinuxEmulation - -DefaultTarget=true -ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d -TransportName=TCP -AutoSetJtagFrequency=false -PeerTypeId=XRT_SERVER -UserName=ly0kos -Port=1222 -Host=127.0.0.1 -OSName=Linux -ID=XRTServer -AgentID=0362f829-e89b-432f-b55e-58f745adaf5d -Name=XRTServer - -DefaultTarget=true -ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d -TransportName=TCP -AutoSetJtagFrequency=true -PeerTypeId=HARDWARE_SERVER -UserName=ly0kos -Port=3121 -Host=127.0.0.1 -OSName=Linux -ID=Local -AgentID=0362f829-e89b-432f-b55e-58f745adaf5d -Name=Local - -DefaultTarget=true -ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d -TransportName=TCP -AutoSetJtagFrequency=false -PeerTypeId=LINUX_TCF_AGENT -UserName=ly0kos -Port=1534 -Host=192.168.0.1 -OSName=Linux -ID=Linux Agent -AgentID=0362f829-e89b-432f-b55e-58f745adaf5d -Name=Linux Agent - -DefaultTarget=true -ServiceManagerID=0362f829-e89b-432f-b55e-58f745adaf5d -TransportName=TCP -AutoSetJtagFrequency=false -PeerTypeId=QEMU_TCF_GDB_CLIENT -UserName=ly0kos -Port=1138 -Host=127.0.0.1 -OSName=Linux -ID=QEMU -AgentID=0362f829-e89b-432f-b55e-58f745adaf5d -Name=QEMU - diff --git a/2.FW/Zynq/proj_cal/Vitis/.repo.yaml b/2.FW/Zynq/proj_cal/Vitis/.repo.yaml deleted file mode 100644 index c10eba0..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/.repo.yaml +++ /dev/null @@ -1,436 +0,0 @@ -paths: - /data/xilinx/Vitis/2023.2/data/embeddedsw: {} -os: - freertos10_xilinx: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/ThirdParty/bsp/freertos10_xilinx_v1_14 - standalone: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/lib/bsp/standalone_v9_0 -driver: - devcfg: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/devcfg_v3_8 - qspips: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/qspips_v3_11 - resetps: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/resetps_v1_6 - scugic: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/scugic_v5_2 - sysmonpsv: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/sysmonpsv_v4_1 - uartps: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartps_v3_13 - uartlite: - path: - - /data/xilinx/Vitis/2023.2/data/embeddedsw/XilinxProcessorIPLib/drivers/uartlite_v3_9 - wdttb: - path: - - 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"clangd.fallbackFlags": [] -} \ No newline at end of file diff --git a/2.FW/Zynq/proj_cal/Vitis/.vitisWorkspace.json b/2.FW/Zynq/proj_cal/Vitis/.vitisWorkspace.json deleted file mode 100644 index 8abf75a..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/.vitisWorkspace.json +++ /dev/null @@ -1,3 +0,0 @@ -[ - "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp" -] \ No newline at end of file diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/.gitignore b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/.gitignore deleted file mode 100644 index 9b16e22..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/.gitignore +++ /dev/null @@ -1,17 +0,0 @@ -# Ignore build output directory -/build - - -# Ignore object files and dependent files -.o -.d - -#Ignore logs folder and log files -/logs -.log - -#Ignore lock files -.lock - -.bin -.pdi \ No newline at end of file diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/_ide/.theia/launch.json b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/_ide/.theia/launch.json deleted file mode 100644 index a93bc40..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/_ide/.theia/launch.json +++ /dev/null @@ -1,54 +0,0 @@ -{ - "version": "0.2.0", - "configurations": [ - { - "type": "tcf-debug", - "request": "launch", - "name": "NewCalBoard_APP_app_hw_1", - "debugType": "baremetal-zynq", - "attachToRunningTargetOptions": { - "targetSetupMode": "standalone", - "executeScript": true, - "scriptPath": "" - }, - "autoAttachProcessChildren": false, - "target": { - "targetConnectionId": "Local", - "peersIniPath": "../../../.peers.ini", - "context": "zynq" - }, - "targetSetup": { - "resetSystem": true, - "programDevice": true, - "resetAPU": false, - "bitstreamFile": "${workspaceFolder}/NewCalBoard_APP/_ide/bitstream/system_wrapper.bit", - "zynqInitialization": { - "isFsbl": true, - "usingFSBL": { - "initWithFSBL": true, - "fsblFile": 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b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/.clangd deleted file mode 100644 index e867464..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/.clangd +++ /dev/null @@ -1,4 +0,0 @@ - -CompileFlags: - Add: [-Wno-unknown-warning-option, -U__linux__, -U__clang__] - Remove: [-m*, -f*] diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/CMakeLists.txt deleted file mode 100644 index 00f0fe8..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/CMakeLists.txt +++ /dev/null @@ -1,64 +0,0 @@ -# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. -# SPDX-License-Identifier: MIT -cmake_minimum_required(VERSION 3.16) - -include(${CMAKE_SOURCE_DIR}/Empty_applicationExample.cmake) -include(${CMAKE_CURRENT_SOURCE_DIR}/UserConfig.cmake) -set(APP_NAME NewCalBoard_APP) -project(${APP_NAME}) - -find_package(common) -enable_language(C ASM CXX) -collect(PROJECT_LIB_DEPS xilstandalone) -collect(PROJECT_LIB_DEPS xil) -collect(PROJECT_LIB_DEPS xiltimer;lwip213) - - - - - - - - - - - - -collect(PROJECT_LIB_DEPS gcc) -collect(PROJECT_LIB_DEPS c) - -aux_source_directory(${CMAKE_SOURCE_DIR} _sources) -foreach (source ${_sources}) - get_filename_component(ext ${source} EXT) - list(APPEND src_ext ${ext}) -endforeach() - -find_project_type ("${src_ext}" PROJECT_TYPE) - -if("${PROJECT_TYPE}" STREQUAL "c++") -collect(PROJECT_LIB_DEPS stdc++) -endif() -collector_list (_deps PROJECT_LIB_DEPS) -list (APPEND _deps ${USER_LINK_LIBRARIES}) - -if("${PROJECT_TYPE}" STREQUAL "c++") -string (REPLACE ";" ",-l" _deps "${_deps}") -endif() -if(CMAKE_EXPORT_COMPILE_COMMANDS) - set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) - set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) -endif() -linker_gen("${CMAKE_SOURCE_DIR}/linker_files/") -string(APPEND CMAKE_C_FLAGS ${USER_COMPILE_OPTIONS}) -string(APPEND CMAKE_CXX_FLAGS ${USER_COMPILE_OPTIONS}) -string(APPEND CMAKE_C_LINK_FLAGS ${USER_LINK_OPTIONS}) -string(APPEND CMAKE_CXX_LINK_FLAGS ${USER_LINK_OPTIONS}) -if(NOT "${_sources}" STREQUAL "") -set_source_files_properties(${_sources} OBJECT_DEPENDS "${CMAKE_LIBRARY_PATH}/*.a") -add_executable(${APP_NAME}.elf ${_sources}) -set_target_properties(${APP_NAME}.elf PROPERTIES LINK_DEPENDS ${CMAKE_SOURCE_DIR}/lscript.ld) -target_link_libraries(${APP_NAME}.elf -Wl,-T -Wl,\"${CMAKE_SOURCE_DIR}/lscript.ld\" -L\"${CMAKE_SOURCE_DIR}/\" -L\"${CMAKE_LIBRARY_PATH}/\" -L\"${USER_LINK_DIRECTORIES}/\" -Wl,--start-group,-l${_deps} -Wl,--end-group) -target_compile_definitions(${APP_NAME}.elf PUBLIC ${USER_COMPILE_DEFINITIONS}) -target_include_directories(${APP_NAME}.elf PUBLIC ${USER_INCLUDE_DIRECTORIES}) -print_elf_size(CMAKE_SIZE ${APP_NAME}) -endif() diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/Empty_applicationExample.cmake b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/Empty_applicationExample.cmake deleted file mode 100644 index a1b8b3d..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/Empty_applicationExample.cmake +++ /dev/null @@ -1,13 +0,0 @@ -set(DDR ps7_ddr_0) -set(ps7_ddr_0 "0x100000;0x3ff00000") -set(ps7_ram_0 "0x0;0x30000") -set(ps7_ram_1 "0xffff0000;0xfe00") -set(TOTAL_MEM_CONTROLLERS "ps7_ddr_0;ps7_ram_0;ps7_ram_1") -set(MEMORY_SECTION "MEMORY -{ - ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3ff00000 - ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000 - ps7_ram_1 : ORIGIN = 0xffff0000, LENGTH = 0xfe00 -}") -set(STACK_SIZE 0x2000) -set(HEAP_SIZE 0x2000) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/README.txt b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/README.txt deleted file mode 100755 index c4d32ef..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/README.txt +++ /dev/null @@ -1 +0,0 @@ -Empty application. Add your own sources. diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/UserConfig.cmake b/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/UserConfig.cmake deleted file mode 100644 index daae09b..0000000 --- a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/src/UserConfig.cmake +++ /dev/null @@ -1,158 +0,0 @@ -# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. -# SPDX-License-Identifier: MIT -cmake_minimum_required(VERSION 3.16) - -### USER SETTINGS START ### -# Below settings can be customized -# User need to edit it manually as per their needs. -### DO NOT ADD OR REMOVE VARIABLES FROM THIS SECTION ### -# ----------------------------------------- -# Add any compiler definitions, they will be added as extra definitions -# Example adding VERBOSE=1 will pass -DVERBOSE=1 to the compiler. -set(USER_COMPILE_DEFINITIONS -"" -) - -# Undefine any previously specified compiler definitions, either built in or provided with a -D option -# Example adding MY_SYMBOL will pass -UMY_SYMBOL to the compiler. -set(USER_UNDEFINED_SYMBOLS -"__clang__" -) - - -# Add any directories below, they will be added as extra include directories. -# Example 1: Adding /proj/data/include will pass -I/proj/data/include -# Example 2: Adding ../../common/include will consider the path as relative to this component directory. -# Example 3: Adding ${CMAKE_SOURCE_DIR}/data/include to add data/include from this project. - -set(USER_INCLUDE_DIRECTORIES - "${CMAKE_SOURCE_DIR}/../../NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include" -) - -# ----------------------------------------- - -# Turn on all optional warnings (-Wall) -set(USER_COMPILE_WARNINGS_ALL -Wall) - -# Enable extra warning flags (-Wextra) -set(USER_COMPILE_WARNINGS_EXTRA -Wextra) - -# Make all warnings into hard errors (-Werror) -set(USER_COMPILE_WARNINGS_AS_ERRORS ) - -# Check the code for syntax errors, but don't do anything beyond that. (-fsyntax-only) -set(USER_COMPILE_WARNINGS_CHECK_SYNTAX_ONLY ) - -# Issue all the mandatory diagnostics listed in the C standard (-pedantic) -set(USER_COMPILE_WARNINGS_PEDANTIC ) - -# Issue all the mandatory diagnostics, and make all mandatory diagnostics into errors. (-pedantic-errors) -set(USER_COMPILE_WARNINGS_PEDANTIC_AS_ERRORS ) - -# Suppress all warnings (-w) -set(USER_COMPILE_WARNINGS_INHIBIT_ALL ) - -# ----------------------------------------- - -# Optimization level "-O0" [None] , "-O1" [Optimize] , "-O2" [Optimize More], "-O3" [Optimize Most] or "-Os" [Optimize Size] -set(USER_COMPILE_OPTIMIZATION_LEVEL -O0) - -# Other flags related to optimization -set(USER_COMPILE_OPTIMIZATION_OTHER_FLAGS ) - -# ----------------------------------------- - -# Debug level "" [None], "-g1" [Minimum], "g2" [Default], "g3" [Maximim] -set(USER_COMPILE_DEBUG_LEVEL -g3) - -# Other flags releated to debugging -set(USER_COMPILE_DEBUG_OTHER_FLAGS ) - -# ----------------------------------------- - -# Enable Profiling (-pg) (This feature is not supported currently) -# set(USER_COMPILE_PROFILING_ENABLE ) - -# ----------------------------------------- - -# Verbose (-v) -set(USER_COMPILE_VERBOSE ) - -# Support ANSI_PROGRAM (-ansi) -set(USER_COMPILE_ANSI ) - -# Add any compiler options that are not covered by the above variables, they will be added as extra compiler options -# To enable profiling -pg [ for gprof ] or -p [ for prof information ] -set(USER_COMPILE_OTHER_FLAGS ) - -# ----------------------------------------- - -# Linker options -# Do not use the standard system startup files when linking. -# The standard system libraries are used normally, unless -nostdlib or -nodefaultlibs is used. (-nostartfiles) -set(USER_LINK_NO_START_FILES ) - -# Do not use the standard system libraries when linking. (-nodefaultlibs) -set(USER_LINK_NO_DEFAULT_LIBS ) - -# Do not use the standard system startup files or libraries when linking. (-nostdlib) -set(USER_LINK_NO_STDLIB ) - -# Omit all symbol information (-s) -set(USER_LINK_OMIT_ALL_SYMBOL_INFO ) - - -# ----------------------------------------- - -# Add any libraries to be linked below, they will be added as extra libraries. -# User need to update USER_LINK_DIRECTORIES below with these library paths. -set(USER_LINK_LIBRARIES -) - -# Add any directories to look for the libraries to be linked. -# Example 1: Adding /proj/compression/lib will pass -L/proj/compression/lib to the linker. -# Example adding Adding ../../common/lib will consider the path as relative to this directory. and will pass the path to -L option. -set(USER_LINK_DIRECTORIES -) - -# ----------------------------------------- - -set(USER_LINKER_SCRIPT "${CMAKE_SOURCE_DIR}/lscript.ld") - -# Add linker options to be passed, they will be added as extra linker options -# Example : adding -s will pass -s to the linker. -set(USER_LINK_OTHER_FLAGS -) - -# ----------------------------------------- - -### END OF USER SETTINGS SECTION ### -### DO NOT EDIT BEYOND THIS LINE ### - -set(USER_COMPILE_OPTIONS - " ${USER_COMPILE_WARNINGS_ALL}" - " ${USER_COMPILE_WARNINGS_EXTRA}" - " ${USER_COMPILE_WARNINGS_AS_ERRORS}" - " ${USER_COMPILE_WARNINGS_CHECK_SYNTAX_ONLY}" - " ${USER_COMPILE_WARNINGS_PEDANTIC}" - " ${USER_COMPILE_WARNINGS_PEDANTIC_AS_ERRORS}" - " ${USER_COMPILE_WARNINGS_INHIBIT_ALL}" - " ${USER_COMPILE_OPTIMIZATION_LEVEL}" - " ${USER_COMPILE_OPTIMIZATION_OTHER_FLAGS}" - " ${USER_COMPILE_DEBUG_LEVEL}" - " ${USER_COMPILE_DEBUG_OTHER_FLAGS}" - " ${USER_COMPILE_VERBOSE}" - " ${USER_COMPILE_ANSI}" - " ${USER_COMPILE_OTHER_FLAGS}" -) -foreach(entry ${USER_UNDEFINED_SYMBOLS}) - list(APPEND USER_COMPILE_OPTIONS " -U${entry}") -endforeach() - -set(USER_LINK_OPTIONS - " ${USER_LINKER_NO_START_FILES}" - " ${USER_LINKER_NO_DEFAULT_LIBS}" - " ${USER_LINKER_NO_STDLIB}" - " ${USER_LINKER_OMIT_ALL_SYMBOL_INFO}" - " ${USER_LINK_OTHER_FLAGS}" -) diff --git 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.cproject @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.gitignore b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.gitignore new file mode 100644 index 0000000..c283696 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.gitignore @@ -0,0 +1,3 @@ +/export/ +*.o +*.d diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.project b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.project new file mode 100644 index 0000000..84361a2 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/.project @@ -0,0 +1,18 @@ + + + NewInstCal_bsp + Created by Vitis v2023.2 + + + + + com.xilinx.sdx.scw.PlatformProjectBuilder + + + + + + com.xilinx.sdx.scw.platformProject + org.eclipse.cdt.core.cnature + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init_gpl.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init_gpl.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init_gpl.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/sdt/ps7_init_gpl.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/ps7_init_gpl.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/_ide/bitstream/system_wrapper.bit b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.bit similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewCalBoard_APP/_ide/bitstream/system_wrapper.bit rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.bit diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/system_wrapper.xsa b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/hw/system_wrapper.xsa rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/platform.spr b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/platform.spr new file mode 100644 index 0000000..198f7f2 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/platform.spr @@ -0,0 +1 @@ +{"platformName":"NewInstCal_bsp","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"NewInstCal_bsp","platHandOff":"/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa","platIntHandOff":"/hw/system_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"NewInstCal_bsp","systems":[{"systemName":"NewInstCal_bsp","systemDesc":"NewInstCal_bsp","sysIsBootAutoGen":"true","systemDispName":"NewInstCal_bsp","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"88a630cf45945e27dbb40d72cff1145a","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt","qemuData":"/resources/NewInstCal_bsp/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"36df5c3fd5a33f289a56469b013613e2","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["lwip213:1.1"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/Makefile new file mode 100644 index 0000000..c99f4a8 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/Makefile @@ -0,0 +1,49 @@ +# Makefile generated by Xilinx. + +DRIVER_LIB_VERSION = 1.0 +PROCESSOR = ps7_cortexa9_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) +BSP_SEQUENTIAL_MAKEFILES := ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile +BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES)) +SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES)) +PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: + $(MAKE) --no-print-directory seq_libs + $(MAKE) -j 30 --no-print-directory par_libs + $(MAKE) --no-print-directory archive + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +seq_libs: $(addsuffix /make.libs,$(SEQ_SUBDIRS)) + @echo 'Finished building libraries sequentially.' + +par_libs: $(addsuffix /make.libs,$(PAR_SUBDIRS)) + @echo 'Finished building libraries parallelly.' + +archive: + arm-none-eabi-ar -r $(LIBRARIES) $(sort $(wildcard $(PROCESSOR)/lib/*.o)) + +clean: $(addsuffix /make.clean,$(SUBDIRS)) + rm -f ${PROCESSOR}/lib/libxil.a + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" + +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/dep.mk b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/dep.mk new file mode 100644 index 0000000..dc5ac1c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/dep.mk @@ -0,0 +1,3 @@ +# generated by Xilinx. + +DEPENDENCY_FLAGS= -MMD -MP diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile/_profile_timer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/_profile_timer_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile/_profile_timer_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/_profile_timer_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/cpu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/cpu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/cpu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/cpu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/perf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/perf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/perf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/perf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/sys_arch.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/sys_arch.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/arch/sys_arch.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/arch/sys_arch.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/bspconfig.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/bspconfig.h new file mode 100644 index 0000000..5498919 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/bspconfig.h @@ -0,0 +1,24 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + +#define MICROBLAZE_PVR_NONE + +/* Definition for hard-float ABI */ +#define FPU_HARD_FLOAT_ABI_ENABLED 1 + +#endif /*end of __BSPCONFIG_H_*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/altcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/altcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/altcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/altcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/altcp_tcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/altcp_tcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/altcp_tcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/altcp_tcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/altcp_tls.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/altcp_tls.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/altcp_tls.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/altcp_tls.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/FILES b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/FILES similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/FILES rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/FILES diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/altcp_proxyconnect.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/altcp_proxyconnect.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/altcp_proxyconnect.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/altcp_proxyconnect.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/altcp_tls_mbedtls_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/altcp_tls_mbedtls_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/altcp_tls_mbedtls_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/altcp_tls_mbedtls_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/fs.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/fs.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/fs.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/fs.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/http_client.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/http_client.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/http_client.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/http_client.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/httpd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/httpd.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/httpd.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/httpd.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/httpd_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/httpd_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/httpd_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/httpd_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/lwiperf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/lwiperf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/lwiperf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/lwiperf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mdns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mdns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mdns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mdns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mdns_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mdns_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mdns_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mdns_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mdns_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mdns_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mdns_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mdns_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mqtt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mqtt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mqtt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mqtt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mqtt_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mqtt_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mqtt_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/mqtt_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/mqtt_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/netbiosns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/netbiosns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/netbiosns_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/netbiosns_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/netbiosns_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/smtp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/smtp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/smtp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/smtp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/smtp_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/smtp_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/smtp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/smtp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_core.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_core.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_core.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_core.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_mib2.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_mib2.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_mib2.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_mib2.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_scalar.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_scalar.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_scalar.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_scalar.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_snmpv2_framework.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_framework.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_snmpv2_framework.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_framework.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_snmpv2_usm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_usm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_snmpv2_usm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_snmpv2_usm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_table.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_table.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_table.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_table.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_threadsync.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_threadsync.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmp_threadsync.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmp_threadsync.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmpv3.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmpv3.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/snmpv3.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/snmpv3.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/sntp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/sntp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/sntp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/sntp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/sntp_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/sntp_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/sntp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/sntp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/tftp_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/tftp_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/tftp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/tftp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/tftp_server.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/tftp_server.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/apps/tftp_server.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/apps/tftp_server.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/arch.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/arch.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/arch.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/arch.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/autoip.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/autoip.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/autoip.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/autoip.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/debug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/debug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/debug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/debug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/def.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/def.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/def.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/def.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/dhcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/dhcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/dhcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/dhcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/dhcp6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/dhcp6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/dhcp6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/dhcp6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/dns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/dns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/dns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/dns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/err.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/err.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/err.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/err.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/errno.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/errno.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/errno.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/errno.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/etharp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/etharp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/etharp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/etharp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ethip6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ethip6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ethip6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ethip6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/icmp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/icmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/icmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/icmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/icmp6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/icmp6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/icmp6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/icmp6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/if_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/if_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/if_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/if_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/igmp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/igmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/igmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/igmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/inet.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/inet.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/inet.h rename to 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/init.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/init.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/init.h.cmake.in b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/init.h.cmake.in similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/init.h.cmake.in rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/init.h.cmake.in diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip4.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip4.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip4.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip4.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip4_addr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip4_addr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip4_addr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip4_addr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip4_frag.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip4_frag.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip4_frag.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip4_frag.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6_addr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6_addr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6_addr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6_addr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6_frag.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6_frag.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6_frag.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6_frag.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6_zone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6_zone.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip6_zone.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip6_zone.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip_addr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip_addr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/ip_addr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/ip_addr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/memp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/memp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/memp.h rename to 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/nd6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/nd6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netbuf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netbuf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netbuf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netbuf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netdb.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netdb.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netdb.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netdb.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netifapi.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netifapi.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/netifapi.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/netifapi.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/opt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/opt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/opt.h rename to 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/mem_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/mem_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/mem_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/mem_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/memp_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/memp_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/memp_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/memp_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/memp_std.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/memp_std.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/memp_std.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/memp_std.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/nd6_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/nd6_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/nd6_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/nd6_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/raw_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/raw_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/raw_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/raw_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/sockets_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/sockets_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/sockets_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/sockets_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/tcp_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/tcp_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/tcp_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/tcp_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/priv/tcpip_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/priv/tcpip_priv.h similarity index 100% rename from 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/dhcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/dhcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/dhcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/dhcp6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/dhcp6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/dhcp6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/dhcp6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/dns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/dns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/dns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/dns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/etharp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/etharp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/etharp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/etharp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ethernet.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ethernet.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ethernet.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ethernet.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/iana.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/iana.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/iana.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/iana.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/icmp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/icmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/icmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/icmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/icmp6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/icmp6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/icmp6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/icmp6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ieee.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ieee.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ieee.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ieee.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/igmp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/igmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/igmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/igmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ip.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ip.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ip.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ip.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ip4.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ip4.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ip4.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ip4.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ip6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ip6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/ip6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/ip6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/mld6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/mld6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/mld6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/mld6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/nd6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/nd6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/nd6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/nd6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/tcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/tcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/tcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/tcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/udp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/udp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/prot/udp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/prot/udp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/raw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/raw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/raw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/raw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/sio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/sio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/sio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/sio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/snmp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/snmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/snmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/snmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/sockets.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/sockets.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/sockets.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/sockets.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/stats.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/stats.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/stats.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/stats.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/sys.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/sys.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/sys.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/sys.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/tcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/tcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/tcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/tcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/tcpbase.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/tcpbase.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/tcpbase.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/tcpbase.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/tcpip.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/tcpip.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/tcpip.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/tcpip.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/timeouts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/timeouts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/timeouts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/timeouts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/udp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/udp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/lwip/udp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwip/udp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwipopts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwipopts.h new file mode 100644 index 0000000..f57e3bf --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/lwipopts.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * Copyright (C) 2007 - 2022 Xilinx, Inc. + * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H_ +#define __LWIPOPTS_H_ + +#ifndef PROCESSOR_LITTLE_ENDIAN +#define PROCESSOR_LITTLE_ENDIAN +#endif + +#define SYS_LIGHTWEIGHT_PROT 1 + +#define NO_SYS 1 +#define LWIP_SOCKET 0 +#define LWIP_COMPAT_SOCKETS 0 +#define LWIP_NETCONN 0 + +#define NO_SYS_NO_TIMERS 1 + +#define LWIP_TCP_KEEPALIVE 0 + +#define MEM_ALIGNMENT 64 +#define MEM_SIZE 131072 +#define MEMP_NUM_PBUF 16 +#define MEMP_NUM_UDP_PCB 4 +#define MEMP_NUM_TCP_PCB 32 +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#define MEMP_NUM_TCP_SEG 256 +#define MEMP_NUM_SYS_TIMEOUT 8 +#define MEMP_NUM_NETBUF 8 +#define MEMP_NUM_NETCONN 16 +#define MEMP_NUM_TCPIP_MSG_API 16 +#define MEMP_NUM_TCPIP_MSG_INPKT 64 + +#define MEMP_NUM_SYS_TIMEOUT 8 +#define PBUF_POOL_SIZE 256 +#define PBUF_POOL_BUFSIZE 1700 +#define PBUF_LINK_HLEN 16 + +#define ARP_TABLE_SIZE 10 +#define ARP_QUEUEING 1 + +#define ICMP_TTL 255 + +#define IP_OPTIONS 0 +#define IP_FORWARD 0 +#define IP_REASSEMBLY 1 +#define IP_FRAG 1 +#define IP_REASS_MAX_PBUFS 128 +#define IP_FRAG_MAX_MTU 1500 +#define IP_DEFAULT_TTL 255 +#define LWIP_CHKSUM_ALGORITHM 3 + +#define LWIP_UDP 1 +#define UDP_TTL 255 +#define LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE 0 + +#define LWIP_TCP 1 +#define TCP_MSS 1460 +#define TCP_SND_BUF 8192 +#define TCP_WND 2048 +#define TCP_TTL 255 +#define TCP_MAXRTX 12 +#define TCP_SYNMAXRTX 4 +#define TCP_QUEUE_OOSEQ 1 +#define TCP_SND_QUEUELEN 16 * TCP_SND_BUF/TCP_MSS +#define CHECKSUM_GEN_TCP 0 +#define CHECKSUM_GEN_UDP 0 +#define CHECKSUM_GEN_IP 0 +#define CHECKSUM_CHECK_TCP 0 +#define CHECKSUM_CHECK_UDP 0 +#define CHECKSUM_CHECK_IP 0 +#define LWIP_FULL_CSUM_OFFLOAD_RX 1 +#define LWIP_FULL_CSUM_OFFLOAD_TX 1 + +#define MEMP_SEPARATE_POOLS 1 +#define MEMP_NUM_FRAG_PBUF 256 +#define IP_OPTIONS_ALLOWED 0 +#define TCP_OVERSIZE TCP_MSS + +#define LWIP_DHCP 0 +#define DHCP_DOES_ARP_CHECK 0 + +#define CONFIG_LINKSPEED_AUTODETECT 1 + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile/mblaze_nt_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/mblaze_nt_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile/mblaze_nt_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/mblaze_nt_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/bridgeif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/bridgeif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/bridgeif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/bridgeif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/bridgeif_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/bridgeif_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/bridgeif_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/bridgeif_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/etharp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/etharp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/etharp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/etharp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ethernet.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ethernet.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ethernet.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ethernet.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ieee802154.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ieee802154.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ieee802154.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ieee802154.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6_ble.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6_ble.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6_ble.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6_ble.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6_common.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6_common.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6_common.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6_common.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/lowpan6_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/lowpan6_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ccp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ccp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ccp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ccp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/chap-md5.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/chap-md5.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/chap-md5.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/chap-md5.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/chap-new.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/chap-new.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/chap-new.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/chap-new.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/chap_ms.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/chap_ms.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/chap_ms.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/chap_ms.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/eap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/eap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/eap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/eap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ecp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ecp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ecp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ecp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/eui64.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/eui64.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/eui64.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/eui64.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/fsm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/fsm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/fsm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/fsm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ipcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ipcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ipcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ipcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ipv6cp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ipv6cp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ipv6cp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ipv6cp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/lcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/lcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/lcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/lcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/magic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/magic.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/magic.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/magic.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/mppe.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/mppe.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/mppe.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/mppe.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/arc4.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/arc4.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/arc4.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/arc4.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/des.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/des.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/des.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/des.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/md4.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md4.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/md4.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md4.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/md5.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md5.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/md5.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/md5.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/sha1.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/sha1.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/polarssl/sha1.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/polarssl/sha1.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ppp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ppp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ppp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ppp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ppp_impl.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ppp_impl.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ppp_impl.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ppp_impl.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ppp_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ppp_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/ppp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/ppp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppapi.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppapi.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppapi.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppapi.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppcrypt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppcrypt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppcrypt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppcrypt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppdebug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppoe.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppoe.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppoe.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppoe.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppol2tp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppol2tp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppol2tp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppol2tp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppos.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppos.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/pppos.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/ppp/pppos.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/ppp/upap.h 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xemacliteif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xemacliteif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xemacpsif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xemacpsif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xemacpsif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xemacpsif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xlltemacif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xlltemacif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xlltemacif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xlltemacif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xpqueue.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xpqueue.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xpqueue.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xpqueue.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xtopology.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xtopology.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/netif/xtopology.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/xtopology.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/zepif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/netif/zepif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/include/netif/zepif.h rename to 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/profile/profile.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/profile.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/sleep.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/sleep.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/sleep.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/sleep.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/smc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/smc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/smc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/vectors.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/vectors.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/vectors.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xadcps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xadcps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xbasic_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xbasic_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xbasic_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xbasic_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xcoresightpsdcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xcortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xcortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xcortexa9_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xcortexa9_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h new file mode 100644 index 0000000..f6b3728 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9 Overview +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into +# extra compiler flags. Now, user can remove default flags +# from extra compiler flags. It fixes CR#998768. +******************************************************************************/ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xddrps.h new file mode 100644 index 0000000..271da20 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xddrps.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ + +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps Overview + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
+ * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdebug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdevcfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdevcfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdevcfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdevcfg_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdevcfg_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdevcfg_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdmaps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdmaps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdmaps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdmaps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xdmaps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdmaps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps_bd.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps_bd.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps_bd.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps_bdring.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps_bdring.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps_bdring.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xemacps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xenv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xenv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xenv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xenv_standalone.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xenv_standalone.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xenv_standalone.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xgpiops.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xgpiops.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xgpiops.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xgpiops_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xgpiops_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xgpiops_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_assert.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_assert.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_assert.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache_l.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cache_l.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache_l.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cache_vxworks.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_clocking.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_clocking.h new file mode 100644 index 0000000..d40a6f7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_clocking.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.h +* +* The xil_clocking.h file contains clocking related functions and macros. +* certain conditions. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  12/11/19 First release
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 7.7 sk  01/10/22 Add function prototype for Xil_ClockGetRate to fix
+* 		   misra_c_2012_rule_8_4 violation.
+* 9.0 ml  03/03/23 Added description to fix doxygen warnings.
+*
+* +******************************************************************************/ + +#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */ +#define XIL_CLOCKING_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xdebug.h" +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xparameters.h" +#include "xstatus.h" +#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR) +#include "xclockps.h" +#else +typedef u32 XClock_OutputClks; +typedef u64 XClockRate; +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + + +XStatus Xil_ClockDisable(XClock_OutputClks ClockId); +XStatus Xil_ClockEnable(XClock_OutputClks ClockId); +XStatus Xil_ClockInit(void); +XStatus Xil_ClockGet(void); +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate); +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cryptoalginfo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_cryptoalginfo.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_errata.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_errata.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_errata.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_hal.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_hal.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_hal.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_io.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_io.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_io.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_macroback.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_macroback.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_macroback.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_mmu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_mmu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_mmu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_printf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_printf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_printf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_sleeptimer.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/xil_sleeptimer.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_sleeptimer.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_spinlock.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_spinlock.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_spinlock.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_spinlock.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testcache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_testcache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testcache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_testio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testmem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_testmem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testmem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_util.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_util.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xil_util.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_util.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xinterrupt_wrap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xl2cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xl2cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xl2cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xl2cc_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xl2cc_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xl2cc_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/xlwipconfig.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xlwipconfig.h similarity index 84% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/xlwipconfig.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xlwipconfig.h index ad99c2d..acec86b 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/xlwipconfig.h +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xlwipconfig.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. * Copyright (C) 2007 - 2022 Xilinx, Inc. * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. * All rights reserved. @@ -28,13 +28,18 @@ * * This file is part of the lwIP TCP/IP stack. * + * Author: Adam Dunkels + * */ - #ifndef __XLWIPCONFIG_H_ #define __XLWIPCONFIG_H_ -/* this is a generated file: do not modify */ -#define XLWIP_CONFIG_INCLUDE_EMACLITE 1 +/* This is a generated file - do not edit */ + +#define XLWIP_CONFIG_INCLUDE_GEM 1 +#define XLWIP_CONFIG_EMAC_NUMBER 0 +#define XLWIP_CONFIG_N_TX_DESC 64 +#define XLWIP_CONFIG_N_RX_DESC 64 #endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters.h new file mode 100644 index 0000000..b9d630a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters.h @@ -0,0 +1,465 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0U + +/* Definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +#define STDIN_BASEADDRESS 0xE0001000 +#define STDOUT_BASEADDRESS 0xE0001000 + +/******************************************************************/ + +/* Platform specific definitions */ +#define PLATFORM_ZYNQ + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ + +/* Definitions for peripheral PS7_DDR_0 */ +#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF + + +/******************************************************************/ + +/* Definitions for driver DEVCFG */ +#define XPAR_XDCFG_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID +#define XPAR_XDCFG_0_BASEADDR 0xF8007000U +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Definitions for driver DMAPS */ +#define XPAR_XDMAPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PS7_DMA_NS */ +#define XPAR_PS7_DMA_NS_DEVICE_ID 0 +#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 +#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF + + +/* Definitions for peripheral PS7_DMA_S */ +#define XPAR_PS7_DMA_S_DEVICE_ID 1 +#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 +#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DMA_NS */ +#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID +#define XPAR_XDMAPS_0_BASEADDR 0xF8004000 +#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF + +/* Canonical definitions for peripheral PS7_DMA_S */ +#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID +#define XPAR_XDMAPS_1_BASEADDR 0xF8003000 +#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 +#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 +#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF +#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 +#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 +#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 +#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0 + + +/******************************************************************/ + + +/* Peripheral Definitions for peripheral MYDNA_READ_V1_0_0 */ +#define XPAR_MYDNA_READ_V1_0_0_BASEADDR 0x43C00000 +#define XPAR_MYDNA_READ_V1_0_0_HIGHADDR 0x43C0FFFF + + +/* Peripheral Definitions for peripheral PS7_AFI_0 */ +#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 +#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF + + +/* Peripheral Definitions for peripheral PS7_AFI_1 */ +#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 +#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF + + +/* Peripheral Definitions for peripheral PS7_AFI_2 */ +#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 +#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF + + +/* Peripheral Definitions for peripheral PS7_AFI_3 */ +#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 +#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF + + +/* Peripheral Definitions for peripheral PS7_DDRC_0 */ +#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 +#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF + + +/* Peripheral Definitions for peripheral PS7_GLOBALTIMER_0 */ +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF + + +/* Peripheral Definitions for peripheral PS7_GPV_0 */ +#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 +#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF + + +/* Peripheral Definitions for peripheral PS7_INTC_DIST_0 */ +#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 +#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF + + +/* Peripheral Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF + + +/* Peripheral Definitions for peripheral PS7_L2CACHEC_0 */ +#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Peripheral Definitions for peripheral PS7_OCMC_0 */ +#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 +#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF + + +/* Peripheral Definitions for peripheral PS7_PL310_0 */ +#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Peripheral Definitions for peripheral PS7_PMU_0 */ +#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 +#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF +#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 +#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF + + +/* Peripheral Definitions for peripheral PS7_QSPI_LINEAR_0 */ +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF + + +/* Peripheral Definitions for peripheral PS7_RAM_0 */ +#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF + + +/* Peripheral Definitions for peripheral PS7_RAM_1 */ +#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Peripheral Definitions for peripheral PS7_SCUC_0 */ +#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 +#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC + + +/* Peripheral Definitions for peripheral PS7_SLCR_0 */ +#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 +#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF + + +/******************************************************************/ + + +/* Canonical Definitions for peripheral MYDNA_READ_V1_0_0 */ +#define XPAR_MYDNA_READ_V1_0_BASEADDR 0x43C00000 +#define XPAR_MYDNA_READ_V1_0_HIGHADDR 0x43C0FFFF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_GPIO_0 */ +#define XPAR_PS7_GPIO_0_DEVICE_ID 0 +#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 +#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Definitions for driver QSPIPS */ +#define XPAR_XQSPIPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_QSPI_0 */ +#define XPAR_PS7_QSPI_0_DEVICE_ID 0 +#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 +#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF +#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 142857132 +#define XPAR_PS7_QSPI_0_QSPI_MODE 0 +#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_QSPI_0 */ +#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 +#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF +#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 142857132 +#define XPAR_XQSPIPS_0_QSPI_MODE 0 +#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Definitions for driver SCUTIMER */ +#define XPAR_XSCUTIMER_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 +#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID +#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Definitions for driver SCUWDT */ +#define XPAR_XSCUWDT_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 +#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID +#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SD_0 */ +#define XPAR_PS7_SD_0_DEVICE_ID 0 +#define XPAR_PS7_SD_0_BASEADDR 0xE0100000 +#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF +#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 +#define XPAR_PS7_SD_0_HAS_CD 1 +#define XPAR_PS7_SD_0_HAS_WP 1 +#define XPAR_PS7_SD_0_BUS_WIDTH 0 +#define XPAR_PS7_SD_0_MIO_BANK 0 +#define XPAR_PS7_SD_0_HAS_EMIO 0 +#define XPAR_PS7_SD_0_SLOT_TYPE 0 +#define XPAR_PS7_SD_0_CLK_50_SDR_ITAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_50_SDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_50_DDR_ITAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY 0 + + +/******************************************************************/ + +#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xE0100000 +#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 +#define XPAR_XSDPS_0_HAS_CD 1 +#define XPAR_XSDPS_0_HAS_WP 1 +#define XPAR_XSDPS_0_BUS_WIDTH 0 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 +#define XPAR_XSDPS_0_SLOT_TYPE 0 +#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0 +#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0 +#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0 +#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0 + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_UART_1 */ +#define XPAR_PS7_UART_1_DEVICE_ID 0 +#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 +#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF +#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000 +#define XPAR_PS7_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_UART_1 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xE0001000 +#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definition for input Clock */ +/* Definitions for driver XADCPS */ +#define XPAR_XADCPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_XADC_0 */ +#define XPAR_PS7_XADC_0_DEVICE_ID 0 +#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 +#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_XADC_0 */ +#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID +#define XPAR_XADCPS_0_BASEADDR 0xF8007100 +#define XPAR_XADCPS_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xplatform_info.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xplatform_info.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xplatform_info.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpm_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xpm_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpm_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xpm_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpm_init.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xpm_init.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpm_init.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xqspips.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xqspips.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xqspips.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xqspips_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xqspips_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xqspips_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xreg_cortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xreg_cortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xreg_cortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscugic.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscugic.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscugic.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscugic_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscugic_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscugic_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscutimer.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscutimer.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscutimer.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscutimer_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscutimer_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscutimer_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscuwdt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscuwdt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscuwdt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscuwdt_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xscuwdt_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscuwdt_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xsdps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xsdps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xsdps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xsdps_core.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xsdps_core.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xsdps_core.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xsdps_core.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xsdps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xsdps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xsdps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xstatus.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xstatus.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xstatus.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xtime_l.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xtime_l.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xtime_l.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xuartps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xuartps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xuartps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xuartps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xuartps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xuartps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/xcoresightpsdcc.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/xcoresightpsdcc.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xcoresightpsdcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h new file mode 100644 index 0000000..f6b3728 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9 Overview +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into +# extra compiler flags. Now, user can remove default flags +# from extra compiler flags. It fixes CR#998768. +******************************************************************************/ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h new file mode 100644 index 0000000..271da20 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ + +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps Overview + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
+ * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/Makefile old mode 100755 new mode 100644 similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdevcfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c new file mode 100644 index 0000000..6eb100d --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdevcfg.h" + +/* +* The configuration table for devices +*/ + +XDcfg_Config XDcfg_ConfigTable[] = +{ + { + XPAR_PS7_DEV_CFG_0_DEVICE_ID, + XPAR_PS7_DEV_CFG_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdevcfg_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdmaps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c new file mode 100644 index 0000000..b36c8c3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c @@ -0,0 +1,35 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdmaps.h" + +/* +* The configuration table for devices +*/ + +XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_DMA_NS_DEVICE_ID, + XPAR_PS7_DMA_NS_BASEADDR + }, + { + XPAR_PS7_DMA_S_DEVICE_ID, + XPAR_PS7_DMA_S_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xdmaps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bd.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps_bd.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bd.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_bdring.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_bdring.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps_bdring.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_control.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_control.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_control.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_control.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c new file mode 100644 index 0000000..07a1fe9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c @@ -0,0 +1,38 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xemacps.h" + +/* +* The configuration table for devices +*/ + +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_ETHERNET_0_DEVICE_ID, + XPAR_PS7_ETHERNET_0_BASEADDR, + XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT, + XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0, + XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1, + XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0, + XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1, + XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0, + XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xgpiops.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c new file mode 100644 index 0000000..abe5fe0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xgpiops.h" + +/* +* The configuration table for devices +*/ + +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_GPIO_0_DEVICE_ID, + XPAR_PS7_GPIO_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xgpiops_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/ChangeLog b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/ChangeLog similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/ChangeLog rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/ChangeLog diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Filelists.cmake b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Filelists.cmake similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Filelists.cmake rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Filelists.cmake diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Makefile.adapter b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.adapter similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Makefile.adapter rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.adapter diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.config b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.config new file mode 100644 index 0000000..528aca5 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.config @@ -0,0 +1,3 @@ +GCC_COMPILER=arm-none-eabi-gcc +CONFIG_PROCESSOR_LITTLE_ENDIAN=y +CONFIG_PS_ETHERNET=y diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Makefile.lwip b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.lwip similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/Makefile.lwip rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/Makefile.lwip diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/cpu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/cpu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/cpu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/cpu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/perf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/perf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/perf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/perf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/sys_arch.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/sys_arch.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/arch/sys_arch.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/arch/sys_arch.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/lwipopts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/lwipopts.h new file mode 100644 index 0000000..f57e3bf --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/lwipopts.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * Copyright (C) 2007 - 2022 Xilinx, Inc. + * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H_ +#define __LWIPOPTS_H_ + +#ifndef PROCESSOR_LITTLE_ENDIAN +#define PROCESSOR_LITTLE_ENDIAN +#endif + +#define SYS_LIGHTWEIGHT_PROT 1 + +#define NO_SYS 1 +#define LWIP_SOCKET 0 +#define LWIP_COMPAT_SOCKETS 0 +#define LWIP_NETCONN 0 + +#define NO_SYS_NO_TIMERS 1 + +#define LWIP_TCP_KEEPALIVE 0 + +#define MEM_ALIGNMENT 64 +#define MEM_SIZE 131072 +#define MEMP_NUM_PBUF 16 +#define MEMP_NUM_UDP_PCB 4 +#define MEMP_NUM_TCP_PCB 32 +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#define MEMP_NUM_TCP_SEG 256 +#define MEMP_NUM_SYS_TIMEOUT 8 +#define MEMP_NUM_NETBUF 8 +#define MEMP_NUM_NETCONN 16 +#define MEMP_NUM_TCPIP_MSG_API 16 +#define MEMP_NUM_TCPIP_MSG_INPKT 64 + +#define MEMP_NUM_SYS_TIMEOUT 8 +#define PBUF_POOL_SIZE 256 +#define PBUF_POOL_BUFSIZE 1700 +#define PBUF_LINK_HLEN 16 + +#define ARP_TABLE_SIZE 10 +#define ARP_QUEUEING 1 + +#define ICMP_TTL 255 + +#define IP_OPTIONS 0 +#define IP_FORWARD 0 +#define IP_REASSEMBLY 1 +#define IP_FRAG 1 +#define IP_REASS_MAX_PBUFS 128 +#define IP_FRAG_MAX_MTU 1500 +#define IP_DEFAULT_TTL 255 +#define LWIP_CHKSUM_ALGORITHM 3 + +#define LWIP_UDP 1 +#define UDP_TTL 255 +#define LWIP_UDP_OPT_BLOCK_TX_TILL_COMPLETE 0 + +#define LWIP_TCP 1 +#define TCP_MSS 1460 +#define TCP_SND_BUF 8192 +#define TCP_WND 2048 +#define TCP_TTL 255 +#define TCP_MAXRTX 12 +#define TCP_SYNMAXRTX 4 +#define TCP_QUEUE_OOSEQ 1 +#define TCP_SND_QUEUELEN 16 * TCP_SND_BUF/TCP_MSS +#define CHECKSUM_GEN_TCP 0 +#define CHECKSUM_GEN_UDP 0 +#define CHECKSUM_GEN_IP 0 +#define CHECKSUM_CHECK_TCP 0 +#define CHECKSUM_CHECK_UDP 0 +#define CHECKSUM_CHECK_IP 0 +#define LWIP_FULL_CSUM_OFFLOAD_RX 1 +#define LWIP_FULL_CSUM_OFFLOAD_TX 1 + +#define MEMP_SEPARATE_POOLS 1 +#define MEMP_NUM_FRAG_PBUF 256 +#define IP_OPTIONS_ALLOWED 0 +#define TCP_OVERSIZE TCP_MSS + +#define LWIP_DHCP 0 +#define DHCP_DOES_ARP_CHECK 0 + +#define CONFIG_LINKSPEED_AUTODETECT 1 + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/lwipopts.h.in b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/lwipopts.h.in similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/lwipopts.h.in rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/lwipopts.h.in diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xadapter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xadapter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xadapter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xadapter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xaxiemacif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xaxiemacif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xaxiemacif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xaxiemacif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xemacliteif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xemacliteif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xemacliteif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xemacliteif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xemacpsif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xemacpsif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xemacpsif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xemacpsif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xlltemacif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xlltemacif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xlltemacif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xlltemacif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xpqueue.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xpqueue.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xpqueue.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xpqueue.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xtopology.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xtopology.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/netif/xtopology.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/netif/xtopology.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacpsif_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/xlwipconfig.h similarity index 80% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacpsif_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/xlwipconfig.h index 7a3834c..acec86b 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xemacpsif_hw.h +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/xlwipconfig.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2010 - 2022 Xilinx, Inc. + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * Copyright (C) 2007 - 2022 Xilinx, Inc. * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. * All rights reserved. * @@ -27,24 +28,18 @@ * * This file is part of the lwIP TCP/IP stack. * + * Author: Adam Dunkels + * */ +#ifndef __XLWIPCONFIG_H_ +#define __XLWIPCONFIG_H_ -#ifndef __XEMACPSIF_HW_H_ -#define __XEMACPSIF_HW_H_ -#include "netif/xemacpsif.h" -#include "lwip/netif.h" +/* This is a generated file - do not edit */ -#ifdef __cplusplus -extern "C" { -#endif - -XEmacPs_Config * lookup_config(unsigned mac_base); - -void init_emacps(xemacpsif_s *xemacpsif, struct netif *netif); - -#ifdef __cplusplus -} -#endif +#define XLWIP_CONFIG_INCLUDE_GEM 1 +#define XLWIP_CONFIG_EMAC_NUMBER 0 +#define XLWIP_CONFIG_N_TX_DESC 64 +#define XLWIP_CONFIG_N_RX_DESC 64 #endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/xlwipconfig.h.in b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/xlwipconfig.h.in similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/include/xlwipconfig.h.in rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/include/xlwipconfig.h.in diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xadapter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xadapter.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xadapter.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xadapter.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_dma.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_fifo.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_mcdma.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xaxiemacif_physpeed.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemac_ieee_reg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemac_ieee_reg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemac_ieee_reg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemac_ieee_reg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacliteif.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacliteif.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacliteif.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacliteif.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif_dma.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_dma.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif_dma.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_dma.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacpsif_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/xemacpsif_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xemacpsif_physpeed.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xpqueue.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xpqueue.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/netif/xpqueue.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xpqueue.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xtopology_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xtopology_g.c new file mode 100644 index 0000000..f1edcdf --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/netif/xtopology_g.c @@ -0,0 +1,15 @@ +#include "netif/xtopology.h" +#include "xparameters.h" + +struct xtopology_t xtopology[] = { + { + 0xE000B000, + xemac_type_emacps, + 0x0, + 0x0, + 0xF8F00100, + 0x36, + }, +}; + +int xtopology_n_emacs = 1; diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/sys_arch.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/contrib/ports/xilinx/sys_arch.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/lwip213/src/contrib/ports/xilinx/sys_arch.c rename to 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/altcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/altcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/altcp_tcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/altcp_tcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/altcp_tcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/altcp_tcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/altcp_tls.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/altcp_tls.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/altcp_tls.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/altcp_tls.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/FILES b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/FILES similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/FILES rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/FILES diff --git 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/httpd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/httpd.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/httpd.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/httpd.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/httpd_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/httpd_opts.h similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/mdns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/mdns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/mdns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/mdns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/mdns_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/mdns_opts.h similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/mqtt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/mqtt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/mqtt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/mqtt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/mqtt_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/mqtt_opts.h similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/netbiosns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/netbiosns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/netbiosns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/netbiosns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/netbiosns_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/netbiosns_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/netbiosns_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/netbiosns_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/smtp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/smtp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/smtp.h rename to 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_core.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_core.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_core.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_core.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_mib2.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_mib2.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_mib2.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_mib2.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_scalar.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_scalar.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_scalar.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_scalar.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_snmpv2_framework.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_snmpv2_framework.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_snmpv2_framework.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_snmpv2_framework.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_snmpv2_usm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_snmpv2_usm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_snmpv2_usm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_snmpv2_usm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_table.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_table.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_table.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_table.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_threadsync.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_threadsync.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmp_threadsync.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmp_threadsync.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmpv3.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmpv3.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/snmpv3.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/snmpv3.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/sntp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/sntp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/sntp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/sntp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/sntp_opts.h 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/tftp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/tftp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/tftp_server.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/tftp_server.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/apps/tftp_server.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/apps/tftp_server.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/arch.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/arch.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/arch.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/arch.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/autoip.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/autoip.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/autoip.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/autoip.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/debug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/debug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/debug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/debug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/def.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/def.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/def.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/def.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/dhcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/dhcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/dhcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/dhcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/dhcp6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/dhcp6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/dhcp6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/dhcp6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/dns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/dns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/dns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/dns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/err.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/err.h similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/ip_addr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/ip_addr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/ip_addr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/ip_addr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/mem.h similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/mld6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/mld6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/mld6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/mld6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/nd6.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/nd6.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/nd6.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/nd6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netbuf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netbuf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netbuf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netbuf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netdb.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netdb.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netdb.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netdb.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netifapi.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netifapi.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/netifapi.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/netifapi.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/opt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/opt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/opt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/opt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/pbuf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/pbuf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/pbuf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/pbuf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/altcp_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/altcp_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/altcp_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/altcp_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/api_msg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/api_msg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/api_msg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/api_msg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/mem_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/mem_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/mem_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/mem_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/memp_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/memp_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/memp_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/memp_priv.h diff --git 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rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/nd6_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/nd6_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/raw_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/raw_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/raw_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/raw_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/sockets_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/sockets_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/sockets_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/sockets_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/tcp_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/tcp_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/tcp_priv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/tcp_priv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/tcpip_priv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/priv/tcpip_priv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/priv/tcpip_priv.h rename to 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2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/dhcp6.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/prot/dns.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/dns.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/prot/dns.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/dns.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/prot/etharp.h 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rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/ethernet.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/prot/iana.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/iana.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/prot/iana.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/iana.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/prot/icmp.h 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2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/prot/udp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/raw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/raw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/raw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/raw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/sio.h 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2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/sys.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/tcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/tcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/tcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/tcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/tcpbase.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/tcpbase.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/tcpbase.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/tcpbase.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/tcpip.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/tcpip.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/tcpip.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/tcpip.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/timeouts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/timeouts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/timeouts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/timeouts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/udp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/udp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/lwip/udp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/lwip/udp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/bridgeif.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/bridgeif.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/bridgeif.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/bridgeif.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/bridgeif_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/bridgeif_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/bridgeif_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/bridgeif_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/etharp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/etharp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/etharp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/etharp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ethernet.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ethernet.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ethernet.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ethernet.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ieee802154.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ieee802154.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ieee802154.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ieee802154.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/lowpan6.h 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2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/lowpan6_ble.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/lowpan6_common.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/lowpan6_common.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/lowpan6_common.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/lowpan6_common.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/lowpan6_opts.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/lowpan6_opts.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/lowpan6_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/lowpan6_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ccp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ccp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ccp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ccp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/chap-md5.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/chap-md5.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/chap-md5.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/chap-md5.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/chap-new.h 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ecp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ecp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ecp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ecp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/eui64.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/eui64.h similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ipcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ipcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ipcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ipcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ipv6cp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ipv6cp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ipv6cp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ipv6cp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/lcp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/lcp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/lcp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/lcp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/magic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/magic.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/magic.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/magic.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/mppe.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/mppe.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/mppe.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/mppe.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/arc4.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/arc4.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/arc4.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/arc4.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/des.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/des.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/des.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/des.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/md4.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/md4.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/md4.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/md4.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/md5.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/md5.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/md5.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/md5.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/sha1.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/sha1.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/polarssl/sha1.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/polarssl/sha1.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ppp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ppp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ppp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ppp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ppp_impl.h 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/ppp_opts.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/ppp_opts.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppapi.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppapi.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppapi.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppapi.h diff --git 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rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppoe.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppoe.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppoe.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppoe.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppol2tp.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppol2tp.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppol2tp.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppol2tp.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppos.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppos.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/pppos.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/pppos.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/upap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/upap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/src/include/netif/ppp/upap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/lwip213_v1_1/src/lwip-2.1.3/src/include/netif/ppp/upap.h diff --git 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xqspips.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c new file mode 100644 index 0000000..ae3635a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c @@ -0,0 +1,33 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xqspips.h" + +/* +* The configuration table for devices +*/ + +XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_QSPI_0_DEVICE_ID, + XPAR_PS7_QSPI_0_BASEADDR, + XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ, + XPAR_PS7_QSPI_0_QSPI_MODE + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xqspips_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_options.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_options.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_options.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_options.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscugic.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c new file mode 100644 index 0000000..a2acc53 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c @@ -0,0 +1,33 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xscugic.h" + +/* +* The configuration table for devices +*/ + +XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = +{ + { + XPAR_PS7_SCUGIC_0_DEVICE_ID, + XPAR_PS7_SCUGIC_0_BASEADDR, + XPAR_PS7_SCUGIC_0_DIST_BASEADDR, + {{0}} /**< Initialize the HandlerTable to 0 */ + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscugic_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscutimer.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c new file mode 100644 index 0000000..68cb0c6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xscutimer.h" + +/* +* The configuration table for devices +*/ + +XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] = +{ + { + XPAR_PS7_SCUTIMER_0_DEVICE_ID, + XPAR_PS7_SCUTIMER_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscutimer_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/CMakeLists.txt old mode 100755 new mode 100644 similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscuwdt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c new file mode 100644 index 0000000..f4313f9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xscuwdt.h" + +/* +* The configuration table for devices +*/ + +XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] = +{ + { + XPAR_PS7_SCUWDT_0_DEVICE_ID, + XPAR_PS7_SCUWDT_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xscuwdt_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xsdps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_card.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_card.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_card.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_card.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xsdps_core.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_core.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xsdps_core.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_core.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c new file mode 100644 index 0000000..e3e0812 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c @@ -0,0 +1,45 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xsdps.h" + +/* +* The configuration table for devices +*/ + +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_SD_0_DEVICE_ID, + XPAR_PS7_SD_0_BASEADDR, + XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ, + XPAR_PS7_SD_0_HAS_CD, + XPAR_PS7_SD_0_HAS_WP, + XPAR_PS7_SD_0_BUS_WIDTH, + XPAR_PS7_SD_0_MIO_BANK, + XPAR_PS7_SD_0_HAS_EMIO, + XPAR_PS7_SD_0_SLOT_TYPE, + XPAR_PS7_SD_0_IS_CACHE_COHERENT, + XPAR_PS7_SD_0_CLK_50_SDR_ITAP_DLY, + XPAR_PS7_SD_0_CLK_50_SDR_OTAP_DLY, + XPAR_PS7_SD_0_CLK_50_DDR_ITAP_DLY, + XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY, + XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY, + XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_host.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_host.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_host.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_host.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xsdps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_options.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_options.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_options.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_options.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/gcc/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/gcc/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/gcc/Makefile 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h new file mode 100644 index 0000000..5498919 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h @@ -0,0 +1,24 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + +#define MICROBLAZE_PVR_NONE + +/* Definition for hard-float ABI */ +#define FPU_HARD_FLOAT_ABI_ENABLED 1 + +#endif /*end of __BSPCONFIG_H_*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/bspconfig.h.in b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h.in similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/bspconfig.h.in rename to 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2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_printf.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_printf.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_printf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_sleepcommon.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_sleepcommon.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_sleepcommon.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_sleepcommon.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testcache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testcache.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_testcache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testio.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testio.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_testio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testmem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testmem.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_testmem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_util.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_util.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_util.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xil_util.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xplatform_info.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xplatform_info.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xplatform_info.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xpm_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xpm_init.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xpm_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xpm_init.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xstatus.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xstatus.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xstatus.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make new file mode 100644 index 0000000..2668199 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make @@ -0,0 +1,3 @@ +LIBSOURCES = *.c *.S +PROFILE_ARCH_OBJS = profile_mcount_arm.o +LIBS = standalone_libs diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/cpputest_time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpputest_time.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/cpputest_time.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpputest_time.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc/cpu_init.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpu_init.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc/cpu_init.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpu_init.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/errno.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/errno.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/errno.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/errno.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/fcntl.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fcntl.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/fcntl.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fcntl.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/fstat.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fstat.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/fstat.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fstat.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/getentropy.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getentropy.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/getentropy.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getentropy.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/getpid.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getpid.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/getpid.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getpid.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c new file mode 100644 index 0000000..0036459 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c @@ -0,0 +1,14 @@ +#include "xparameters.h" +#include "xuartps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif +char inbyte(void); +#ifdef __cplusplus +} +#endif + +char inbyte(void) { + return XUartPs_RecvByte(STDIN_BASEADDRESS); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/intr/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/intr/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/intr/xinterrupt_wrap.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/intr/xinterrupt_wrap.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xinterrupt_wrap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/isatty.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/isatty.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/isatty.c rename to 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_exception.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xmicroblaze.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xmicroblaze.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xmicroblaze_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/microblaze/xmicroblaze_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/open.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/open.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/open.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c new file mode 100644 index 0000000..8b56036 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c @@ -0,0 +1,15 @@ +#include "xparameters.h" +#include "xuartps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif +void outbyte(char c); + +#ifdef __cplusplus +} +#endif + +void outbyte(char c) { + XUartPs_SendByte(STDOUT_BASEADDRESS, c); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h new file mode 100644 index 0000000..d5d2838 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h @@ -0,0 +1,269 @@ +/****************************************************************************** +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * @file pm_api_version.h + * + * @addtogroup xpm_versal_apis XilPM APIs + *****************************************************************************/ + + +#ifndef PM_API_VERSION_H_ +#define PM_API_VERSION_H_ + +/*****************************************************************************/ +/** + * @section EEMI_API_DETAIL XilPM EEMI API Version Detail + * + * This section provides details of EEMI API version and it's history for PM APIs of XilPM library. + * + * | NAME | ID | Platform | Version| Description | + * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------| + * | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API | + * | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device | + * | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality | + * | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event | + * | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem | + * | PM_SELF_SUSPEND | 0x7 | Both | 2 | V1 - The API is used to suspend a child subsystem | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem | + * | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem | + * | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source | + * | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system | + * | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use | + * | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device | + * | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device | + * | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state | + * | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices | + * | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip | + * | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin | + * | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin | + * | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function | + * | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function | + * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value | + * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value | + * | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 | + * | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 | + * | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock | + * | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock | + * | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state | + * | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock | + * | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider | + * | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock | + * | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent | + * | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock | + * | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock | + * | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock | + * | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock | + * | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail + * + * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|---------------------------------------| + * | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode | + * | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode | + * | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config | + * | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config | + * | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass | + * | IOCTL_SET_SGMII_MODE | 5 | ZynqMP | SGMII mode | + * | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset | + * | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay | + * | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode | + * | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode | + * | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data | + * | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data | + * | IOCTL_WRITE_GGS | 12 | Both | Write GGS | + * | IOCTL_READ_GGS | 13 | Both | Read GGS | + * | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS | + * | IOCTL_READ_PGGS | 15 | Both | Read PGGS | + * | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset | + * | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status | + * | IOCTL_AFI | 18 | ZynqMP | AFI | + * | IOCTL_PROBE_COUNTER_READ | 19 | Versal | Probe counter read | + * | IOCTL_PROBE_COUNTER_WRITE | 20 | Versal | Probe counter write | + * | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select | + * | IOCTL_USB_SET_STATE | 22 | Versal | USB set state | + * | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason | + * | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear | + * | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF | + * | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config | + * | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config | + * | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register | + * | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register | + * | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value | + * | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value | + * | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value | + * | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations | + * | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value | + * | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode | + * | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode | + * | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down | + * | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail + * + * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |--------------------------------------------|-------|---------------|---------------------------------------| + * | XPM_QID_INVALID | 0 | Both | Invalid Query ID | + * | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name | + * | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology | + * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter | + * | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources | + * | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes | + * | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups | + * | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name | + * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups | + * | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups | + * | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks | + * | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor | + * | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent | + * | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes | + * + *****************************************************************************/ + + +/*****************************************************************************/ +/** + * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail + * + * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|-----------------------------------------------| + * | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power | + * | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature | + * | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency | + * + *****************************************************************************/ + + +/** + * PM API IDs + */ +typedef enum { + PM_API_MIN, /**< 0x0 */ + PM_GET_API_VERSION, /**< 0x1 */ + PM_SET_CONFIGURATION, /**< 0x2 */ + PM_GET_NODE_STATUS, /**< 0x3 */ + PM_GET_OP_CHARACTERISTIC, /**< 0x4 */ + PM_REGISTER_NOTIFIER, /**< 0x5 */ + PM_REQUEST_SUSPEND, /**< 0x6 */ + PM_SELF_SUSPEND, /**< 0x7 */ + PM_FORCE_POWERDOWN, /**< 0x8 */ + PM_ABORT_SUSPEND, /**< 0x9 */ + PM_REQUEST_WAKEUP, /**< 0xA */ + PM_SET_WAKEUP_SOURCE, /**< 0xB */ + PM_SYSTEM_SHUTDOWN, /**< 0xC */ + PM_REQUEST_NODE, /**< 0xD */ + PM_RELEASE_NODE, /**< 0xE */ + PM_SET_REQUIREMENT, /**< 0xF */ + PM_SET_MAX_LATENCY, /**< 0x10 */ + PM_RESET_ASSERT, /**< 0x11 */ + PM_RESET_GET_STATUS, /**< 0x12 */ + PM_MMIO_WRITE, /**< 0x13 */ + PM_MMIO_READ, /**< 0x14 */ + PM_INIT_FINALIZE, /**< 0x15 */ + PM_FPGA_LOAD, /**< 0x16 */ + PM_FPGA_GET_STATUS, /**< 0x17 */ + PM_GET_CHIPID, /**< 0x18 */ + PM_SECURE_RSA_AES, /**< 0x19 */ + PM_SECURE_SHA, /**< 0x1A */ + PM_SECURE_RSA, /**< 0x1B */ + PM_PINCTRL_REQUEST, /**< 0x1C */ + PM_PINCTRL_RELEASE, /**< 0x1D */ + PM_PINCTRL_GET_FUNCTION, /**< 0x1E */ + PM_PINCTRL_SET_FUNCTION, /**< 0x1F */ + PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */ + PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */ + PM_IOCTL, /**< 0x22 */ + PM_QUERY_DATA, /**< 0x23 */ + PM_CLOCK_ENABLE, /**< 0x24 */ + PM_CLOCK_DISABLE, /**< 0x25 */ + PM_CLOCK_GETSTATE, /**< 0x26 */ + PM_CLOCK_SETDIVIDER, /**< 0x27 */ + PM_CLOCK_GETDIVIDER, /**< 0x28 */ + PM_CLOCK_SETRATE, /**< 0x29 */ + PM_CLOCK_GETRATE, /**< 0x2A */ + PM_CLOCK_SETPARENT, /**< 0x2B */ + PM_CLOCK_GETPARENT, /**< 0x2C */ + PM_SECURE_IMAGE, /**< 0x2D */ + PM_FPGA_READ, /**< 0x2E */ + PM_SECURE_AES, /**< 0x2F */ + PM_PLL_SET_PARAMETER, /**< 0x30 */ + PM_PLL_GET_PARAMETER, /**< 0x31 */ + PM_PLL_SET_MODE, /**< 0x32 */ + PM_PLL_GET_MODE, /**< 0x33 */ + PM_REGISTER_ACCESS, /**< 0x34 */ + PM_EFUSE_ACCESS, /**< 0x35 */ + PM_ADD_SUBSYSTEM, /**< 0x36 */ + PM_DESTROY_SUBSYSTEM, /**< 0x37 */ + PM_DESCRIBE_NODES, /**< 0x38 */ + PM_ADD_NODE, /**< 0x39 */ + PM_ADD_NODE_PARENT, /**< 0x3A */ + PM_ADD_NODE_NAME, /**< 0x3B */ + PM_ADD_REQUIREMENT, /**< 0x3C */ + PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */ + PM_INIT_NODE, /**< 0x3E */ + PM_FEATURE_CHECK, /**< 0x3F */ + PM_ISO_CONTROL, /**< 0x40 */ + PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */ + PM_SET_NODE_ACCESS, /**< 0x42 */ + PM_BISR, /**< 0x43 */ + PM_APPLY_TRIM, /**< 0x44 */ + PM_NOC_CLOCK_ENABLE, /**< 0x45 */ + PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */ + PM_FORCE_HOUSECLEAN, /**< 0x47 */ + PM_FPGA_GET_VERSION, /**< 0x48 */ + PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */ + PM_API_MAX /**< 0x4A */ +} XPm_ApiId; + +#endif /* PM_API_VERSION_H_ */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/print.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/print.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/print.c rename to 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/riscv/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/riscv/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/riscv/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/riscv/xreg_riscv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xreg_riscv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/riscv/xreg_riscv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xreg_riscv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/sbrk.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sbrk.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/sbrk.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sbrk.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/sleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/sleep.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/sleep.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.h similarity index 52% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/sleep.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.h index fd70448..0d881b6 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/include/sleep.h +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.h @@ -1,25 +1,37 @@ /****************************************************************************** -* -* Copyright (C) 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT -* ******************************************************************************/ + /*****************************************************************************/ /** * @file sleep.h * -* This header file contains sleep related APIs. +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. * * 
 * MODIFICATION HISTORY :
 *
 * Ver   Who  Date	 Changes
 * ----- ---- -------- -------------------------------------------------------
-*  1.0  adk	 24/11/21 Initial release.
-*  1.2  adk	 22/12/22 Fixed doxygen style and indentation issues.
-*
+* 6.6   srm  11/02/17 Added processor specific sleep routines
+*								 function prototypes.
+* 7.7	sk   01/10/22 Typecast sleep declaration argument from unsigned int to
+* 		      u32 to fix misra_c_2012_directive_4_6 violation.
+* 7.7	sk   01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
+* 		      unsigned to void to fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk   03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
+*		      c_2012_directive_4_6 violation.
+* 8.0	sk   03/17/22 Modify the return type of usleep_MB from int to void and
+*		      sleep_MB from unsigned to void to fix misra_c_2012_rule_
+*		      17_7 violation.
+* 8.0	sk   03/17/22 Modify sleep_MB parameter type from unsigned int to
+*		      u32 and usleep_MB parameter type from unsigned long to
+*		      ULONG to fix misra_c_2012_rule_4_6 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
 *
* ******************************************************************************/ @@ -51,9 +63,8 @@ extern "C" { * @param COND - Condition to checked (usually involves VALUE) * @param TIMEOUT_US - timeout in micro seconds * -* @return -* - 0 - when the condition is met -* - 1 - when the condition is not met till the timeout period +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period * * @note none * @@ -77,8 +88,19 @@ extern "C" { (timeout>0) ? 0 : -1; \ } ) -void usleep(unsigned long useconds); -void sleep(unsigned int seconds); +/************************** Function Prototypes ******************************/ +void usleep(ULONG useconds); +void sleep(u32 seconds); +void usleep_R5(ULONG useconds); +void sleep_R5(u32 seconds); +void usleep_MB(ULONG useconds); +void sleep_MB(u32 seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +/*****************************************************************************/ #ifdef __cplusplus } diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/smc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/smc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/smc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/time.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/time.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/time.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc/translation_table.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/translation_table.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc/translation_table.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/translation_table.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/unlink.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/unlink.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/unlink.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/unlink.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/usleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/usleep.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/usleep.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/usleep.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/vectors.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/vectors.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/vectors.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal/xil_error_node.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_error_node.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal/xil_error_node.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_error_node.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal/xil_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal/xil_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal_net/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal_net/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/versal_net/xil_error_node.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_error_node.h similarity index 100% rename from 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b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/write.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/write.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/write.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xbasic_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xbasic_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xbasic_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xbasic_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xcortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xcortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xcortexa9_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xcortexa9_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xdebug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xenv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv_standalone.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xenv_standalone.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv_standalone.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc/xil-crt0.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil-crt0.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/gcc/xil-crt0.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil-crt0.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_assert.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_assert.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_assert.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xil_cache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xil_cache.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_l.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cache_l.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_l.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_vxworks.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cache_vxworks.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_vxworks.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c new file mode 100644 index 0000000..421de02 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c @@ -0,0 +1,256 @@ +/****************************************************************************** +* Copyright (C) 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.c +* +* The xil_clocking.c file contains clocking related functions and macros. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  02/06/20 First release of clocking
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 9.0 ml  03/03/23 Add description to fix doxygen warnings.
+*
+* +******************************************************************************/ + +#include "xil_clocking.h" +/************************** Variable Definitions *****************************/ + +#if (defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR)) && defined (XCLOCKING) +XClock ClockInstance; /* Instance of clock Controller */ +XClockPs_Config *ConfigPtr; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This API initialize the Clock controller driver. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockInit(void) +{ + XStatus Status = XST_FAILURE; + + /* Lookup clock configurations */ +#ifndef SDT + ConfigPtr = XClock_LookupConfig(XPAR_XCLOCKPS_DEVICE_ID); +#else + ConfigPtr = XClock_LookupConfig(XPAR_PSU_CRL_APB_BASEADDR); +#endif + + /* Initialize the Clock controller driver */ + Status = XClock_CfgInitialize(&ClockInstance, ConfigPtr); + return Status; +} + +/*****************************************************************************/ +/** +* +* This function enables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockEnable(XClock_OutputClks ClockId) +{ + + XStatus Status = XST_FAILURE; + + Status = XClock_EnableClock(ClockId); + return Status; +} + +/*****************************************************************************/ +/** +* +* This function disables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockDisable(XClock_OutputClks ClockId) +{ + XStatus Status = XST_FAILURE; + + Status = XClock_DisableClock(ClockId); + return Status; +} + +/*****************************************************************************/ +/** +* +* This function is used to fetch rate of output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is a pointer to variable storing rate. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate) +{ + XStatus Status = XST_FAILURE; + + Xil_AssertNonvoid(Rate != NULL); + + Status = XClock_GetRate(ClockId, Rate); + if (XST_SUCCESS == Status) { + xdbg_printf(XDBG_DEBUG_GENERAL, "Operating rate = %lx\n",*Rate); + } else { + xdbg_printf(XDBG_DEBUG_ERROR, "Failed: Fetching rate\r\n"); + } + return Status; +} +/*****************************************************************************/ +/** +* +* This function is used to set rate for output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is the clock rate to set. +* @param SetRate is a pointer to variable holding rate that is set. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, + XClockRate *SetRate) +{ + XStatus Status = XST_FAILURE; + + Xil_AssertNonvoid(SetRate != NULL); + + if (Rate == 0) { + return XST_FAILURE; + } + Status = XClock_SetRate(ClockId, Rate, SetRate); + if (XST_SUCCESS != Status) { + xdbg_printf(XDBG_DEBUG_ERROR, "Failed Setting rate\n"); + } + return Status; +} + +#else + +/*****************************************************************************/ +/** +* +* This function is used to fetch rate of output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is pointer to variable storing rate. +* +* @return XST_FAILURE to indicate failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate) +{ + (void) ClockId; + (void) Rate; + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* +* This function is used to set rate for output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is the clock rate to set. +* @param SetRate is a pointer to variable holding rate that is set. +* +* @return XST_FAILURE to indicate failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, + XClockRate *SetRate) { + (void) ClockId; + (void) Rate; + (void) SetRate; + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* +* This API initialize the Clock controller driver. +* +* @return XST_SUCCESS to indicate success. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockInit(void) +{ + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function enables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return XST_SUCCESS to indicate success. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockEnable(XClock_OutputClks ClockId) +{ + (void) ClockId; + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return XST_SUCCESS to indicate success. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockDisable(XClock_OutputClks ClockId) +{ + (void) ClockId; + return XST_SUCCESS; +} + +#endif /* XCLOCKING */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h new file mode 100644 index 0000000..d40a6f7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.h +* +* The xil_clocking.h file contains clocking related functions and macros. +* certain conditions. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  12/11/19 First release
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 7.7 sk  01/10/22 Add function prototype for Xil_ClockGetRate to fix
+* 		   misra_c_2012_rule_8_4 violation.
+* 9.0 ml  03/03/23 Added description to fix doxygen warnings.
+*
+* +******************************************************************************/ + +#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */ +#define XIL_CLOCKING_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xdebug.h" +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xparameters.h" +#include "xstatus.h" +#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR) +#include "xclockps.h" +#else +typedef u32 XClock_OutputClks; +typedef u64 XClockRate; +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + + +XStatus Xil_ClockDisable(XClock_OutputClks ClockId); +XStatus Xil_ClockEnable(XClock_OutputClks ClockId); +XStatus Xil_ClockInit(void); +XStatus Xil_ClockGet(void); +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate); +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cryptoalginfo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cryptoalginfo.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_cryptoalginfo.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cryptoalginfo.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_errata.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_errata.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_errata.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xil_exception.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_hal.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_hal.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_hal.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_io.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_io.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_io.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_macroback.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_macroback.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_macroback.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_mem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_mem.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xil_misc_psreset_api.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xil_misc_psreset_api.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xil_mmu.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xil_mmu.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_mmu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_printf.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_printf.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_printf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_sleepcommon.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleepcommon.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_sleepcommon.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleepcommon.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xil_sleeptimer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xil_sleeptimer.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h new file mode 100644 index 0000000..adcb7e6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 7.0   mus  01/07/19 Add cpp extern macro
+* 7.7	sk   01/10/22 Add explicit parentheses for EL3==1 to fix
+* 		      misra_c_2012_rule_12_1 violation.
+* 7.7	sk   01/10/22 Add void to XTime_StartTTCTimer function declaration
+* 		      to fix misra_c_2012_rule_8_2 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
+*****************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && (EL3==1)) || defined (ARMA53_32) +#if defined (versal) +#define CRL_TTC_RST 0xFF5E0344U +#define CRL_TTC_BASE_RST_MASK 0x1U +#else +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ +/** + *@endcond + */ +/************************** Function Prototypes ******************************/ + +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ +void Xil_SleepTTCCommon(u32 delay, u64 frequency); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_SLEEPTIMER_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xil_spinlock.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xil_spinlock.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_spinlock.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_spinlock.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_testcache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_testcache.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_testcache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_testio.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_testio.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_testio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_testmem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_testmem.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_testmem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_util.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xil_util.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_util.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xil_util.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/xilstandalone.cmake b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xilstandalone.cmake similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/xilstandalone.cmake rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xilstandalone.cmake diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c new file mode 100644 index 0000000..10f339e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c @@ -0,0 +1,455 @@ +/****************************************************************************** +* Copyright (c) 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xinterrupt_wrap.c +* +* The xinterrupt_wrap.c file contains interrupt related functions and macros. +* Contains wrapper functions for the scugic/axi intc Interrupt controller +* drivers. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2   mus  22/11/21 First release of xil interrupt support
+* 9.0   adk  17/04/23 Added support for system device-tree flow
+* 9.0   adk  27/04/23 Use XScuGic_LookupConfigBaseAddr() API for xsct flow
+*
+* +******************************************************************************/ + +#include "xinterrupt_wrap.h" + +#ifdef XIL_INTERRUPT + +#if defined (XPAR_SCUGIC) /* available in xscugic.h */ +static XScuGic XScuGicInstance; +static int ScuGicInitialized; +#endif + +#if defined (XPAR_AXI_INTC) /* available in xintc.h */ +static XIntc XIntcInstance ; +#endif + +/*****************************************************************************/ +/** +* +* @brief Initializes the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConfigInterruptCntrl(UINTPTR IntcParent) +{ + int Status = XST_FAILURE; + UINTPTR BaseAddr = XGet_BaseAddr(IntcParent); + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Config *CfgPtr = NULL; + if (XScuGicInstance.IsReady != XIL_COMPONENT_IS_READY) { +#if defined(SDT) + CfgPtr = XScuGic_LookupConfig(BaseAddr); +#else + CfgPtr = XScuGic_LookupConfigBaseAddr(BaseAddr); +#endif + if (!ScuGicInitialized) { + Status = XScuGic_CfgInitialize(&XScuGicInstance, CfgPtr, 0); + } else { + Status = XST_SUCCESS; + } + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Initialize(&XIntcInstance, BaseAddr); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief connects to the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntrHandler: Interrupt handler. +* @param CallBackRef: Callback reference for handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent) +{ + int Status; + int Doconnect = FALSE; + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (ScuGicInitialized) { + Doconnect = 1; + } + if (Doconnect) { + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + Status = XScuGic_Connect(&XScuGicInstance, IntrNum, \ + (Xil_ExceptionHandler) IntrHandler, CallBackRef); + return Status; + } else { + return XST_SUCCESS; + } +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + Status = XIntc_Connect(&XIntcInstance, IntrNum, \ + (XInterruptHandler)IntrHandler, CallBackRef); + return Status; +#else + return XST_FAILURE; +#endif + + } +} + +/*****************************************************************************/ +/** +* +* @brief disconnects the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disconnect(&XScuGicInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Disconnect(&XIntcInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* @brief Starts the interrupt controller. +* +* @param Mode: Interrupt controller mode type. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent) +{ +#if defined (XPAR_AXI_INTC) + int Status = XST_FAILURE; +#else + (void) Mode; +#endif + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + /* + * For XPAR_SCUGIC, XConfigInterruptCntrl starts controller + * hence returning without doing anything + */ + return 0; + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Start(&XIntcInstance, Mode); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + + } + +} + +/*****************************************************************************/ +/** +* +* @brief Enable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XEnableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + IntrNum += Offset; + XScuGic_Enable(&XScuGicInstance, IntrNum); +#endif + + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Enable(&XIntcInstance, IntrNum); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief disable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDisableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disable(&XScuGicInstance, IntrNum); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Disable(&XIntcInstance, IntrId); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Configures the priority and trigger type. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent) +{ +#if defined (XPAR_SCUGIC) + u8 Trigger = (((XGet_TriggerType(IntrId) == 1) || + (XGet_TriggerType(IntrId) == 2)) ? XINTR_IS_EDGE_TRIGGERED + : XINTR_IS_LEVEL_TRIGGERED); + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + XScuGic_SetPriorityTriggerType(&XScuGicInstance, IntrNum, Priority, Trigger); + } +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Gets the priority of the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param Trigger: Trigger type of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_GetPriorityTriggerType(&XScuGicInstance, IntrId, Priority, Trigger); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief stops the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XStopInterruptCntrl( UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Stop(&XScuGicInstance); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Stop(&XIntcInstance); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief Registers the interrupt handler. +* +* @param IntrHandler: Interrupt handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XRegisterInterruptHandler(void *IntrHandler, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XScuGic_InterruptHandler, + &XScuGicInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XScuGicInstance); + + } +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XIntc_InterruptHandler, + &XIntcInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XIntcInstance); + } +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Setup the interrupt system. +* +* @param DriverInstance: Driver instance pointer. +* @param IntrHandler: Interrupt handler funtion pointer. +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* @param Priority: Interrupt priority. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent, u16 Priority) +{ + int Status; + + Status = XConfigInterruptCntrl(IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_SCUGIC) + ScuGicInitialized = TRUE; +#endif + XSetPriorityTriggerType( IntrId, Priority, IntcParent); + Status = XConnectToInterruptCntrl( IntrId, (Xil_ExceptionHandler) IntrHandler, \ + DriverInstance, IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_AXI_INTC) + XStartInterruptCntrl(XIN_REAL_MODE, IntcParent); +#endif + XRegisterInterruptHandler(NULL, IntcParent); + XEnableIntrId(IntrId, IntcParent); + Xil_ExceptionInit(); + Xil_ExceptionEnable(); + return XST_SUCCESS; +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/intr/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/intr/xinterrupt_wrap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xl2cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xl2cc_counter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xl2cc_counter.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xl2cc_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xplatform_info.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xplatform_info.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xplatform_info.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xpm_counter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/xpm_counter.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xpm_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xpm_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/xpm_init.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h new file mode 100644 index 0000000..f2856be --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h @@ -0,0 +1,46 @@ +/****************************************************************************** +*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +*SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.h +* @addtogroup xpm_init xpm_init APIs +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
+******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xreg_cortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xreg_cortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xreg_cortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xstatus.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xstatus.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xstatus.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xtime_l.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/xtime_l.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h new file mode 100644 index 0000000..9d17f5c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h @@ -0,0 +1,86 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Updated get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Updated get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
+* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
+* 7.5   mus    04/30/21  Moved pragma message from xtime_l.h to xtime_l.c, to avoid
+*                        displaying same warnings multiple times. It fixes CR#1090562.
+*
+* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +#endif +/************************** Variable Definitions *****************************/ + +/** +*@endcond +*/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xuartps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c new file mode 100644 index 0000000..6872364 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c @@ -0,0 +1,33 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xuartps.h" + +/* +* The configuration table for devices +*/ + +XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_UART_1_DEVICE_ID, + XPAR_PS7_UART_1_BASEADDR, + XPAR_PS7_UART_1_UART_CLK_FREQ_HZ, + XPAR_PS7_UART_1_HAS_MODEM + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xuartps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_options.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_options.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_options.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_options.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/CMakeLists.txt old mode 100755 new mode 100644 similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xadcps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c new file mode 100644 index 0000000..197994e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xadcps.h" + +/* +* The configuration table for devices +*/ + +XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_XADC_0_DEVICE_ID, + XPAR_PS7_XADC_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/xadcps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/qemu/qemu_args.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu/qemu_args.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/qemu/qemu_args.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu/qemu_args.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/qemu/qemu_args.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/export/NewInstrCalBoard_bsp/sw/standalone_ps7_cortexa9_0/qemu/qemu_args.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/CMakeLists.txt similarity index 97% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/CMakeLists.txt index 327537c..0c58b9e 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/CMakeLists.txt +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/CMakeLists.txt @@ -3,7 +3,7 @@ cmake_minimum_required(VERSION 3.15) -set(APP_NAME fsbl) +set(APP_NAME zynq_fsbl) project(${APP_NAME}) include_directories(${CMAKE_BINARY_DIR}/include) @@ -12,12 +12,7 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/UserConfig.cmake) find_package(common) enable_language(C ASM) -collect(PROJECT_LIB_DEPS xiltimer;xilffs;xilrsa) - - - - - +collect(PROJECT_LIB_DEPS xiltimer) collect(PROJECT_LIB_DEPS xilffs) collect(PROJECT_LIB_DEPS xilrsa) collect(PROJECT_LIB_DEPS xil) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Makefile new file mode 100644 index 0000000..75b1ef6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Makefile @@ -0,0 +1,46 @@ +# Auto Generated by Xilinx generate_app. Modify at your own risk + +CC := arm-none-eabi-gcc +CC_FLAGS := -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard +CFLAGS := +BSP_FLAGS := -O2 -c +LN_FLAGS := -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections + +c_SOURCES := $(wildcard *.c) +S_SOURCES := $(wildcard *.S) +s_SOURCES := $(wildcard *.s) +INCLUDES := $(wildcard *.h) +OBJS := $(patsubst %.c, %.o, $(c_SOURCES)) +OBJS += $(patsubst %.S, %.o, $(S_SOURCES)) +OBJS += $(patsubst %.s, %.o, $(s_SOURCES)) +LSCRIPT := -Tlscript.ld + +CURRENT_DIR = $(shell pwd) +DEPFILES := $(patsubst %.o, %.d, $(OBJS)) +LIBS := zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a +EXEC := fsbl.elf + +INCLUDEPATH := -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I. +LIBPATH := -Lzynq_fsbl_bsp/ps7_cortexa9_0/lib -L./ + +all: $(EXEC) + +$(EXEC): $(LIBS) $(OBJS) $(INCLUDES) + $(CC) -o $@ $(sort $(OBJS)) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT) + +$(LIBS): + $(MAKE) -C zynq_fsbl_bsp + +%.o:%.c + $(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH) + +%.o:%.S + $(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH) + +%.o:%.s + $(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH) + +clean: + rm -rf $(OBJS) $(LIBS) $(EXEC) *.o + +-include $(DEPFILES) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Xilinx.spec b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Xilinx.spec new file mode 100644 index 0000000..8eea377 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/Xilinx.spec @@ -0,0 +1,2 @@ +*startfile: +crti%O%s crtbegin%O%s diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/fsbl.elf b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/fsbl.elf new file mode 100755 index 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z#AdU#$+cu7x(L#vB1tiq*EXucA(dD((mLnw61Ou3HA$_qtVcanL>VZrX1JnF({fU& z%efoX4UMy!8Ij(Nh1NTzMmB7C77>a~I2BcN4jv{w^^`1g+tN(MNKpA=e!jdJ)>RM7 zWwzA%T)-Rd33zjc!1*dTkuh;M3k&+7E3)ISWoX? z<7?GR6#?|J)QueF9O?Wmc5gH#qHB33tGl^`63A9~3O;h`T7B^1Lu83gGqNKs9&#Dd z91mn%gOs`tiA}_4Crtu>WKkI+qsjJ9KEFBlxqUF)MT!NkzTW96>AAH;wX!qhJ?VebFui}&M zasCVK_->gWKJHI&f&K9o_a7gIR|EH&`thcnbn(e{>`&gSeTuWE{Gtc%@#y34d-#)~ zKF8J1@sAjI!w#PF4_l}4R+YAU9qnF!NxKSdNCW%h?_0cyb{}#RwH-b#w(_#gf|t3k zmhB!{8-94ZpX1#7^LF^hM)7#p&c47WpONSAUdfNqUw(LhU*V$n$M*|3Zg@Af^mbq8 z?c}{OQ2V#dcE7?UKJ(CSaa_D=6c66x-*4^HZ}i#jJs-{J#?9YbJMXXj^=sjG{*c|{ zQ-88^e8} +#include "xil_types.h" +#include "profile_config.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void _system_init( void ) ; +void _system_clean( void ) ; +void mcount(u32 frompc, u32 selfpc); +void profile_intr_handler( void ) ; +void _profile_init( void ); + + + +/**************************************************************************** + * Profiling on hardware - Hash table maintained on hardware and data sent + * to xmd for gmon.out generation. + ****************************************************************************/ +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER u16 + +struct tostruct { + u32 selfpc; + s32 count; + s16 link; + u16 pad; +}; + +struct fromstruct { + u32 frompc ; + s16 link ; + u16 pad ; +} ; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + s32 state; + + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ + + /* Call-graph Information */ + struct fromstruct *froms; + u32 fromssize; + struct tostruct *tos; + u32 tossize; + + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ +}; +extern struct gmonparam *_gmonparam; +extern s32 n_gmon_sections; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +#ifdef __cplusplus +} +#endif + +#endif /* PROFILE_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/sleep.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h similarity index 52% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/sleep.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h index fd70448..0d881b6 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/sleep.h +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h @@ -1,25 +1,37 @@ /****************************************************************************** -* -* Copyright (C) 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT -* ******************************************************************************/ + /*****************************************************************************/ /** * @file sleep.h * -* This header file contains sleep related APIs. +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. * * 

     * MODIFICATION HISTORY :
 *
 * Ver   Who  Date	 Changes
 * ----- ---- -------- -------------------------------------------------------
-*  1.0  adk	 24/11/21 Initial release.
-*  1.2  adk	 22/12/22 Fixed doxygen style and indentation issues.
-*
+* 6.6   srm  11/02/17 Added processor specific sleep routines
+*								 function prototypes.
+* 7.7	sk   01/10/22 Typecast sleep declaration argument from unsigned int to
+* 		      u32 to fix misra_c_2012_directive_4_6 violation.
+* 7.7	sk   01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
+* 		      unsigned to void to fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk   03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
+*		      c_2012_directive_4_6 violation.
+* 8.0	sk   03/17/22 Modify the return type of usleep_MB from int to void and
+*		      sleep_MB from unsigned to void to fix misra_c_2012_rule_
+*		      17_7 violation.
+* 8.0	sk   03/17/22 Modify sleep_MB parameter type from unsigned int to
+*		      u32 and usleep_MB parameter type from unsigned long to
+*		      ULONG to fix misra_c_2012_rule_4_6 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
 *
    * ******************************************************************************/ @@ -51,9 +63,8 @@ extern "C" { * @param COND - Condition to checked (usually involves VALUE) * @param TIMEOUT_US - timeout in micro seconds * -* @return -* - 0 - when the condition is met -* - 1 - when the condition is not met till the timeout period +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period * * @note none * @@ -77,8 +88,19 @@ extern "C" { (timeout>0) ? 0 : -1; \ } ) -void usleep(unsigned long useconds); -void sleep(unsigned int seconds); +/************************** Function Prototypes ******************************/ +void usleep(ULONG useconds); +void sleep(u32 seconds); +void usleep_R5(ULONG useconds); +void sleep_R5(u32 seconds); +void usleep_MB(ULONG useconds); +void sleep_MB(u32 seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +/*****************************************************************************/ #ifdef __cplusplus } diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/smc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/smc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/vectors.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/vectors.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xadcps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xadcps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xbasic_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xbasic_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xcoresightpsdcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xcortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xcortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xcortexa9_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xcortexa9_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h new file mode 100644 index 0000000..f6b3728 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9 Overview +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into +# extra compiler flags. Now, user can remove default flags +# from extra compiler flags. It fixes CR#998768. +******************************************************************************/ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h new file mode 100644 index 0000000..271da20 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ + +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps Overview + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
    + * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdevcfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdevcfg_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdmaps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xdmaps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps_bd.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps_bdring.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xemacps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xenv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xenv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xenv_standalone.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xgpiops.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xgpiops_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_assert.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_cache_l.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_cache_vxworks.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_clocking.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_clocking.h new file mode 100644 index 0000000..d40a6f7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_clocking.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.h +* +* The xil_clocking.h file contains clocking related functions and macros. +* certain conditions. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  12/11/19 First release
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 7.7 sk  01/10/22 Add function prototype for Xil_ClockGetRate to fix
+* 		   misra_c_2012_rule_8_4 violation.
+* 9.0 ml  03/03/23 Added description to fix doxygen warnings.
+*
    +* +******************************************************************************/ + +#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */ +#define XIL_CLOCKING_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xdebug.h" +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xparameters.h" +#include "xstatus.h" +#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR) +#include "xclockps.h" +#else +typedef u32 XClock_OutputClks; +typedef u64 XClockRate; +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + + +XStatus Xil_ClockDisable(XClock_OutputClks ClockId); +XStatus Xil_ClockEnable(XClock_OutputClks ClockId); +XStatus Xil_ClockInit(void); +XStatus Xil_ClockGet(void); +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate); +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_cryptoalginfo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_cryptoalginfo.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_errata.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_hal.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_io.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_macroback.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xil_mmu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_printf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h new file mode 100644 index 0000000..adcb7e6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 7.0   mus  01/07/19 Add cpp extern macro
+* 7.7	sk   01/10/22 Add explicit parentheses for EL3==1 to fix
+* 		      misra_c_2012_rule_12_1 violation.
+* 7.7	sk   01/10/22 Add void to XTime_StartTTCTimer function declaration
+* 		      to fix misra_c_2012_rule_8_2 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
    +*****************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && (EL3==1)) || defined (ARMA53_32) +#if defined (versal) +#define CRL_TTC_RST 0xFF5E0344U +#define CRL_TTC_BASE_RST_MASK 0x1U +#else +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ +/** + *@endcond + */ +/************************** Function Prototypes ******************************/ + +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ +void Xil_SleepTTCCommon(u32 delay, u64 frequency); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_SLEEPTIMER_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/xil_spinlock.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_spinlock.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/xil_spinlock.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_spinlock.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testcache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_testmem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_util.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xil_util.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xilrsa.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xilrsa.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xinterrupt_wrap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xl2cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xl2cc_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h new file mode 100644 index 0000000..20f947c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h @@ -0,0 +1,472 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0U + +/* Definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +#define STDIN_BASEADDRESS 0xE0001000 +#define STDOUT_BASEADDRESS 0xE0001000 + +/******************************************************************/ + +/* Platform specific definitions */ +#define PLATFORM_ZYNQ + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ + +/* Definitions for peripheral PS7_DDR_0 */ +#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF + + +/******************************************************************/ + +/* Definitions for driver DEVCFG */ +#define XPAR_XDCFG_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID +#define XPAR_XDCFG_0_BASEADDR 0xF8007000U +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Definitions for driver DMAPS */ +#define XPAR_XDMAPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PS7_DMA_NS */ +#define XPAR_PS7_DMA_NS_DEVICE_ID 0 +#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 +#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF + + +/* Definitions for peripheral PS7_DMA_S */ +#define XPAR_PS7_DMA_S_DEVICE_ID 1 +#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 +#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DMA_NS */ +#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID +#define XPAR_XDMAPS_0_BASEADDR 0xF8004000 +#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF + +/* Canonical definitions for peripheral PS7_DMA_S */ +#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID +#define XPAR_XDMAPS_1_BASEADDR 0xF8003000 +#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 +#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 +#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF +#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 +#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 +#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 +#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0 + + +/******************************************************************/ + + +/* Peripheral Definitions for peripheral MYDNA_READ_V1_0_0 */ +#define XPAR_MYDNA_READ_V1_0_0_BASEADDR 0x43C00000 +#define XPAR_MYDNA_READ_V1_0_0_HIGHADDR 0x43C0FFFF + + +/* Peripheral Definitions for peripheral PS7_AFI_0 */ +#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 +#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF + + +/* Peripheral Definitions for peripheral PS7_AFI_1 */ +#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 +#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF + + +/* Peripheral Definitions for peripheral PS7_AFI_2 */ +#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 +#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF + + +/* Peripheral Definitions for peripheral PS7_AFI_3 */ +#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 +#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF + + +/* Peripheral Definitions for peripheral PS7_DDRC_0 */ +#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 +#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF + + +/* Peripheral Definitions for peripheral PS7_GLOBALTIMER_0 */ +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF + + +/* Peripheral Definitions for peripheral PS7_GPV_0 */ +#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 +#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF + + +/* Peripheral Definitions for peripheral PS7_INTC_DIST_0 */ +#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 +#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF + + +/* Peripheral Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF + + +/* Peripheral Definitions for peripheral PS7_L2CACHEC_0 */ +#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Peripheral Definitions for peripheral PS7_OCMC_0 */ +#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 +#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF + + +/* Peripheral Definitions for peripheral PS7_PL310_0 */ +#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Peripheral Definitions for peripheral PS7_PMU_0 */ +#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 +#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF +#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 +#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF + + +/* Peripheral Definitions for peripheral PS7_QSPI_LINEAR_0 */ +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF + + +/* Peripheral Definitions for peripheral PS7_RAM_0 */ +#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF + + +/* Peripheral Definitions for peripheral PS7_RAM_1 */ +#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Peripheral Definitions for peripheral PS7_SCUC_0 */ +#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 +#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC + + +/* Peripheral Definitions for peripheral PS7_SLCR_0 */ +#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 +#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF + + +/******************************************************************/ + + +/* Canonical Definitions for peripheral MYDNA_READ_V1_0_0 */ +#define XPAR_MYDNA_READ_V1_0_BASEADDR 0x43C00000 +#define XPAR_MYDNA_READ_V1_0_HIGHADDR 0x43C0FFFF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_GPIO_0 */ +#define XPAR_PS7_GPIO_0_DEVICE_ID 0 +#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 +#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Definitions for driver QSPIPS */ +#define XPAR_XQSPIPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_QSPI_0 */ +#define XPAR_PS7_QSPI_0_DEVICE_ID 0 +#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 +#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF +#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 142857132 +#define XPAR_PS7_QSPI_0_QSPI_MODE 0 +#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_QSPI_0 */ +#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 +#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF +#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 142857132 +#define XPAR_XQSPIPS_0_QSPI_MODE 0 +#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Definitions for driver SCUTIMER */ +#define XPAR_XSCUTIMER_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 +#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID +#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Definitions for driver SCUWDT */ +#define XPAR_XSCUWDT_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 +#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID +#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SD_0 */ +#define XPAR_PS7_SD_0_DEVICE_ID 0 +#define XPAR_PS7_SD_0_BASEADDR 0xE0100000 +#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF +#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 +#define XPAR_PS7_SD_0_HAS_CD 1 +#define XPAR_PS7_SD_0_HAS_WP 1 +#define XPAR_PS7_SD_0_BUS_WIDTH 0 +#define XPAR_PS7_SD_0_MIO_BANK 0 +#define XPAR_PS7_SD_0_HAS_EMIO 0 +#define XPAR_PS7_SD_0_SLOT_TYPE 0 +#define XPAR_PS7_SD_0_CLK_50_SDR_ITAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_50_SDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_50_DDR_ITAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY 0 +#define XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY 0 + + +/******************************************************************/ + +#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xE0100000 +#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 +#define XPAR_XSDPS_0_HAS_CD 1 +#define XPAR_XSDPS_0_HAS_WP 1 +#define XPAR_XSDPS_0_BUS_WIDTH 0 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 +#define XPAR_XSDPS_0_SLOT_TYPE 0 +#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0 +#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0 +#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0 +#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0 +#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0 + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_UART_1 */ +#define XPAR_PS7_UART_1_DEVICE_ID 0 +#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 +#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF +#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000 +#define XPAR_PS7_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_UART_1 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xE0001000 +#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definition for input Clock */ +/* Definitions for driver XADCPS */ +#define XPAR_XADCPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_XADC_0 */ +#define XPAR_PS7_XADC_0_DEVICE_ID 0 +#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 +#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_XADC_0 */ +#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID +#define XPAR_XADCPS_0_BASEADDR 0xF8007100 +#define XPAR_XADCPS_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +/* Xilinx FAT File System Library (XilFFs) User Settings */ +#define FILE_SYSTEM_INTERFACE_SD +#define FILE_SYSTEM_USE_MKFS +#define FILE_SYSTEM_NUM_LOGIC_VOL 2 +#define FILE_SYSTEM_USE_STRFUNC 0 +#define FILE_SYSTEM_SET_FS_RPATH 0 +#define FILE_SYSTEM_WORD_ACCESS +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xplatform_info.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xpm_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_init.h new file mode 100644 index 0000000..f2856be --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_init.h @@ -0,0 +1,46 @@ +/****************************************************************************** +*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +*SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.h +* @addtogroup xpm_init xpm_init APIs +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
    +******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xqspips.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xqspips_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/arm/cortexa9/xreg_cortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscugic.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscugic_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscutimer.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscutimer_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscuwdt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xscuwdt_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xsdps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xsdps_core.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_core.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xsdps_core.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_core.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xsdps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xsdps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/standalone/src/common/xstatus.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h new file mode 100644 index 0000000..9d17f5c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h @@ -0,0 +1,86 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Updated get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Updated get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
+* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
+* 7.5   mus    04/30/21  Moved pragma message from xtime_l.h to xtime_l.c, to avoid
+*                        displaying same warnings multiple times. It fixes CR#1090562.
+*
    +* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +#endif +/************************** Variable Definitions *****************************/ + +/** +*@endcond +*/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xuartps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/build_configs/gen_bsp/include/xuartps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc/src/xcoresightpsdcc.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/coresightps_dcc/src/xcoresightpsdcc.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/xcoresightpsdcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/coresightps_dcc/src/xcoresightpsdcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src/xcoresightpsdcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h new file mode 100644 index 0000000..f6b3728 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9 Overview +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into +# extra compiler flags. Now, user can remove default flags +# from extra compiler flags. It fixes CR#998768. +******************************************************************************/ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h new file mode 100644 index 0000000..271da20 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ + +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps Overview + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
    + * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/Makefile old mode 100755 new mode 100644 similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c new file mode 100644 index 0000000..6eb100d --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdevcfg.h" + +/* +* The configuration table for devices +*/ + +XDcfg_Config XDcfg_ConfigTable[] = +{ + { + XPAR_PS7_DEV_CFG_0_DEVICE_ID, + XPAR_PS7_DEV_CFG_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/devcfg/src/xdevcfg_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/devcfg/src/xdevcfg_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c new file mode 100644 index 0000000..b36c8c3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_g.c @@ -0,0 +1,35 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdmaps.h" + +/* +* The configuration table for devices +*/ + +XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_DMA_NS_DEVICE_ID, + XPAR_PS7_DMA_NS_BASEADDR + }, + { + XPAR_PS7_DMA_S_DEVICE_ID, + XPAR_PS7_DMA_S_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/dmaps/src/xdmaps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/dmaps/src/xdmaps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_9/src/xdmaps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_bd.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bd.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_bd.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bd.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_bdring.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_bdring.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_bdring.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_bdring.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_bdring.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_control.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_control.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_control.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_control.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c new file mode 100644 index 0000000..07a1fe9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_g.c @@ -0,0 +1,38 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xemacps.h" + +/* +* The configuration table for devices +*/ + +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_ETHERNET_0_DEVICE_ID, + XPAR_PS7_ETHERNET_0_BASEADDR, + XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT, + XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0, + XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1, + XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0, + XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1, + XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0, + XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/emacps/src/xemacps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/emacps/src/xemacps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/emacps_v3_19/src/xemacps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c new file mode 100644 index 0000000..abe5fe0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xgpiops.h" + +/* +* The configuration table for devices +*/ + +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_GPIO_0_DEVICE_ID, + XPAR_PS7_GPIO_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/gpiops/src/xgpiops_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/gpiops/src/xgpiops_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_12/src/xgpiops_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c new file mode 100644 index 0000000..ae3635a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_g.c @@ -0,0 +1,33 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xqspips.h" + +/* +* The configuration table for devices +*/ + +XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_QSPI_0_DEVICE_ID, + XPAR_PS7_QSPI_0_BASEADDR, + XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ, + XPAR_PS7_QSPI_0_QSPI_MODE + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/qspips/src/xqspips_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_options.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_options.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_options.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_options.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/qspips/src/xqspips_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_11/src/xqspips_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c new file mode 100644 index 0000000..a2acc53 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_g.c @@ -0,0 +1,33 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xscugic.h" + +/* +* The configuration table for devices +*/ + +XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = +{ + { + XPAR_PS7_SCUGIC_0_DEVICE_ID, + XPAR_PS7_SCUGIC_0_BASEADDR, + XPAR_PS7_SCUGIC_0_DIST_BASEADDR, + {{0}} /**< Initialize the HandlerTable to 0 */ + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scugic/src/xscugic_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scugic/src/xscugic_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_2/src/xscugic_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/Makefile similarity index 73% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/Makefile index a8b0f07..eb496ea 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/Makefile +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/Makefile @@ -29,7 +29,7 @@ $(RELEASEDIR)%.o: %.c ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@ .PHONY: include -include: $(addprefix $(INCLUDEDIR),$(wildcard xbasic_types.h) $(wildcard xenv.h) $(wildcard xenv_none.h) $(wildcard xenv_standalone.h) $(wildcard xenv_vxworks.h) $(wildcard xstatus.h) $(wildcard xutil.h) $(wildcard xversion.h) $(wildcard xdebug.h)) +include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(INCLUDEDIR)%.h: %.h $(CP) $< $@ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/xscutimer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/xscutimer.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c new file mode 100644 index 0000000..68cb0c6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xscutimer.h" + +/* +* The configuration table for devices +*/ + +XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] = +{ + { + XPAR_PS7_SCUTIMER_0_DEVICE_ID, + XPAR_PS7_SCUTIMER_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scutimer/src/xscutimer_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/xscutimer_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/xscutimer_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/xscutimer_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scutimer/src/xscutimer_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_5/src/xscutimer_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/CMakeLists.txt old mode 100755 new mode 100644 similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile similarity index 73% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile index a8b0f07..eb496ea 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/Makefile +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile @@ -29,7 +29,7 @@ $(RELEASEDIR)%.o: %.c ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@ .PHONY: include -include: $(addprefix $(INCLUDEDIR),$(wildcard xbasic_types.h) $(wildcard xenv.h) $(wildcard xenv_none.h) $(wildcard xenv_standalone.h) $(wildcard xenv_vxworks.h) $(wildcard xstatus.h) $(wildcard xutil.h) $(wildcard xversion.h) $(wildcard xdebug.h)) +include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(INCLUDEDIR)%.h: %.h $(CP) $< $@ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/xscuwdt.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/xscuwdt.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c new file mode 100644 index 0000000..f4313f9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xscuwdt.h" + +/* +* The configuration table for devices +*/ + +XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] = +{ + { + XPAR_PS7_SCUWDT_0_DEVICE_ID, + XPAR_PS7_SCUWDT_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/scuwdt/src/xscuwdt_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/xscuwdt_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/xscuwdt_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/xscuwdt_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/scuwdt/src/xscuwdt_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/Makefile new file mode 100644 index 0000000..5feeb49 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/Makefile @@ -0,0 +1,39 @@ +DRIVER_LIB_VERSION = 1.0 +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib/ +INCLUDEDIR=../../../include/ +INCLUDES=-I./. -I$(INCLUDEDIR) + +SRCFILES:=$(wildcard *.c) + +OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c)))) + +libs: $(OBJECTS) + +DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d) + +include $(wildcard $(DEPFILES)) + +include $(wildcard ../../../../dep.mk) + +$(RELEASEDIR)%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@ + +.PHONY: include +include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) + +$(INCLUDEDIR)%.h: %.h + $(CP) $< $@ + +clean: + rm -rf ${OBJECTS} + rm -rf $(DEPFILES) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_card.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_card.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_card.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_card.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_core.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_core.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_core.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_core.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c new file mode 100644 index 0000000..e3e0812 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_g.c @@ -0,0 +1,45 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xsdps.h" + +/* +* The configuration table for devices +*/ + +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_SD_0_DEVICE_ID, + XPAR_PS7_SD_0_BASEADDR, + XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ, + XPAR_PS7_SD_0_HAS_CD, + XPAR_PS7_SD_0_HAS_WP, + XPAR_PS7_SD_0_BUS_WIDTH, + XPAR_PS7_SD_0_MIO_BANK, + XPAR_PS7_SD_0_HAS_EMIO, + XPAR_PS7_SD_0_SLOT_TYPE, + XPAR_PS7_SD_0_IS_CACHE_COHERENT, + XPAR_PS7_SD_0_CLK_50_SDR_ITAP_DLY, + XPAR_PS7_SD_0_CLK_50_SDR_OTAP_DLY, + XPAR_PS7_SD_0_CLK_50_DDR_ITAP_DLY, + XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY, + XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY, + XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_host.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_host.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_host.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_host.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/sdps/src/xsdps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_options.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_options.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_options.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_options.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/sdps/src/xsdps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/sdps_v4_2/src/xsdps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/CMakeLists.txt new file mode 100644 index 0000000..b692cb2 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: MIT +# Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. +if(NOT "${CMAKE_SYSTEM_NAME}" STREQUAL "FreeRTOS") +collect (PROJECT_LIB_SOURCES asm_vectors.S) +endif() +collect (PROJECT_LIB_SOURCES translation_table.S) +collect (PROJECT_LIB_SOURCES boot.S) +collect (PROJECT_LIB_SOURCES cpu_init.S) +collect (PROJECT_LIB_SOURCES xil-crt0.S) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/Makefile new file mode 100644 index 0000000..d90ef88 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/Makefile @@ -0,0 +1,83 @@ +############################################################################### +# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved. +# SPDX-License-Identifier: MIT +############################################################################### +DRIVER_LIB_VERSION = v1.0 + +include config.make + +CC=$(COMPILER) +AR=$(ARCHIVER) +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + +ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc) +ECC_FLAGS += -nostartfiles\ + -march=armv7-a \ + -mfloat-abi=soft \ + -mfpu=neon +endif + +ifeq (($(notdir $(CC))) , arm-none-eabi-gcc) +ECC_FLAGS += -nostartfiles +endif + +RELEASEDIR=../../../lib/ +INCLUDEDIR=../../../include/ +INCLUDES=-I./. -I${INCLUDEDIR} + +SRCFILES:=$(wildcard *.c) + +ASSEMBLY_SRCFILES:=$(wildcard *.S) + +OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c)))) + +ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S)))) + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS) + +DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d) + +include $(wildcard $(DEPFILES)) + +ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d) + +include $(wildcard $(ASSEMBLY_DEPFILES)) + +include $(wildcard ../../../../dep.mk) + +$(RELEASEDIR)%.o: %.S + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $< + +$(RELEASEDIR)%.o: %.c + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $< + +profile_libs: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs + +.PHONY: include +include: standalone_includes profile_includes + +standalone_includes: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) + +$(INCLUDEDIR)%.h: %.h + $(CP) $< $@ + +profile_includes: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include + +clean: + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS} + rm -rf $(DEPFILES) + rm -rf $(ASSEMBLY_DEPFILES) + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_exit.c new file mode 100644 index 0000000..4c55bbd --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_exit.c @@ -0,0 +1,18 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) { + ; + } +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_open.c new file mode 100644 index 0000000..df9d192 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_open.c @@ -0,0 +1,32 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#ifndef UNDEFINE_FILE_OPS +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); + +#ifdef __cplusplus +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_sbrk.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_sbrk.c new file mode 100644 index 0000000..c3010ea --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/_sbrk.c @@ -0,0 +1,43 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { + heap += incr; + Status = (caddr_t) ((void *)prev_heap); + } else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/abort.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/abort.c new file mode 100644 index 0000000..4c9faef --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/abort.c @@ -0,0 +1,16 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/asm_vectors.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/asm_vectors.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/asm_vectors.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/asm_vectors.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/boot.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/boot.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/boot.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/boot.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/cpu_init.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/cpu_init.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/cpu_init.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/cpu_init.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/xil-crt0.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/xil-crt0.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/gcc/xil-crt0.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/gcc/xil-crt0.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/32bit/platform/ZynqMP/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/32bit/platform/ZynqMP/xparameters_ps.h similarity index 100% rename from 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--git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/xarmv8.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/xarmv8.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/xarmv8.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/xarmv8.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/xarmv8_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/xarmv8_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/ARMv8/xarmv8_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/ARMv8/xarmv8_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_close.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_close.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_close.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_close.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_exit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_exit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_exit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_iserror.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_iserror.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_iserror.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_iserror.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_istty.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_istty.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_istty.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_istty.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_open.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_open.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_open.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_read.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_read.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_read.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_read.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_time.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_time.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_time.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_write.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_write.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/armclang/_sys_write.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/armclang/_sys_write.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/gcc/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_exit.c new file mode 100644 index 0000000..4c55bbd --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_exit.c @@ -0,0 +1,18 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +/* _exit - Simple implementation. Does not return. +*/ +__attribute__((weak)) void _exit (sint32 status) +{ + (void)status; + while (1) { + ; + } +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_open.c new file mode 100644 index 0000000..df9d192 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_open.c @@ -0,0 +1,32 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#ifndef UNDEFINE_FILE_OPS +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode); + +#ifdef __cplusplus +} +#endif + +/* + * _open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) +{ + (void)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_sbrk.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_sbrk.c new file mode 100644 index 0000000..c3010ea --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/_sbrk.c @@ -0,0 +1,43 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +extern u8 _heap_start[]; +extern u8 _heap_end[]; + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) caddr_t _sbrk ( s32 incr ) +{ + static u8 *heap = NULL; + u8 *prev_heap; + static u8 *HeapEndPtr = (u8 *)&_heap_end; + caddr_t Status; + + if (heap == NULL) { + heap = (u8 *)&_heap_start; + } + prev_heap = heap; + + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { + heap += incr; + Status = (caddr_t) ((void *)prev_heap); + } else { + Status = (caddr_t) -1; + } + + return Status; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/abort.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/abort.c new file mode 100644 index 0000000..4c9faef --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/abort.c @@ -0,0 +1,16 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include + +/* + * abort -- go out via exit... + */ +__attribute__((weak)) void abort(void) +{ + _exit(1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/close.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/close.c new file mode 100644 index 0000000..50f10a0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/close.c @@ -0,0 +1,27 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#ifndef UNDEFINE_FILE_OPS +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _close(s32 fd); + +#ifdef __cplusplus +} +#endif + +/* + * close -- We don't need to do anything, but pretend we did. + */ + +__attribute__((weak)) s32 _close(s32 fd) +{ + (void)fd; + return (0); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/cpputest_time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/cpputest_time.c new file mode 100644 index 0000000..77ea3bc --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/cpputest_time.c @@ -0,0 +1,31 @@ +/****************************************************************************** +* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#ifndef UNDEFINE_FILE_OPS +#include +#include "xil_types.h" +#include +struct tms* tms; +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) clock_t _times(struct tms* tms); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) clock_t _times(struct tms* tms) +{ + (void)tms; + + errno = EIO; + return (-1); +} + + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/errno.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/errno.c new file mode 100644 index 0000000..3d12021 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/errno.c @@ -0,0 +1,29 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 * __errno (void); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) sint32 * +__errno (void) +{ + return &_REENT->_errno; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fcntl.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fcntl.c new file mode 100644 index 0000000..40e2729 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fcntl.c @@ -0,0 +1,22 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, LONG arg); + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, LONG arg) +{ + (void)fd; + (void)cmd; + (void)arg; + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fstat.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fstat.c new file mode 100644 index 0000000..0faffb8 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/fstat.c @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); + +#ifdef __cplusplus +} +#endif +/* + * fstat -- Since we have no file system, we just return an error. + */ +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) +{ + (void)fd; + buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ + + return (0); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getentropy.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getentropy.c new file mode 100644 index 0000000..344325c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getentropy.c @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 getentropy(void *buffer, sint32 length); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) sint32 getentropy(void *buffer, sint32 length) +{ + (void)buffer; + (void)length; + + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getpid.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getpid.c new file mode 100644 index 0000000..c657e1c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/getpid.c @@ -0,0 +1,30 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include "xil_types.h" +/* + * getpid -- only one process, so just return 1. + */ +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _getpid(void); +__attribute__((weak)) s32 getpid(void); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) s32 getpid(void) +{ + return 1; +} + +__attribute__((weak)) s32 _getpid(void) +{ + return 1; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/isatty.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/isatty.c new file mode 100644 index 0000000..a513bf6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/isatty.c @@ -0,0 +1,34 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 _isatty(sint32 fd); + +#ifdef __cplusplus +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/kill.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/kill.c new file mode 100644 index 0000000..5181c02 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/kill.c @@ -0,0 +1,38 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _kill(pid_t pid, s32 sig); + +#ifdef __cplusplus +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) int kill(pid_t pid, int sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) s32 _kill(pid_t pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/lseek.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/lseek.c new file mode 100644 index 0000000..7b2c126 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/lseek.c @@ -0,0 +1,40 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence); + +#ifdef __cplusplus +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/open.c new file mode 100644 index 0000000..c5a33d7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/open.c @@ -0,0 +1,31 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#ifndef UNDEFINE_FILE_OPS +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); + +#ifdef __cplusplus +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) +{ + (void)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/read.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/read.c new file mode 100644 index 0000000..decf665 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/read.c @@ -0,0 +1,87 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/* read.c -- read bytes from a input device. + */ +#ifndef UNDEFINE_FILE_OPS +#include "xil_printf.h" +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +__attribute__((weak)) s32 read (s32 fd, char8* buf, s32 nbytes); + +#ifdef __cplusplus +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#if defined (STDIN_BASEADDRESS) || defined(SDT) + s32 i; + s32 numbytes = 0; + char8* LocalBuf = buf; + + (void)fd; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + LocalBuf[i] = inbyte(); + if ((LocalBuf[i] == '\n' )|| (LocalBuf[i] == '\r')) { + break; + } + } + } + + return numbytes; +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#if defined(STDIN_BASEADDRESS) || defined(SDT) + s32 i; + s32 numbytes = 0; + char8* LocalBuf = buf; + + (void)fd; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + LocalBuf[i] = inbyte(); + if ((LocalBuf[i] == '\n' )|| (LocalBuf[i] == '\r')) { + break; + } + } + } + + return numbytes; +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/sbrk.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/sbrk.c new file mode 100644 index 0000000..fd00c99 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/sbrk.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) char8 *sbrk (s32 nbytes); + +#ifdef __cplusplus +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if((heap_ptr != NULL) && ((heap_ptr + nbytes) <= ((char8 *)&HeapLimit + 1))) { + heap_ptr += nbytes; + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/time.c new file mode 100644 index 0000000..541b0e3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/time.c @@ -0,0 +1,27 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) clock_t clock(void); + +#ifdef __cplusplus +} +#endif +/* + * clock -- It supposed to return processor time. We are not implementing + * this function, as timekeeping is tightly coupled with system, hence + * always returning 0. Users can override this with their system + * specific implementation. + * + */ +__attribute__((weak)) clock_t clock(void) +{ + return (0); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/unlink.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/unlink.c new file mode 100644 index 0000000..5092095 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/unlink.c @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 unlink(char8 *path); + +#ifdef __cplusplus +} +#endif +/* + * unlink -- since we have no file system, + * we just return an error. + */ +__attribute__((weak)) sint32 unlink(char8 *path) +{ + (void) path; + errno = EIO; + return (-1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/write.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/write.c new file mode 100644 index 0000000..279a0cd --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/write.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/* write.c -- write bytes to an output device. + */ +#ifndef UNDEFINE_FILE_OPS +#include "xil_printf.h" +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes); +__attribute__((weak)) sint32 write (sint32 fd, char8* buf, sint32 nbytes); + +#ifdef __cplusplus +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +__attribute__((weak)) sint32 +write (sint32 fd, char8* buf, sint32 nbytes) + +{ +#if defined(STDOUT_BASEADDRESS) || defined(SDT) + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) sint32 +_write (sint32 fd, char8* buf, sint32 nbytes) +{ +#if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE) + sint32 length; + + (void)fd; + (void)nbytes; + length = XPVXenConsole_Write(buf); + return length; +#else +#if defined(STDOUT_BASEADDRESS) || defined(SDT) + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +#endif +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/gcc/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/abort.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/abort.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/abort.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/abort.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/clock.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/clock.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/clock.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/clock.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/close.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/close.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/close.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/close.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/exit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/exit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/exit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/low_level_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/low_level_init.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/low_level_init.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/low_level_init.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/lseek.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/lseek.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/lseek.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/lseek.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/open.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/open.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/open.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/read.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/read.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/read.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/read.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/remove.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/remove.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/remove.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/remove.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/write.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/write.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/write.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/write.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/xpseudo_asm_iccarm.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/xpseudo_asm_iccarm.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/xpseudo_asm_iccarm.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/xpseudo_asm_iccarm.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/xpseudo_asm_iccarm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/xpseudo_asm_iccarm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/common/iccarm/xpseudo_asm_iccarm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/iccarm/xpseudo_asm_iccarm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/putnum.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/putnum.c new file mode 100644 index 0000000..3582ffe --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/putnum.c @@ -0,0 +1,56 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + *****************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_printf.h" + +/************************** Function Prototypes ******************************/ +void putnum(u32 num); + +/*****************************************************************************/ +/** +* putnum -- print a 32 bit number in hex +* +******************************************************************************/ +void putnum(u32 num) +{ + char8 buf[9]; + s32 cnt, val=7; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 0 ; cnt <= 7 ; cnt++) { + digit = (num >> ((u32)val * 4U)) & 0x0000000fU; + + if (digit <= 9U) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } + val--; + } + + print (buf); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/vectors.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/vectors.c new file mode 100644 index 0000000..91ddaa9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/vectors.c @@ -0,0 +1,166 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex A9 core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
+* 8.0	sk   03/02/22 Move XExc_VectorTableEntry structure to xil_exception.h
+* 		      header file to fix misra_c_2012_rule_5_6 violation.
+* 8.0	sk   03/02/22 Move XExc_VectorTableEntry declaration to xil_exception.h
+* 		      header file to fix misra_c_2012_rule_8_4 violation.
+*
    +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +#if !defined (__aarch64__) +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Undefined exception called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void UndefinedException(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_UNDEFINED_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SW Interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void SWInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SWI_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the DataAbort Interrupt called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void DataAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the PrefetchAbort Interrupt called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void PrefetchAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); +} +#else + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void SynchronousInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SYNC_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SError Interrupt called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void SErrorInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data); +} + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/vectors.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/vectors.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/vectors.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_exception.c new file mode 100644 index 0000000..e08ecb9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_exception.c @@ -0,0 +1,863 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex A53,A9,R5 exception +* Handler. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
+* 6.7   mna      26/04/18 Add an API to obtain a corresponding
+*                         Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7  asa       18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+* 7.0  mus       07/03/19 Tweak Xil_ExceptionRegisterHandler and
+*                         Xil_GetExceptionRegisterHandler to support legacy
+*                         examples for Cortexa72 EL3 exception level.
+* 7.3  mus       07/27/20 Updated Xil_ExceptionRegisterHandler and
+*                         Xil_GetExceptionRegisterHandler to ignore
+*                         Exception_id, only if its pointing to IRQ.
+*                         It fixes CR#1069524
+* 8.0  mus       02/24/22 Updated Xil_ExceptionRegisterHandler and
+*                         Xil_GetExceptionRegisterHandler to support legacy
+*                         driver examples for CortexR52. This is needed, as
+*                         by default scugic driver configures interrupts as
+*                         group0, and CortexR52 GIC triggers FIQ for group0
+*                         interrupts.
+* 8.0  sk	 03/02/22 Move XExc_VectorTableEntry structure to header
+* 			  file to fix misra_c_2012_rule_5_6 violation.
+* 8.1  asa       02/12/23 Updated data abort and prefetch abort fault
+*                         status reporting for ARMv7.
+*			  Updated Sync and SError fault status reporting
+*			  for ARMv8.
+* 9.0  ml        03/03/23 Add description to fix doxygen warnings.
+* 9.0  ml	 14/04/23 Add comment to default case in switch statement to fix
+*                         misra-c violation.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +#include "bspconfig.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ +#ifdef DEBUG +#if defined (__aarch64__) +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u64 FaultStatus); +static void DecodeSyncAbortWithIss(u32 Type, u64 IssVal); +static void DecodeSErrorWithIss(u64 IssVal); +#else +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u32 FaultStatus); +#endif +#endif +/************************** Function Prototypes *****************************/ +static void Xil_ExceptionNullHandler(void *Data); +#if defined (__aarch64__) +static void Xil_SyncErrorHandler(void *CallBackRef); +static void Xil_SErrorHandler(void *CallBackRef); +#else +static void Xil_DataAbortHandler(void *CallBackRef); +static void Xil_PrefetchAbortHandler(void *CallBackRef); +static void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +#if defined (__aarch64__) +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_SyncErrorHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_SErrorHandler, NULL}, + +}; +#else +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_UndefinedExceptionHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_PrefetchAbortHandler, NULL}, + {Xil_DataAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, +}; +#endif /* #if defined (__aarch64__) */ +#if !defined (__aarch64__) +u32 DataAbortAddr; /* Address of instruction causing data abort */ +u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ +u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined + exception */ +#endif + +/*****************************************************************************/ + +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void) Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* @brief The function is a common API used to initialize exception handlers +* across all supported arm processors. For ARM Cortex-A53, Cortex-R5, +* and Cortex-A9, the exception handlers are being initialized +* statically and this function does not do anything. +* However, it is still present to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to +* initialize exception handlers). +* +* @return None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* @brief Register a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. +* +* @param Exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ +#if (defined (versal) && !defined(ARMR5) && EL3) + if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id ) + { + /* + * Cortexa72 processor in versal is coupled with GIC-500, and + * GIC-500 supports only FIQ at EL3. Hence, tweaking this API + * to act on IRQ, if Exception_id is pointing to IRQ + */ + Exception_id = XIL_EXCEPTION_ID_FIQ_INT; + } +#endif + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* @brief Get a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. +* +* @param Exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +****************************************************************************/ +void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, + void **Data) +{ +#if (defined (versal) && !defined(ARMR5) && EL3) + if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id ) + { + /* + * Cortexa72 processor in versal is coupled with GIC-500, and + * GIC-500 supports only FIQ at EL3. Hence, tweaking this API + * to act on IRQ, if Exception_id is pointing to IRQ + */ + + Exception_id = XIL_EXCEPTION_ID_FIQ_INT; + } +#endif + + *Handler = XExc_VectorTable[Exception_id].Handler; + *Data = XExc_VectorTable[Exception_id].Data; +} + +/*****************************************************************************/ +/** +* +* @brief Removes the Handler for a specific exception id. The stub Handler +* is then registered for this exception id. +* +* @param Exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* +* @return None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} + +#if defined (__aarch64__) +/*****************************************************************************/ +/** +* +* Default Synchronous abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @return None. +* +****************************************************************************/ + +static void Xil_SyncErrorHandler(void *CallBackRef){ + (void) CallBackRef; + +#ifdef __GNUC__ +#ifdef DEBUG + volatile u64 EsrVal; + volatile u64 ElrVal; + volatile u64 FarVal; + u32 Far_Status; +#if (EL3 == 1) + EsrVal = mfesrel3(); + ElrVal = mfelrel3(); +#else + EsrVal = mfesrel1(); + ElrVal = mfelrel1(); +#endif + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + Far_Status = NotifyFaultStatusDetails(ARMV8_SYNC_ERROR, EsrVal); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Instruction causing Sync error is: 0x%lx\n", ElrVal); + if (Far_Status) { +#if (EL3 == 1) + FarVal = mffarel3(); +#else + FarVal = mffarel1(); +#endif + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Memory whose access caused the Sync Error is: 0x%lx\n", + FarVal); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#endif +#else + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous Error \n"); +#endif + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default SError abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @return None. +* +****************************************************************************/ +static void Xil_SErrorHandler(void *CallBackRef){ + (void) CallBackRef; + +#ifdef __GNUC__ +#ifdef DEBUG + volatile u64 EsrVal; +#if (EL3 == 1) + EsrVal = mfesrel3(); +#else + EsrVal = mfesrel1(); +#endif + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + (void)NotifyFaultStatusDetails(ARMV8_SERROR, EsrVal); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#endif +#else + xdbg_printf(XDBG_DEBUG_ERROR, "Asynchronous SError \n"); +#endif + + while(1) { + ; + } +} + +#if defined (__aarch64__) +#ifdef DEBUG +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u64 EsrVal) +{ + u32 Far_Status = 0x0; + u64 EcVal = ARMV8_EXTRACT_ESR_EC(EsrVal); + u64 IssVal = ARMV8_EXTRACT_ESR_ISS(EsrVal); + + if (Fault_Type == ARMV8_SYNC_ERROR) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Sync Error with ESR = 0x%lx, EC = 0x%lx, ISS = 0x%lx \n", + EsrVal, EcVal, IssVal); + + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Type based on Exception Class (EC val) : "); + switch (EcVal) { + case ARMV8_ESR_EC_UNKNOWN_ERR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Unknown Error\n"); + break; + case ARMV8_ESR_EC_FP_ASIMD: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access to ASIMD or floating point functionality based " + "on CPACR_EL1 FPEN configuration\n"); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_DATA_ABORT_LOWER: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Data Abort From a Lower " + "Exception Level\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_DATA_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_DATA_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Data Abort \n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_DATA_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_INS_ABORT_LOWER: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Instruction Abort Taken From a Lower Exception Level\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_INS_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_INS_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Instruction Abort\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_INS_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_PC_ALIGNMENT_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "PC Alignment Fault\n"); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_SP_ALIGNMENT_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "SP Alignment Fault\n"); + break; + case ARMV8_ESR_ILL_EXECUTION_STATE: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Illegal Execution State\n"); + break; + default: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Other error\n"); + break; + } + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Asynchronous SError with ESR = 0x%lx, EC = 0x%lx, ISS = 0x%lx \n", + EsrVal, EcVal, IssVal); + + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details (based on Instruction Specific Syndrome " + "(ISS val) : "); + + DecodeSErrorWithIss(IssVal); + } + return Far_Status; +} + +static void DecodeSyncAbortWithIss(u32 Type, u64 IssVal) +{ + u64 FscVal; + + FscVal = IssVal & ARMV8_ESR_ISS_FSC; + switch (FscVal) { + case ARMV8_LEVEL_0_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 3 translation \n"); + break; + case ARMV8_LEVEL_0_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 3 translation \n"); + break; + case ARMV8_LEVEL_0_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 3 translation \n"); + break; + case ARMV8_LEVEL_0_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 3 translation \n"); + break; + + case ARMV8_SYNC_EXT_ABORT_NOT_ON_TTW: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort, not on translation table walk or " + "hw update of translation table \n"); + break; + case ARMV8_LEVEL_0_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 0 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_LEVEL_1_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 1 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_LEVEL_2_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 2 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_LEVEL_3_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 3 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_SYNC_PAR_OR_ECC_ERROR_NOT_ON_TTW: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "not on translation table walk \n"); + break; + case ARMV8_LEVEL_0_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 0 translation \n"); + break; + case ARMV8_LEVEL_1_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 1 translation \n"); + break; + case ARMV8_LEVEL_2_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 2 translation \n"); + break; + case ARMV8_LEVEL_3_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 3 translation \n"); + break; + case ARMV8_ALIGNMENT_FAULT: + if (Type == ARMV8_ESR_EC_DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Alignment Fault \n"); + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Unknown fault \n"); + } + break; + case ARMV8_TLB_CONFLICT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "TLB Conflict Abort \n"); + break; + default: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Unknown fault \n"); + } + + if (Type == ARMV8_ESR_EC_DATA_ABORT) { + if (IssVal & ARMV8_ESR_ISS_WNR_MASK) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data abort caused by instruction writing to a memory location.\n "); + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data abort caused by instruction reading from a memory location.\n"); + } + if (IssVal & ARMV8_ESR_ISS_CM_MASK) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data abort caused by a cache maintenance instruction \n"); + } + } +} + +static void DecodeSErrorWithIss(u64 IssVal) +{ + u64 FscVal; + u64 MaskVal; + + FscVal = IssVal & ARMV8_ESR_ISS_FSC; + if (FscVal == ARMV8_ASYNC_SEEROR_INTERRUPT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "SError caused by Asynchronous Serror Interrupt \n "); + + MaskVal = IssVal & ARMV8_ESR_ISS_AET_MASK; + switch (MaskVal) { + case ARMV8_ESR_ISS_AET_UC: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Uncontainable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_UEU: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Unrecoverable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_UEO: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Restartable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_UER: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Recoverable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_CE: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Corrected Error State \n "); + break; + default: + break; + + } + + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "SError caused by uncategorized error \n "); + } +} + + +#endif /* #ifdef DEBUG */ +#endif /* #if defined (__aarch64__) */ + +#else /* #if defined (__aarch64__) */ +/*****************************************************************************/ +/** +* +* Default Data abort handler which prints data fault status register through +* which information about data fault can be acquired +* +* @return None. +* +****************************************************************************/ + +static void Xil_DataAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + u32 FaultStatus; +#ifdef __GNUC__ + u32 DataAbortMemAddr; + u32 DfarStatus; +#endif + +#ifdef __GNUC__ + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); +#else + { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); + FaultStatus = Reg; } +#endif /* #ifdef __GNUC__ */ + +#ifdef __GNUC__ + DfarStatus = NotifyFaultStatusDetails(DATA_ABORT, FaultStatus); + if (DfarStatus) { + DataAbortMemAddr = mfcp(XREG_CP15_DATA_FAULT_ADDRESS); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Instruction causing data abort is: 0x%lx\n", + DataAbortAddr); + if (DfarStatus) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Memory whose access caused the data abort is: 0x%lx\n", + DataAbortMemAddr); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#else + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr); +#endif +#endif /* #ifdef DEBUG */ + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default Prefetch abort handler which prints prefetch fault status register through +* which information about instruction prefetch fault can be acquired +* +* @return None. +* +****************************************************************************/ +static void Xil_PrefetchAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + u32 FaultStatus; +#ifdef __GNUC__ + u32 IfarStatus; +#endif + +#ifdef __GNUC__ + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); +#else + { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); + FaultStatus = Reg; } +#endif /* #ifdef __GNUC__ */ + +#ifdef __GNUC__ + IfarStatus = NotifyFaultStatusDetails(INS_PREFETCH_ABORT, FaultStatus); + if (IfarStatus) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Instruction Causing Prefetch Abort is: 0x%lx\n", + PrefetchAbortAddr); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#else + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr); +#endif +#endif /* #ifdef DEBUG */ + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default undefined exception handler which prints address of the undefined +* instruction if debug prints are enabled +* +* @return None. +* +****************************************************************************/ +static void Xil_UndefinedExceptionHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of the undefined instruction 0x%lx\n", + UndefinedExceptionAddr); +#endif + while(1) { + ; + } +} + +#ifdef DEBUG +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u32 FaultStatus) +{ + u32 Far_Status = 0x0; + + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data Abort with Fault Status Register (DFSR) = 0x%lx\n", + FaultStatus); + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Instruction Prefetch Abort with Fault Status Register (IFSR) = 0x%lx\n", + FaultStatus); + } + + /* Extract bit 10 and bits 3:0 to form the 5 bit error identifier */ + + FaultStatus = EXTRACT_BITS_10_AND_3_TO_0(FaultStatus); + + switch (FaultStatus) { +#if defined(ARMR5) + case ARMV7_BACKGROUND_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Background Fault\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + case ARMV7_ALIGNMENT_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Alignment Fault\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; + case ARMV7_DEBUG_EVENT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Debug Event\n"); + break; +#if !defined(ARMR5) + case ARMV7_ACCESS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Debug Event\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; + case ARMV7_ICACHE_MAINTENANCE_FAULT: + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Fault on Instruction Cache Maintenance\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + } + break; + case ARMV7_TRANSLATION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Translation Fault\n"); + break; + case ARMV7_DOMAIN_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Domain Fault\n"); + break; + case ARMV7_SYNC_ABORT_TRANSTAB_WALK: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort on Translation Table Walk\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + case ARMV7_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Permission Fault\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#if !defined(ARMR5) + case ARMV7_TLB_CONFLICT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "TLB Conflict Abort\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + case ARMV7_ASYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Asynchronous External Abort\n"); + break; + case ARMV7_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Synchronous External Abort\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; + case ARMV7_MEM_ACS_SYNC_PAR_ERR: + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity Error on Memory Access\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + } + break; + case ARMV7_MEM_ACS_ASYNC_PAR_ERR: + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Asynchronous Parity Error on Memory Access\n"); + } + break; +#if !defined(ARMR5) + case ARMV7_SYNCPAR_ERR_TRANSTAB_WALK: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity Error on Translation Table Walk\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + default: + /* if above cases doesn't match, then + default case will execute and terminate a statement sequence */ + break; + } + + return Far_Status; +} +#endif /* #ifdef DEBUG */ +#endif /* #if defined (__aarch64__) */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.c new file mode 100644 index 0000000..2d3df6c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.c @@ -0,0 +1,152 @@ +/****************************************************************************** +* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.c +* +* This file provides the common helper routines for the sleep API's +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 6.6   srm  04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+* 7.0   mus  03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
+*                     space access, if processor is nonsecure and IOU slcr
+*                     address space is secure. CR#1015725.
+* 7.7	sk   01/10/22 Update values from signed to unsigned to fix
+* 		      misra_c_2012_rule_10_4 violation.
+* 7.7	sk   01/10/22 Add explicit parentheses for EL3==1 to fix
+* 		      misra_c_2012_rule_12_1 violation.
+* 7.7	sk   01/10/22 Add void argument to XTime_StartTTCTimer function to
+* 		      fix misra_c_2012_rule_8_2 violation.
+* 7.7	sk   01/10/22 Add braces for the if statement to make it a compound
+* 		      statement and fix misra_c_2012_rule_15_6 violation.
+*
+*
    +*****************************************************************************/ + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xil_sleeptimer.h" +#include "xtime_l.h" + +/**************************** Constant Definitions *************************/ + + +/* Function definitions are applicable only when TTC3 is present*/ +#if defined (SLEEP_TIMER_BASEADDR) +/****************************************************************************/ +/** +* +* This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec +* +* @param delay - delay time in seconds/micro seconds +* +* @param frequency - Number of counts per second/micro second +* +* @return none +* +* @note none +* +*****************************************************************************/ +void Xil_SleepTTCCommon(u32 delay, u64 frequency) +{ + u64 tEnd = 0U; + u64 tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + + TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency); + do + { + TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (u64)TimeLowVal2; + }while (tCur < tEnd); +} + + +/*****************************************************************************/ +/** +* +* This API starts the Triple Timer Counter +* +* @param none +* +* @return none +* +* @note none +* +*****************************************************************************/ +void XTime_StartTTCTimer(void) +{ + u32 TimerPrescalar; + u32 TimerCntrl; + +#if (defined (__aarch64__) && (EL3==1)) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32) + u32 LpdRst; + +#if defined (versal) + u32 RstAddr = CRL_TTC_RST; + u32 RstMask = CRL_TTC_BASE_RST_MASK << XSLEEP_TTC_INSTANCE; +#else + u32 RstAddr = RST_LPD_IOU2; + u32 RstMask = RST_LPD_IOU2_TTC_BASE_RESET_MASK << XSLEEP_TTC_INSTANCE; +#endif + /* check if the timer is reset */ + LpdRst = XSleep_ReadCounterVal(RstAddr); + if ((LpdRst & RstMask) != 0U ) { + LpdRst = LpdRst & (~RstMask); + Xil_Out32(RstAddr, LpdRst); + } else { +#endif + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + /* check if Timer is disabled */ + if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0U) { + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + /* check if Timer is configured with proper functionalty for sleep */ + if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0U) { + return; + } + } +#if (defined (__aarch64__) && (EL3==1)) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32) + } +#endif + /* Disable the timer to configure */ + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK; + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); + /* Disable the prescalar */ + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET, + TimerPrescalar); + /* Enable the Timer */ + TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.h new file mode 100644 index 0000000..adcb7e6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_sleeptimer.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 7.0   mus  01/07/19 Add cpp extern macro
+* 7.7	sk   01/10/22 Add explicit parentheses for EL3==1 to fix
+* 		      misra_c_2012_rule_12_1 violation.
+* 7.7	sk   01/10/22 Add void to XTime_StartTTCTimer function declaration
+* 		      to fix misra_c_2012_rule_8_2 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
    +*****************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && (EL3==1)) || defined (ARMA53_32) +#if defined (versal) +#define CRL_TTC_RST 0xFF5E0344U +#define CRL_TTC_BASE_RST_MASK 0x1U +#else +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ +/** + *@endcond + */ +/************************** Function Prototypes ******************************/ + +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ +void Xil_SleepTTCCommon(u32 delay, u64 frequency); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_SLEEPTIMER_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_spinlock.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_spinlock.c new file mode 100644 index 0000000..e1b5240 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_spinlock.c @@ -0,0 +1,368 @@ +/****************************************************************************** +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_spinlock.c +* +* Implements a spinlocking mechanism using ARM load-exclusive and +* store-exclusive instructions. +* +* spinlocks in baremetal world are useful mainly for AMP kind of use cases +* where different applications run in different CPUs in a CPU cluster and +* they have a common resource to work with. +* A simple yet common example is: +* R5-0 and R5-1 have separate applications and at runtime they try to access a +* shared register space (GIC) or shared memory space. Mutual exclusion is +* really needed for such use cases. +* Similar use case applies for Zynq CortexA9-0 and CortesA9-1. +* +* The spinlock mechanism provided with this file is very simple to cater to +* baremetal world requirements. +* +* A) Unlike OS type of use cases, at any point of time, only a single lock +* can be used. There is no way in BM world we can support multiple locks +* at the same time. +* B) The spinlocking is available for ARM v7 (Cortex-R5 and Cortex-A9). +* C) Users need to provide a lock (essentially a shared address), and a flag +* (also a shared address) for spinlocking to work. These shared addresses +* must be agreed upon by apps running on both CPUs. Needless to say, +* the linker scripts must change accordingly so that apps running on both +* CPUs can have a shared DDR region from which address can be used for +* spinlocking. +* D) The address that is used for spinlocking and the address that is used +* as flag address must be in a memory region that is strongly-ordered +* or device memory. +* E) Like any similar standard use cases, one application running in any +* of the CPUs must create the spinlock address. It is advisable that the +* the same application must destroy or release the spinlock address, +* though nothing stops the other CPU in destroying and releasing the +* spinlock addresses. There has to be understanding between applications +* running on both the CPUs to ensure that correct ordering is followed. +* Once a spinlock is released, it spinlock APIs cannot be used anymore. +* F) Once a spinlock address is created it can be used any number of times +* to protect critical sections as long as a certain set of rules are +* followed and a certain set of sequences are followed. More about the +* sequences later in this description. +* G) To re-iterate, the spinlocking mechanism provided through this file is +* pretty rudimentary. Users can always improvise. The use case that +* the whole mechanism is trying to solve is: common register space +* being accesses in an AMP scenario by independent applications running +* at multiple CPUs. +* +* The usage of APIs provided in this file are summarized below. +* A) Applications running at both the CPUs ensure that they allocate shared +* memory space to be used for locking and flag maintenance. +* B) The memory allocated as shared should be of minimum size 1 MB. This +* limitation is because the way translation tables/memory map is setup +* for R5 or A9. In future, this limitation can be brought down 4 KB. +* C) The spinlock and the flag address must be uncached. Users need to c +* all Xilinx provided API Xil_SetTlbAttributes to mark the shared +* 1 MB memory space as strongly ordered or device memory. +* D) Both the applications must call the API Xil_InitializeSpinLock with +* the spinlock address, flag address and flag value to be used. Currently +* only one flag value is supported (i.e. XIL_SPINLOCK_ENABLE with +* a value of 1). +* Only if the Xil_InitializeSpinLock returns success, should they +* proceed to use Xil_SpinLock and Xil_SpinUnlock. +* F) Afterwards applications can start using the APIs Xil_SpinLock() and +* Xil_SpinUnlock() to protect the critical sections. +* G) It is highly suggested to use Xil_IsSpinLockEnabled() as a check +* before using Xil_SpinLock() or Xil_SpinUnlock(). Refer to the code +* snippet below. +* H) If spinlock is no more needed by an application, they can use the API +* Xil_ReleaseSpinLock(). +* I) Once a spinlock is created it can be used as many numbers of time as +* needed. +* +* A typical code snippet with R5 as an example and lock address falling +* in the 1 MB memory region (0x300000 to 0x400000) is given below. +* +* Code snippet for R5-0 (that runs first): +* int main() +* { +* u32 *sharedlockaddr = (int *)0x300008; +* u32 *sharedlockflagaddr = int *)0x30000C; +* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); +* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr, +* XIL_SPINLOCK_ENABLE); +* .... +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinLock(); +* // Critical Section +* .... +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinUnlock(); +* ..... +* ..... +* Xil_ReleaseSpinLock(); +* } // End of main +* +* * Code snippet for R5-1 (that runs second): +* int main() +* { +* u32 *sharedlockaddr = (int *)0x300008; +* u32 *sharedlockflagaddr = int *)0x30000C; +* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); +* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr, +* XIL_SPINLOCK_ENABLE); +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinLock(); +* // Critical Section +* .... +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinUnlock(); +* ..... +* ..... +* Xil_ReleaseSpinLock(); +* } // End of main +* +* Xil_SpinLock() and Xil_SpinLock() return XST_FAILURE if the spinlock +* is initialized. Instead of calling Xil_IsSpinLockEnabled before using +* Xil_SpinLock() or Xil_SpinLock(), users can also check the return +* value of Xil_SpinLock and Xil_SpinLock. If a lock is not initialized, +* Xil_SpinLock will just return failure and not perform load-exclusive +* operations. +* +* Guidelines on when to use the spinlocking mechanism in Xilinx baremetal +* environment: +* A) Spinlocking mechanism can only be used for Cortex-R5s (split mode) +* and Cortex-A9s (Zynq). +* B) In Cortex-R5 split mode or Cortex-A9 cluster, applications running on +* both the CPUs, by design should never be sharing the same peripheral. +* It is impossible to support such use cases reliably. +* Hence none of the peripheral drivers (except GIC driver) have +* spinlocking support added into their APIs. +* C) GIC register space is shared by both the CPUs (R5 split mode, A9s). +* The GIC driver APIs have spinlocking mechanism added to the relevant +* APIs. Users need to follow the guidelines stated earlier to enable +* the spinlocks and use them. +* It is really advisable to use spinlock mechanism for use cases where +* applications running on multiple CPUs can simultaneously access +* GIC register space through driver APIs. +* D) The spinlock mechanism can be used to protect any critical region +* implemented through shared memory space. +* +* IMPORTANT NOTE: Circular spinlocks are not allowed (as expected). +* Use case where an application calls Xil_SpinLock back to back without +* calling Xil_SpinUnlock in between will/may result in a deadlock +* condition. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 7.5 	asa      02/23/21 First release
+* 7.5   asa      04/28/21 Fixed bug Xil_IsSpinLockEnabled to avoid
+*                         dereferencing to address zero.
+* 7.7	sk	 01/10/22 Update values from signed to unsigned to fix
+* 			  misra_c_2012_rule_10_4 violation.
+*
    +* +******************************************************************************/ + + +/***************************** Include Files ********************************/ +#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) +#include "xil_spinlock.h" + + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + + + +/************************** Variable Definitions ****************************/ +static UINTPTR Xil_Spinlock_Addr = 0x0; +static UINTPTR Xil_Spinlock_Flag_Addr = 0x0; + +/************************** Function Prototypes *****************************/ + +/****************************************************************************/ +/** +* +* @brief Used at the beginning of a critical section. This API takes the +* lock using load-exclusive and store-exclusive operations. In +* case the lock is not available (being held by an application +* running at the other CPU and doing operations inside the +* critical section, the control will never go out from the API +* till the other CPU releases the lock. +* +* @param None. +* +* @return XST_FAILURE: If spinlock is not properly initialized. +* XST_SUCCESS: If the lock was successfully obtained. +* +* @note None. +* +*****************************************************************************/ +u32 Xil_SpinLock(void) +{ + UINTPTR lockaddr = Xil_Spinlock_Addr; + u32 LockTempVar; + + if (Xil_Spinlock_Addr == 0U) { + return XST_FAILURE; + } + + __asm__ __volatile__( + "1: ldrex %0, [%1] \n" + " teq %0, %3 \n" + " strexeq %0, %2, [%1] \n" + " teqeq %0, #0 \n" + " bne 1b \n" + " dmb \n" + : "=&r" (LockTempVar) + : "r" (lockaddr), "r"(XIL_SPINLOCK_LOCKVAL), "r"(XIL_SPINLOCK_RESETVAL) + : "cc"); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* @brief Used to release a lock previously held by calling Xil_SpinLock. +* +* @param None. +* +* @return XST_FAILURE: If spinlock is not properly initialized. +* XST_SUCCESS: If the lock was successfully obtained. +* +* @note None. +* +*****************************************************************************/ +u32 Xil_SpinUnlock(void) +{ + UINTPTR lockaddr = Xil_Spinlock_Addr; + + if (Xil_Spinlock_Addr == 0U) { + return XST_FAILURE; + } + __asm__ __volatile__( + "dmb \n" + "str %1, [%0] \n" + : + : "r" (lockaddr), "r" (XIL_SPINLOCK_RESETVAL) + : "cc"); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* @brief Used to initialize a spinlock. +* +* @param lockaddr: Address of the lock variable. The address must be in +* a shared memory region. +* lockflagaddr: Address of the flag variable. The address must be +* in a shared memory region. +* lockflag: The value of the flag. Currently only one value +* is supported, which is XIL_SPINLOCK_ENABLE. +* +* @return XST_SUCCESS, if the initialization succeeded. +* XST_FAILURE, if the initialization failed +* +* @note None. +* +*****************************************************************************/ +u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr, + u32 lockflag) +{ + if (Xil_Spinlock_Flag_Addr == 0U) { + Xil_Spinlock_Flag_Addr = lockflagaddr; + if (*(u32 *)Xil_Spinlock_Flag_Addr == XIL_SPINLOCK_ENABLED) { + /* + * spinlock is already initialized by one of the CPUs, just update + * the local variable Xil_Spinlock_Addr with the passed address + * and dont write to the lock value as it might be currently + * getting used. + */ + /* + * Ensure to update the global variable Xil_Spinlock_Addr only + * if it is zero. A non-zero value may mean that there is something + * wrong. + */ + if (Xil_Spinlock_Addr == 0U) { + Xil_Spinlock_Addr = lockaddr; + } else { + /* + * May be spinlock is already initialized and the user has not + * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock. + */ + return XST_FAILURE; + } + } else { + /* All good, do the necessary initializations */ + Xil_Spinlock_Addr = lockaddr; + *(u32 *)(Xil_Spinlock_Addr) = XIL_SPINLOCK_RESETVAL; + *(u32 *)(Xil_Spinlock_Flag_Addr) = lockflag; + } + return XST_SUCCESS; + } else { + /* + * Most probably spinlock is already initialized and the user has not + * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock. + */ + return XST_FAILURE; + } +} + + +/****************************************************************************/ +/** +* @brief Used to release the spinlock. Typically called by the application +* once spinlock feature is no more required. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ReleaseSpinLock(void) +{ + Xil_Spinlock_Addr = 0; + Xil_Spinlock_Flag_Addr = 0; +} + +/****************************************************************************/ +/** +* @brief Used to know if the spinlock feature has been enabled. To ensure +* that spinlock feature does not break use cases where lock is +* not initialized, the application must call this API first to know +* if it can use spinlock. If this API returns non-zero value, an +* application should then use Xil_SpinLock or Xil_SpinUnlock. +* +* @param None +* +* @return Non-zero, if spinlock is already initialized and can be used. +* Zero, if spinlock is not initialized. +* +* @note +* +*****************************************************************************/ +u32 Xil_IsSpinLockEnabled(void) +{ + u32 retVal = FALSE; + + if (Xil_Spinlock_Flag_Addr != 0U) { + if (*(u32 *)(Xil_Spinlock_Flag_Addr) == XIL_SPINLOCK_ENABLED) { + retVal = TRUE; + } + } + return retVal; +} +#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_spinlock.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_spinlock.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_spinlock.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xil_spinlock.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xpm_counter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xpm_counter.c new file mode 100644 index 0000000..70156c4 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/common/xpm_counter.c @@ -0,0 +1,621 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_counter.c +* +* This file contains APIs for configuring and controlling the Performance +* Monitor Events for ARM based processors supported by standalone BSP. +* For more information about the event counters, see xpm_counter.h. +* The file contains APIs to setup an event, return the event counter value, +* disable event(s), enable events, reset event counters. +* It also provides a helper function: Xpm_SleepPerfCounter that is used to +* implement sleep routines in non-OS environment. +* It also contains two APIs which are being deprecated. Users are advised +* not to use them. +* On usage of these APIs, please refer to xpm_conter_example.c file which can +* be found at standalone example folder. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 8.00  mus  07/07/22 Initial version
+* 8.00  mus  07/14/22 Existing PMU APIs dont have support for CortexA53 32
+*                     bit processor, added check to skip PMU APIs
+*                     compilation in case of CortexA53 32 bit BSP.
+* 8.2   asa  02/23/23 Add instruction sync barrier as mandated by ARM specs.
+*                     Do other clean ups.
+*                     Remove xil_printfs for failure cases where we return
+*                     appropriate error return value. It is expected that
+*                     callers of the APIs would check for return value to
+*                     know the cause of the error.
+* 8.2   asa  03/09/23 Xpm_SetEvents and Xpm_GetEventCounters are deprecated
+*                     APIs. They need not be supported for Versal Net.
+* 8.2   adk  03/13/23 Include xstatus.h when xiltimer is enabled.
+* 9.0   ml   14/04/23 Add U to numericals to fix misra-c violation
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#if !defined(ARMA53_32) +#include "xpm_counter.h" +#if !defined(XPAR_XILTIMER_ENABLED) && !defined(SDT) +#include "xil_sleeptimer.h" +#include "xtime_l.h" +#else +#include "xstatus.h" +#endif + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ +typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT]; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* @brief This function disables the event counters. +* +* @return None. +* +*****************************************************************************/ +void Xpm_DisableEventCounters(void) +{ + u32 RegVal; + +#if defined(__aarch64__) + RegVal = mfcp(PMCNTENCLR_EL0); +#else + /* Disable the event counters */ +#ifdef __GNUC__ + RegVal = mfcp(XREG_CP15_COUNT_ENABLE_CLR); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR); + RegVal = C15Reg; } +#endif +#endif + + RegVal &= 0x7FFFFFFFU; + RegVal |= XPM_EVENT_CNTRS_MASK; +#if defined(__aarch64__) + mtcp(PMCNTENCLR_EL0, RegVal); +#else + mtcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal); +#endif +} + +/****************************************************************************/ +/** +* +* @brief This function enables the event counters. +* +* @return None. +* +*****************************************************************************/ +void Xpm_EnableEventCounters(void) +{ + u32 RegVal; + +#if defined(__aarch64__) + RegVal = mfcp(PMCNTENSET_EL0); +#else + /* Enable the event counters */ +#ifdef __GNUC__ + RegVal = mfcp(XREG_CP15_COUNT_ENABLE_SET); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_SET, RegVal); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET); + RegVal = C15Reg; } +#endif +#endif + RegVal |= XPM_EVENT_CNTRS_MASK; +#if defined(__aarch64__) + mtcp(PMCNTENSET_EL0, RegVal); +#if defined(VERSAL_NET) + RegVal = mfcp(MDCR_EL3); + mtcp(MDCR_EL3, RegVal | XPM_MDCR_EL3_SPME_MASK); +#endif +#else + mtcp(XREG_CP15_COUNT_ENABLE_SET, RegVal); +#endif +} + +/****************************************************************************/ +/** +* +* @brief This function resets the event counters. +* +* @return None. +* +*****************************************************************************/ +void Xpm_ResetEventCounters(void) +{ + u32 Reg; + +#if defined(__aarch64__) + Reg = mfcp(PMCR_EL0); +#else +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); + Reg = C15Reg; } +#endif +#endif + + Reg |= (1U << 1U); /* reset event counters */ + +#if defined(__aarch64__) + mtcp(PMCR_EL0, Reg); +#else + mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +#endif + isb(); +} + +/*****************************************************************************/ +/** + * + * Disables the requested event counter. + * + * + * @param EventCntrId: Event Counter ID. The counter ID is the same that + * was earlier returned through a call to Xpm_SetUpAnEvent. + * + * @return + * - XST_SUCCESS if successful. + * - XST_FAILURE if the passed Counter ID is invalid + * + ******************************************************************************/ +u32 Xpm_DisableEvent(u32 EventCntrId) +{ + u32 Counters; + u32 CntrMask = 0x1U; + + if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) { + return XST_FAILURE; + } else { + CntrMask = CntrMask << EventCntrId; +#if defined(__aarch64__) + Counters = mfcp(PMCNTENCLR_EL0); +#else +#ifdef __GNUC__ + Counters = mfcp(XREG_CP15_COUNT_ENABLE_CLR); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_CLR, Counters); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR); + Counters = C15Reg; } +#endif +#endif + Counters &= ~CntrMask; +#if defined(__aarch64__) + mtcp(PMCNTENCLR_EL0, Counters); +#else + mtcp(XREG_CP15_COUNT_ENABLE_CLR, Counters); +#endif + return XST_SUCCESS; + } +} + +/*****************************************************************************/ +/** + * + * Sets up one of the event counters to count events based on the Event ID + * passed. For supported Event IDs please refer xpm_counter.h. + * Upon invoked, the API searches for an available counter. After finding + * one, it sets up the counter to count events for the requested event. + * + * + * @param EventID: For valid values, please refer xpm_counter.h. + * + * @return + * - Counter Number if successful. For Cortex-R5, valid return values are + * 0, 1, or 2, and for others valid values are 0 to 5 + * - XPM_NO_COUNTERS_AVAILABLE (0xFF) if all counters are being used + * + ******************************************************************************/ +u32 Xpm_SetUpAnEvent(u32 EventID) +{ + u32 Counters; + u32 OriginalCounters; + u32 Index; + +#if defined(__aarch64__) + OriginalCounters = mfcp(PMCNTENSET_EL0); +#else +#ifdef __GNUC__ + OriginalCounters = mfcp(XREG_CP15_COUNT_ENABLE_SET); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET); + OriginalCounters = C15Reg; } +#endif +#endif + + OriginalCounters &= XPM_EVENT_CNTRS_BIT_MASK; + Counters = OriginalCounters; + if (Counters == XPM_ALL_EVENT_CNTRS_IN_USE) { + return XPM_NO_COUNTERS_AVAILABLE; + } else { + for(Index = 0U; Index < XPM_CTRCOUNT; Index++) { + if ((Counters & 0x1U) == 0x0U) { + break; + } else { + Counters = Counters >> 0x1U; + } + } + } + +#if defined(__aarch64__) + /* Select event counter */ + mtcp(PMSELR_EL0, Index); + isb(); + /* Set the event */ + mtcp( PMXEVTYPER_EL0, EventID); + /* Enable event counter */ + mtcp(PMCNTENSET_EL0, OriginalCounters | (1U << Index)); +#else + /* Select event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Index); + isb(); + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, EventID); + /* Enable event counter */ + mtcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters | ((u32)1U << Index)); +#endif + return Index; +} + +/*****************************************************************************/ +/** + * + * Reads the counter value for the requested counter ID. This is used to read + * the number of events that has been counted for the requsted event ID. + * This can only be called after a call to Xpm_SetUpAnEvent. + * + * + * @param EventCntrId: The counter ID is the same that was earlier + * returned through a call to Xpm_SetUpAnEvent. + * Cortex-R5 supports only 3 counters. The valid values are 0, 1, + * or 2 for other processors valid values are 0 to 5. + * @param CntVal: Pointer to a 32 bit unsigned int type. This is used to return + * the event counter value. + * + * @return + * - XST_SUCCESS if successful. + * - XST_FAILURE if the passed Counter ID is invalid + * + ******************************************************************************/ +u32 Xpm_GetEventCounter(u32 EventCntrId, u32 *CntVal) +{ + if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) { + return XST_FAILURE; + } else { +#if defined(__aarch64__) + mtcp(PMSELR_EL0, EventCntrId); + isb(); + *CntVal = mfcp(PMXEVCNTR_EL0); +#else + mtcp(XREG_CP15_EVENT_CNTR_SEL, EventCntrId); + isb(); +#ifdef __GNUC__ + *CntVal = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, (*CntVal)); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + *CntVal = C15Reg; } +#endif +#endif + return XST_SUCCESS; + } +} + +/****************************************************************************/ +/** +* +* @brief This is helper function used by sleep/usleep APIs to generate +* delay in sec/usec +* +* @param delay - delay time in sec/usec +* @param frequency - Number of countes in second/micro second +* +* @return None. +* +*****************************************************************************/ +#ifndef XPAR_XILTIMER_ENABLED +void Xpm_SleepPerfCounter(u32 delay, u64 frequency) +{ + u64 tEnd = 0U; + u64 tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + +#if defined (__GNUC__) + TimeLowVal1 = Xpm_ReadCycleCounterVal(); +#elif defined (__ICCARM__) + Xpm_ReadCycleCounterVal(TimeLowVal1); +#endif + tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency); + do { +#if defined (__GNUC__) + TimeLowVal2 = Xpm_ReadCycleCounterVal(); +#elif defined (__ICCARM__) + Xpm_ReadCycleCounterVal(TimeLowVal2); +#endif + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (u64)TimeLowVal2; + }while (tCur < tEnd); +} +#endif +#if !defined(__aarch64__) && !defined(VERSAL_NET) +/****************************************************************************/ +/** +* +* @brief This function configures the event counters controller, +* with the event codes, in a configuration selected by the user and +* enables the counters. +* +* @param PmcrCfg: Configuration value based on which the event counters +* are configured.XPM_CNTRCFG* values defined in xpm_counter.h can +* be utilized for setting configuration +* +* @return None. +* +*****************************************************************************/ +void Xpm_SetEvents(s32 PmcrCfg) +{ + u32 Counter; + static PmcrEventCfg32 PmcrEvents[] = { + +#if defined(ARMR5) + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSTRCACHEMISS, + XPM_EVENT_DATACACHEMISS + }, + { + XPM_EVENT_DATACACHEACCESS, + XPM_EVENT_DATAREAD, + XPM_EVENT_DATAWRITE + }, + { + XPM_EVENT_INSTR, + XPM_EVENT_DUALINSTR, + XPM_EVENT_EXCEPTION + }, + { + XPM_EVENT_EXCEPTIONRET, + XPM_EVENT_CHANGETOCONTEXID, + XPM_EVENT_SWCHANGE + }, + { + XPM_EVENT_IMMEDIATEINSTR, + XPM_EVENT_PROCEDURERET, + XPM_EVENT_UNALIGNACCESS + }, + { + XPM_EVENT_BRANCHMISPREDICT, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT + }, + { + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL, + XPM_EVENT_DATACACHEWRITE + }, + { + XPM_EVENT_EXTERNALMEMREQ, + XPM_EVENT_LSUSTALL, + XPM_EVENT_FORCEDRAINSTORE + }, + { + XPM_EVENT_INSTRTAGPARITY, + XPM_EVENT_INSTRDATAPARITY, + XPM_EVENT_DATATAGPARITY + }, + { + XPM_EVENT_DATADATAPARITY, + XPM_EVENT_TCMERRORPREFETCH, + XPM_EVENT_TCMERRORSTORE + }, + { + XPM_EVENT_INSTRCACHEACCESS, + XPM_EVENT_DUALISSUEA, + XPM_EVENT_DUALISSUEB + }, + { + XPM_EVENT_DUALISSUEOTHER, + XPM_EVENT_FPA, + XPM_EVENT_DATACACHEDATAERROR + }, + { + XPM_EVENT_DATACACHETAGERROR, + XPM_EVENT_PROCESSORLIVELOCK, + XPM_EVENT_ATCMMULTIBITERROR + }, + { + XPM_EVENT_B0TCMMULTIBITERROR, + XPM_EVENT_B1TCMMULTIBITERROR, + XPM_EVENT_ATCMSINGLEBITERROR + }, + { + XPM_EVENT_B0TCMSINGLEBITERROR, + XPM_EVENT_B1TCMSINGLEBITERROR, + XPM_EVENT_TCMERRORLSU + }, + { + XPM_EVENT_TCMERRORPFU, + XPM_EVENT_TCMFATALERRORAXI, + XPM_EVENT_TCMERRORAXI + }, +#else + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + { + XPM_EVENT_DATA_READS, + XPM_EVENT_DATA_WRITE, + XPM_EVENT_EXCEPTION, + XPM_EVENT_EXCEPRETURN, + XPM_EVENT_CHANGECONTEXT, + XPM_EVENT_SW_CHANGEPC + }, + { + XPM_EVENT_IMMEDBRANCH, + XPM_EVENT_UNALIGNEDACCESS, + XPM_EVENT_BRANCHMISS, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT, + XPM_EVENT_JAVABYTECODE + }, + { + XPM_EVENT_SWJAVABYTECODE, + XPM_EVENT_JAVABACKBRANCH, + XPM_EVENT_COHERLINEMISS, + XPM_EVENT_COHERLINEHIT, + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL + }, + { + XPM_EVENT_MAINTLBSTALL, + XPM_EVENT_STREXPASS, + XPM_EVENT_STREXFAIL, + XPM_EVENT_DATAEVICT, + XPM_EVENT_NODISPATCH, + XPM_EVENT_ISSUEEMPTY + }, + { + XPM_EVENT_INSTRRENAME, + XPM_EVENT_PREDICTFUNCRET, + XPM_EVENT_MAINEXEC, + XPM_EVENT_SECEXEC, + XPM_EVENT_LDRSTR, + XPM_EVENT_FLOATRENAME + }, + { + XPM_EVENT_NEONRENAME, + XPM_EVENT_PLDSTALL, + XPM_EVENT_WRITESTALL, + XPM_EVENT_INSTRTLBSTALL, + XPM_EVENT_DATATLBSTALL, + XPM_EVENT_INSTR_uTLBSTALL + }, + { + XPM_EVENT_DATA_uTLBSTALL, + XPM_EVENT_DMB_STALL, + XPM_EVENT_INT_CLKEN, + XPM_EVENT_DE_CLKEN, + XPM_EVENT_INSTRISB, + XPM_EVENT_INSTRDSB + }, + { + XPM_EVENT_INSTRDMB, + XPM_EVENT_EXTINT, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_PLE_OVFL, + XPM_EVENT_PLE_PROG, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_DATASTALL, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, +#endif + }; + const u32 *ptr = PmcrEvents[PmcrCfg]; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + /* Select event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]); + } + + Xpm_ResetEventCounters(); + Xpm_EnableEventCounters(); +} + +/****************************************************************************/ +/** +* +* @brief This function disables the event counters and returns the counter +* values. +* +* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. +* +* @return None. +* +*****************************************************************************/ +void Xpm_GetEventCounters(u32 *PmCtrValue) +{ + u32 Counter; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + +#ifdef __GNUC__ + PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); +#else + { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + PmCtrValue[Counter] = Cp15Reg; } +#endif + } +} +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/ARM_argv_veneer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/ARM_argv_veneer.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/ARM_argv_veneer.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/ARM_argv_veneer.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_close.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_close.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_close.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_close.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_exit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_exit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_exit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_iserror.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_iserror.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_iserror.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_iserror.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_istty.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_istty.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_istty.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_istty.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_open.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_open.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_open.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_read.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_read.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_read.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_read.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_time.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_time.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_time.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_write.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_write.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/_sys_write.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/_sys_write.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/asm_vectors.s b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/asm_vectors.s similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/asm_vectors.s rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/asm_vectors.s diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/boot.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/boot.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/boot.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/boot.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/translation_table.s b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/translation_table.s similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/translation_table.s rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/translation_table.s diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/CMakeLists.txt new file mode 100644 index 0000000..b692cb2 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: MIT +# Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. +if(NOT "${CMAKE_SYSTEM_NAME}" STREQUAL "FreeRTOS") +collect (PROJECT_LIB_SOURCES asm_vectors.S) +endif() +collect (PROJECT_LIB_SOURCES translation_table.S) +collect (PROJECT_LIB_SOURCES boot.S) +collect (PROJECT_LIB_SOURCES cpu_init.S) +collect (PROJECT_LIB_SOURCES xil-crt0.S) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/Makefile new file mode 100644 index 0000000..d90ef88 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/Makefile @@ -0,0 +1,83 @@ +############################################################################### +# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved. +# SPDX-License-Identifier: MIT +############################################################################### +DRIVER_LIB_VERSION = v1.0 + +include config.make + +CC=$(COMPILER) +AR=$(ARCHIVER) +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) +ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) + +ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc) +ECC_FLAGS += -nostartfiles\ + -march=armv7-a \ + -mfloat-abi=soft \ + -mfpu=neon +endif + +ifeq (($(notdir $(CC))) , arm-none-eabi-gcc) +ECC_FLAGS += -nostartfiles +endif + +RELEASEDIR=../../../lib/ +INCLUDEDIR=../../../include/ +INCLUDES=-I./. -I${INCLUDEDIR} + +SRCFILES:=$(wildcard *.c) + +ASSEMBLY_SRCFILES:=$(wildcard *.S) + +OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c)))) + +ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S)))) + +INCLUDEFILES=*.h + +libs: $(LIBS) + +standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS) + +DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d) + +include $(wildcard $(DEPFILES)) + +ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d) + +include $(wildcard $(ASSEMBLY_DEPFILES)) + +include $(wildcard ../../../../dep.mk) + +$(RELEASEDIR)%.o: %.S + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $< + +$(RELEASEDIR)%.o: %.c + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $< + +profile_libs: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs + +.PHONY: include +include: standalone_includes profile_includes + +standalone_includes: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) + +$(INCLUDEDIR)%.h: %.h + $(CP) $< $@ + +profile_includes: + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include + +clean: + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS} + rm -rf $(DEPFILES) + rm -rf $(ASSEMBLY_DEPFILES) + $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/asm_vectors.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/asm_vectors.S new file mode 100644 index 0000000..9be0b25 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/asm_vectors.S @@ -0,0 +1,176 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.S +* +* This file contains the initial vector table for the Cortex A9 processor +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.00a pkp	22/01/14 Modified return addresses for interrupt
+*			 handlers (DataAbortHandler and SVCHandler)
+*			 to fix CR#767251
+* 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+*			 abort and prefetch abort into DataAbortAddr and
+*			 PrefetchAbortAddr for further use to fix CR#854523
+* 5.4	pkp	12/03/15 Added handler for undefined exception
+* 6.8	mus	04/27/18 Removed __ARM_NEON__ flag definition. Now,
+*			 saving/restoring of of HW floating point register
+*			 would be done through newly introduced flag
+*			 FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
+*			 configured based on the -mfpu-abi option in extra
+*			 compiler flags.
+*
    +* +* @note +* +* None. +* +******************************************************************************/ +#include "xil_errata.h" +#include "bspconfig.h" + +.org 0 +.text + +.globl _vector_table + +.section .vectors +_vector_table: + B _boot + B Undefined + B SVCHandler + B PrefetchAbortHandler + B DataAbortHandler + NOP /* Placeholder for address exception vector*/ + B IRQHandler + B FIQHandler + + +IRQHandler: /* IRQ vector handler */ + + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ +#if FPU_HARD_FLOAT_ABI_ENABLED + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif + +#ifdef PROFILING + ldr r2, =prof_pc + subs r3, lr, #0 + str r3, [r2] +#endif + + bl IRQInterrupt /* IRQ vector */ + +#if FPU_HARD_FLOAT_ABI_ENABLED + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} +#endif + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + + subs pc, lr, #4 /* adjust return */ + + +FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +#if FPU_HARD_FLOAT_ABI_ENABLED + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif + +FIQLoop: + bl FIQInterrupt /* FIQ vector */ + +#if FPU_HARD_FLOAT_ABI_ENABLED + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} +#endif + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + + +Undefined: /* Undefined handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =UndefinedExceptionAddr + sub r1, lr, #4 + str r1, [r0] /* Store address of instruction causing undefined exception */ + + bl UndefinedException /* UndefinedException: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + movs pc, lr + +SVCHandler: /* SWI handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + + tst r0, #0x20 /* check the T bit */ + ldrneh r0, [lr,#-2] /* Thumb mode */ + bicne r0, r0, #0xff00 /* Thumb mode */ + ldreq r0, [lr,#-4] /* ARM mode */ + biceq r0, r0, #0xff000000 /* ARM mode */ + + bl SWInterrupt /* SWInterrupt: call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + movs pc, lr /*return to the next instruction after the SWI instruction */ + + +DataAbortHandler: /* Data Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =DataAbortAddr + sub r1, lr, #8 + str r1, [r0] /* Stores instruction causing data abort */ + + bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */ + +PrefetchAbortHandler: /* Prefetch Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =PrefetchAbortAddr + sub r1, lr, #4 + str r1, [r0] /* Stores instruction causing prefetch abort */ + + bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */ + +.end diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/boot.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/boot.S new file mode 100644 index 0000000..5305e14 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/boot.S @@ -0,0 +1,447 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* @addtogroup a9_boot_code Cortex A9 Processor Boot Code +* @{ +*

    boot.S

    +* The boot code performs minimum configuration which is required for an +* application to run starting from processor reset state of the processor. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function. +* +* 1. Program vector table base for exception handling +* 2. Invalidate instruction cache, data cache and TLBs +* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, +* abort, system) +* 4. Configure MMU with short descriptor translation table format and program +* base address of translation table +* 5. Enable data cache, instruction cache and MMU +* 6. Enable Floating point unit +* 7. Transfer control to _start which clears BSS sections, initializes +* global timer and runs global constructor before jumping to main +* application +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+*			 register settings.
+* 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+*		         register settings.
+* 3.07a asa     07/16/12 Modified the L2 Cache controller settings to improve
+*			 performance. Changed the property of the ".boot"
+*			 section.
+* 3.07a sgd     08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+*               Register settings
+* 3.09a sgd     02/06/13 Updated SLCR l2c Ram Control register to a
+*               value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.2   pkp	06/19/14 Enabled asynchronous abort exception
+* 5.0	pkp	16/15/14 Modified initialization code to enable scu after
+*			 MMU is enabled
+* 5.1   pkp	05/13/15 Changed the initialization order so to first invalidate
+*			 caches and TLB, enable MMU and caches, then enable SMP
+*			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+*			 is done later.
+* 5.4   asa     12/6/15  Added code to initialize SPSR for all relevant modes.
+* 6.0   mus     08/04/16 Added code to detect zynq-7000 base silicon configuration and
+*                        attempt to enable dual core behavior on single cpu zynq-7000s
+*                        devices is prevented from corrupting system behavior.
+* 6.0   mus     08/24/16 Check CPU core before putting cpu1 to reset for single core
+*                        zynq-7000s devices
+* 7.6   mus     09/02/21 SCU invalidation should be done only from primary CPU, so
+*                        skipping it when USE_AMP is set to 1. It fixes CR#1109723
+* 7.7   asa     01/06/22 Removed Cortex-A9 errata handling for errata
+* 			 742230 and 743622. These do not apply to
+* 			 Cortex-A9 revision r3p0 being used in Zynq
+* 			 platforms.
+* 9.0   mus     07/27/23 Removed dependency on XPAR_CPU_ID, updated logic to use
+*                        CPU affinity register to read CPU ID.
+*
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif +#include "xil_errata.h" + +.globl MMUTable +.global _prestart +.global _boot +.global __stack +.global __irq_stack +.global __supervisor_stack +.global __abort_stack +.global __fiq_stack +.global __undef_stack +.global _vector_table + +.set PSS_L2CC_BASE_ADDR, 0xF8F02000 +.set PSS_SLCR_BASE_ADDR, 0xF8000000 + +.set RESERVED, 0x0fffff00 +.set TblBase , MMUTable +.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */ +.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/ +.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/ +.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/ +.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/ +.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/ +.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/ +.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/ +.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/ + +.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ +.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ +.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ +.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/ +.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/ + +/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ +.if SIM_MODE == 1 +.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */ +.else +.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */ +.endif + +.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */ + +.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, + Event monitor bus enable and Way Size (64 KB) */ +.set L2CCControl, 0x01 /* Enable L2CC */ +.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */ +.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */ + +.set SLCRlockKey, 0x767B /* SLCR lock key */ +.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */ +.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */ + +/* Stack Pointer locations for boot code */ +.set Undef_stack, __undef_stack +.set FIQ_stack, __fiq_stack +.set Abort_stack, __abort_stack +.set SPV_stack, __supervisor_stack +.set IRQ_stack, __irq_stack +.set SYS_stack, __stack + +.set vector_base, _vector_table + +.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */ + +.section .boot,"ax" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + /* only allow cpu0 through */ + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #0 + beq CheckEFUSE + b OKToRun + +CheckEFUSE: + ldr r0,=EFUSEStaus + ldr r1,[r0] /* Read eFuse setting */ + ands r1,r1,#0x80 /* Check whether device is having single core */ + beq OKToRun + + /* single core device, reset cpu1 */ + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRCPURSTReg + ldr r1,[r0] /* Read CPU Software Reset Control register */ + orr r1,r1,#0x22 + str r1,[r0] /* Reset CPU1 */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + +OKToRun: + mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ + and r5, r0, #0x00f00000 + and r6, r0, #0x0000000f + orr r6, r6, r5, lsr #20-4 + + /* set VBAR to the _vector_table address in linker script */ + ldr r0, =vector_base + mcr p15, 0, r0, c12, c0, 0 + + /*invalidate scu*/ +#if USE_AMP!=1 + ldr r7, =0xf8f0000c + ldr r6, =0xffff + str r6, [r7] +#endif + + /* Invalidate caches and TLBs */ + mov r0,#0 /* r0 = 0 */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ + bl invalidate_dcache /* invalidate dcache */ + + /* Disable MMU, if enabled */ + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ + bic r0, r0, #0x1 /* clear bit 0 */ + mcr p15, 0, r0, c1, c0, 0 /* write value back */ + +#ifdef SHAREABLE_DDR + /* Mark the entire DDR memory as shareable */ + ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */ + ldr r0, =TblBase /* MMU Table address in memory */ + ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +shareable_loop: + str r2, [r0] /* write the entry to MMU table */ + add r0, r0, #0x4 /* next entry in the table */ + add r2, r2, #0x100000 /* next section */ + subs r3, r3, #1 + bge shareable_loop /* loop till 1G is covered */ +#endif + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the irq stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x12 /* IRQ mode */ + msr cpsr, r2 + ldr r13,=IRQ_stack /* IRQ stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the supervisor stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x13 /* supervisor mode */ + msr cpsr, r2 + ldr r13,=SPV_stack /* Supervisor stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Abort stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x17 /* Abort mode */ + msr cpsr, r2 + ldr r13,=Abort_stack /* Abort stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the FIQ stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x11 /* FIQ mode */ + msr cpsr, r2 + ldr r13,=FIQ_stack /* FIQ stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Undefine stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1b /* Undefine mode */ + msr cpsr, r2 + ldr r13,=Undef_stack /* Undefine stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the system stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1F /* SYS mode */ + msr cpsr, r2 + ldr r13,=SYS_stack /* SYS stack pointer */ + + /*set scu enable bit in scu*/ + ldr r7, =0xf8f00000 + ldr r0, [r7] + orr r0, r0, #0x1 + str r0, [r7] + + /* enable MMU and cache */ + + ldr r0,=TblBase /* Load MMU translation table base */ + orr r0, r0, #0x5B /* Outer-cacheable, WB */ + mcr 15, 0, r0, c2, c0, 0 /* TTB0 */ + + mvn r0,#0 /* Load MMU domains -- all ones=manager */ + mcr p15,0,r0,c3,c0,0 + + /* Enable mmu, icahce and dcache */ + ldr r0,=CRValMmuCac + mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */ + dsb /* dsb allow the MMU to start up */ + isb /* isb flush prefetch buffer */ + + /* Write to ACTLR */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + orr r0, r0, #(0x01 << 6) /* set SMP bit */ + orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + +/* Invalidate L2 Cache and enable L2 Cache*/ +/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */ +#if USE_AMP!=1 + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + mov r1, #0 /* force the disable bit */ + str r1, [r0] /* disable the L2 Caches */ + + ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */ + ldr r1,[r0] /* read the register */ + ldr r2,=L2CCAuxControl /* set the default bits */ + orr r1,r1,r2 + str r1, [r0] /* store the Aux Control Register */ + + ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */ + ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/ + str r1, [r0] /* store the TAG Latency register Register */ + + ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */ + ldr r1,=L2CCDataLatency /* set the latencies for the Data*/ + str r1, [r0] /* store the Data Latency register Register */ + + ldr r0,=L2CCWay /* Load L2CC base address base + way register*/ + ldr r2, =0xFFFF + str r2, [r0] /* force invalidate */ + + ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */ + /* Load L2CC base address base + sync register*/ + /* poll for completion */ +Sync: ldr r1, [r0] + cmp r1, #0 + bne Sync + + ldr r0,=L2CCIntRaw /* clear pending interrupts */ + ldr r1,[r0] + ldr r0,=L2CCIntClear + str r1,[r0] + + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ + ldr r1,=SLCRL2cRamConfig /* set the configuration value */ + str r1, [r0] /* store the L2c Ram Control Register */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + ldr r1,[r0] /* read the register */ + mov r2, #L2CCControl /* set the enable bit */ + orr r1,r1,r2 + str r1, [r0] /* enable the L2 Caches */ +#endif + + mov r0, r0 + mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */ + orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */ + mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */ + + /* enable vfp */ + fmrx r1, FPEXC /* read the exception register */ + orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */ + fmxr FPEXC, r1 /* write back the exception register */ + + mrc p15,0,r0,c1,c0,0 /* flow prediction enable */ + orr r0, r0, #(0x01 << 11) /* #0x8000 */ + mcr p15,0,r0,c1,c0,0 + + mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */ + orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */ + orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */ + mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */ + + mrs r0, cpsr /* get the current PSR */ + bic r0, r0, #0x100 /* enable asynchronous abort exception */ + msr cpsr_xsf, r0 + + + b _start /* jump to C startup code */ + and r0, r0, r0 /* no op */ + +.Ldone: b .Ldone /* Paranoia: we should never get here */ + + +/* + ************************************************************************* + * + * invalidate_dcache - invalidate the entire d-cache by set/way + * + * Note: for Cortex-A9, there is no cp instruction for invalidating + * the whole D-cache. Need to invalidate each line. + * + ************************************************************************* + */ +invalidate_dcache: + mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ + beq finished + mov r10, #0 /* start with level 0 */ +loop1: + add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ + mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ + and r1, r1, #7 /* get those 3 bits alone */ + cmp r1, #2 + blt skip /* no cache or only instruction cache at this level */ + mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ + isb /* isb to sync the change to the CacheSizeID reg */ + mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ + and r2, r1, #7 /* extract the line length field */ + add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ + clz r5, r4 /* r5 is the bit position of the way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ +loop2: + mov r9, r4 /* r9 working copy of the max way size (right aligned) */ +loop3: + orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ + orr r11, r11, r7, lsl r2 /* factor in the index number */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way number */ + bge loop3 + subs r7, r7, #1 /* decrement the index */ + bge loop2 +skip: + add r10, r10, #2 /* increment the cache number */ + cmp r3, r10 + bgt loop1 + +finished: + mov r10, #0 /* switch back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + dsb + isb + + bx lr + +.end +/** +* @} End of "addtogroup a9_boot_code". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/cpu_init.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/cpu_init.S new file mode 100644 index 0000000..48dcec3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/cpu_init.S @@ -0,0 +1,53 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file cpu_init.S +* +* This file contains CPU specific initialization. Invoked from main CRT +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0   pkp	12/16/14 removed incorrect initialization of TLB lockdown
+*			 register to fix CR#830580
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + + .text + .global __cpu_init + .align 2 +__cpu_init: + +/* Clear cp15 regs with unknown reset values */ + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 /* DFSR */ + mcr p15, 0, r0, c5, c0, 1 /* IFSR */ + mcr p15, 0, r0, c6, c0, 0 /* DFAR */ + mcr p15, 0, r0, c6, c0, 2 /* IFAR */ + mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */ + mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */ + mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */ + +/* Reset and start Cycle Counter */ + mov r2, #0x80000000 /* clear overflow */ + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd /* D, C, E */ + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 /* enable cycle counter */ + mcr p15, 0, r2, c9, c12, 1 + + bx lr + +.end diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/translation_table.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/translation_table.S new file mode 100644 index 0000000..cd8e49f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/translation_table.S @@ -0,0 +1,213 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file translation_table.S +* +* @addtogroup a9_boot_code +* @{ +*

    translation_table.S

    +* The translation_table.S contains a static page table required by MMU for +* cortex-A9. This translation table is flat mapped (input address = output +* address) with default memory attributes defined for zynq architecture. It +* utilizes short descriptor translation table format with each section defining +* 1 MB of memory. +* +* The overview of translation table memory attributes is described below. +* +*| | Memory Range | Definition in Translation Table | +*|-----------------------|-------------------------|-----------------------------------| +*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable | +*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered | +*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned | +*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory | +*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned | +*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory | +*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable | +*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned | +*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned | +*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable | +*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned | +*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable | +* +* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB, +* region after DDR and before PL is marked as undefined/reserved in translation +* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 - +* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size +* of 1 MB, it is not possible to define separate regions for them. For region +* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB +* granual size, it is not possible to define separate region for it. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*		       instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2	pkp  09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+*			and  0xe0000000 - 0xe1ffffff is broken down into
+*			0xe0000000 - 0xe02fffff (memory mapped divides)
+*			0xe0300000 - 0xe0ffffff (reserved) and
+*			0xe1000000 - 0xe1ffffff (NAND)
+* 5.2	pkp  06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+*			if DDR is present or not and accordingly generate the
+*			translation table
+* 6.1	pkp  07/11/2016 Corrected comments for memory attributes
+* 6.8   mus  07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
+*			with the USE_AMP flag.
+*
    +* +* +******************************************************************************/ +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#else +#include "xmem_config.h" +#endif + .globl MMUTable + + .section .mmu_tbl,"a" + +MMUTable: + /* Each table entry occupies one 32-bit word and there are + * 4096 entries, so the entire table takes up 16KB. + * Each entry covers a 1MB section. + */ +.set SECT, 0 + +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR +.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR +.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 +#elif defined(XPAR_PS7_DDR_0_BASEADDRESS) +.set DDR_START, XPAR_PS7_DDR_0_BASEADDRESS +.set DDR_END, XPAR_PS7_DDR_0_HIGHADDRESS +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 +#else +.set DDR_REG, 0 +#endif + +.set UNDEF_REG, 0x3FF - DDR_REG + +#ifndef USE_AMP + /*0x00000000 - 0x00100000 (inner and outer cacheable )*/ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +#else + /*0x00000000 - 0x00100000 (inner cacheable )*/ +.word SECT + 0x14de6 /* S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1 */ +#endif +.set SECT, SECT+0x100000 + +.rept DDR_REG /* (DDR Cacheable) */ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept UNDEF_REG /* (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + + +.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices) + * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */ +.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and + 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of + 1MB, it is not possible to define separate regions for them */ + +.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */ + +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */ +.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of + 1MB, it is not possible to define separate region for it + + 0xfff00000 - 0xffffffff + 256K OCM when mapped to high address space + inner-cacheable */ +.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 + +.end +/** +* @} End of "addtogroup a9_boot_code". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/xil-crt0.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/xil-crt0.S new file mode 100644 index 0000000..a560286 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/gcc/xil-crt0.S @@ -0,0 +1,136 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil-crt0.S +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.05a sdm  02/02/12 Added code for profiling
+* 3.06a sgd  05/16/12 Added global constructors and cleanup code
+*                     Uart initialization based on compiler flag
+* 3.07a sgd  07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2	pkp  08/04/14 Removed PEEP board related code which contained
+*		      initialization of uart smc nor and sram
+* 5.3	pkp  10/07/15 Added support for OpenAMP by not initializing global
+*		      timer when USE_AMP flag is defined
+* 6.6   srm  10/18/17 Added timer configuration using XTime_StartTTCTimer API.
+*		      Now the TTC instance as specified by the user will be
+*		      started.
+* 7.7   adk  11/30/21 Added support for xiltimer library.
+*
    +* +* @note +* +* None. +* +******************************************************************************/ +#include "bspconfig.h" +#include "xparameters.h" + + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .long __sbss_start + +.Lsbss_end: + .long __sbss_end + +.Lbss_start: + .long __bss_start + +.Lbss_end: + .long __bss_end + +.Lstack: + .long __stack + + + .globl _start +_start: + bl __cpu_init /* Initialize the CPU first (BSP provides this) */ + + mov r0, #0 + + /* clear sbss */ + ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr r2,.Lsbss_end /* calculate end of the SBSS */ + +.Lloop_sbss: + cmp r1,r2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr r1,.Lbss_start /* calculate beginning of the BSS */ + ldr r2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp r1,r2 + bge .Lenclbss /* If no BSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_bss + +.Lenclbss: + + /* set stack pointer */ + ldr r13,.Lstack /* stack address */ + + /* Reset and start Global Timer */ + mov r0, #0x0 + mov r1, #0x0 + + /* Reset and start Triple Timer Counter */ + #if defined SLEEP_TIMER_BASEADDR + bl XTime_StartTTCTimer + #endif + +#ifndef XPAR_XILTIMER_ENABLED +#if USE_AMP != 1 + bl XTime_SetTime +#endif +#endif + +#ifdef PROFILING /* defined in Makefile */ + /* Setup profiling stuff */ + bl _profile_init +#endif /* PROFILING */ + + /* run global constructors */ + bl __libc_init_array + + /* make sure argc and argv are valid */ + mov r0, #0 + mov r1, #0 + + /* Let her rip */ + bl main + + /* Cleanup global constructors */ + bl __libc_fini_array + +#ifdef PROFILING + /* Cleanup profiling stuff */ + bl _profile_clean +#endif /* PROFILING */ + + /* All done */ + bl exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _start,.Lstart-_start diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/asm_vectors.s b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/asm_vectors.s similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/asm_vectors.s rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/asm_vectors.s diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/boot.s b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/boot.s similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/boot.s rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/boot.s diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/translation_table.s b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/translation_table.s similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexa9/iccarm/translation_table.s rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/iccarm/translation_table.s diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/sleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/sleep.c new file mode 100644 index 0000000..d3e3d76 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/sleep.c @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex A9 MP core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6	srm      10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+* 9.0   ml       03/03/23 Add description to fix doxygen warnings.
+*
    +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + +/*****************************************************************************/ +/** +* +* This API is used to provide delays in seconds +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +******************************************************************************/ +unsigned sleep_A9(unsigned int seconds) +{ +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); +#else + XTime tEnd, tCur; + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); +#endif + + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/smc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/smc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/smc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/usleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/usleep.c new file mode 100644 index 0000000..82f15ce --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/usleep.c @@ -0,0 +1,83 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file usleep.c +* +* This function provides a microsecond delay using the Global Timer register in +* the ARM Cortex A9 MP core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated micro sleep function to make use Global Timer
+* 4.2	pkp		 08/04/14 Removed unimplemented nanosleep routine as it is not
+*						  possible to generate timer in nanosecond due to
+*						  limited cpu frequency
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6	srm	 10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+* 9.0   ml       03/03/23 Added description to fix doxygen warnings.
+*
    +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xreg_cortexa9.h" + +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + +/**************************** Constant Definitions ************************/ +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000) +#else +/**< Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U)) +#endif + +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ +int usleep_A9(unsigned long useconds) +{ +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); +#else + XTime tEnd, tCur; + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); +#endif + + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xcortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xcortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xcortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xcortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xcortexa9_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xcortexa9_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xcortexa9_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xcortexa9_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache.c new file mode 100644 index 0000000..0f6b14f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache.c @@ -0,0 +1,1535 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      		  to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      		  L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      		  at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      		  APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      		  'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  		  operation was being done with L1 Data cache disabled. This is
+*			  		  fixed so that L2 cache disable operation happens independent of
+*			  		  L1 cache disable operation. This fixes CR #706464.
+*			  		  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  		  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 		  Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 		  relevant cache APIs to disable and enable back the interrupts.
+*			 		  This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 		  out that for L2 cache flush/clean/invalidation by cache lines
+*			 		  does not need a cache sync as these are atomic nature. Similarly
+*			 		  figured out that for complete L2 cache flush/invalidation by way
+*			 		  we need to wait for some more time in a loop till the status
+*			 		  shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 		  cache lines were missed to invalidate when unaligned address
+*			 		  invalidation was accommodated. That fixes CR #766768.
+*			 		  Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 		  stack memory which contains return address was invalidated. So
+*			 		  stack memory was flushed first and then L1D cache is invalidated.
+*			 		  This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02	 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+*					  explanation of CR#785243
+* 5.00   kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+*					  has stack memory which has return address. Before invalidating
+*					  cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01	 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+*					  to remove unnecessary dsb in the APIs. Instead of using dsb
+*					  for L2 Cache, L2CacheSync has been used for each L2 cache line
+*					  and single dsb has been used for L1 cache. Also L2CacheSync is
+*					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+*					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
+*					  stack instead of just System Stack
+* 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+*					  application(when USE_AMP flag is defined for BSP) as master CPU
+*					  would be utilizing L2 cache for its operation
+* 6.6    mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+*                     version r0p2, which is present in zynq. So,removed the handling
+*                     related to same.It fixes CR#989132.
+* 6.6    asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+*					  routines to ensure the stack data flushed only when the respective
+*					  caches are enabled. This fixes CR-992023.
+* 7.5    mus 01/19/21 Implement workaround for errata#588369 in Xil_DCacheFlushRange.
+*					  It fixes CR#1086022.
+* 8.0    asa 05/25/22 Fix issues in cache maintenance APIs Xil_DCacheFlushRange
+*                     and Xil_DCacheInvalidateRange to ensure that clean and
+*                     invalidation of outer cache (L2 cache) is separated out and
+*                     is independent from inner cache (L1 cache). This is inline
+*                     with recommendations and implementations available in open
+*                     source. It fixes CR#1130368.
+*                     Minimize use of barriers (dsb) as per guidances.
+*                     Remove the use of XREG_CP15_CACHE_SIZE_SEL register as it is
+*                     not needed for Zynq architecture.
+*                     Replace dsb with Xil_L2CacheSync as applicable as the latter
+*                     is more efficient while handling L2 cache maintenance.
+* 8.1    asa 02/13/23 The existing Xil_DCacheInvalidateRange has a bug where
+*                     the last cache line will not get invalidated under certain
+*                     scenarios. Changes are made to fix the same.
+* 9.0    ml  03/03/23 Added description to fix doxygen warnings.
+*        mus 09/21/23 Fix infinite loop in Xil_DCacheInvalidateRange when
+*                     USE_AMP=1.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_cache_l.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexa9.h" +#include "xl2cc.h" +#include "xil_errata.h" +#include "xil_exception.h" + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#define IRQ_FIQ_MASK 0xC0U /**< Mask IRQ and FIQ interrupts in cpsr */ + +#ifdef __GNUC__ + extern s32 _stack_end; + extern s32 __undef_stack; +#endif + +#ifndef USE_AMP +/***************************************************************************/ +/** +* +* Access L2 Debug Control Register. +* +* @param Value, value to be written to Debug Control Register. +* +* @return None. +* +****************************************************************************/ +#ifdef __GNUC__ +static inline void Xil_L2WriteDebugCtrl(u32 Value) +#else +static void Xil_L2WriteDebugCtrl(u32 Value) +#endif +{ +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value); +#else + (void)(Value); +#endif +} + +/***************************************************************************/ +/** +* +* Perform L2 Cache Sync Operation. +* +* @return None. +* +****************************************************************************/ +#ifdef __GNUC__ +static inline void Xil_L2CacheSync(void) +#else +static void Xil_L2CacheSync(void) +#endif +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U); +} +#endif +/****************************************************************************/ +/** +* @brief Enable the Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheEnable(void) +{ + Xil_L1DCacheEnable(); +#ifndef USE_AMP + Xil_L2CacheEnable(); +#endif +} + +/****************************************************************************/ +/** +* @brief Disable the Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ +#ifndef USE_AMP + Xil_L2CacheDisable(); +#endif + Xil_L1DCacheDisable(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the entire Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidate(); +#endif + Xil_L1DCacheInvalidate(); + + mtcpsr(currmask); +} + +/*****************************************************************************/ +/** +* @brief Invalidate a Data cache line. If the byte specified by the address +* (adr) is cached by the Data cache, the cacheline containing that +* byte is invalidated. If the cacheline is modified (dirty), the +* modified contents are lost and are NOT written to the system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidateLine(adr); +#endif + Xil_L1DCacheInvalidateLine(adr); + + mtcpsr(currmask); +} + + +/*****************************************************************************/ +/** +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If +* the cachelines are modified (dirty), the modified contents are lost +* and NOT written to the system memory before the lines are +* invalidated. +* +* In this function, if start address or end address is not aligned to +* cache-line, particular cache-line containing unaligned start or end +* address is flush first and then invalidated the others as +* invalidating the same unaligned cache line may result into loss of +* data. This issue raises few possibilities. +* +* If the address to be invalidated is not cache-line aligned, the +* following choices are available: +* 1. Invalidate the cache line when required and do not bother much +* for the side effects. Though it sounds good, it can result in +* hard-to-debug issues. The problem is, if some other variable are +* allocated in the same cache line and had been recently updated +* (in cache), the invalidation would result in loss of data. +* 2. Flush the cache line first. This will ensure that if any other +* variable present in the same cache line and updated recently are +* flushed out to memory. Then it can safely be invalidated. Again it +* sounds good, but this can result in issues. For example, when the +* invalidation happens in a typical ISR (after a DMA transfer has +* updated the memory), then flushing the cache line means, losing +* data that were updated recently before the ISR got invoked. +* +* Linux prefers the second one. To have uniform implementation +* (across standalone and Linux), the second option is implemented. +* This being the case, following needs to be taken care of: +* 1. Whenever possible, the addresses must be cache line aligned. +* Please nore that, not just start address, even the end address must +* be cache line aligned. If that is taken care of, this will always +* work. +* 2. Avoid situations where invalidation has to be done after the +* data is updated by peripheral/DMA directly into the memory. It is +* not tough to achieve (may be a bit risky). The common use case to +* do invalidation is when a DMA happens. Generally for such use +* cases, buffers can be allocated first and then start the DMA. The +* practice that needs to be followed here is, immediately after +* buffer allocation and before starting the DMA, do the invalidation. +* With this approach, invalidation need not to be done after the DMA +* transfer is over. +* +* This is going to always work if done carefully. +* However, the concern is, there is no guarantee that invalidate has +* not needed to be done after DMA is complete. For example, because +* of some reasons if the first cache line or last cache line +* (assuming the buffer in question comprises of multiple cache lines) +* are brought into cache (between the time it is invalidated and DMA +* completes) because of some speculative prefetching or reading data +* for a variable present in the same cache line, then we will have to +* invalidate the cache after DMA is complete. +* +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + INTPTR tempadr; + INTPTR opendaddr; + INTPTR endaddr; + u32 currmask; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + opendaddr = adr + len; + endaddr = opendaddr; + + if ((adr & (cacheline-1U)) != 0U) { + adr &= (~(cacheline - 1U)); + + Xil_L1DCacheFlushLine(adr); +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + Xil_L2CacheFlushLine(adr); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); +#endif + adr += cacheline; + } + if ((opendaddr & (cacheline-1U)) != 0U) { + opendaddr &= (~(cacheline - 1U)); + + if (opendaddr != adr) { + Xil_L1DCacheFlushLine(opendaddr); +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + Xil_L2CacheFlushLine(opendaddr); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); +#endif + } + } + + tempadr = adr; + +#ifndef USE_AMP + while (tempadr < endaddr) { + /* Invalidate L2 cache line */ + *L2CCOffset = tempadr; + Xil_L2CacheSync(); + tempadr += cacheline; + } +#endif + + while (adr < endaddr) { + /* Invalidate L1 Data cache line */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_dc_line_mva_poc(adr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); + Reg = adr; } +#endif + adr += cacheline; + } + /* Wait for L1 cache invalidation to complete */ + dsb(); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the entire Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L1DCacheFlush(); +#ifndef USE_AMP + Xil_L2CacheFlush(); +#endif + mtcpsr(currmask); +} + + +/****************************************************************************/ +/** +* @brief Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param adr: 32bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheFlushLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L1DCacheFlushLine(adr); +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + Xil_L2CacheFlushLine(adr); + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); +#endif + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address range are cached by the +* data cache, the cachelines containing those bytes are invalidated. +* If the cachelines are modified (dirty), they are written to the +* system memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheFlushRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + u32 opendadr; + u32 currmask; + u32 tempadr; + + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + opendadr = adr + len; + adr &= ~(cacheline - 1U); + + tempadr = adr; + + while (tempadr < opendadr) { + /* Flush L1 Data cache line */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_clean_inval_dc_line_mva_poc(tempadr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); + Reg = tempadr; } +#endif + tempadr += cacheline; + } + /* Wait for L1 cache clean and invalidation to complete */ + dsb(); + +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + while ((u32)adr < opendadr) { + /* Flush L2 cache line */ + *L2CCOffset = adr; + Xil_L2CacheSync(); + adr += cacheline; + } + Xil_L2WriteDebugCtrl(0x0U); +#endif + } + mtcpsr(currmask); +} +/****************************************************************************/ +/** +* @brief Store a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param adr: 32bit address of the data to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheStoreLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + Xil_L1DCacheStoreLine(adr); +#ifndef USE_AMP + Xil_L2CacheStoreLine(adr); +#endif + mtcpsr(currmask); +} + +/***************************************************************************/ +/** +* @brief Enable the instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheEnable(void) +{ + Xil_L1ICacheEnable(); +#ifndef USE_AMP + Xil_L2CacheEnable(); +#endif +} + +/***************************************************************************/ +/** +* @brief Disable the instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ +#ifndef USE_AMP + Xil_L2CacheDisable(); +#endif + Xil_L1ICacheDisable(); +} + + +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidate(); +#endif + Xil_L1ICacheInvalidate(); + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate an instruction cache line. If the instruction specified +* by the address is cached by the instruction cache, the cacheline +* containing that instruction is invalidated. +* +* @param adr: 32bit address of the instruction to be invalidated. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_ICacheInvalidateLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidateLine(adr); +#endif + Xil_L1ICacheInvalidateLine(adr); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the instructions specified by the address range are cached by +* the instrunction cache, the cachelines containing those +* instructions are invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { +#ifndef USE_AMP + /* Invalidate L2 cache line */ + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); +#endif + + /* Invalidate L1 I-cache line */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_ic_line_mva_pou(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + /* Wait for L1 I cache invalidation to complete */ + dsb(); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Enable the level 1 Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { + return; + } + + /* clean and invalidate the Data cache */ + Xil_L1DCacheInvalidate(); + + /* enable the Data cache */ + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/***************************************************************************/ +/** +* @brief Disable the level 1 Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheDisable(void) +{ + register u32 CtrlReg; + + /* clean and invalidate the Data cache */ + Xil_L1DCacheFlush(); + +#ifdef __GNUC__ + /* disable the Data cache */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 1 Data cache. +* +* @return None. +* +* @note In Cortex A9, there is no cp instruction for invalidating +* the whole D-cache. This function invalidates each line by +* set/way. +* +****************************************************************************/ +void Xil_L1DCacheInvalidate(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way, WayIndex, Set, SetIndex, NumSet; + u32 currmask; + +#ifdef __GNUC__ + u32 stack_start,stack_end,stack_size; + register u32 CtrlReg; +#endif + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + +#ifdef __GNUC__ + stack_end = (u32)&_stack_end; + stack_start = (u32)&__undef_stack; + stack_size=stack_start-stack_end; + + /* Check for the cache status. If cache is enabled, then only + * flush stack memory to save return address. If cache is disabled, + * don't flush anything as it might result in flushing stale date into + * memory which is undesirable. + * */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { + Xil_DCacheFlushRange(stack_end, stack_size); + } +#endif + +#ifdef __GNUC__ + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); + CsidReg = Reg; } +#endif + /* Determine Cache Size */ + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x07U) + 4U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + + /* Invalidate by Set/Way */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_dc_line_sw(C7Reg); +#else + /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */ + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_SW); + Reg = C7Reg; } +#endif + Set += (0x00000001U << LineSize); + } + Set=0U; + Way += 0x40000000U; + } + + /* Wait for L1 invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate a level 1 Data cache line. If the byte specified by the +* address (Addr) is cached by the Data cache, the cacheline +* containing that byte is invalidated. If the cacheline is modified +* (dirty), the modified contents are lost and are NOT written to +* system memory before the line is invalidated. +* +* @param adr: 32bit address of the data to be invalidated. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheInvalidateLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 1 Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If the +* cachelines are modified (dirty), the modified contents are lost and +* NOT written to the system memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_dc_line_mva_poc(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + + /* Wait for L1 cache invalidation to complete */ + dsb(); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the level 1 Data cache. +* +* @return None. +* +* @note In Cortex A9, there is no cp instruction for flushing +* the whole D-cache. Need to flush each line. +* +****************************************************************************/ +void Xil_L1DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way; + u32 WayIndex, Set, SetIndex, NumSet; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + +#ifdef __GNUC__ + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); + CsidReg = Reg; } +#endif + + /* Determine Cache Size */ + + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x07U) + 4U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + /* Flush by Set/Way */ + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_clean_inval_dc_line_sw(C7Reg); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW); + Reg = C7Reg; } +#endif + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += 0x40000000U; + } + + /* Wait for L1 flush to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush a level 1 Data cache line. If the byte specified by the +* address (adr) is cached by the Data cache, the cacheline containing +* that byte is invalidated. If the cacheline is modified (dirty), the +* entire contents of the cacheline are written to system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheFlushLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 flush to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Flush the level 1 Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), they are written to system memory +* before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheFlushRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + + /* Wait for L1 cache clean and invalidation to complete */ + dsb(); + } + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Store a level 1 Data cache line. If the byte specified by the +* address (adr) is cached by the Data cache and the cacheline is +* modified (dirty), the entire contents of the cacheline are written +* to system memory. After the store completes, the cacheline is +* marked as unmodified (not dirty). +* +* @param adr: Address to be stored. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheStoreLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 store to complete */ + dsb(); +} + + +/****************************************************************************/ +/** +* @brief Enable the level 1 instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) { + return; + } + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* enable the instruction cache */ + CtrlReg |= (XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/****************************************************************************/ +/** +* @brief Disable level 1 the instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheDisable(void) +{ + register u32 CtrlReg; + + dsb(); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* disable the instruction cache */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/****************************************************************************/ +/** +* @brief Invalidate the entire level 1 instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheInvalidate(void) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate a level 1 instruction cache line. If the instruction +* specified by the address is cached by the instruction cache, the +* cacheline containing that instruction is invalidated. +* +* @param adr: 32bit address of the instruction to be invalidated. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1ICacheInvalidateLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU))); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 1 instruction cache for the given address +* range. If the instrucions specified by the address range are cached +* by the instruction cache, the cacheline containing those bytes are +* invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_ic_line_mva_pou(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + + /* Wait for L1 cache invalidation to complete */ + dsb(); + } + + mtcpsr(currmask); +} + +#ifndef USE_AMP +/****************************************************************************/ +/** +* @brief Enable the L2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheEnable(void) +{ + register u32 L2CCReg; + + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + + /* only enable if L2CC is currently disabled */ + if ((L2CCReg & 0x01U) == 0U) { + /* set up the way size and latencies */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_AUX_CNTRL_OFFSET); + L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK; + L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK; + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET, + L2CCReg); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET, + XPS_L2CC_TAG_RAM_DEFAULT_MASK); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET, + XPS_L2CC_DATA_RAM_DEFAULT_MASK); + + /* Clear the pending interrupts */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_ISR_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg); + + Xil_L2CacheInvalidate(); + /* Enable the L2CC */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_CNTRL_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, + (L2CCReg | (0x01U))); + + Xil_L2CacheSync(); + /* synchronize the processor */ + dsb(); + + } +} + +/****************************************************************************/ +/** +* @brief Disable the L2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheDisable(void) +{ + register u32 L2CCReg; + + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + + if((L2CCReg & 0x1U) != 0U) { + + /* Clean and Invalidate L2 Cache */ + Xil_L2CacheFlush(); + + /* Disable the L2CC */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, + (L2CCReg & (~0x01U))); + /* Wait for the cache operations to complete */ + + dsb(); + } +} + +/*****************************************************************************/ +/** +* @brief Invalidate the entire level 2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheInvalidate(void) +{ + #ifdef __GNUC__ + u32 stack_start,stack_end,stack_size; + register u32 L2CCReg; + stack_end = (u32)&_stack_end; + stack_start = (u32)&__undef_stack; + stack_size=stack_start-stack_end; + + /* Check for the cache status. If cache is enabled, then only + * flush stack memory to save return address. If cache is disabled, + * don't flush anything as it might result in flushing stale date into + * memory which is undesirable. + */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + if ((L2CCReg & 0x01U) != 0U) { + /*Flush stack memory to save return address*/ + Xil_DCacheFlushRange(stack_end, stack_size); + } + + #endif + u32 ResultDCache; + /* Invalidate the caches */ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET, + 0x0000FFFFU); + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + while(ResultDCache != (u32)0U) { + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + } + + /* Wait for the invalidate to complete */ + Xil_L2CacheSync(); + + /* synchronize the processor */ + dsb(); +} + +/*****************************************************************************/ +/** +* @brief Invalidate a level 2 cache line. If the byte specified by the +* address (adr) is cached by the Data cache, the cacheline containing +* that byte is invalidated. If the cacheline is modified (dirty), +* the modified contents are lost and are NOT written to system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data/instruction to be invalidated. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheInvalidateLine(u32 adr) +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr); + /* synchronize the processor */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 2 cache for the given address range. +* If the bytes specified by the address range are cached by the L2 +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), the modified contents are lost and +* are NOT written to system memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + } + + /* synchronize the processor */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the entire level 2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheFlush(void) +{ + u32 ResultL2Cache; + + /* Flush the caches */ + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET, + 0x0000FFFFU); + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + + while(ResultL2Cache != (u32)0U) { + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + } + + Xil_L2CacheSync(); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + + /* synchronize the processor */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Flush a level 2 cache line. If the byte specified by the address +* (adr) is cached by the L2 cache, the cacheline containing that +* byte is invalidated. If the cacheline is modified (dirty), the +* entire contents of the cacheline are written to system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data/instruction to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheFlushLine(u32 adr) +{ +#ifdef CONFIG_PL310_ERRATA_588369 + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr); +#else + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr); +#endif + Xil_L2CacheSync(); +} + +/****************************************************************************/ +/** +* @brief Flush the level 2 cache for the given address range. +* If the bytes specified by the address range are cached by the L2 +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), they are written to the system +* memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheFlushRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Store a level 2 cache line. If the byte specified by the address +* (adr) is cached by the L2 cache and the cacheline is modified +* (dirty), the entire contents of the cacheline are written to +* system memory. After the store completes, the cacheline is marked +* as unmodified (not dirty). +* +* @param adr: 32bit address of the data/instruction to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheStoreLine(u32 adr) +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); + Xil_L2CacheSync(); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache_l.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cache_l.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_cache_l.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_errata.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_errata.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_errata.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_misc_psreset_api.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_misc_psreset_api.c new file mode 100644 index 0000000..10366fb --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_misc_psreset_api.c @@ -0,0 +1,436 @@ +/****************************************************************************** +* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_misc_psreset_api.c +* +* This file contains the implementation of the reset sequence for various +* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset +* sequence provided to the interfaces is based on the provision in +* slcr reset functional block. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 5.4	pkp	  09/11/15 Change the description for XOcm_Remap function
+*
    +* +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_misc_psreset_api.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* This function contains the implementation for ddr reset. +* +* +* @return N/A. +* +******************************************************************************/ +void XDdr_ResetHw(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert and deassert the ddr softreset bit */ + RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for remapping the ocm memory region +* to postbootrom state. +* +* @return N/A. +* +******************************************************************************/ +void XOcm_Remap(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Map the ocm region to postbootrom state */ + RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; + Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for SMC reset sequence +* +* @param BaseAddress of the interface +* +* @return N/A. +* +******************************************************************************/ +void XSmc_ResetHw(u32 BaseAddress) +{ + u32 RegVal; + + /* Clear the interuupts */ + RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); + RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK; + Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); + /* Clear the idle counter registers */ + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); + /* Update the ecc registers with reset values */ + Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, + XSMC_ECC_MEMCFG1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET, + XSMC_ECC_MEMCMD1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET, + XSMC_ECC_MEMCMD2_RESET_VAL); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr mio registers +* with reset values +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_MioWriteResetValues(void) +{ + u32 i; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Update all the MIO registers with reset values */ + for (i=0U; i<=1U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + for (; i<=8U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_02_RESET_VAL); + } + for (; i<=53U ;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr pll registers +* with reset values +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_PllWriteResetValues(void) +{ + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + + /* update the pll control registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL); + /* update the pll config registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL); + /* update the clock control registers with reset values */ + Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for disabling the level shifters +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_DisableLevelShifters(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Disable the level shifters */ + RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); + Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); + +} +/*****************************************************************************/ +/** +* This function contains the implementation for OCM software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_OcmReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for Ethernet software reset from +* the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_EmacPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for USB software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_UsbPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for QSPI software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_QspiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SPI software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_SpiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for i2c software reset from the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_I2cPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for UART software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_UartPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for CAN software reset from slcr +* registers +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_CanPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SMC software reset from the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_SmcPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for DMA controller software reset +* from the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_DmaPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for Gpio AMBA software reset from +* the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_GpioPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_mmu.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_mmu.c new file mode 100644 index 0000000..9e15c6a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_mmu.c @@ -0,0 +1,208 @@ +/****************************************************************************** +* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xil_mmu.c +* +* This file provides APIs for enabling/disabling MMU and setting the memory +* attributes for sections, in the MMU translation table. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
+*                     It fixes CR#1008309.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mmu.h" +#include "xil_errata.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024 /**< Each TTB descriptor + * covers a 1MB region */ +#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL)) +/**< Mask off lower bits of addr */ + +/************************** Variable Definitions *****************************/ + +extern u32 MMUTable; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* @brief This function sets the memory attributes for a section covering 1MB +* of memory in the translation table. +* +* @param Addr 32-bit address for which memory attributes need to be set. +* @param attrib Attribute for the given memory region. xil_mmu.h contains +* definitions of commonly used memory attributes which can be +* utilized for this function. +* +* +* @return None. +* +* @note The MMU or D-cache does not need to be disabled before changing a +* translation table entry. +* +******************************************************************************/ +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib) +{ + u32 *ptr; + u32 section; + + section = Addr / 0x100000U; + ptr = &MMUTable; + ptr += section; + if(ptr != NULL) { + *ptr = (Addr & 0xFFF00000U) | attrib; + } + + Xil_DCacheFlush(); + + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + /* Invalidate all branch predictors */ + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); + + dsb(); /* ensure completion of the BP and TLB invalidation */ + isb(); /* synchronize context on this processor */ +} + +/*****************************************************************************/ +/** +* @brief Enable MMU for cortex A9 processor. This function invalidates the +* instruction and data caches, and then enables MMU. +* +* @return None. +* +******************************************************************************/ +void Xil_EnableMMU(void) +{ + u32 Reg; + Xil_DCacheInvalidate(); + Xil_ICacheInvalidate(); + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, Reg); +#else + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + Reg = Cp15Reg; } +#endif + Reg |= (u32)0x05U; + mtcp(XREG_CP15_SYS_CONTROL, Reg); + + dsb(); + isb(); +} + +/*****************************************************************************/ +/** +* @brief Disable MMU for Cortex A9 processors. This function invalidates +* the TLBs, Branch Predictor Array and flushed the D Caches before +* disabling the MMU. +* +* @return None. +* +* @note When the MMU is disabled, all the memory accesses are treated as +* strongly ordered. +******************************************************************************/ +void Xil_DisableMMU(void) +{ + u32 Reg; + + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); + Xil_DCacheFlush(); + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, Reg); +#else + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + Reg = Cp15Reg; } +#endif + Reg &= (u32)(~0x05U); +#ifdef CONFIG_ARM_ERRATA_794073 + /* Disable Branch Prediction */ + Reg &= (u32)(~0x800U); +#endif + mtcp(XREG_CP15_SYS_CONTROL, Reg); +} + +/*****************************************************************************/ +/** +* @brief Memory mapping for Cortex A9 processor. +* +* @param PhysAddr is physical address. +* @param size is size of region. +* @param flags is flags used to set translation table. +* +* @return Pointer to virtual address. +* +* @note: Previously this was implemented in libmetal. Move to embeddedsw as this +* functionality is specific to A9 processor. +* +******************************************************************************/ +void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags) +{ + u32 Sectionoffset; + u32 Ttbaddr; + + if (!flags) + return (void*)PhysAddr; + + /* Ensure alignment on a section boundary */ + PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK; + + /* Loop through entire region of memory (one MMU section at a time). + Each section requires a TTB entry. */ + for (Sectionoffset = 0; Sectionoffset < size; + Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) { + /* Calculate translation table entry for this memory section */ + Ttbaddr = (PhysAddr + Sectionoffset); + + /* Write translation table entry value to entry address */ + Xil_SetTlbAttributes(Ttbaddr, flags); + } + return (void*)PhysAddr; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_mmu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_mmu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xil_mmu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xl2cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc_counter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc_counter.c new file mode 100644 index 0000000..ea3a08c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc_counter.c @@ -0,0 +1,133 @@ +/****************************************************************************** +* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.c +* +* This file contains APIs for configuring and controlling the event counters +* in PL310 L2 cache controller. For more information about the event counters, +* see xl2cc_counter.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include +#include "xparameters_ps.h" +#include "xl2cc_counter.h" +#include "xl2cc.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XL2cc_EventCtrReset(void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* @brief This function initializes the event counters in L2 Cache controller +* with a set of event codes specified by the user. +* +* @param Event0: Event code for counter 0. +* @param Event1: Event code for counter 1. +* +* @return None. +* +* @note The definitions for event codes XL2CC_* can be found in +* xl2cc_counter.h. +* +*****************************************************************************/ +void XL2cc_EventCtrInit(s32 Event0, s32 Event1) +{ + + /* Write event code into cnt1 cfg reg */ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2); + + /* Write event code into cnt0 cfg reg */ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2); + + /* Reset counters */ + XL2cc_EventCtrReset(); +} + + +/****************************************************************************/ +/** +* +* @brief This function starts the event counters in L2 Cache controller. +* +* @return None. +* +*****************************************************************************/ +void XL2cc_EventCtrStart(void) +{ + u32 *LocalPtr; + LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET); + XL2cc_EventCtrReset(); + + /* Enable counter */ + /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */ + *LocalPtr = (u32)1; +} + +/****************************************************************************/ +/** +* +* @brief This function disables the event counters in L2 Cache controller, +* saves the counter values and resets the counters. +* +* @param EveCtr0: Output parameter which is used to return the value +* in event counter 0. +* @param EveCtr1: Output parameter which is used to return the value +* in event counter 1. +* +* @return None. +* +*****************************************************************************/ +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1) +{ + /* Disable counter */ + *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U; + + /* Save counter values */ + *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET)); + *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET)); + + XL2cc_EventCtrReset(); +} + +/****************************************************************************/ +/** +* +* @brief This function resets the event counters in L2 Cache controller. +* +* @return None. +* +*****************************************************************************/ +void XL2cc_EventCtrReset(void) +{ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xl2cc_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xl2cc_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xpm_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xpm_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xpm_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xreg_cortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xreg_cortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xreg_cortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.c new file mode 100644 index 0000000..a2443fe --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex A9 MP core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Updated get/set time functions to make use Global Timer
+* 7.5   mus    04/30/21  Moved pragma message from xtime_l.h to xtime_l.c, to avoid
+*                        displaying same warnings multiple times. It fixes CR#1090562.
+*
    +* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) +#pragma message ("For the sleep routines, Global timer is being used") +#endif +/****************************************************************************/ +/** +* @brief Set the time in the Global Timer Counter Register. +* +* @param Xtime_Global: 64-bit Value to be written to the Global Timer +* Counter Register. +* +* @return None. +* +* @note When this function is called by any one processor in a multi- +* processor environment, reference time will reset/lost for all +* processors. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ + /* Disable Global Timer */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0); + + /* Updating Global Timer Counter Register */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET, + (u32)((u32)(Xtime_Global>>32U))); + + /* Enable Global Timer */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1); +} + +/****************************************************************************/ +/** +* @brief Get the time from the Global Timer Counter Register. +* +* @param Xtime_Global: Pointer to the 64-bit location which will be +* updated with the current timer value. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + u32 low; + u32 high; + + /* Reading Global Timer Counter Register */ + do + { + high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET); + low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET); + } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high); + + *Xtime_Global = (((XTime) high) << 32U) | (XTime) low; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.h new file mode 100644 index 0000000..9d17f5c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexa9/xtime_l.h @@ -0,0 +1,86 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Updated get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Updated get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
+* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
+* 7.5   mus    04/30/21  Moved pragma message from xtime_l.h to xtime_l.c, to avoid
+*                        displaying same warnings multiple times. It fixes CR#1090562.
+*
    +* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +#endif +/************************** Variable Definitions *****************************/ + +/** +*@endcond +*/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/armclang/ARM_argv_veneer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/armclang/ARM_argv_veneer.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/armclang/ARM_argv_veneer.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/armclang/ARM_argv_veneer.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/armclang/Makefile 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/versal-net/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/versal-net/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/versal-net/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/versal-net/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/versal-net/mpu_r52.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/versal-net/mpu_r52.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/versal-net/mpu_r52.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/versal-net/mpu_r52.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/platform/versal/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/platform/versal/CMakeLists.txt similarity index 100% rename from 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/xil_mmu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/xil_mmu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/xil_mmu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/cortexr5/xpm_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/cortexr5/xpm_counter.h rename to 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a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/platform/versal_net/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/platform/versal_net/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/platform/versal_net/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/platform/versal_net/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/platform/versal_net/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/platform/versal_net/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/arm/platform/versal_net/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/arm/platform/versal_net/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/asm_vectors.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/asm_vectors.S new file mode 100644 index 0000000..9be0b25 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/asm_vectors.S @@ -0,0 +1,176 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.S +* +* This file contains the initial vector table for the Cortex A9 processor +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.00a pkp	22/01/14 Modified return addresses for interrupt
+*			 handlers (DataAbortHandler and SVCHandler)
+*			 to fix CR#767251
+* 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+*			 abort and prefetch abort into DataAbortAddr and
+*			 PrefetchAbortAddr for further use to fix CR#854523
+* 5.4	pkp	12/03/15 Added handler for undefined exception
+* 6.8	mus	04/27/18 Removed __ARM_NEON__ flag definition. Now,
+*			 saving/restoring of of HW floating point register
+*			 would be done through newly introduced flag
+*			 FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
+*			 configured based on the -mfpu-abi option in extra
+*			 compiler flags.
+*
    +* +* @note +* +* None. +* +******************************************************************************/ +#include "xil_errata.h" +#include "bspconfig.h" + +.org 0 +.text + +.globl _vector_table + +.section .vectors +_vector_table: + B _boot + B Undefined + B SVCHandler + B PrefetchAbortHandler + B DataAbortHandler + NOP /* Placeholder for address exception vector*/ + B IRQHandler + B FIQHandler + + +IRQHandler: /* IRQ vector handler */ + + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ +#if FPU_HARD_FLOAT_ABI_ENABLED + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif + +#ifdef PROFILING + ldr r2, =prof_pc + subs r3, lr, #0 + str r3, [r2] +#endif + + bl IRQInterrupt /* IRQ vector */ + +#if FPU_HARD_FLOAT_ABI_ENABLED + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} +#endif + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + + subs pc, lr, #4 /* adjust return */ + + +FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +#if FPU_HARD_FLOAT_ABI_ENABLED + vpush {d0-d7} + vpush {d16-d31} + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif + +FIQLoop: + bl FIQInterrupt /* FIQ vector */ + +#if FPU_HARD_FLOAT_ABI_ENABLED + pop {r1} + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d16-d31} + vpop {d0-d7} +#endif + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + + +Undefined: /* Undefined handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =UndefinedExceptionAddr + sub r1, lr, #4 + str r1, [r0] /* Store address of instruction causing undefined exception */ + + bl UndefinedException /* UndefinedException: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + movs pc, lr + +SVCHandler: /* SWI handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + + tst r0, #0x20 /* check the T bit */ + ldrneh r0, [lr,#-2] /* Thumb mode */ + bicne r0, r0, #0xff00 /* Thumb mode */ + ldreq r0, [lr,#-4] /* ARM mode */ + biceq r0, r0, #0xff000000 /* ARM mode */ + + bl SWInterrupt /* SWInterrupt: call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + movs pc, lr /*return to the next instruction after the SWI instruction */ + + +DataAbortHandler: /* Data Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =DataAbortAddr + sub r1, lr, #8 + str r1, [r0] /* Stores instruction causing data abort */ + + bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */ + +PrefetchAbortHandler: /* Prefetch Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + ldr r0, =PrefetchAbortAddr + sub r1, lr, #4 + str r1, [r0] /* Stores instruction causing prefetch abort */ + + bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ + + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + + subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */ + +.end diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/boot.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/boot.S new file mode 100644 index 0000000..5305e14 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/boot.S @@ -0,0 +1,447 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file boot.S +* +* @addtogroup a9_boot_code Cortex A9 Processor Boot Code +* @{ +*

    boot.S

    +* The boot code performs minimum configuration which is required for an +* application to run starting from processor reset state of the processor. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function. +* +* 1. Program vector table base for exception handling +* 2. Invalidate instruction cache, data cache and TLBs +* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, +* abort, system) +* 4. Configure MMU with short descriptor translation table format and program +* base address of translation table +* 5. Enable data cache, instruction cache and MMU +* 6. Enable Floating point unit +* 7. Transfer control to _start which clears BSS sections, initializes +* global timer and runs global constructor before jumping to main +* application +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+*			 register settings.
+* 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+*		         register settings.
+* 3.07a asa     07/16/12 Modified the L2 Cache controller settings to improve
+*			 performance. Changed the property of the ".boot"
+*			 section.
+* 3.07a sgd     08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+*               Register settings
+* 3.09a sgd     02/06/13 Updated SLCR l2c Ram Control register to a
+*               value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.2   pkp	06/19/14 Enabled asynchronous abort exception
+* 5.0	pkp	16/15/14 Modified initialization code to enable scu after
+*			 MMU is enabled
+* 5.1   pkp	05/13/15 Changed the initialization order so to first invalidate
+*			 caches and TLB, enable MMU and caches, then enable SMP
+*			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+*			 is done later.
+* 5.4   asa     12/6/15  Added code to initialize SPSR for all relevant modes.
+* 6.0   mus     08/04/16 Added code to detect zynq-7000 base silicon configuration and
+*                        attempt to enable dual core behavior on single cpu zynq-7000s
+*                        devices is prevented from corrupting system behavior.
+* 6.0   mus     08/24/16 Check CPU core before putting cpu1 to reset for single core
+*                        zynq-7000s devices
+* 7.6   mus     09/02/21 SCU invalidation should be done only from primary CPU, so
+*                        skipping it when USE_AMP is set to 1. It fixes CR#1109723
+* 7.7   asa     01/06/22 Removed Cortex-A9 errata handling for errata
+* 			 742230 and 743622. These do not apply to
+* 			 Cortex-A9 revision r3p0 being used in Zynq
+* 			 platforms.
+* 9.0   mus     07/27/23 Removed dependency on XPAR_CPU_ID, updated logic to use
+*                        CPU affinity register to read CPU ID.
+*
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif +#include "xil_errata.h" + +.globl MMUTable +.global _prestart +.global _boot +.global __stack +.global __irq_stack +.global __supervisor_stack +.global __abort_stack +.global __fiq_stack +.global __undef_stack +.global _vector_table + +.set PSS_L2CC_BASE_ADDR, 0xF8F02000 +.set PSS_SLCR_BASE_ADDR, 0xF8000000 + +.set RESERVED, 0x0fffff00 +.set TblBase , MMUTable +.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */ +.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/ +.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/ +.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/ +.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/ +.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/ +.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/ +.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/ +.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/ + +.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ +.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ +.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ +.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/ +.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/ + +/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ +.if SIM_MODE == 1 +.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */ +.else +.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */ +.endif + +.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */ + +.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, + Event monitor bus enable and Way Size (64 KB) */ +.set L2CCControl, 0x01 /* Enable L2CC */ +.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */ +.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */ + +.set SLCRlockKey, 0x767B /* SLCR lock key */ +.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */ +.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */ + +/* Stack Pointer locations for boot code */ +.set Undef_stack, __undef_stack +.set FIQ_stack, __fiq_stack +.set Abort_stack, __abort_stack +.set SPV_stack, __supervisor_stack +.set IRQ_stack, __irq_stack +.set SYS_stack, __stack + +.set vector_base, _vector_table + +.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */ + +.section .boot,"ax" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + /* only allow cpu0 through */ + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #0 + beq CheckEFUSE + b OKToRun + +CheckEFUSE: + ldr r0,=EFUSEStaus + ldr r1,[r0] /* Read eFuse setting */ + ands r1,r1,#0x80 /* Check whether device is having single core */ + beq OKToRun + + /* single core device, reset cpu1 */ + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRCPURSTReg + ldr r1,[r0] /* Read CPU Software Reset Control register */ + orr r1,r1,#0x22 + str r1,[r0] /* Reset CPU1 */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + +OKToRun: + mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ + and r5, r0, #0x00f00000 + and r6, r0, #0x0000000f + orr r6, r6, r5, lsr #20-4 + + /* set VBAR to the _vector_table address in linker script */ + ldr r0, =vector_base + mcr p15, 0, r0, c12, c0, 0 + + /*invalidate scu*/ +#if USE_AMP!=1 + ldr r7, =0xf8f0000c + ldr r6, =0xffff + str r6, [r7] +#endif + + /* Invalidate caches and TLBs */ + mov r0,#0 /* r0 = 0 */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ + bl invalidate_dcache /* invalidate dcache */ + + /* Disable MMU, if enabled */ + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ + bic r0, r0, #0x1 /* clear bit 0 */ + mcr p15, 0, r0, c1, c0, 0 /* write value back */ + +#ifdef SHAREABLE_DDR + /* Mark the entire DDR memory as shareable */ + ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */ + ldr r0, =TblBase /* MMU Table address in memory */ + ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +shareable_loop: + str r2, [r0] /* write the entry to MMU table */ + add r0, r0, #0x4 /* next entry in the table */ + add r2, r2, #0x100000 /* next section */ + subs r3, r3, #1 + bge shareable_loop /* loop till 1G is covered */ +#endif + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the irq stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x12 /* IRQ mode */ + msr cpsr, r2 + ldr r13,=IRQ_stack /* IRQ stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the supervisor stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x13 /* supervisor mode */ + msr cpsr, r2 + ldr r13,=SPV_stack /* Supervisor stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Abort stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x17 /* Abort mode */ + msr cpsr, r2 + ldr r13,=Abort_stack /* Abort stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the FIQ stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x11 /* FIQ mode */ + msr cpsr, r2 + ldr r13,=FIQ_stack /* FIQ stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the Undefine stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1b /* Undefine mode */ + msr cpsr, r2 + ldr r13,=Undef_stack /* Undefine stack pointer */ + bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ + msr spsr_fsxc,r2 + + mrs r0, cpsr /* get the current PSR */ + mvn r1, #0x1f /* set up the system stack pointer */ + and r2, r1, r0 + orr r2, r2, #0x1F /* SYS mode */ + msr cpsr, r2 + ldr r13,=SYS_stack /* SYS stack pointer */ + + /*set scu enable bit in scu*/ + ldr r7, =0xf8f00000 + ldr r0, [r7] + orr r0, r0, #0x1 + str r0, [r7] + + /* enable MMU and cache */ + + ldr r0,=TblBase /* Load MMU translation table base */ + orr r0, r0, #0x5B /* Outer-cacheable, WB */ + mcr 15, 0, r0, c2, c0, 0 /* TTB0 */ + + mvn r0,#0 /* Load MMU domains -- all ones=manager */ + mcr p15,0,r0,c3,c0,0 + + /* Enable mmu, icahce and dcache */ + ldr r0,=CRValMmuCac + mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */ + dsb /* dsb allow the MMU to start up */ + isb /* isb flush prefetch buffer */ + + /* Write to ACTLR */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + orr r0, r0, #(0x01 << 6) /* set SMP bit */ + orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + +/* Invalidate L2 Cache and enable L2 Cache*/ +/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */ +#if USE_AMP!=1 + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + mov r1, #0 /* force the disable bit */ + str r1, [r0] /* disable the L2 Caches */ + + ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */ + ldr r1,[r0] /* read the register */ + ldr r2,=L2CCAuxControl /* set the default bits */ + orr r1,r1,r2 + str r1, [r0] /* store the Aux Control Register */ + + ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */ + ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/ + str r1, [r0] /* store the TAG Latency register Register */ + + ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */ + ldr r1,=L2CCDataLatency /* set the latencies for the Data*/ + str r1, [r0] /* store the Data Latency register Register */ + + ldr r0,=L2CCWay /* Load L2CC base address base + way register*/ + ldr r2, =0xFFFF + str r2, [r0] /* force invalidate */ + + ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */ + /* Load L2CC base address base + sync register*/ + /* poll for completion */ +Sync: ldr r1, [r0] + cmp r1, #0 + bne Sync + + ldr r0,=L2CCIntRaw /* clear pending interrupts */ + ldr r1,[r0] + ldr r0,=L2CCIntClear + str r1,[r0] + + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ + ldr r1,=SLCRL2cRamConfig /* set the configuration value */ + str r1, [r0] /* store the L2c Ram Control Register */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + ldr r1,[r0] /* read the register */ + mov r2, #L2CCControl /* set the enable bit */ + orr r1,r1,r2 + str r1, [r0] /* enable the L2 Caches */ +#endif + + mov r0, r0 + mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */ + orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */ + mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */ + + /* enable vfp */ + fmrx r1, FPEXC /* read the exception register */ + orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */ + fmxr FPEXC, r1 /* write back the exception register */ + + mrc p15,0,r0,c1,c0,0 /* flow prediction enable */ + orr r0, r0, #(0x01 << 11) /* #0x8000 */ + mcr p15,0,r0,c1,c0,0 + + mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */ + orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */ + orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */ + mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */ + + mrs r0, cpsr /* get the current PSR */ + bic r0, r0, #0x100 /* enable asynchronous abort exception */ + msr cpsr_xsf, r0 + + + b _start /* jump to C startup code */ + and r0, r0, r0 /* no op */ + +.Ldone: b .Ldone /* Paranoia: we should never get here */ + + +/* + ************************************************************************* + * + * invalidate_dcache - invalidate the entire d-cache by set/way + * + * Note: for Cortex-A9, there is no cp instruction for invalidating + * the whole D-cache. Need to invalidate each line. + * + ************************************************************************* + */ +invalidate_dcache: + mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ + beq finished + mov r10, #0 /* start with level 0 */ +loop1: + add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ + mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ + and r1, r1, #7 /* get those 3 bits alone */ + cmp r1, #2 + blt skip /* no cache or only instruction cache at this level */ + mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ + isb /* isb to sync the change to the CacheSizeID reg */ + mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ + and r2, r1, #7 /* extract the line length field */ + add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ + clz r5, r4 /* r5 is the bit position of the way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ +loop2: + mov r9, r4 /* r9 working copy of the max way size (right aligned) */ +loop3: + orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ + orr r11, r11, r7, lsl r2 /* factor in the index number */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way number */ + bge loop3 + subs r7, r7, #1 /* decrement the index */ + bge loop2 +skip: + add r10, r10, #2 /* increment the cache number */ + cmp r3, r10 + bgt loop1 + +finished: + mov r10, #0 /* switch back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + dsb + isb + + bx lr + +.end +/** +* @} End of "addtogroup a9_boot_code". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h new file mode 100644 index 0000000..5498919 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h @@ -0,0 +1,24 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + +#define MICROBLAZE_PVR_NONE + +/* Definition for hard-float ABI */ +#define FPU_HARD_FLOAT_ABI_ENABLED 1 + +#endif /*end of __BSPCONFIG_H_*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/bspconfig.h.in b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h.in similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/bspconfig.h.in rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/bspconfig.h.in diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/changelog.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/changelog.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/changelog.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/changelog.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/close.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/close.c new file mode 100644 index 0000000..50f10a0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/close.c @@ -0,0 +1,27 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#ifndef UNDEFINE_FILE_OPS +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _close(s32 fd); + +#ifdef __cplusplus +} +#endif + +/* + * close -- We don't need to do anything, but pretend we did. + */ + +__attribute__((weak)) s32 _close(s32 fd) +{ + (void)fd; + return (0); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/inbyte.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/inbyte.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/inbyte.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/inbyte.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/CMakeLists.txt new file mode 100644 index 0000000..755890f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT + + +set(INTC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../../../intc/src/") +set(SCUGIC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../../../scugic/src/") +find_package(INTC QUIET) +set(defs "") +list(APPEND defs "#ifndef XCOMMON_DRV_CONFIG_H_\n") +list(APPEND defs "#define XCOMMON_DRV_CONFIG_H_\n\n") +if ((EXISTS "${INTC_DIR}/INTCConfig.cmake") AND + DRIVER_INSTANCES) + list(APPEND defs "#define XPAR_AXI_INTC\n") +endif() + +find_package(SCUGIC QUIET) +if ((EXISTS "${SCUGIC_DIR}/SCUGICConfig.cmake") AND + DRIVER_INSTANCES) + list(APPEND defs "#define XPAR_SCUGIC\n") +endif() +list(APPEND defs "\n#endif") +file(WRITE ${CMAKE_CURRENT_SOURCE_DIR}/xcommon_drv_config.h ${defs}) +collect (PROJECT_LIB_SOURCES xinterrupt_wrap.c) +collect (PROJECT_LIB_HEADERS xinterrupt_wrap.h) +collect (PROJECT_LIB_HEADERS xcommon_drv_config.h) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/xinterrupt_wrap.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/xinterrupt_wrap.c new file mode 100644 index 0000000..10f339e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/xinterrupt_wrap.c @@ -0,0 +1,455 @@ +/****************************************************************************** +* Copyright (c) 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xinterrupt_wrap.c +* +* The xinterrupt_wrap.c file contains interrupt related functions and macros. +* Contains wrapper functions for the scugic/axi intc Interrupt controller +* drivers. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2   mus  22/11/21 First release of xil interrupt support
+* 9.0   adk  17/04/23 Added support for system device-tree flow
+* 9.0   adk  27/04/23 Use XScuGic_LookupConfigBaseAddr() API for xsct flow
+*
    +* +******************************************************************************/ + +#include "xinterrupt_wrap.h" + +#ifdef XIL_INTERRUPT + +#if defined (XPAR_SCUGIC) /* available in xscugic.h */ +static XScuGic XScuGicInstance; +static int ScuGicInitialized; +#endif + +#if defined (XPAR_AXI_INTC) /* available in xintc.h */ +static XIntc XIntcInstance ; +#endif + +/*****************************************************************************/ +/** +* +* @brief Initializes the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConfigInterruptCntrl(UINTPTR IntcParent) +{ + int Status = XST_FAILURE; + UINTPTR BaseAddr = XGet_BaseAddr(IntcParent); + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Config *CfgPtr = NULL; + if (XScuGicInstance.IsReady != XIL_COMPONENT_IS_READY) { +#if defined(SDT) + CfgPtr = XScuGic_LookupConfig(BaseAddr); +#else + CfgPtr = XScuGic_LookupConfigBaseAddr(BaseAddr); +#endif + if (!ScuGicInitialized) { + Status = XScuGic_CfgInitialize(&XScuGicInstance, CfgPtr, 0); + } else { + Status = XST_SUCCESS; + } + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Initialize(&XIntcInstance, BaseAddr); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief connects to the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntrHandler: Interrupt handler. +* @param CallBackRef: Callback reference for handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent) +{ + int Status; + int Doconnect = FALSE; + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (ScuGicInitialized) { + Doconnect = 1; + } + if (Doconnect) { + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + Status = XScuGic_Connect(&XScuGicInstance, IntrNum, \ + (Xil_ExceptionHandler) IntrHandler, CallBackRef); + return Status; + } else { + return XST_SUCCESS; + } +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + Status = XIntc_Connect(&XIntcInstance, IntrNum, \ + (XInterruptHandler)IntrHandler, CallBackRef); + return Status; +#else + return XST_FAILURE; +#endif + + } +} + +/*****************************************************************************/ +/** +* +* @brief disconnects the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disconnect(&XScuGicInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Disconnect(&XIntcInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* @brief Starts the interrupt controller. +* +* @param Mode: Interrupt controller mode type. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent) +{ +#if defined (XPAR_AXI_INTC) + int Status = XST_FAILURE; +#else + (void) Mode; +#endif + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + /* + * For XPAR_SCUGIC, XConfigInterruptCntrl starts controller + * hence returning without doing anything + */ + return 0; + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Start(&XIntcInstance, Mode); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + + } + +} + +/*****************************************************************************/ +/** +* +* @brief Enable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XEnableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + IntrNum += Offset; + XScuGic_Enable(&XScuGicInstance, IntrNum); +#endif + + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Enable(&XIntcInstance, IntrNum); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief disable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDisableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disable(&XScuGicInstance, IntrNum); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Disable(&XIntcInstance, IntrId); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Configures the priority and trigger type. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent) +{ +#if defined (XPAR_SCUGIC) + u8 Trigger = (((XGet_TriggerType(IntrId) == 1) || + (XGet_TriggerType(IntrId) == 2)) ? XINTR_IS_EDGE_TRIGGERED + : XINTR_IS_LEVEL_TRIGGERED); + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + XScuGic_SetPriorityTriggerType(&XScuGicInstance, IntrNum, Priority, Trigger); + } +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Gets the priority of the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param Trigger: Trigger type of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_GetPriorityTriggerType(&XScuGicInstance, IntrId, Priority, Trigger); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief stops the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XStopInterruptCntrl( UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Stop(&XScuGicInstance); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Stop(&XIntcInstance); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief Registers the interrupt handler. +* +* @param IntrHandler: Interrupt handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XRegisterInterruptHandler(void *IntrHandler, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XScuGic_InterruptHandler, + &XScuGicInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XScuGicInstance); + + } +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XIntc_InterruptHandler, + &XIntcInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XIntcInstance); + } +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Setup the interrupt system. +* +* @param DriverInstance: Driver instance pointer. +* @param IntrHandler: Interrupt handler funtion pointer. +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* @param Priority: Interrupt priority. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent, u16 Priority) +{ + int Status; + + Status = XConfigInterruptCntrl(IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_SCUGIC) + ScuGicInitialized = TRUE; +#endif + XSetPriorityTriggerType( IntrId, Priority, IntcParent); + Status = XConnectToInterruptCntrl( IntrId, (Xil_ExceptionHandler) IntrHandler, \ + DriverInstance, IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_AXI_INTC) + XStartInterruptCntrl(XIN_REAL_MODE, IntcParent); +#endif + XRegisterInterruptHandler(NULL, IntcParent); + XEnableIntrId(IntrId, IntcParent); + Xil_ExceptionInit(); + Xil_ExceptionEnable(); + return XST_SUCCESS; +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/xinterrupt_wrap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xinterrupt_wrap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/intr/xinterrupt_wrap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/outbyte.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/outbyte.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/outbyte.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/outbyte.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/pm_api_version.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/pm_api_version.h new file mode 100644 index 0000000..d5d2838 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/pm_api_version.h @@ -0,0 +1,269 @@ +/****************************************************************************** +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * @file pm_api_version.h + * + * @addtogroup xpm_versal_apis XilPM APIs + *****************************************************************************/ + + +#ifndef PM_API_VERSION_H_ +#define PM_API_VERSION_H_ + +/*****************************************************************************/ +/** + * @section EEMI_API_DETAIL XilPM EEMI API Version Detail + * + * This section provides details of EEMI API version and it's history for PM APIs of XilPM library. + * + * | NAME | ID | Platform | Version| Description | + * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------| + * | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API | + * | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device | + * | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality | + * | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event | + * | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem | + * | PM_SELF_SUSPEND | 0x7 | Both | 2 | V1 - The API is used to suspend a child subsystem | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem | + * | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem | + * | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source | + * | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system | + * | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use | + * | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device | + * | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device | + * | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state | + * | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices | + * | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip | + * | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin | + * | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin | + * | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function | + * | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function | + * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value | + * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value | + * | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 | + * | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 | + * | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock | + * | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock | + * | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state | + * | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock | + * | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider | + * | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock | + * | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent | + * | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock | + * | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock | + * | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock | + * | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock | + * | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail + * + * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|---------------------------------------| + * | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode | + * | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode | + * | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config | + * | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config | + * | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass | + * | IOCTL_SET_SGMII_MODE | 5 | ZynqMP | SGMII mode | + * | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset | + * | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay | + * | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode | + * | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode | + * | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data | + * | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data | + * | IOCTL_WRITE_GGS | 12 | Both | Write GGS | + * | IOCTL_READ_GGS | 13 | Both | Read GGS | + * | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS | + * | IOCTL_READ_PGGS | 15 | Both | Read PGGS | + * | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset | + * | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status | + * | IOCTL_AFI | 18 | ZynqMP | AFI | + * | IOCTL_PROBE_COUNTER_READ | 19 | Versal | Probe counter read | + * | IOCTL_PROBE_COUNTER_WRITE | 20 | Versal | Probe counter write | + * | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select | + * | IOCTL_USB_SET_STATE | 22 | Versal | USB set state | + * | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason | + * | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear | + * | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF | + * | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config | + * | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config | + * | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register | + * | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register | + * | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value | + * | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value | + * | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value | + * | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations | + * | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value | + * | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode | + * | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode | + * | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down | + * | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail + * + * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |--------------------------------------------|-------|---------------|---------------------------------------| + * | XPM_QID_INVALID | 0 | Both | Invalid Query ID | + * | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name | + * | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology | + * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter | + * | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources | + * | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes | + * | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups | + * | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name | + * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups | + * | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups | + * | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks | + * | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor | + * | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent | + * | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes | + * + *****************************************************************************/ + + +/*****************************************************************************/ +/** + * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail + * + * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|-----------------------------------------------| + * | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power | + * | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature | + * | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency | + * + *****************************************************************************/ + + +/** + * PM API IDs + */ +typedef enum { + PM_API_MIN, /**< 0x0 */ + PM_GET_API_VERSION, /**< 0x1 */ + PM_SET_CONFIGURATION, /**< 0x2 */ + PM_GET_NODE_STATUS, /**< 0x3 */ + PM_GET_OP_CHARACTERISTIC, /**< 0x4 */ + PM_REGISTER_NOTIFIER, /**< 0x5 */ + PM_REQUEST_SUSPEND, /**< 0x6 */ + PM_SELF_SUSPEND, /**< 0x7 */ + PM_FORCE_POWERDOWN, /**< 0x8 */ + PM_ABORT_SUSPEND, /**< 0x9 */ + PM_REQUEST_WAKEUP, /**< 0xA */ + PM_SET_WAKEUP_SOURCE, /**< 0xB */ + PM_SYSTEM_SHUTDOWN, /**< 0xC */ + PM_REQUEST_NODE, /**< 0xD */ + PM_RELEASE_NODE, /**< 0xE */ + PM_SET_REQUIREMENT, /**< 0xF */ + PM_SET_MAX_LATENCY, /**< 0x10 */ + PM_RESET_ASSERT, /**< 0x11 */ + PM_RESET_GET_STATUS, /**< 0x12 */ + PM_MMIO_WRITE, /**< 0x13 */ + PM_MMIO_READ, /**< 0x14 */ + PM_INIT_FINALIZE, /**< 0x15 */ + PM_FPGA_LOAD, /**< 0x16 */ + PM_FPGA_GET_STATUS, /**< 0x17 */ + PM_GET_CHIPID, /**< 0x18 */ + PM_SECURE_RSA_AES, /**< 0x19 */ + PM_SECURE_SHA, /**< 0x1A */ + PM_SECURE_RSA, /**< 0x1B */ + PM_PINCTRL_REQUEST, /**< 0x1C */ + PM_PINCTRL_RELEASE, /**< 0x1D */ + PM_PINCTRL_GET_FUNCTION, /**< 0x1E */ + PM_PINCTRL_SET_FUNCTION, /**< 0x1F */ + PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */ + PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */ + PM_IOCTL, /**< 0x22 */ + PM_QUERY_DATA, /**< 0x23 */ + PM_CLOCK_ENABLE, /**< 0x24 */ + PM_CLOCK_DISABLE, /**< 0x25 */ + PM_CLOCK_GETSTATE, /**< 0x26 */ + PM_CLOCK_SETDIVIDER, /**< 0x27 */ + PM_CLOCK_GETDIVIDER, /**< 0x28 */ + PM_CLOCK_SETRATE, /**< 0x29 */ + PM_CLOCK_GETRATE, /**< 0x2A */ + PM_CLOCK_SETPARENT, /**< 0x2B */ + PM_CLOCK_GETPARENT, /**< 0x2C */ + PM_SECURE_IMAGE, /**< 0x2D */ + PM_FPGA_READ, /**< 0x2E */ + PM_SECURE_AES, /**< 0x2F */ + PM_PLL_SET_PARAMETER, /**< 0x30 */ + PM_PLL_GET_PARAMETER, /**< 0x31 */ + PM_PLL_SET_MODE, /**< 0x32 */ + PM_PLL_GET_MODE, /**< 0x33 */ + PM_REGISTER_ACCESS, /**< 0x34 */ + PM_EFUSE_ACCESS, /**< 0x35 */ + PM_ADD_SUBSYSTEM, /**< 0x36 */ + PM_DESTROY_SUBSYSTEM, /**< 0x37 */ + PM_DESCRIBE_NODES, /**< 0x38 */ + PM_ADD_NODE, /**< 0x39 */ + PM_ADD_NODE_PARENT, /**< 0x3A */ + PM_ADD_NODE_NAME, /**< 0x3B */ + PM_ADD_REQUIREMENT, /**< 0x3C */ + PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */ + PM_INIT_NODE, /**< 0x3E */ + PM_FEATURE_CHECK, /**< 0x3F */ + PM_ISO_CONTROL, /**< 0x40 */ + PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */ + PM_SET_NODE_ACCESS, /**< 0x42 */ + PM_BISR, /**< 0x43 */ + PM_APPLY_TRIM, /**< 0x44 */ + PM_NOC_CLOCK_ENABLE, /**< 0x45 */ + PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */ + PM_FORCE_HOUSECLEAN, /**< 0x47 */ + PM_FPGA_GET_VERSION, /**< 0x48 */ + PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */ + PM_API_MAX /**< 0x4A */ +} XPm_ApiId; + +#endif /* PM_API_VERSION_H_ */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/print.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/print.c new file mode 100644 index 0000000..cb66494 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/print.c @@ -0,0 +1,39 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + *****************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_printf.h" + +/*****************************************************************************/ +/** +* print -- do a raw print of a string +* +******************************************************************************/ +void print(const char8 *ptr) +{ +#if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE) + XPVXenConsole_Write(ptr); +#else +#if defined(STDOUT_BASEADDRESS) || defined(SDT) + while (*ptr != (char8)0) { + outbyte (*ptr); + ptr++; + } +#else +(void)ptr; +#endif +#endif +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xiltimer/src/sleep.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/sleep.h similarity index 52% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xiltimer/src/sleep.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/sleep.h index fd70448..0d881b6 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xiltimer/src/sleep.h +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/sleep.h @@ -1,25 +1,37 @@ /****************************************************************************** -* -* Copyright (C) 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT -* ******************************************************************************/ + /*****************************************************************************/ /** * @file sleep.h * -* This header file contains sleep related APIs. +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. * * 
     * MODIFICATION HISTORY :
 *
 * Ver   Who  Date	 Changes
 * ----- ---- -------- -------------------------------------------------------
-*  1.0  adk	 24/11/21 Initial release.
-*  1.2  adk	 22/12/22 Fixed doxygen style and indentation issues.
-*
+* 6.6   srm  11/02/17 Added processor specific sleep routines
+*								 function prototypes.
+* 7.7	sk   01/10/22 Typecast sleep declaration argument from unsigned int to
+* 		      u32 to fix misra_c_2012_directive_4_6 violation.
+* 7.7	sk   01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
+* 		      unsigned to void to fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk   03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
+*		      c_2012_directive_4_6 violation.
+* 8.0	sk   03/17/22 Modify the return type of usleep_MB from int to void and
+*		      sleep_MB from unsigned to void to fix misra_c_2012_rule_
+*		      17_7 violation.
+* 8.0	sk   03/17/22 Modify sleep_MB parameter type from unsigned int to
+*		      u32 and usleep_MB parameter type from unsigned long to
+*		      ULONG to fix misra_c_2012_rule_4_6 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
 *
    * ******************************************************************************/ @@ -51,9 +63,8 @@ extern "C" { * @param COND - Condition to checked (usually involves VALUE) * @param TIMEOUT_US - timeout in micro seconds * -* @return -* - 0 - when the condition is met -* - 1 - when the condition is not met till the timeout period +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period * * @note none * @@ -77,8 +88,19 @@ extern "C" { (timeout>0) ? 0 : -1; \ } ) -void usleep(unsigned long useconds); -void sleep(unsigned int seconds); +/************************** Function Prototypes ******************************/ +void usleep(ULONG useconds); +void sleep(u32 seconds); +void usleep_R5(ULONG useconds); +void sleep_R5(u32 seconds); +void usleep_MB(ULONG useconds); +void sleep_MB(u32 seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +/*****************************************************************************/ #ifdef __cplusplus } diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/CMakeLists.txt new file mode 100644 index 0000000..00f7985 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT +collect (PROJECT_LIB_HEADERS xil_error_node.h) +collect (PROJECT_LIB_HEADERS xil_hw.h) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_error_node.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_error_node.h new file mode 100644 index 0000000..7a15448 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_error_node.h @@ -0,0 +1,491 @@ +/****************************************************************************** +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_error_node.h +* +* This is the file which contains node IDs information for error events. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who 	 Date        Changes
+* ----- -------- -------- -----------------------------------------------------
+* 7.7   bsv      12/22/2021 Initial release
+*       ma       01/17/2022 Add PLM exceptions to SW errors list
+* 7.8   rama     06/28/2022 Add XilSem errors to SW error events
+* 7.9   rama     07/19/2023 Add STL errors to SW error events
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef XIL_ERROR_NODE_H +#define XIL_ERROR_NODE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/**@name Versal Event Node IDs + * @defgroup xileventnodes Event Node IDs + * @ingroup xilnodeids + * @{ + */ + +#define XIL_NODETYPE_EVENT_ERROR_ID_ENCODING (0x28100000U) + + /** + * Error Event Node Ids + */ +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR1 (0x28100000U) +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR2 (0x28104000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR1 (0x28108000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR2 (0x2810C000U) +#define XIL_NODETYPE_EVENT_ERROR_SW_ERR (0x28110000U) +/** + * @} + */ + +/**@name Versal Error event Mask + * @defgroup xilerroreventmask Error Event Mask + * @ingroup xilnodeids + * @{ + * @defgroup pmcerr1 Error Event Mask for PMC ERR1 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PMC ERR1 Node + */ + +/** Error event mask for PMC Boot Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_CR (0x00000001U) + +/** Error event mask for PMC Boot Non-Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_NCR (0x00000002U) + +/** Error event mask for PMC Firmware Boot Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_CR (0x00000004U) + +/** Error event mask for PMC Firmware Boot Non-Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_NCR (0x00000008U) + +/** Error event mask for General Software Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_CR (0x00000010U) + +/** Error event mask for General Software Non-Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_NCR (0x00000020U) + +/** Error event mask for CFU Error. */ +#define XIL_EVENT_ERROR_MASK_CFU (0x00000040U) + +/** Error event mask for CFRAME Error. */ +#define XIL_EVENT_ERROR_MASK_CFRAME (0x00000080U) + +/** Error event mask for PSM Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_CR (0x00000100U) + +/** Error event mask for PSM Non-Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_NCR (0x00000200U) + +/** Error event mask for DDRMC MB Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_CR (0x00000400U) + +/** Error event mask for DDRMC MB Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_NCR (0x00000800U) + +/** Error event mask for NoC Type1 Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_CR (0x00001000U) + +/** Error event mask for NoC Type1 Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_NCR (0x00002000U) + +/** Error event mask for NoC User Error. */ +#define XIL_EVENT_ERROR_MASK_NOCUSER (0x00004000U) + +/** Error event mask for MMCM Lock Error. */ +#define XIL_EVENT_ERROR_MASK_MMCM (0x00008000U) + +/** Error event mask for ME Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_CR (0x00010000U) + +/** Error event mask for ME Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_NCR (0x00020000U) + +/** Error event mask for DDRMC MC Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_CR (0x00040000U) + +/** Error event mask for DDRMC MC Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_NCR (0x00080000U) + +/** Error event mask for GT Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_CR (0x00100000U) + +/** Error event mask for GT Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_NCR (0x00200000U) + +/** Error event mask for PL Sysmon Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_CR (0x00400000U) + +/** Error event mask for PL Sysmon Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_NCR (0x00800000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL0 (0x01000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL1 (0x02000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL2 (0x04000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL3 (0x08000000U) + +/** Error event mask for NPI Root Error. */ +#define XIL_EVENT_ERROR_MASK_NPIROOT (0x10000000U) + +/** Error event mask for SSIT Error from Slave SLR1, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT3 (0x20000000U) + +/** Error event mask for SSIT Error from Slave SLR2, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT4 (0x40000000U) + +/** Error event mask for SSIT Error from Slave SLR3, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT5 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup pmcerr2 Error Event Mask for PMC ERR2 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PMC ERR2 Node + */ +/** Error event mask for General purpose PMC error, + * can be triggered by any of the following peripherals:, + * - PMC Global Regsiters,- PMC Clock & Reset (CRP),- PMC IOU Secure SLCR, + * - PMC IOU SLCR,- BBRAM Controller,- PMC Analog Control Registers, + * - RTC Control Registers. */ +#define XIL_EVENT_ERROR_MASK_PMCAPB (0x00000001U) + +/** Error event mask for PMC ROM Validation Error. */ +#define XIL_EVENT_ERROR_MASK_PMCROM (0x00000002U) + +/** Error event mask for PMC PPU0 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL0 (0x00000004U) + +/** Error event mask for PMC PPU1 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL1 (0x00000008U) + +/** Error event mask for PMC Switch and PMC IOU Parity Errors. */ +#define XIL_EVENT_ERROR_MASK_PMCPAR (0x00000010U) + +/** Error event mask for PMC Correctable Errors:, + * PPU0 RAM correctable error.,PPU1 instruction RAM correctable error., + * PPU1 data RAM correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_CR (0x00000020U) + +/** Error event mask for PMC Non-Correctable Errors: + * PPU0 RAM non-correctable error, PPU1 instruction RAM non-correctable error, + * PPU1 data RAM non-correctable error, PRAM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_NCR (0x00000040U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[0]. + * Indicates an alarm condition on any of SUPPLY0 to SUPPLY31. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON0 (0x00000080U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[1]. + * Indicates an alarm condition on any of SUPPLY32 to SUPPLY63. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON1 (0x00000100U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[2]. + * Indicates an alarm condition on any of SUPPLY64 to SUPPLY95. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON2 (0x00000200U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[3]. + * Indicates an alarm condition on any of SUPPLY96 to SUPPLY127. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON3 (0x00000400U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[4]. + * Indicates an alarm condition on any of SUPPLY128 to SUPPLY159. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON4 (0x00000800U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[8]. + * Indicates an over-temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON8 (0x00008000U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[9]. + * Indicates a device temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON9 (0x00010000U) + +/** Error event mask for CFI Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CFI (0x00020000U) + +/** Error event mask for CFRAME SEU CRC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUCRC (0x00040000U) + +/** Error event mask for CFRAME SEU ECC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUECC (0x00080000U) + +/** Error event mask for RTC Alarm Error. */ +#define XIL_EVENT_ERROR_MASK_RTCALARM (0x00400000U) + +/** Error event mask for PMC NPLL Lock Error, + * this error can be unmasked after the NPLL is locked to alert when the + * NPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_NPLL (0x00800000U) + +/** Error event mask for PMC PPLL Lock Error, + * this error can be unmasked after the PPLL is locked to alert when the + * PPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_PPLL (0x01000000U) + +/** Error event mask for Clock Monitor Errors, collected from CRP's + * CLKMON_STATUS register. */ +#define XIL_EVENT_ERROR_MASK_CLKMON (0x02000000U) + +/** Error event mask for PMC Interconnect Timeout Errors. + * Collected from: Interconnect mission interrupt status register, + * Interconnect latent status register, Timeout interrupt status register + * for SERBs. */ +#define XIL_EVENT_ERROR_MASK_PMCTO (0x04000000U) + +/** Error event mask for PMC XMPU Errors: Register access error on APB, + * Read permission violation, Write permission violation, Security violation. */ +#define XIL_EVENT_ERROR_MASK_PMCXMPU (0x08000000U) + +/** Error event mask for PMC XPPU Errors: Register access error on APB, + * Master ID not found, Read permission violation, Master ID parity error, + * Master ID access violation, TrustZone violation, Aperture parity error. */ +#define XIL_EVENT_ERROR_MASK_PMCXPPU (0x10000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR1, + * For Slave SLRs: SSIT Error0 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT0 (0x20000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR2, + * For Slave SLRs: SSIT Error1 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT1 (0x40000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR3, + * For Slave SLRs: SSIT Error2 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT2 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup psmerr1 Error Event Mask for PSM ERR1 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PSM ERR1 Node + */ +/** Error event mask for PS Software can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_CR (0x00000001U) + +/** Error event mask for PS Software can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_NCR (0x00000002U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_CR (0x00000004U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_NCR (0x00000008U) + +/** Error event mask for Or of MB Fatal1, Fatal2, Fatal3 Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL (0x00000010U) + +/** Error event mask for PSM Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_CR (0x00000020U) + +/** Error event mask for PSM Non-Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_NCR (0x00000040U) + +/** Error event mask for Non-Correctable ECC Error during an OCM access. */ +#define XIL_EVENT_ERROR_MASK_OCM_ECC (0x00000080U) + +/** Error event mask for Non-Correctable ECC Error during APU L2 Cache access. */ +#define XIL_EVENT_ERROR_MASK_L2_ECC (0x00000100U) + +/** Error event mask for ECC Errors during a RPU memory access. + * Floating-point operation exceptions. RPU REG APB error. */ +#define XIL_EVENT_ERROR_MASK_RPU_ECC (0x00000200U) + +/** Error event mask for RPU Lockstep Errors from R5_0. + * The Lockstep error is not initialized until RPU clock is enabled. + * Therefore the error outcomes are masked by default and are expected to be + * unmasked after processor clock is enabled and before its reset is released. */ +#define XIL_EVENT_ERROR_MASK_RPU_LS (0x00000400U) + +/** Error event mask for RPU Common Cause Failures ORed together. + * The CCF Error register with the masking capability has to reside in the RPU. */ +#define XIL_EVENT_ERROR_MASK_RPU_CCF (0x00000800U) + +/** Error event mask for APU GIC AXI Error by the AXI4 master port, + * such as SLVERR or DECERR. */ +#define XIL_EVENT_ERROR_MASK_GIC_AXI (0x00001000U) + +/** Error event mask for APU GIC ECC Error, + * a Non-Correctable ECC error occurred in any ECC-protected RAM. */ +#define XIL_EVENT_ERROR_MASK_GIC_ECC (0x00002000U) + +/** Error event mask for APLL Lock Errors. + * The error can be unmasked after the PLL is locked to alert when the + * PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_APLL_LOCK (0x00004000U) + +/** Error event mask for RPLL Lock Errors. + * The error can be unmasked after the PLL is locked to alert when the + * PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_RPLL_LOCK (0x00008000U) + +/** Error event mask for CPM Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CPM_CR (0x00010000U) + +/** Error event mask for CPM Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CPM_NCR (0x00020000U) + +/** Error event mask for LPD APB Errors from: IPI REG, USB2 REG, CRL REG, + * LPD AFIFM4 REG, LPD IOU REG, LPD IOU SECURE SLCR REG, LPD SLCR REG, + * LPD SLCR SECURE REG. */ +#define XIL_EVENT_ERROR_MASK_LPD_APB (0x00040000U) + +/** Error event mask for FPD APB Errors from: FPD AFIFM0 REG, FPD AFIFM2 REG, + * FPD SLCR REG,FPD SLCR SECURE REG, CRF REG. */ +#define XIL_EVENT_ERROR_MASK_FPD_APB (0x00080000U) + +/** Error event mask for Data parity errors from the interfaces connected + * to the LPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_LPD_PAR (0x00100000U) + +/** Error event mask for Data parity errors from the interfaces connected + * to the FPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_FPD_PAR (0x00200000U) + +/** Error event mask for LPD IO Peripheral Unit Parity Error. */ +#define XIL_EVENT_ERROR_MASK_IOU_PAR (0x00400000U) + +/** Error event mask for Data parity errors from the interfaces connected + * to the PSM interconnect. */ +#define XIL_EVENT_ERROR_MASK_PSM_PAR (0x00800000U) + +/** Error event mask for LPD Interconnect Timeout errors. + * Collected from: Timeout errors at the slaves connected to the LPD + * interconnect, Address decode error, Interconnect mission errors for + * the slaves connected to the LPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_LPD_TO (0x01000000U) + +/** Error event mask for FPD Interconnect Timeout errors. + * Collected from: Coresight debug trace alarms, Timeout errors at the + * slaves connected to the FPD interconnect, Address decode error, + * Data parity errors on the interfaces connected to the FPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_FPD_TO (0x02000000U) + +/** Error event mask for PSM Interconnect Timeout Errors. + * Collected from: Interconnect mission errors for PSM_LOCAL slave or + * PSM_GLOBAL slave or MDM slave or LPD interconnect or PSM master, + * Interconnect latent errors for PSM_LOCAL slave or PSM_GLOBAL slave or + * MDM slave or LPD interconnect or PSM master, Timeout errors at the slaves + * connected to the PSM interconnect. */ +#define XIL_EVENT_ERROR_MASK_PSM_TO (0x04000000U) + +/** Error event mask for XRAM Correctable error. + * Only applicable in devices that have XRAM. */ +#define XIL_EVENT_ERROR_MASK_XRAM_CR (0x08000000U) + +/** Error event mask for XRAM Non-Correctable error. + * Only applicable in devices that have XRAM. */ +#define XIL_EVENT_ERROR_MASK_XRAM_NCR (0x10000000U) +/** + * @} + */ + +/** + * @defgroup psmerr2 Error Event Mask for PSM ERR2 + * @ingroup xilerroreventmask + * @brief Error Events belong to PSM ERR2 Node + * @{ + */ +/** Error event mask for Error from Watchdog Timer in the LPD Subsystem. */ +#define XIL_EVENT_ERROR_MASK_LPD_SWDT (0x00000001U) + +/** Error event mask for Error from Watchdog Timer in the FPD Subsystem. */ +#define XIL_EVENT_ERROR_MASK_FPD_SWDT (0x00000002U) + +/** Error event mask for LPD XMPU Errors: Register access error on APB, + * Read permission violation, Write permission violation, Security violation. */ +#define XIL_EVENT_ERROR_MASK_LPD_XMPU (0x00040000U) + +/** Error event mask for LPD XPPU Errors: Register access error on APB, + * Master ID not found, Read permission violation, Master ID parity error, + * Master ID access violation, TrustZone violation, Aperture parity error. */ +#define XIL_EVENT_ERROR_MASK_LPD_XPPU (0x00080000U) + +/** Error event mask for FPD XMPU Errors: Register access error on APB, + * Read permission violation, Write permission violation, Security violation. */ +#define XIL_EVENT_ERROR_MASK_FPD_XMPU (0x00100000U) +/** + * @} + */ + +/** + * @defgroup swerr Error Event Mask for Software error events + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to SW ERR Node + */ +/** Error event mask for Software error events */ +/** Health Boot Monitoring errors */ +#define XIL_EVENT_ERROR_MASK_HB_MON_0 (0x00000001U) +#define XIL_EVENT_ERROR_MASK_HB_MON_1 (0x00000002U) +#define XIL_EVENT_ERROR_MASK_HB_MON_2 (0x00000004U) +#define XIL_EVENT_ERROR_MASK_HB_MON_3 (0x00000008U) +#define XIL_EVENT_ERROR_MASK_PLM_EXCEPTION (0x00000010U) +/** XilSem errors */ +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_CE (0x00000020U) +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_UE (0x00000040U) +#define XIL_EVENT_ERROR_MASK_XSEM_NPI_UE (0x00000080U) +/** STL errors */ +#define XIL_EVENT_ERROR_MASK_XSTL_UE (0x00000100U) +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* XIL_ERROR_NODE_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_hw.h new file mode 100644 index 0000000..cf288bf --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal/xil_hw.h @@ -0,0 +1,98 @@ +/****************************************************************************** +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** +* +* @file xil_hw.h +* +* This is the header file which contains definitions for the hardware +* registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date        Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.7   bsv   02/21/2017 Initial release
+* 7.8   skd   03/09/2022 Compilation warning fix
+* 8.0   bm    07/06/2022 Refactor versal and versal_net code
+*       bsv   07/19/2022 Moved PCSR_LOCK macros to standalone from xilpm
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HW_H +#define XIL_HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/**@cond xil_internal + * @{ + */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +/* + * PMC_GLOBAL Base Address + */ +#define PMC_GLOBAL_BASEADDR (0XF1110000U) + +/* + * Register: PMC_GLOBAL_DOMAIN_ISO_CNTRL + */ +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL (PMC_GLOBAL_BASEADDR + 0X00010000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_MASK (0X00000400U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_MASK (0X00000800U) + +/* + * Definitions required from pmc_tap.h + */ +#define PMC_TAP_BASEADDR (0XF11A0000U) +#define PMC_TAP_IDCODE (PMC_TAP_BASEADDR + 0X00000000U) +#define PMC_TAP_VERSION (PMC_TAP_BASEADDR + 0X00000004U) +#define PMC_TAP_VERSION_PMC_VERSION_MASK (0X000000FFU) +/* + * Definitions required from crp.h + */ +#define CRP_BASEADDR (0XF1260000U) +#define CRP_RESET_REASON (CRP_BASEADDR + 0X00000220U) +#define CRP_RST_NONPS (CRP_BASEADDR + 0X00000320U) +#define CRP_RST_NONPS_NPI_RESET_MASK (0X10U) +/* + * Register: CRP_RST_PS + */ +#define CRP_RST_PS (CRP_BASEADDR + 0x0000031CU) +/* + * Register: PMC_IOU_SLCR + */ +#define PMC_IOU_SLCR_BASEADDR (0XF1060000U) + +#define IPI_BASEADDR (0xFF300000U) + +#define PCSR_UNLOCK_VAL (0xF9E8D7C6U) +#define PCSR_LOCK_VAL (0U) + +/** + * @} + * @endcond + */ + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_HW_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/CMakeLists.txt new file mode 100644 index 0000000..00f7985 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT +collect (PROJECT_LIB_HEADERS xil_error_node.h) +collect (PROJECT_LIB_HEADERS xil_hw.h) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_error_node.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_error_node.h new file mode 100644 index 0000000..01bc5f0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_error_node.h @@ -0,0 +1,735 @@ +/****************************************************************************** +* Copyright (c) 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_error_node.h +* +* This is the file which contains node IDs information for versal net error events. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who 	 Date        Changes
+* ----- -------- -------- -----------------------------------------------------
+* 8.0   bm       07/06/2022 Initial release
+*       dc       07/12/2022 Added XIL_EVENT_ERROR_MASK_DEV_STATE_CHANGE
+* 8.1   kal      01/05/2023 Added XIL_EVENT_ERROR_PCR_LOG_UPDATE
+*       rama     01/19/2023 Add XilSem errors to SW error events
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef XIL_ERROR_NODE_H +#define XIL_ERROR_NODE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/**@name Versalnet Event Node IDs + * @defgroup xileventnodes Event Node IDs + * @ingroup xilnodeids + * @{ + */ + +#define XIL_NODETYPE_EVENT_ERROR_ID_ENCODING (0x28100000U) + + /** + * Error Event Node Ids + */ +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR1 (0x28100000U) +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR2 (0x28104000U) +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR3 (0x28108000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR1 (0x2810C000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR2 (0x28110000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR3 (0x28114000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR4 (0x28118000U) +#define XIL_NODETYPE_EVENT_ERROR_SW_ERR (0x2811C000U) +/** + * @} + */ + +/**@name Versalnet Error event Mask + * @defgroup xilerroreventmask Error Event Mask + * @ingroup xilnodeids + * @{ + * @defgroup pmcerr1 Error Event Mask for PMC ERR1 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PMC ERR1 Node + */ + +/** Error event mask for PMC Boot Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_CR (0x00000001U) + +/** Error event mask for PMC Boot Non-Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_NCR (0x00000002U) + +/** Error event mask for PMC Firmware Boot Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_CR (0x00000004U) + +/** Error event mask for PMC Firmware Boot Non-Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_NCR (0x00000008U) + +/** Error event mask for General Software Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_CR (0x00000010U) + +/** Error event mask for General Software Non-Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_NCR (0x00000020U) + +/** Error event mask for CFU Error. */ +#define XIL_EVENT_ERROR_MASK_CFU (0x00000040U) + +/** Error event mask for CFRAME Error. */ +#define XIL_EVENT_ERROR_MASK_CFRAME (0x00000080U) + +/** Error event mask for PSM Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_CR (0x00000100U) + +/** Error event mask for PSM Non-Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_NCR (0x00000200U) + +/** Error event mask for DDRMC MB Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_CR (0x00000400U) + +/** Error event mask for DDRMC MB Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_NCR (0x00000800U) + +/** Error event mask for NoC Type1 Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_CR (0x00001000U) + +/** Error event mask for NoC Type1 Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_NCR (0x00002000U) + +/** Error event mask for NoC User Error. */ +#define XIL_EVENT_ERROR_MASK_NOCUSER (0x00004000U) + +/** Error event mask for MMCM Lock Error. */ +#define XIL_EVENT_ERROR_MASK_MMCM (0x00008000U) + +/** Error event mask for ME Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_CR (0x00010000U) + +/** Error event mask for ME Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_NCR (0x00020000U) + +/** Error event mask for DDRMC MC Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_CR (0x00040000U) + +/** Error event mask for DDRMC MC Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_NCR (0x00080000U) + +/** Error event mask for GT Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_CR (0x00100000U) + +/** Error event mask for GT Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_NCR (0x00200000U) + +/** Error event mask for PL Sysmon Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_CR (0x00400000U) + +/** Error event mask for PL Sysmon Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_NCR (0x00800000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL0 (0x01000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL1 (0x02000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL2 (0x04000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL3 (0x08000000U) + +/** Error event mask for NPI Root Error. */ +#define XIL_EVENT_ERROR_MASK_NPIROOT (0x10000000U) + +/** Error event mask for SSIT Error from Slave SLR1, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT3 (0x20000000U) + +/** Error event mask for SSIT Error from Slave SLR2, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT4 (0x40000000U) + +/** Error event mask for SSIT Error from Slave SLR3, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT5 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup pmcerr2 Error Event Mask for PMC ERR2 + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to PMC ERR2 Node + */ +/** Error event mask for General purpose PMC error, + * can be triggered by any of the following peripherals:, + * - PMC Global Regsiters,- PMC Clock & Reset (CRP),- PMC IOU Secure SLCR, + * - PMC IOU SLCR,- BBRAM Controller,- PMC Analog Control Registers, + * - RTC Control Registers. */ +#define XIL_EVENT_ERROR_MASK_PMCAPB (0x00000001U) + +/** Error event mask for PMC ROM Validation Error. */ +#define XIL_EVENT_ERROR_MASK_PMCROM (0x00000002U) + +/** Error event mask for PMC PPU0 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL0 (0x00000004U) + +/** Error event mask for PMC PPU1 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL1 (0x00000008U) + +/** Error event mask for PMC Correctable Errors:, + * PPU0 RAM correctable error.,PPU1 instruction RAM correctable error., + * PPU1 data RAM correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_CR (0x00000020U) + +/** Error event mask for PMC Non-Correctable Errors:, + * PPU0 RAM non-correctable error.,PPU1 instruction RAM non-correctable error., + * PPU1 data RAM non-correctable error.,PRAM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_NCR (0x00000040U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[0]. + * Indicates an alarm condition on any of SUPPLY0 to SUPPLY31. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON0 (0x00000080U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[1]. + * Indicates an alarm condition on any of SUPPLY32 to SUPPLY63. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON1 (0x00000100U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[2]. + * Indicates an alarm condition on any of SUPPLY64 to SUPPLY95. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON2 (0x00000200U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[3]. + * Indicates an alarm condition on any of SUPPLY96 to SUPPLY127. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON3 (0x00000400U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[4]. + * Indicates an alarm condition on any of SUPPLY128 to SUPPLY159. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON4 (0x00000800U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[8]. + * Indicates an over-temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON8 (0x00008000U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[9]. + * Indicates a device temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON9 (0x00010000U) + +/** Error event mask for CFI Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CFI (0x00020000U) + +/** Error event mask for CFRAME SEU CRC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUCRC (0x00040000U) + +/** Error event mask for CFRAME SEU ECC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUECC (0x00080000U) + +/** Error event mask for PMX WDT Error. */ +#define XIL_EVENT_ERROR_MASK_PMX_WWDT (0x00100000U) + +/** Error event mask for RTC Alarm Error. */ +#define XIL_EVENT_ERROR_MASK_RTCALARM (0x00400000U) + +/** Error event mask for PMC NPLL Lock Error, + * This error can be unmasked after the NPLL is locked to alert when the + * NPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_NPLL (0x00800000U) + +/** Error event mask for PMC PPLL Lock Error, + * This error can be unmasked after the PPLL is locked to alert when the + * PPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_PPLL (0x01000000U) + +/** Error event mask for Clock Monitor Errors., + * Collected from CRP's CLKMON_STATUS register. */ +#define XIL_EVENT_ERROR_MASK_CLKMON (0x02000000U) + +/** Error event mask for PMC interconnect correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PMX_CORR_ERR (0x08000000U) + +/** Error event mask for PMC interconnect uncorrectable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PMX_UNCORR_ERR (0x10000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR1., + * For Slave SLRs: SSIT Error0 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT0 (0x20000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR2., + * For Slave SLRs: SSIT Error1 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT1 (0x40000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR3., + * For Slave SLRs: SSIT Error2 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT2 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup pmcerr3 Error Event Mask for PMC ERR3 + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to PMC ERR3 Node + */ +/** Error event mask for PMC IOU correctable error. */ +#define XIL_EVENT_ERROR_MASK_IOU_CR (0x00000001U) + +/** Error event mask for PMC IOU uncorrectable error. */ +#define XIL_EVENT_ERROR_MASK_IOU_NCR (0x00000002U) + +/** Error event mask for DFX unexpected activation. */ +#define XIL_EVENT_ERROR_MASK_DFX_UXPT_ACT (0x00000004U) + +/** Error event mask for DICE CDI SEED parity. */ +#define XIL_EVENT_ERROR_MASK_DICE_CDI_PAR (0x00000008U) + +/** Error event mask for Device identity private key parity. */ +#define XIL_EVENT_ERROR_MASK_DEVIK_PRIV (0x00000010U) + +/** Error event mask for Next SW CDI SEED parity. */ +#define XIL_EVENT_ERROR_MASK_NXTSW_CDI_PAR (0x00000020U) + +/** Error event mask for Device attestation private key parity. */ +#define XIL_EVENT_ERROR_MASK_DEVAK_PRIV (0x00000040U) + +/** Error event mask for DME public key X component's parity. */ +#define XIL_EVENT_ERROR_MASK_DME_PUB_X (0x00000080U) + +/** Error event mask for DME public key Y component's parity. */ +#define XIL_EVENT_ERROR_MASK_DME_PUB_Y (0x00000100U) + +/** Error event mask for DEVAK public key X component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVAK_PUB_X (0x00000200U) + +/** Error event mask for DEVAK public key Y component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVAK_PUB_Y (0x00000400U) + +/** Error event mask for DEVIK public key X component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVIK_PUB_X (0x00000800U) + +/** Error event mask for DEVIK public key Y component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVIK_PUB_Y (0x00001000U) + +/** Error event mask for PCR parity. */ +#define XIL_EVENT_ERROR_MASK_PCR_PAR (0x00002000U) +/** + * @} + */ + +/** + * @defgroup psmerr1 Error Event Mask for PSM ERR1 + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to PSM ERR1 Node + */ +/** Error event mask for PS Software can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_CR (0x00000001U) + +/** Error event mask for PS Software can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_NCR (0x00000002U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_CR (0x00000004U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_NCR (0x00000008U) + +/** Error event mask for Or of MB Fatal1, Fatal2, Fatal3 Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL (0x00000010U) + +/** Error event mask for PSM Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_CR (0x00000020U) + +/** Error event mask for PSM Non-Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_NCR (0x00000040U) + +/** Error event mask for PSMX CHK error. */ +#define XIL_EVENT_ERROR_MASK_PSMX_CHK (0x00000080U) + +/** Error event mask for APLL1 lock error. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_APLL1_LOCK (0x00000100U) + +/** Error event mask for APLL2 lock error. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_APLL2_LOCK (0x00000200U) + +/** Error event mask for RPLL Lock Errors. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_RPLL_LOCK (0x00000400U) + +/** Error event mask for FLXPLL Lock Errors. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_FLXPLL_LOCK (0x00000800U) + +/** Error event mask for INT_PSM correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PSM_CR (0x00001000U) + +/** Error event mask for INT_PSM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PSM_NCR (0x00002000U) + +/** Error event mask for Consolidated Error from the two USB2 blocks. */ +#define XIL_EVENT_ERROR_MASK_USB2 (0x00004000U) + +/** Error event mask for LPX unexpected dfx activation error. */ +#define XIL_EVENT_ERROR_MASK_LPX_UXPT_ACT (0x00008000U) + +/** Error event mask for INT_LPD correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_LPD_CR (0x00020000U) + +/** Error event mask for INT_LPD non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_LPD_NCR (0x00040000U) + +/** Error event mask for INT_OCM correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_OCM_CR (0x00080000U) + +/** Error event mask for INT_OCM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_OCM_NCR (0x00100000U) + +/** Error event mask for INT_FPD correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_FPD_CR (0x00200000U) + +/** Error event mask for INT_FPD non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_FPD_NCR (0x00400000U) + +/** Error event mask for INT_IOU correctable Error. */ +#define XIL_EVENT_ERROR_MASK_INT_IOU_CR (0x00800000U) + +/** Error event mask for INT_IOU non-correctable Error. */ +#define XIL_EVENT_ERROR_MASK_INT_IOU_NCR (0x01000000U) + +/** Error event mask for RPU lockstep error for ClusterA. */ +#define XIL_EVENT_ERROR_MASK_RPUA_LOCKSTEP (0x02000000U) + +/** Error event mask for RPU lockstep error for ClusterB. */ +#define XIL_EVENT_ERROR_MASK_RPUB_LOCKSTEP (0x04000000U) + +/** Error event mask for APU GIC AXI error (slverr, decerr). */ +#define XIL_EVENT_ERROR_MASK_APU_GIC_AXI (0x08000000U) + +/** Error event mask for APU GIC ECC error. */ +#define XIL_EVENT_ERROR_MASK_APU_GIC_ECC (0x10000000U) + +/** Error event mask for CPM correctable error. */ +#define XIL_EVENT_ERROR_MASK_CPM_CR (0x20000000U) + +/** Error event mask for CPM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_CPM_NCR (0x40000000U) + +/** Error event mask for CPI error. */ +#define XIL_EVENT_ERROR_MASK_CPI (0x80000000U) +/** + * @} + */ + + +/** + * @defgroup psmerr2 Error Event Mask for PSM ERR2 + * @ingroup xilpmerroreventmask + * @brief Error Events belong to PSM ERR2 Node + * @{ + */ +/** Error event mask for FPD WDT0 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT0 (0x00000001U) + +/** Error event mask for FPD WDT1 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT1 (0x00000002U) + +/** Error event mask for FPD WDT2 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT2 (0x00000004U) + +/** Error event mask for FPD WDT3 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT3 (0x00000008U) + +/** Error event mask for Memory Errors for Splitter0. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER0 (0x00000010U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter0. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER0 (0x00000020U) + +/** Error event mask for Memory Errors for Splitter1. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER1 (0x00000040U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter1. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER1 (0x00000080U) + +/** Error event mask for Memory Errors for Splitter2. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER2 (0x00000100U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter2. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER2 (0x00000200U) + +/** Error event mask for Memory Errors for Splitter3. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER3 (0x00000400U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter3. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER3 (0x00000800U) + +/** Error event mask for APU Cluster 0 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER0 (0x00001000U) + +/** Error event mask for APU Cluster 1 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER1 (0x00002000U) + +/** Error event mask for APU Cluster 2 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER2 (0x00004000U) + +/** Error event mask for APU Cluster 3 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER3 (0x00008000U) + +/** Error event mask for WWDT0 LPX Error. */ +#define XIL_EVENT_ERROR_MASK_LPD_WWDT0 (0x00010000U) + +/** Error event mask for WWDT0 LPX Error. */ +#define XIL_EVENT_ERROR_MASK_LPD_WWDT1 (0x00020000U) + +/** Error event mask for ADMA Lockstep Error. */ +#define XIL_EVENT_ERROR_MASK_ADMA_LOCKSTEP (0x00040000U) + +/** Error event mask for IPI Error */ +#define XIL_EVENT_ERROR_MASK_IPI (0x00080000U) + +/** Error event mask for OCM Bank0 Corr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK0_CR (0x00100000U) + +/** Error event mask for OCM Bank1 Corr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK1_CR (0x00200000U) + +/** Error event mask for OCM Bank0 UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK0_NCR (0x00400000U) + +/** Error event mask for OCM Bank1 UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK1_NCR (0x00800000U) + +/** Error event mask for LPXAFIFS Corr Error. */ +#define XIL_EVENT_ERROR_MASK_LPXAFIFS_CR (0x01000000U) + +/** Error event mask for LPXAFIFS UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_LPXAFIFS_NCR (0x02000000U) + +/** Error event mask for LPX Glitch Detector0 glitch detected. */ +#define XIL_EVENT_ERROR_MASK_LPX_GLITCH_DETECT0 (0x04000000U) + +/** Error event mask for LPX Glitch Detector1 glitch detected. */ +#define XIL_EVENT_ERROR_MASK_LPX_GLITCH_DETECT1 (0x08000000U) + +/** Error event mask for Firewall write errors from NOC NMUs. */ +#define XIL_EVENT_ERROR_MASK_FWALL_WR_NOC_NMU (0x10000000U) + +/** Error event mask for Firewall read error from NOC NMU. */ +#define XIL_EVENT_ERROR_MASK_FWALL_RD_NOC_NMU (0x20000000U) + +/** Error event mask for Firewall error from NOC NSU. */ +#define XIL_EVENT_ERROR_MASK_FWALL_NOC_NSU (0x40000000U) + +/** Error event mask for Bit[18] from R52 Core A0, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_A0 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup psmerr3 Error Event Mask for PSM ERR3 + * @ingroup xilpmerroreventmask + * @brief Error Events belong to PSM ERR3 Node + * @{ + */ +/** Error event mask for Bit[18] from R52 Core A1, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_A1 (0x00000001U) + +/** Error event mask for Bit[18] from R52 Core B0, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_B0 (0x00000002U) + +/** Error event mask for Bit[18] from R52 Core B1, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_B1 (0x00000004U) + +/** Error event mask for R52 A0 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A0_CR (0x00000008U) + +/** Error event mask for R52 A0 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A0_TFATAL (0x00000010U) + +/** Error event mask for R52 A0 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A0_TIMEOUT (0x00000020U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUA0. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUA0 (0x00000040U) + +/** Error event mask for Bit[25] of ERREVNT for RPUA0. */ +#define XIL_EVENT_ERROR_MASK_B25_RPUA0 (0x00000080U) + +/** Error event mask for R52 A1 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A1_CR (0x00000100U) + +/** Error event mask for R52 A1 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A1_TFATAL (0x00000200U) + +/** Error event mask for R52 A1 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A1_TIMEOUT (0x00000400U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUA1. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUA1 (0x00000800U) + +/** Error event mask for Bit[25] of ERREVNT for RPUA1. */ +#define XIL_EVENT_ERROR_MASK_B25_RPUA1 (0x00001000U) + +/** Error event mask for R52 A1 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B0_CR (0x00002000U) + +/** Error event mask for R52 A1 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B0_TFATAL (0x00004000U) + +/** Error event mask for R52 A1 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B0_TIMEOUT (0x00008000U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUB0. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUB0 (0x00010000U) + +/** Error event mask for Bit[25] of ERREVNT for RPUB0. */ +#define XIL_EVENT_ERROR_MASK_B25_RPUB0 (0x00020000U) + +/** Error event mask for R52 A1 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B1_CR (0x00040000U) + +/** Error event mask for R52 A1 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B1_TFATAL (0x00080000U) + +/** Error event mask for R52 A1 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B1_TIMEOUT (0x00100000U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUB1. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUB1 (0x00200000U) + +/** Error event mask for Bit[25] of ERREVNT for RPUB1.*/ +#define XIL_EVENT_ERROR_MASK_B25_RPUB1 (0x00400000U) + +/** Error event mask for PCIL ERR FOR RPU Clusters. */ +#define XIL_EVENT_ERROR_MASK_PCIL_RPU (0x01000000U) + +/** Error event mask for FPXAFIFS Corr Error. */ +#define XIL_EVENT_ERROR_MASK_FPXAFIFS_CR (0x02000000U) + +/** Error event mask for FPXAFIFS UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_FPXAFIFS_NCR (0x04000000U) + +/** Error event mask for PSX_CMN_1 PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CMN_1 (0x08000000U) + +/** Error event mask for PSX_CMN_2 PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CMN_2 (0x10000000U) + +/** Error event mask for PSX_CMN_3 PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CMN_3 (0x20000000U) + +/** Error event mask for PSX_CML PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CML (0x40000000U) + +/** Error event mask for FPD_INT_WRAP PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_FPD_INT_WRAP (0x80000000U) +/** + * @} + */ + +/** + * @defgroup psmerr4 Error Event Mask for PSM ERR4 + * @ingroup xilpmerroreventmask + * @brief Error Events belong to PSM ERR4 Node + * @{ + */ +/** Error event mask for FPD Reset Monitor ERROR. */ +#define XIL_EVENT_ERROR_MASK_FPD_RST_MON (0x00000001U) + +/** Error event mask for LPD reset and Clock Monitor Error. */ +#define XIL_EVENT_ERROR_MASK_LPD_RST_CLK_MON (0x00000002U) + +/** Error event mask for Fatal Error from all AFI FM. */ +#define XIL_EVENT_ERROR_MASK_FATAL_AFI_FM (0x00000004U) + +/** Error event mask for Non Fatal Error from AFI FM in LPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM_LPX (0x00000008U) + +/** Error event mask for Non Fatal Error from AFI FM0 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM0_FPX (0x00000010U) + +/** Error event mask for Non Fatal Error from AFI FM1 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM1_FPX (0x00000020U) + +/** Error event mask for Non Fatal Error from AFI FM2 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM2_FPX (0x00000040U) + +/** Error event mask for Non Fatal Error from AFI FM3 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM3_FPX (0x00000080U) + +/** Error event mask for Errors from RPU cluster A. */ +#define XIL_EVENT_ERROR_MASK_RPU_CLUSTERA (0x00000100U) + +/** Error event mask for Errors from RPU cluster B. */ +#define XIL_EVENT_ERROR_MASK_RPU_CLUSTERB (0x00000200U) +/** + * @} + */ + +/** + * @defgroup swerr Error Event Mask for Software error events + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to SW ERR Node + */ +/** Error event mask for Software error events */ +/** Health Boot Monitoring errors */ +#define XIL_EVENT_ERROR_MASK_HB_MON_0 (0x00000001U) +#define XIL_EVENT_ERROR_MASK_HB_MON_1 (0x00000002U) +#define XIL_EVENT_ERROR_MASK_HB_MON_2 (0x00000004U) +#define XIL_EVENT_ERROR_MASK_HB_MON_3 (0x00000008U) +#define XIL_EVENT_ERROR_MASK_PLM_EXCEPTION (0x00000010U) +#define XIL_EVENT_ERROR_MASK_DEV_STATE_CHANGE (0x00000020U) +#define XIL_EVENT_ERROR_PCR_LOG_UPDATE (0x00000040U) +/** XilSem errors */ +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_CE (0x00000080U) +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_UE (0x00000100U) +#define XIL_EVENT_ERROR_MASK_XSEM_NPI_UE (0x00000200U) +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* XIL_ERROR_NODE_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_hw.h new file mode 100644 index 0000000..42a7947 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/versal_net/xil_hw.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* Copyright (c) 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** +* +* @file xil_hw.h +* +* This is the header file which contains definitions for the hardware +* registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date        Changes
+* ----- ---- -------- -------------------------------------------------------
+* 8.0   bm   07/06/2022 Initial release
+*       bsv  07/19/2022 Moved PCSR_LOCK macros to standalone from xilpm
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HW_H +#define XIL_HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/**@cond xil_internal + * @{ + */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +/* + * PMC_GLOBAL Base Address + */ +#define PMC_GLOBAL_BASEADDR (0XF1110000U) + +/* + * Register: PMC_GLOBAL_DOMAIN_ISO_CNTRL + */ +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL (PMC_GLOBAL_BASEADDR + 0X00010000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_MASK (0x00040000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_MASK (0x00020000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_MASK (0x00010000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_MASK (0x00008000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_MASK (0x00004000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_MASK (0x00002000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_MASK (0x00001000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_MASK (0x00000800U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_MASK (0X00000400U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_MASK (0x00000200U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_MASK (0x00000100U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_MASK (0x00000080U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_MASK (0x00000040U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_MASK (0x00000020U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_MASK (0x00000010U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_MASK (0x00000008U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_MASK (0x00000004U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_MASK (0x00000002U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_MASK (0x00000001U) +/* + * Definitions required from pmc_tap.h + */ +#define PMC_TAP_BASEADDR (0XF11A0000U) +#define PMC_TAP_IDCODE (PMC_TAP_BASEADDR + 0X00000000U) +#define PMC_TAP_VERSION (PMC_TAP_BASEADDR + 0X00000004U) +#define PMC_TAP_VERSION_PMC_VERSION_MASK (0X000000FFU) +/* + * Definitions required from crp.h + */ +#define CRP_BASEADDR (0XF1260000U) +#define CRP_RESET_REASON (CRP_BASEADDR + 0X00000220U) +#define CRP_RST_NONPS (CRP_BASEADDR + 0X00000320U) +#define CRP_RST_NONPS_NPI_RESET_MASK (0X10U) +/* + * Register: CRP_RST_PS + */ +#define CRP_RST_PS (CRP_BASEADDR + 0x0000031CU) +/* + * Register: PMC_IOU_SLCR + */ +#define PMC_IOU_SLCR_BASEADDR (0XF1060000U) + +#define IPI_BASEADDR (0xEB300000U) + +#define PCSR_UNLOCK_VAL (0xF9E8D7C6U) +#define PCSR_LOCK_VAL (0U) + +/** + * @} + * @endcond + */ + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_HW_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xbasic_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xbasic_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xbasic_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xbasic_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xdebug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xenv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xenv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xenv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xenv_standalone.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xenv_standalone.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xenv_standalone.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/xbasic_types.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_assert.c similarity index 55% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/xbasic_types.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_assert.c index 67d02ae..b3dd7e9 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/common/src/xbasic_types.c +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_assert.c @@ -1,33 +1,32 @@ /****************************************************************************** -* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /*****************************************************************************/ /** * -* @file xbasic_types.c -* @addtogroup common Overview +* @file xil_assert.c +* @addtogroup common_assert_apis Assert APIs and Macros * @{ * -* This file contains basic functions for Xilinx software IP. +* This file contains basic assert related functions for Xilinx software IP. * * 
     * MODIFICATION HISTORY:
 *
 * Ver   Who    Date   Changes
 * ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
-* 1.00a xd   11/03/04 Improved support for doxygen.
-* 1.00a bss  13/01/12 Removed a compiler warning in XNullHandler;
+* 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
 *
    * ******************************************************************************/ /***************************** Include Files *********************************/ -#include "xbasic_types.h" +#include "xil_types.h" +#include "xil_assert.h" /************************** Constant Definitions *****************************/ @@ -38,80 +37,80 @@ /************************** Variable Definitions *****************************/ /** - * This variable allows testing to be done easier with asserts. An assert + * @brief This variable allows testing to be done easier with asserts. An assert * sets this variable such that a driver can evaluate this variable * to determine if an assert occurred. */ -unsigned int XAssertStatus; +u32 Xil_AssertStatus; /** - * This variable allows the assert functionality to be changed for testing + * @brief This variable allows the assert functionality to be changed for testing * such that it does not wait infinitely. Use the debugger to disable the * waiting during testing of asserts. */ -int XWaitInAssert = TRUE; +s32 Xil_AssertWait = 1; /* The callback function to be invoked when an assert is taken */ -static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL; +static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; /************************** Function Prototypes ******************************/ /*****************************************************************************/ /** * -* Implements assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the XWaitInAssert variable. +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. * -* @param File is the name of the filename of the source -* @param Line is the linenumber within File +* @param File: filename of the source +* @param Line: linenumber within File * * @return None. * * @note None. * ******************************************************************************/ -void XAssert(char *File, int Line) +void Xil_Assert(const char8 *File, s32 Line) { /* if the callback has been set then invoke it */ - if (XAssertCallbackRoutine != NULL) { - (*XAssertCallbackRoutine) (File, Line); + if (Xil_AssertCallbackRoutine != 0) { + (*Xil_AssertCallbackRoutine)(File, Line); } /* if specified, wait indefinitely such that the assert will show up * in testing */ - while (XWaitInAssert) { + while (Xil_AssertWait != 0) { } } /*****************************************************************************/ /** * -* Sets up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. * -* @param Routine is the callback to be invoked when an assert is taken +* @param Routine: callback to be invoked when an assert is taken * * @return None. * * @note This function has no effect if NDEBUG is set * ******************************************************************************/ -void XAssertSetCallback(XAssertCallback Routine) +void Xil_AssertSetCallback(Xil_AssertCallback Routine) { - XAssertCallbackRoutine = Routine; + Xil_AssertCallbackRoutine = Routine; } - /*****************************************************************************/ /** * -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. * -* @param NullParameter is an arbitrary void pointer and not used. +* @param NullParameter: arbitrary void pointer and not used. * * @return None. * @@ -120,6 +119,8 @@ void XAssertSetCallback(XAssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void) NullParameter; + (void) NullParameter; } -/** @} */ +/** +* @} End of "addtogroup common_assert_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_assert.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_assert.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_assert.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_cache_vxworks.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cache_vxworks.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_cache_vxworks.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cryptoalginfo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_cryptoalginfo.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_cryptoalginfo.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_cryptoalginfo.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_hal.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_hal.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_hal.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_io.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_io.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_io.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_macroback.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_macroback.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_macroback.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.c new file mode 100644 index 0000000..44e7d9a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.c @@ -0,0 +1,70 @@ +/******************************************************************************/ +/** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_mem.c +* +* This file contains xil mem copy function to use in case of word aligned +* data copies. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+* 7.7	sk	 01/10/22 Update Xil_MemCpy functions variables typecast
+* 			  from int to s32 to fix misra_c_2012_directive_4_6
+* 			  violations.
+* 7.7	sk	 01/10/22 Include xil_mem.h header file to fix Xil_MemCpy
+* 			  prototype misra_c_2012_rule_8_4 violation.
+*
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_mem.h" + +/***************** Inline Functions Definitions ********************/ +/*****************************************************************************/ +/** +* @brief This function copies memory from once location to other. +* +* @param dst: pointer pointing to destination memory +* +* @param src: pointer pointing to source memory +* +* @param cnt: 32 bit length of bytes to be copied +* +*****************************************************************************/ +void Xil_MemCpy(void* dst, const void* src, u32 cnt) +{ + char *d = (char*)(void *)dst; + const char *s = src; + + while (cnt >= sizeof (s32)) { + *(s32*)d = *(s32*)s; + d += sizeof (s32); + s += sizeof (s32); + cnt -= sizeof (s32); + } + while (cnt >= sizeof (u16)) { + *(u16*)d = *(u16*)s; + d += sizeof (u16); + s += sizeof (u16); + cnt -= sizeof (u16); + } + while ((cnt) > 0U){ + *d = *s; + d += 1U; + s += 1U; + cnt -= 1U; + } +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.c new file mode 100644 index 0000000..c116a15 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.c @@ -0,0 +1,461 @@ +/****************************************************************************** +* Copyright (C) 1995 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "bspconfig.h" +#include +#include +#include + +/************************** Function Prototypes ******************************/ + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static s32 getnum( charptr* linep); + +/**************************** Type Definitions *******************************/ + +typedef struct params_s { + s32 len; /**< length */ + s32 num1; /**< number 1 */ + s32 num2; /**< number 2 */ + char8 pad_character; /**< pad character */ + s32 do_padding; /**< do padding */ + s32 left_flag; /**< left flag */ + s32 unsigned_flag; /**< unsigned flag */ +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + + +/*****************************************************************************/ +/** +* This routine puts pad characters into the output buffer. +* +******************************************************************************/ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( par->pad_character); +#endif + } + } +} + +/******************************************************************************/ +/** +* This routine moves a string to the output buffer +* as directed by the padding and positioning flags. +* +*******************************************************************************/ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + padding( !(par->left_flag), par); + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte(*LocalPtr); +#endif + LocalPtr += 1; + } +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + padding( par->left_flag, par); +} + +/*****************************************************************************/ +/** +* +* This routine moves a number to the output buffer +* as directed by the padding and positioning flags. +* +******************************************************************************/ +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % (u32)base)]; + i++; + num /= base; + } while (num > 0U); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = '\0'; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( outbuf[i] ); +#endif + i--; +} + padding( par->left_flag, par); +} +/*---------------------------------------------------*/ +/* */ +/* This routine moves a 64-bit number to the output */ +/* buffer as directed by the padding and positioning */ +/* flags. */ +/* */ +#if defined (__aarch64__) || defined (__arch64__) +static void outnum1( const s64 n, const s32 base, params_t *par) +{ + s32 negative; + s32 i; + char8 outbuf[64]; + const char8 digits[] = "0123456789ABCDEF"; + u64 num; + for(i = 0; i<64; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = (n); + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = '\0'; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); + i--; +} + padding( par->left_flag, par); +} +#endif + +/*****************************************************************************/ +/** +* +* This routine gets a number from the format string. +* +******************************************************************************/ +static s32 getnum(charptr* linep) +{ + s32 n = 0; + s32 ResultIsDigit = 0; + charptr cptr = *linep; + + while (cptr != NULL) { + ResultIsDigit = isdigit(((u8)*cptr)); + if (ResultIsDigit == 0) { + break; + } + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + } + + *linep = ((charptr)(cptr)); + return(n); +} + +/*****************************************************************************/ +/** +* This routine operates just like a printf/sprintf +* routine. It outputs a set of data under the +* control of a formatting string. Not all of the +* standard C format control are supported. The ones +* provided are primarily those needed for embedded +* systems work. Primarily the floating point +* routines are omitted. Other formats could be +* added easily by following the examples shown for +* the supported formats. +* void esp_printf( const func_ptr f_ptr, +* const charptr ctrl1, ...) +* +*******************************************************************************/ +#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +void xil_printf( const char8 *ctrl1, ...){ + XPVXenConsole_Printf(ctrl1); +} +#else +void xil_printf( const char8 *ctrl1, ...) +{ + va_list argp; + + va_start(argp, ctrl1); + + xil_vprintf(ctrl1, argp); + + va_end(argp); +} +#endif + +/*****************************************************************************/ +/** +* This routine is equivalent to vprintf routine +******************************************************************************/ +void xil_vprintf(const char8 *ctrl1, va_list argp) +{ + s32 Check; +#if defined (__aarch64__) || defined (__arch64__) + s32 long_flag; +#endif + s32 dot_flag; + + params_t par; + + u8 ch; + char8 *ctrl = (char8 *)ctrl1; + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte(*ctrl); +#endif + ctrl += 1; + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; +#if defined (__aarch64__) || defined (__arch64__) + long_flag = 0; +#endif + par.unsigned_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = (u8)*ctrl; + } else { + break; + } + + if (isdigit(ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == (u8)'0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower(ch)) { + case '%': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + #if defined (__aarch64__) || defined (__arch64__) + long_flag = 1; + #endif + Check = 0; + break; + + case 'u': + par.unsigned_flag = 1; + /* fall through */ + case 'i': + case 'd': + #if defined (__aarch64__) || defined (__arch64__) + if (long_flag != 0){ + outnum1((s64)va_arg(argp, s64), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + #else + outnum( va_arg(argp, s32), 10L, &par); + #endif + Check = 1; + break; + case 'p': + #if defined (__aarch64__) || defined (__arch64__) + par.unsigned_flag = 1; + outnum1((s64)va_arg(argp, s64), 16L, &par); + Check = 1; + break; + #endif + case 'X': + case 'x': + par.unsigned_flag = 1; + #if defined (__aarch64__) || defined (__arch64__) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 16L, &par); + } + else { + outnum((s32)va_arg(argp, s32), 16L, &par); + } + #else + outnum((s32)va_arg(argp, s32), 16L, &par); + #endif + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( (char8)va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } +} +/*---------------------------------------------------*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_printf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_printf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_sleepcommon.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_sleepcommon.c new file mode 100644 index 0000000..aba3a08 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_sleepcommon.c @@ -0,0 +1,85 @@ +/****************************************************************************** +* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +*@file xil_sleepcommon.c +* +* This file contains the sleep API's +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 	srm  	 11/02/17 First release
+* 7.7	sk	 01/10/22 Typecast sleep function argument from unsigned
+* 			  int to u32 to fix misra_c_2012_directive_4_6
+* 			  violation.
+* 8.0	sk	 03/02/22 Update usleep argument type to fix misra_c_2012_
+* 			  directive_4_6 violation.
+*
    +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "sleep.h" + +/**************************** Constant Definitions *************************/ + + +/*****************************************************************************/ +/** +* +* This API gives delay in sec +* +* @param seconds - delay time in seconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void sleep(u32 seconds) + { +#if defined (ARMR5) + sleep_R5(seconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + sleep_A53(seconds); +#elif defined (__MICROBLAZE__) + sleep_MB(seconds); +#else + sleep_A9(seconds); +#endif + + } + +/****************************************************************************/ +/** +* +* This API gives delay in usec +* +* @param useconds - delay time in useconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void usleep(ULONG useconds) + { +#if defined (ARMR5) + usleep_R5(useconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + usleep_A53(useconds); +#elif defined (__MICROBLAZE__) + usleep_MB(useconds); +#else + usleep_A9(useconds); +#endif + + } diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.c new file mode 100644 index 0000000..f101c14 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.c @@ -0,0 +1,341 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testcache.c +* @addtogroup common_test_utils +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+*
    +* +******************************************************************************/ +#ifdef __ARM__ +#include "xil_cache.h" +#include "xil_testcache.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#ifdef __aarch64__ +#include "xreg_cortexa53.h" +#else +#include "xreg_cortexr5.h" +#endif + +#include "xil_types.h" + +extern void xil_printf(const char8 *ctrl1, ...); + +#define DATA_LENGTH 128 + +#ifdef __aarch64__ +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); +#else +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); +#endif + + +/*****************************************************************************/ +/** +* +* @brief Perform DCache range related API test such as Xil_DCacheFlushRange +* and Xil_DCacheInvalidateRange. This test function writes a constant +* value to the Data array, flushes the range, writes a new value, then +* invalidates the corresponding range. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestDCacheRange(void) +{ + s32 Index; + s32 Status = 0; + u32 CtrlReg; + INTPTR Value; + + xil_printf("-- Cache Range Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A00505; + + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" flush range done\r\n"); + + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A00505) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush worked\r\n"); + } + else { + xil_printf("Error: flush dcache range not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0C505; + + + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0A05; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A0A05) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + + if (!Status) { + xil_printf(" Invalidate worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache range not working\r\n"); + } + xil_printf("-- Cache Range Test Complete --\r\n"); + return Status; + +} + +/*****************************************************************************/ +/** +* @brief Perform DCache all related API test such as Xil_DCacheFlush and +* Xil_DCacheInvalidate. This test function writes a constant value +* to the Data array, flushes the DCache, writes a new value, +* then invalidates the DCache. +* +* @return +* - 0 is returned for a pass +* - -1 is returned for a failure +*****************************************************************************/ +s32 Xil_TestDCacheAll(void) +{ + s32 Index; + s32 Status; + INTPTR Value; + u32 CtrlReg; + + xil_printf("-- Cache All Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50500A0A; + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlush(); + xil_printf(" flush all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + + if (Value != 0x50500A0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush all worked\r\n"); + } + else { + xil_printf("Error: Flush dcache all not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x505FFA0A; + + Xil_DCacheFlush(); + + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidate(); + + xil_printf(" invalidate all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50CFA0A; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0x50CFA0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Invalidate all worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache all not working\r\n"); + } + + xil_printf("-- DCache all Test Complete --\n\r"); + + return Status; +} + +/*****************************************************************************/ +/** +* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers. +* +* @return +* - 0 is returned for a pass +* +* @note The function will hang if it fails. +*****************************************************************************/ +s32 Xil_TestICacheRange(void) +{ + + Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024); + + xil_printf("-- Invalidate icache range done --\r\n"); + + return 0; +} + +/*****************************************************************************/ +/** +* @brief Perform Xil_ICacheInvalidate() on a few function pointers. +* +* @return +* - 0 is returned for a pass +* +* @note The function will hang if it fails. +*****************************************************************************/ +s32 Xil_TestICacheAll(void) +{ + Xil_ICacheInvalidate(); + xil_printf("-- Invalidate icache all done --\r\n"); + return 0; +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_testcache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testcache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.c new file mode 100644 index 0000000..0fe1204 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.c @@ -0,0 +1,279 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testio.c +* @addtogroup common_test_utils +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 9.00  ml   04/26/23 Updated code to fix sizeof_mismatch coverity warnings.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testio.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + + + +/** + * + * Endian swap a 16-bit word. + * @param Data is the 16-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u16 Swap16(u16 Data) +{ + return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U); +} + +/** + * + * Endian swap a 32-bit word. + * @param Data is the 32-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u32 Swap32(u32 Data) +{ + u16 Lo16; + u16 Hi16; + + u16 Swap16Lo; + u16 Swap16Hi; + + Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU); + Lo16 = (u16)(Data & 0x0000FFFFU); + + Swap16Lo = Swap16(Lo16); + Swap16Hi = Swap16(Hi16); + + return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi); +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide register IO test where the +* register is accessed using Xil_Out8 and Xil_In8, and comparing +* the written values by reading them back. +* +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writing the memory. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) +{ + u8 ValueIn; + s32 Index; + s32 Status = 0; + + for (Index = 0; Index < Length; Index++) { + Xil_Out8((UINTPTR)Addr, Value); + + ValueIn = Xil_In8((UINTPTR)Addr); + + if ((Value != ValueIn) && (Status == 0)) { + Status = -1; + break; + } + } + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide register IO test. Each location +* is tested by sequentially writing a 16-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register +* IO, and big-endian register IO. When testing little/big-endian IO, +* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE, +* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE, +* Compare In-Out values. Whether to swap the read-in value before +* comparing is controlled by the 5th argument. +* +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writing the memory. +* @param Kind: Type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) +{ + u16 *TempAddr16; + u16 ValueIn = 0U; + s32 Index; + u32 Size_16; + TempAddr16 = Addr; + Xil_AssertNonvoid(TempAddr16 != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out16LE((UINTPTR)TempAddr16, Value); + break; + case XIL_TESTIO_BE: + Xil_Out16BE((UINTPTR)TempAddr16, Value); + break; + default: + Xil_Out16((UINTPTR)TempAddr16, Value); + break; + } + + ValueIn = Xil_In16((UINTPTR)TempAddr16); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out16((UINTPTR)TempAddr16, Value); + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In16LE((UINTPTR)TempAddr16); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In16BE((UINTPTR)TempAddr16); + break; + default: + ValueIn = Xil_In16((UINTPTR)TempAddr16); + break; + } + + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + Size_16 = sizeof(u16); + TempAddr16 += Size_16; + } + return 0; +} + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide register IO test. Each location +* is tested by sequentially writing a 32-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register IO, +* and big-endian register IO. When testing little/big-endian IO, +* the function perform the following sequence, Xil_Out32LE/ +* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. +* Whether to swap the read-in value *before comparing is controlled +* by the 5th argument. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writing the memory. +* @param Kind: type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) +{ + u32 *TempAddr; + u32 ValueIn = 0U; + s32 Index; + u32 Size_32; + TempAddr = Addr; + Xil_AssertNonvoid(TempAddr != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out32LE((UINTPTR)TempAddr, Value); + break; + case XIL_TESTIO_BE: + Xil_Out32BE((UINTPTR)TempAddr, Value); + break; + default: + Xil_Out32((UINTPTR)TempAddr, Value); + break; + } + + ValueIn = Xil_In32((UINTPTR)TempAddr); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out32((UINTPTR)TempAddr, Value); + + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In32LE((UINTPTR)TempAddr); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In32BE((UINTPTR)TempAddr); + break; + default: + ValueIn = Xil_In32((UINTPTR)TempAddr); + break; + } + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + Size_32 = sizeof(u32); + TempAddr += Size_32; + } + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_testio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.c new file mode 100644 index 0000000..aaa0617 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.c @@ -0,0 +1,1575 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testmem.c +* @addtogroup common_test_utils +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 7.5   mus  03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
+*                     Xil_TestMem8 APIs to support memory test for memory
+*                     regions mapped at extended addresses
+*                     (addresses > 4 GB). These new set of APIs would be
+*                     compiled only for 32 bit Microblaze processor, if
+*                     XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
+*                     It fixes CR#1089129.
+* 7.6   mus  07/29/21 Updated Xil_TestMem8 to fix issues reported by static
+*                     analysis tool. It fixes CR#1105956.
+* 7.7	sk   01/10/22 Remove commented macro to fix misra_c_2012_directive_4_4
+* 		      violation.
+* 7.7	sk   01/10/22 Modify operands to fix misra_c_2012_rule_10_1 violation.
+* 7.7	sk   01/10/22 Typecast to make the both left and right sides expressions
+* 		      of same type and fix misra_c_2012_rule_10_6 violation.
+* 7.7	sk   01/10/22 Modify varaiable name from I to i to fix misra_c_2012_rule_
+* 		      21_2 violation.
+* 7.7	sk   01/10/22 Remove arithematic operations on pointer varaible to fix
+* 		      misra_c_2012_rule_18_4 violation.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testmem.h" +#include "xil_io.h" +#include "xil_assert.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + +static u32 RotateLeft(u32 Input, u8 Width); + +/* define ROTATE_RIGHT to give access to this functionality */ +#ifdef ROTATE_RIGHT +static u32 RotateRight(u32 Input, u8 Width); +#endif /* ROTATE_RIGHT */ + +#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32) + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide memory test. +* +* @param Addrlow: lower 32 bit address of memory to be tested. +* @param Addrhigh: upper 32 bit address of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u8 Val; + u8 WordMem8; + s32 Status = 0; + u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * select the proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from XIL_TESTMEM_INIT_VALUE + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + sbea(Addr+I, Val); + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = XIL_TESTMEM_INIT_VALUE; + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + Val = (u8)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* write memory location */ + sbea(Addr+I, Val); + Val = (u8)RotateLeft(Val, 8U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val = (u8)RotateLeft(Val, NUM_OF_BITS_IN_BYTE); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking zeros test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) { + /* + * Generate an initial value for walking ones test to test + * for bad data bits + */ + Val = (u8) (~(1U << j)); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* write memory location */ + sbea(Addr+I, Val); + Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8) (~(1U << j)); + /* Read the values from each location that was written */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + + Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE)); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u8) (~((INTPTR) (Addr + I))); + sbea(Addr+I, Val); + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + Val = (u8) (~((INTPTR) (Addr+I))); + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u8)0) { + Val = 0xA5U; + } + else { + Val = Pattern; + } + /* + * Fill the memory with fixed Pattern + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + sbea(Addr+I, Val); + } + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide memory test. +* +* @param Addrlow: lower 32 bit address of memory to be tested. +* @param Addrhigh: upper 32 bit address of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant Pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u16 Val; + u16 WordMem16; + s32 Status = 0; + u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * selectthe proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'XIL_TESTMEM_INIT_VALUE' + */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* write memory location */ + shea(Addr+I, Val); + Val++; + I = I + NUM_OF_BYTES_IN_HW; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference val + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* read memory location */ + WordMem16 = lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val++; + I = I + NUM_OF_BYTES_IN_HW; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking ones test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (u16)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { + /* write memory location */ + shea(Addr+I,Val); + Val = (u16)RotateLeft(Val, 16U); + I = I + NUM_OF_BYTES_IN_HW; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { + /* read memory location */ + WordMem16 = lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = (u16)RotateLeft(Val, NUM_OF_BITS_IN_HW); + I = I + NUM_OF_BYTES_IN_HW; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking zeros test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) { + /* + * Generate an initial value for walking ones + * test to test for bad + * data bits + */ + + Val = ~(1U << j); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) { + shea(Addr+I, Val); + Val = ~((u16)RotateLeft(~Val, 16U)); + I = I + NUM_OF_BYTES_IN_HW; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = ~(1U << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { + WordMem16= lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u16)RotateLeft(~Val, NUM_OF_BITS_IN_HW)); + I = I + NUM_OF_BYTES_IN_HW; + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* write memory location */ + Val = (u16) (~((INTPTR)((Addr+I)))); + shea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_HW; + } + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) { + /* read memory location */ + WordMem16 = lhuea(Addr+I); + Val = (u16) (~((INTPTR) ((Addr+I)))); + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_HW; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + if (Pattern == (u16)0) { + Val = 0xDEADU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed pattern + */ + + for (I = 0U; I < (2*Words);) { + /* write memory location */ + shea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_HW; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed pattern + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* read memory location */ + WordMem16=lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_HW; + } + } +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide memory test. +* +* @param Addrlow: lower 32 bit address of memory to be tested. +* @param Addrhigh: upper 32 bit address of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: test type selected. See xil_testmem.h for possible +* values. +* +* @return +* - 0 is returned for a pass +* - 1 is returned for a failure +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u32 Val; + u32 WordMem32; + s32 Status = 0; + u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'XIL_TESTMEM_INIT_VALUE' + */ + for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) { + swea(Addr+I, Val); + Val++; + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) { + WordMem32 = lwea(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val++; + I = I + NUM_OF_BYTES_IN_WORD; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (1U << j); + + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) { + /* write memory location */ + swea(Addr+I, Val); + Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Restore the reference 'val' to the + * initial value + */ + Val = 1U << j; + + /* Read the values from each location that was + * written */ + for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) { + /* read memory location */ + + WordMem32 = lwea(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val = (u32)RotateLeft(Val, NUM_OF_BITS_IN_WORD); + I = I + NUM_OF_BYTES_IN_WORD; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible + * initial test Patterns for walking zeros test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) { + + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = ~(1U << j); + + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { + /* write memory location */ + swea(Addr+I, Val); + Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD)); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + + Val = ~(1U << j); + + /* Read the values from each location that was + * written */ + for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { + /* read memory location */ + WordMem32 = lwea(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD)); + I = I + NUM_OF_BYTES_IN_WORD; + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + /* write memory location */ + Val = (u32) (~((INTPTR) (Addr+I))); + swea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + /* Read the location */ + WordMem32 = lwea(Addr+I); + Val = (u32) (~((INTPTR) (Addr+I))); + + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_WORD; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed Pattern + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + /* write memory location */ + swea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + + /* read memory location */ + + WordMem32 = lwea(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_WORD; + } + } + +End_Label: + return Status; +} + +#else +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: test type selected. See xil_testmem.h for possible +* values. +* +* @return +* - 0 is returned for a pass +* - 1 is returned for a failure +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) +{ + u32 i; + u32 j; + u32 Val; + u32 FirtVal; + u32 WordMem32; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (i = 0U; i < Words; i++) { + Addr[i] = Val; + Val++; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (i = 0U; i < Words; i++) { + WordMem32 = Addr[i]; + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)32; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (1UL << j); + + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)32; i++) { + /* write memory location */ + Addr[i] = Val; + Val = (u32) RotateLeft(Val, 32U); + } + + /* + * Restore the reference 'val' to the + * initial value + */ + Val = 1UL << j; + + /* Read the values from each location that was + * written */ + for (i = 0U; i < (u32)32; i++) { + /* read memory location */ + + WordMem32 = Addr[i]; + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val = (u32)RotateLeft(Val, 32U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible + * initial test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)32; j++) { + + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = ~(1UL << j); + + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)32; i++) { + /* write memory location */ + Addr[i] = Val; + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + + Val = ~(1UL << j); + + /* Read the values from each location that was + * written */ + for (i = 0U; i < (u32)32; i++) { + /* read memory location */ + WordMem32 = Addr[i]; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Val = ~(u32) (UINTPTR) &Addr[i]; + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (i = 0U; i < Words; i++) { + /* Read the location */ + WordMem32 = Addr[i]; + Val = ~(u32) (UINTPTR) &Addr[i]; + + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed Pattern + */ + + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (i = 0U; i < Words; i++) { + + /* read memory location */ + + WordMem32 = Addr[i]; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant Pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) +{ + u32 i; + u32 j; + u16 Val; + u16 FirtVal; + u16 WordMem16; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * selectthe proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference val + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking ones test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (u16)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)16; i++) { + /* write memory location */ + Addr[i] = Val; + Val = (u16)RotateLeft(Val, 16U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16)((u32)1 << j); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)16; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = (u16)RotateLeft(Val, 16U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones + * test to test for bad + * data bits + */ + + Val = (u16) (~((u16)1U << j)); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)16; i++) { + /* write memory location */ + Addr[i] = Val; + Val = ~((u16)RotateLeft(~((u32)Val), 16U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16) (~((u16)1U << j)); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)16; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u16)RotateLeft(~((u32)Val), 16U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Val = ~(u16) (UINTPTR) &Addr[i]; + Addr[i] = Val; + } + /* + * Check every word within the words + * of tested memory + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + Val = ~(u16) (UINTPTR) &Addr[i]; + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + if (Pattern == (u16)0) { + Val = 0xDEADU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed pattern + */ + + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed pattern + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) +{ + u32 i; + u32 j; + u8 Val; + u8 FirtVal; + u8 WordMem8; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * select the proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + Val = (u8)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + for (i = 0U; i < (u32)8; i++) { + /* write memory location */ + Addr[i] = Val; + Val = (u8)RotateLeft(Val, 8U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8)((u32)1 << j); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)8; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val = (u8)RotateLeft(Val, 8U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test to test + * for bad data bits + */ + Val = (u8) (~(1U << j)); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + for (i = 0U; i < (u32)8; i++) { + /* write memory location */ + Addr[i] = Val; + Val = ~((u8)RotateLeft(~((u32)Val), 8U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8) (~(1U << j)); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)8; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + + Val = ~((u8)RotateLeft(~((u32)Val), 8U)); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Val = ~(u8) (UINTPTR) &Addr[i]; + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + Val = ~(u8) (UINTPTR) &Addr[i]; + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u8)0) { + Val = 0xA5U; + } + else { + Val = Pattern; + } + /* + * Fill the memory with fixed Pattern + */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + } + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} +#endif + +/*****************************************************************************/ +/** +* +* @brief Rotates the provided value to the left one bit position +* +* @param Input is value to be rotated to the left +* @param Width is the number of bits in the input data +* +* @return The resulting unsigned long value of the rotate left +* +* +*****************************************************************************/ +static u32 RotateLeft(u32 Input, u8 Width) +{ + u32 Msb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1UL << (Width - 1U); + + WidthMask = (MsbMask << (u32)1) - (u32)1; + + /* + * set the Width of the Input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + Msb = LocalInput & MsbMask; + + ReturnVal = LocalInput << 1U; + + if (Msb != 0x00000000U) { + ReturnVal = ReturnVal | (u32)0x00000001; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} + +#ifdef ROTATE_RIGHT +/*****************************************************************************/ +/** +* +* @brief Rotates the provided value to the right one bit position +* +* @param Input: value to be rotated to the right +* @param Width: number of bits in the input data +* +* @return +* The resulting u32 value of the rotate right +* +*****************************************************************************/ +static u32 RotateRight(u32 Input, u8 Width) +{ + u32 Lsb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1U << (Width - 1U); + + WidthMask = (MsbMask << 1U) - 1U; + + /* + * set the width of the input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + ReturnVal = LocalInput >> 1U; + + Lsb = LocalInput & 0x00000001U; + + if (Lsb != 0x00000000U) { + ReturnVal = ReturnVal | MsbMask; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} +#endif /* ROTATE_RIGHT */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_testmem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_testmem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.c new file mode 100644 index 0000000..89c6d16 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.c @@ -0,0 +1,1361 @@ +/******************************************************************************/ +/** +* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_util.c +* +* xil_util.c file contains xil utility functions +* Except few functions, most of these functions are wrappers to standard functions. +* The standard string functions do not validate the input and that results into +* buffer overflows. To avoid it, the wrapper function validates the input and +* then passed to standard function. There are few constant time functions +* ( xxx_CT() ) which are used to compare the data in constant time. +* The constant time functions should be used while comparing secure data +* like password, keys which prevent disclosing of the data using +* timing analysis. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.4   mmd      04/21/19 First release.
+* 7.2   nava     08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
+*                         API to use microsecond timeout instead of a free
+*                         counter.
+* 7.3   kal      06/30/20 Converted Xil_Ceil macro to API.
+*       rpo      08/19/20 Added function for read,modify,write
+*       kal      09/22/20 Changed the param type from const char to const char*
+*                         to avoid copying key onto stack
+*       td       10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
+*                         Xil_MemCmp functions
+* 7.4   am       11/26/20 Added Xil_StrCpyRange function
+* 7.6   kpt      07/15/21 Added Xil_SecureZeroize function
+* 7.7   kpt      11/09/21 Added Xil_SMemCmp, Xil_SMemCmp_CT, Xil_SMemCpy,
+*                         Xil_SMemSet, Xil_SStrCat, Xil_SStrCmp, Xil_SStrCmp_CT
+*                         Xil_SStrCpy functions
+*       kpt      11/25/21 Added strnlen function to fix ARMCC compilation
+*                         failure
+* 7.7	sk	 01/10/22 Update functions return type and update RetVal variable
+* 			  data type to fix misra_c_2012_directive_4_6 misrac
+* 			  violations.
+* 7.7	sk	 01/10/22 Update values from signed to unsigned to fix
+* 			  misra_c_2012_rule_10_4 violation.
+* 7.7	sk	 01/10/22 Add explicit parentheses to fix misra_c_2012_rule_12_1
+* 			  violation.
+* 7.7	sk	 01/10/22 Typecast character strings to u8 to fix misra_c_2012_rule_
+* 			  10_3 violation.
+* 7.7	sk	 01/10/22 Modify the code to reduce multiple break statements
+* 			  and fix misra_c_2012_rule_15_4 violation.
+* 7.7	sk	 01/10/22 Modify Xil_SMemCmp_CT and Xil_SMemCmp function argument
+* 			  type to fix misra_c_2012_rule_8_3 violation.
+* 7.7	sk	 01/10/22 Update conditional expression to fix misra_c_2012_rule_14_4
+* 			  violation.
+*       bm       01/20/22 Fix compilation warnings in Xil_SMemCpy
+*       mmd      02/28/22 Added Xil_SMemMove function
+* 8.0	sk	 03/02/22 Add explicit parentheses to fix misra_c_2012_rule_12_1
+* 			  violation.
+* 8.0	sk	 03/02/22 Add const qualifier to varaibles to fix misra_c_2012_rule_
+* 			  11_8 violation.
+* 8.0	sk	 03/02/22 Typecast expression with unsigned int to fix
+* 			  misra_c_2012_rule_10_7 violation.
+* 8.0	sk	 03/02/22 Typecast variables with unsigned or signed to fix misra_c
+* 			  _2012_rule_10_3 violation.
+* 8.0	sk	 03/02/22 Add const to unmodified variable to fix misra_c_2012
+* 			  _rule_8_13 violation.
+* 8.0	sk	 03/02/22 Typecast the function with void as return type is
+* 			  not used and fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk	 03/02/22 Remove increment operations during comparision to
+* 			  fix misra_c_2012_rule_13_3 violation.
+* 8.0	sk	 03/02/22 Update values from signed to unsigned to fix
+* 			  misra_c_2012_rule_10_4 violation.
+* 8.0	sk	 03/17/22 Add const to unmodified pointer variable to fix misra_c
+*			  _2012_rule_8_13 violation.
+* 8.0   adk      04/18/22 Added Xil_WaitForEventSet function.
+*       adk	 07/15/22 Updated the Xil_WaitForEventSet() API to
+*			  support variable number of events.
+*	ssc	 08/25/22 Added Xil_SecureRMW32 API
+* 8.1	sa       09/29/22 Change the type of first argument passed to Xil_WaitForEvent
+*			  API from u32 to UINTPTR for supporting 64 bit addressing.
+* 8.1   sa       10/20/22 Change the type of first argument passed to Xil_WaitForEvents
+*                         API from u32 to UINTPTR for supporting 64 bit addressing.
+* 8.1   akm      01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs.
+* 9.0   ml       03/03/23 Add description to fix doxygen warnings.
+* 9.0   ml       04/26/23 Updated code to fix DC.STRING BUFFER and VARARGS coverity warnings.
+* 9.0   ml       09/13/23 Replaced numerical types (int) with proper typedefs(s32) to
+*                         fix MISRA-C violations for Rule 4.6
+*
    +* +*****************************************************************************/ + +/****************************** Include Files *********************************/ +#include "xil_util.h" +#include "sleep.h" + +/************************** Constant Definitions ****************************/ +#define MAX_NIBBLES 8U /**< maximum nibbles */ + +/************************** Function Prototypes *****************************/ +void (*fptr)(void) = NULL; + +#ifdef __ARMCC_VERSION +/******************************************************************************/ +/** + * + * This API returns the length of the input string + * + * @param StartPtr is the pointer to the input string + * @param StrSize is the maximum length of the input string + * + * @return Returns the length of the input string + * + ******************************************************************************/ +static size_t strnlen (const char *StartPtr, size_t StrSize) +{ + const char *EndPtr = StartPtr; + size_t StrLen = 0U; + + EndPtr = memchr(StartPtr, '\0', StrSize); + if (EndPtr == NULL) { + StrLen = StrSize; + } else { + StrLen = (size_t) (EndPtr - StartPtr); + } + + return StrLen; +} +#endif + +/******************************************************************************/ +/** +* This API ceils the provided float value. +* +* @param Value is a float variable which has to ceiled to nearest +* integer. +* +* @return Returns ceiled value. +* +*******************************************************************************/ +s32 Xil_Ceil(float Value) +{ + s32 Result = Value; + + if (Value > Result) { + Result = Result + 1; + } + + return Result; +} + +/****************************************************************************/ +/** + * Converts the char into the equivalent nibble. + * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9 + * + * @param InChar - Input character to be converted to nibble. + * Valid characters are between 0-9, a-f, A-F + * @param Num - Memory location where nibble is to be stored + * + * @return + * XST_SUCCESS - Character converted to nibble + * XST_FAILURE - Invalid input character + * + * @note None. + * + *****************************************************************************/ + +u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num) +{ + u32 Status; + + /* Convert the char to nibble */ + if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) { + *Num = InChar - (u8)'0'; + Status = XST_SUCCESS; + } else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) { + *Num = InChar - (u8)'a' + 10U; + Status = XST_SUCCESS; + } else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) { + *Num = InChar - (u8)'A' + 10U; + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + return Status; +} + +/****************************************************************************/ +/* + * Converts the string into the equivalent Hex buffer. + * Ex: "abc123" -> {0xab, 0xc1, 0x23} + * + * @param Str - Pointer to string to be converted to Hex. + * Accepted characters in string are between 0-9, a-f and A-F + * @param Buf - Pointer to memory location where converted hex values are to + * be stored. + * @param Len - Length of input string + * + * @return + * XST_SUCCESS - Input string is converted to hex + * XST_FAILURE - Invalid character in inpit string + * + * @note None. + * + *****************************************************************************/ +u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len) +{ + u32 Status = XST_FAILURE; + u8 ConvertedLen = 0U, index = 0U; + u8 Nibble[MAX_NIBBLES] = {0U}; + u8 i; + + while (ConvertedLen < Len) { + for (i = 0U; i < MAX_NIBBLES; i++) { + Status = Xil_ConvertCharToNibble((u8)Str[ConvertedLen], + &Nibble[i]); + ConvertedLen = ConvertedLen + 1U; + if (Status != XST_SUCCESS) { + /* Error converting char to nibble */ + goto END; + } + } + + buf[index] = (((u32)Nibble[0] << (u8)28U) | ((u32)Nibble[1] << (u8)24U) | + ((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) | + ((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) | + ((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]); + index++; + } +END: + return Status; +} + +#ifdef VERSAL_PLM +/****************************************************************************/ +/* + * Register PLM Alive Handler. + * + * @param PlmAlive - Pointer to PlmAlive API. + * + * @return None. + * + *****************************************************************************/ +void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) +{ + fptr = PlmAlive; +} + +/****************************************************************************/ +/* + * PLM Stub Handler called while waiting for event. + * + * @param None. + * + * @return None. + * + *****************************************************************************/ +void Xil_PlmStubHandler(void) +{ + if (fptr != NULL) { + fptr(); + } +} +#endif + +/****************************************************************************/ +/* + * Waits for the event + * + * @param RegAddr - Address of register to be checked for event(s) occurrence + * @param EventMask - Mask indicating event(s) to be checked + * @param Event - Specific event(s) value to be checked + * @param Timeout - Max number of microseconds to wait for an event(s). + * + * @return + * XST_SUCCESS - On occurrence of the event(s). + * XST_FAILURE - Event did not occur before counter reaches 0 + * + * @note None. + * + *****************************************************************************/ +u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout) +{ + u32 EventStatus; + u32 PollCount = Timeout; + u32 Status = XST_FAILURE; + + while (PollCount > 0U) { + EventStatus = Xil_In32(RegAddr) & EventMask; + if (EventStatus == Event) { + Status = XST_SUCCESS; + break; + } + PollCount--; +#ifdef VERSAL_PLM + Xil_PlmStubHandler(); +#endif + usleep(1U); + } + + return Status; +} + + +/******************************************************************************/ +/** + * Waits for the events. Returns on occurrence of first event / timeout. + * + * @param EventsRegAddr - Address of register to be checked for event(s) + * occurrence + * @param EventsMask - Mask indicating event(s) to be checked + * @param WaitEvents - Specific event(s) to be checked + * @param Timeout - Max number of microseconds to wait for an event(s). + * @param Events - Mask of Events occurred returned in memory pointed by + * this variable + * + * @return + * XST_SUCCESS - On occurrence of the event(s). + * XST_FAILURE - Event did not occur before counter reaches 0 + * + ******************************************************************************/ +u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, + u32 Timeout, u32 *Events) +{ + u32 EventStatus; + u32 PollCount = Timeout; + u32 Status = XST_TIMEOUT; + + *Events = 0x00; + do { + EventStatus = Xil_In32(EventsRegAddr); + EventStatus &= EventsMask; + if ((EventStatus & WaitEvents) != 0U) { + Status = XST_SUCCESS; + *Events = EventStatus; + break; + } + PollCount--; +#ifdef VERSAL_PLM + Xil_PlmStubHandler(); +#endif + usleep(1U); + } while (PollCount > 0U); + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether the passed character is a valid hex digit + * + * @param Ch - Pointer to the input character + * + * @return + * XST_SUCCESS - on valid hex digit + * XST_FAILURE - on invalid hex digit + * + * @note None. + * + ******************************************************************************/ +u32 Xil_IsValidHexChar(const char *Ch) +{ + u32 Status = XST_FAILURE; + + if (NULL == Ch) { + goto END; + } + if (((*Ch >= '0') && (*Ch <= '9')) || + ((*Ch >= 'a') && (*Ch <= 'f')) || + ((*Ch >= 'A') && (*Ch <= 'F'))) { + + Status = XST_SUCCESS; + } +END: + return Status; +} + +/******************************************************************************/ +/** + * Validate the input string contains only hexadecimal characters + * + * @param HexStr - Pointer to string to be validated + * + * @return + * XST_SUCCESS - On valid input hex string + * XST_INVALID_PARAM - On invalid length of the input string + * XST_FAILURE - On non hexadecimal character in string + * + * @note None + * + ******************************************************************************/ +u32 Xil_ValidateHexStr(const char *HexStr) +{ + u32 Idx; + u32 Len; + u32 Status = XST_INVALID_PARAM; + + if (NULL == HexStr) { + goto END; + } + + Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U); + if (Len > XIL_MAX_HEX_STR_LEN) { + goto END; + } + + for (Idx = 0U; Idx < Len; Idx++) { + Status = Xil_IsValidHexChar(&HexStr[Idx]); + if (Status != XST_SUCCESS) { + break; + } + } + +END: + return Status; +} + +/****************************************************************************/ +/** + * Converts the string into the equivalent Hex buffer. + * Ex: "abc123" -> {0xab, 0xc1, 0x23} + * + * @param Str is a Input String. Will support the lower and upper case values. + * Value should be between 0-9, a-f and A-F + * @param Buf is Output buffer. + * @param Len of the input string. Should have even values + * + * @return + * - XST_SUCCESS no errors occurred. + * - XST_FAILURE an error when input parameters are not valid + * - an error when input buffer has invalid values + * + * TDD Test Cases: + * ---Initialization--- + * Len is odd + * Len is zero + * Str is NULL + * Buf is NULL + * ---Functionality--- + * Str input with only numbers + * Str input with All values in A-F + * Str input with All values in a-f + * Str input with values in a-f, 0-9, A-F + * Str input with values in a-z, 0-9, A-Z + * Boundary Cases + * Memory Bounds of buffer checking + * ****************************************************************************/ +u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len) +{ + u32 ConvertedLen; + u8 LowerNibble = 0U; + u8 UpperNibble = 0U; + u32 Status = (u32)XST_FAILURE; + + if ((Str == NULL) || (Buf == NULL)) { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + + if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + + ConvertedLen = 0U; + while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), &UpperNibble) + == (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == (u32)XST_SUCCESS)) { + Buf[ConvertedLen / 2U] = + (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | + LowerNibble; + } else { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + ConvertedLen += 2U; + } + Status = (u32)XST_SUCCESS; +END: + return Status; +} + +/******************************************************************************/ +/** + * Converts the string into the equivalent Hex buffer. + * Ex: "abc123" -> {0x23, 0xc1, 0xab} + * + * @param Str - Input String to be converted to hex number in little + * endian format. Valid characters of input strin are between + * 0-9, a-f and A-F + * @param Buf - Pointer to memory location where converted hex numbers are to + * be stored. + * @param Len - Expected number of output bits + * + * @return + * XST_SUCCESS - Input string is converted to hex number(s) + * XST_FAILURE - Invalid input character detected in input string + * + * @note + * + ******************************************************************************/ +u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len) +{ + u32 ConvertedLen; + u8 LowerNibble = 0U; + u8 UpperNibble = 0U; + u32 StrIndex; + u32 Status = XST_FAILURE; + + if ((NULL == Str) || (NULL == Buf)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + Status = XST_INVALID_PARAM; + goto END; + } + + StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U; + ConvertedLen = 0U; + while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), + &UpperNibble) == XST_SUCCESS) && + (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == XST_SUCCESS)) { + Buf[StrIndex] = + (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | + LowerNibble; + StrIndex = StrIndex - 1U; + } else { + Status = XST_INVALID_PARAM; + goto END; + } + ConvertedLen += 2U; + } + + Status = XST_SUCCESS; +END: + return Status; +} + +/******************************************************************************/ +/** + * Returns the length of input string. + * + * @param Str - Input string + * @param MaxLen - Maximum expected length of the input string + * + * @return + * Returns length of the input string if length is less than MaxLen. + * Returns MaxLen if the length of the input string is >= MaxLen. + * + * @note + * + ******************************************************************************/ +u32 Xil_Strnlen(const char *Str, u32 MaxLen) +{ + const char *InStr = Str; + u32 StrLen = 0U; + + if (NULL == Str) { + goto END; + } + + while (StrLen < MaxLen) { + if ('\0' == *InStr) { + break; + } + StrLen++; + InStr++; + } + +END: + return StrLen; +} + +/*****************************************************************************/ +/** + * @brief This function will Read, Modify and Write to an address. + * + * @param Addr denotes Address + * @param Mask denotes the bits to be modified + * @param Value is the value to be written to the address + * + * @return None + * + *****************************************************************************/ +void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value) +{ + u32 Val; + + Val = Xil_In32(Addr); + Val = (Val & (~Mask)) | (Mask & Value); + Xil_Out32(Addr, Val); +} + +/*****************************************************************************/ +/** + * @brief This functions copies source string to destination string. This + * function is a safe version of strcpy + * + * @param DestPtr is pointer to destination string + * @param SrcPtr is pointer to source string + * @param Size is the maximum number of bytes of the source string + * to be copied + * + * @return XST_SUCCESS on success and error code on failure + * + ******************************************************************************/ +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size) +{ + int Status = XST_FAILURE; + u32 Count; + + if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) { + goto END; + } + + for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) { + DestPtr[Count] = SrcPtr[Count]; + } + if (Count == Size) { + DestPtr[0U] = '\0'; + goto END; + } + DestPtr[Count] = '\0'; + Status = XST_SUCCESS; + +END: + return Status; +} + +/****************************************************************************/ +/** + * @brief Copies specified range from source string to destination string + * + * @param Src is a pointer to source string + * @param Dest is a pointer to destination string + * @param From is 0 based index from where string copy starts + * @param To is 0 based index till which string is copied + * @param MaxSrcLen is the maximum length of source string + * @param MaxDstLen is the maximum length of destination string + * + * @return XST_SUCCESS on success + * XST_FAILURE on failure + * + * @note None + * + ****************************************************************************/ +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen) +{ + int Status = XST_FAILURE; + u32 SrcLength; + u32 Index; + + if ((Src == NULL) || (Dest == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if ((To >= MaxSrcLen) || (To < From)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if ((To - From + 1U) >= MaxDstLen) { + Status = XST_INVALID_PARAM; + goto END; + } + + SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen); + if (To >= SrcLength) { + Status = XST_INVALID_PARAM; + goto END; + } + + for (Index = From; (Index <= To) && (Src[Index] != (u8)'\0'); Index++) { + Dest[Index - From] = Src[Index]; + } + + Dest[Index - From] = (u8)'\0'; + Status = XST_SUCCESS; + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function appends string2 to string1. This function is a safe + * version of strcat + * + * @param Str1Ptr is pointer to string1 + * @param Str2Ptr is pointer to string2 + * @param Size is the maximum number of bytes Str1 can hold + * + * @return XST_SUCCESS on success and error code on failure + * + ******************************************************************************/ +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size) +{ + int Status = XST_FAILURE; + u32 Count = 0U; + u32 CountTmp = 0U; + + if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) { + goto END; + } + + while ((Count < Size) && (Str1Ptr[Count] != '\0')) { + Count++; + } + + while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) { + Str1Ptr[Count] = Str2Ptr[CountTmp]; + Count++; + CountTmp++; + } + if (Count == Size) { + Str1Ptr[0U] = '\0'; + goto END; + } + Str1Ptr[Count] = '\0'; + Status = XST_SUCCESS; + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function copies Len bytes from source memory to destination + * memory. If Len is greater than DestPtrLen, then DestPtr is also + * filled with 0s till DestPtrLen bytes and is considered as a failure. + * This function is a secure implementation of memcpy + * + * @param DestPtr is pointer to destination address + * @param DestPtrLen is the memory alloted to the destination buffer + * @param SrcPtr is pointer to source address + * @param Len is number of bytes to be copied + * + * @return XST_SUCCESS on success and error code on failure + * + ******************************************************************************/ +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len) +{ + int Status = XST_FAILURE; + u8 *Dest = (u8 *)DestPtr; + const u8 *Src = (const u8 *)SrcPtr; + + if ((DestPtr == NULL) || (SrcPtr == NULL)) { + goto END; + } + + if (Len > DestPtrLen) { + while (DestPtrLen != 0U) { + *Dest = 0U; + Dest++; + DestPtrLen--; + } + goto END; + } + + /* Loop and copy. */ + while (Len != 0U) { + *Dest = *Src; + Dest++; + Src++; + Len--; + } + Status = XST_SUCCESS; + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares Len bytes from memory1 and memory2. This + * function is a secure implementation of memcmp + * + * @param Buf1Ptr is pointer to memory1 + * @param Buf2Ptr is pointer to memory2 + * @param Len is number of byets to be compared + * + * @return 0 if contents of both the memory regions are same, + * -1 if first non-matching character has lower value in Buf1Ptr + * 1 if first non-matching character is greater value in Buf1Ptr + * + ******************************************************************************/ +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len) +{ + volatile int RetVal = 1; + const u8 *Buf1 = Buf1Ptr; + const u8 *Buf2 = Buf2Ptr; + u32 Size = Len; + + /* Assert validates the input arguments */ + if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) { + goto END; + } + + /* Loop and compare */ + while (Size != 0U) { + if (*Buf1 > *Buf2) { + RetVal = 1; + goto END; + } else if (*Buf1 < *Buf2) { + RetVal = -1; + goto END; + } else { + Buf1++; + Buf2++; + Size--; + } + } + + /* Make sure size is zero to know the whole of data is compared */ + if (Size == 0U) { + RetVal = 0; + } + +END: + return RetVal; +} + +/*****************************************************************************/ +/** + * @brief This function is used to zeroize the memory + * + * @param DataPtr Pointer to the memory which need to be zeroized. + * @param Length Length of the data in bytes. + * + * @return + * - XST_SUCCESS: If Zeroization is successful. + * - XST_FAILURE: If Zeroization is not successful. + ********************************************************************************/ +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length) +{ + u32 Index; + int Status = XST_FAILURE; + + /* Clear the data */ + (void)memset(DataPtr, 0, Length); + + /* Read it back to verify */ + for (Index = 0U; Index < Length; Index++) { + if (DataPtr[Index] != 0x00U) { + goto END; + } + } + if (Index == Length) { + Status = XST_SUCCESS; + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares two memory regions for specified number + * of bytes. This function takes size of two memory regions to + * make sure not to read from or write to out of bound memory + * region. + * + * @param Src1 - Pointer to first memory range + * @param Src1Size - Maximum size of first memory range + * @param Src2 - Pointer to second memory range + * @param Src2Size - Maximum size of second memory range + * @param CmpLen - Number of bytes to be compared + * + * @return + * XST_SUCCESS - If specified number of bytes matches + * XST_FAILURE - If there is a mistmatch found during comparison + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemCmp(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) +{ + int Status = XST_FAILURE; + + if ((Src1 == NULL) || (Src2 == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + Status = XST_INVALID_PARAM; + } else { + Status = memcmp (Src1, Src2, CmpLen); + if (Status != 0) { + Status = XST_FAILURE; + } + } + + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares two memory regions for specified number + * of bytes. This function takes size of two memory regions to + * make sure not to read from or write to out of bound memory + * region. + * Note that this function compares till end to make it execute + * in constant time irrespective of the content of input memory. + * + * @param Src1 - Pointer to first memory range + * @param Src1Size - Maximum size of first memory range + * @param Src2 - Pointer to second memory range + * @param Src2Size - Maximum size of second memory range + * @param CmpLen - Number of bytes to be compared + * + * @return + * XST_SUCCESS - If specified number of bytes matches + * XST_FAILURE - If mistmatch + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) +{ + volatile int Status = XST_FAILURE; + volatile int StatusRedundant = XST_FAILURE; + volatile u32 Data = 0U; + volatile u32 DataRedundant = 0xFFFFFFFFU; + u32 Cnt = CmpLen; + const u8 *Src_1 = (const u8 *)Src1; + const u8 *Src_2 = (const u8 *)Src2; + + + if ((Src1 == NULL) || (Src2 == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + Status = XST_INVALID_PARAM; + } else { + while (Cnt >= sizeof(u32)) { + Data |= (*(const u32 *)Src_1 ^ * (const u32 *)Src_2); + DataRedundant &= ~Data; + Src_1 += sizeof(u32); + Src_2 += sizeof(u32); + Cnt -= sizeof(u32); + } + + while (Cnt > 0U) { + Data |= (u32)(*Src_1 ^ *Src_2); + DataRedundant &= ~Data; + Src_1++; + Src_2++; + Cnt--; + } + + if ((Data == 0U) && (DataRedundant == 0xFFFFFFFFU)) { + Status = XST_SUCCESS; + StatusRedundant = XST_SUCCESS; + } + } + + return (Status | StatusRedundant); +} + +/*****************************************************************************/ +/** + * @brief This is wrapper function to memcpy function. This function + * takes size of two memory regions to make sure not read from + * or write to out of bound memory region. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Src - Pointer to source memory + * @param SrcSize - Maximum data that can be copied from source + * @param CopyLen - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) +{ + int Status = XST_FAILURE; + const u8 *Src8 = (const u8 *) Src; + const u8 *Dst8 = (u8 *) Dest; + void *volatile DestTemp = Dest; + const void *volatile SrcTemp = Src; + + if ((Dest == NULL) || (Src == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + Status = XST_INVALID_PARAM; + } + /* Return error for overlap string */ + else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) { + Status = XST_INVALID_PARAM; + } else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { + Status = XST_INVALID_PARAM; + } else { + (void)memcpy(DestTemp, SrcTemp, CopyLen); + Status = XST_SUCCESS; + } + + return Status; +} + +/*****************************************************************************/ +/** + * @brief This is wrapper function to memset function. This function + * writes specified byte to destination specified number of times. + * This function also takes maximum string size that destination + * holds to make sure not to write out of bound area. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Data - Any value from 0 to 255 + * @param Len - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemSet(void *Dest, const u32 DestSize, + const u8 Data, const u32 Len) +{ + int Status = XST_FAILURE; + + if ((Dest == NULL) || (DestSize < Len) || (Len == 0U)) { + Status = XST_INVALID_PARAM; + } else { + (void)memset(Dest, (s32)Data, Len); + Status = XST_SUCCESS; + } + + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function concatenates two strings. This function + * takes size of both strings to make sure not to read from / + * write to out of bound area. + * + * @param DestStr - Pointer to destination string + * @param DestSize - Maximum string size that detination can hold + * @param SrcStr - Pointer to source string + * @param SrcSize - Maximum string size that source can hold + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) +{ + int Status = XST_FAILURE; + u32 SrcLen; + u32 DstLen; + u32 Length; + + if ((DestStr == NULL) || (SrcStr == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + SrcLen = strnlen((const char *)SrcStr, SrcSize); + DstLen = strnlen((const char *)DestStr, DestSize); + Length = SrcLen + DstLen; + + if ((DestSize <= DstLen) || (SrcSize <= SrcLen)) { + Status = XST_INVALID_PARAM; + } else if (DestSize <= Length) { + Status = XST_INVALID_PARAM; + } else { + (void)strncat((char *)DestStr, (const char *)SrcStr, Length); + Status = XST_SUCCESS; + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares two strings. It also takes maximum string + * size that Src1 and Src2 can hold to make sure not to read out of + * bound data for comparison. + * + * @param Str1 - Pointer to first string + * @param Str1Size - Maximum string size that Str1 can hold + * @param Str2 - Pointer to second string + * @param Str2Size - Maximum string size that Str2 can hold + * + * @return + * XST_SUCCESS - If both strings are same + * XST_FAILURE - If there is difference between two strings + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) +{ + int Status = XST_FAILURE; + u32 Str1Len = 0U; + u32 Str2Len = 0U; + + if ((Str1 == NULL) || (Str2 == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); + + if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { + Status = XST_INVALID_PARAM; + } else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) { + Status = XST_FAILURE; + } else { + Status = memcmp(Str1, Str2, Str1Len); + if (Status != 0) { + Status = XST_FAILURE; + } + } + +END: + return Status; +} + + +/*****************************************************************************/ +/** + * @brief This function compares two strings. It also takes maximum string + * size that Src1 and Src2 can hold to make sure not to read out of + * bound data for comparison. This function compares each character + * of the strings so that execution time of the function is not + * dependent on the content of two input strings. The execution + * time is constant when string size are same. + * + * @param Str1 - Pointer to first string + * @param Str1Size - Maximum string size that Str1 can hold + * @param Str2 - Pointer to second string + * @param Str2Size - Maximum string size that Str2 can hold + * + * @return + * XST_SUCCESS - If both strings are same + * XST_FAILURE - If there is difference between two strings + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) +{ + int Status = XST_FAILURE; + u32 Str1Len = 0U; + u32 Str2Len = 0U; + + if ((Str1 == NULL) || (Str2 == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); + + if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { + Status = XST_INVALID_PARAM; + } else if (Str1Len != Str2Len) { + Status = XST_FAILURE; + } else { + Status = Xil_SMemCmp_CT (Str1, Str1Size, Str2, Str2Size, Str1Len); + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function copies one string to other. This function + * takes size of both strings to make sure not to read from / + * write to out of bound area. + * + * @param DestStr - Pointer to destination string + * @param DestSize - Maximum string size that detination can hold + * @param SrcStr - Pointer to source string + * @param SrcSize - Maximum string size that source can hold + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCpy(u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) +{ + int Status = XST_FAILURE; + u32 SrcLen = 0U; + + if ((DestStr == NULL) || (SrcStr == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + SrcLen = strnlen((const char *)SrcStr, SrcSize); + + if ((DestSize <= SrcLen) || (SrcSize <= SrcLen)) { + Status = XST_INVALID_PARAM; + } else { + (void)memcpy(DestStr, SrcStr, SrcLen + 1U); + Status = XST_SUCCESS; + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This is wrapper function to memmove function. This function + * takes size of two memory regions to avoid out of bound memory region. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Src - Pointer to source memory + * @param SrcSize - Maximum data that can be copied from source + * @param CopyLen - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) +{ + volatile int Status = XST_FAILURE; + const void *Output = NULL; + + if ((Dest == NULL) || (Src == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + Status = XST_INVALID_PARAM; + } else { + Output = memmove(Dest, Src, CopyLen); + if (Output != NULL) { + Status = XST_SUCCESS; + } + } + + return Status; +} + +/****************************************************************************/ +/* + * Waits for the event to be set with in timeout and returns error incase + * event was not set in specified time out. + * + * @param Timeout - Max number of microseconds to wait for an event, + * It should be maximum timeout needed among the + * events specified. + * @param NumOfEvents - Number of event(s) to be checked. + * @param EventAddr - Pointer to address of event(s) to be set. + * + * @return + * XST_SUCCESS - On occurrence of the event(s). + * XST_FAILURE - Event(s) did not occur before counter reaches 0 + * + * @note None. + * + *****************************************************************************/ +u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...) +{ + u32 PollCount = Timeout; + u32 Status = XST_FAILURE; + u32 LoopCnt = 0, i; + va_list Event; + + va_start(Event, EventAddr); + /* wait for all events to complete */ + for (i = 0; i < NumOfEvents; i++) { + while (PollCount > 0U) { + if (Xil_In32((UINTPTR)EventAddr)) { + LoopCnt++; + break; + } + PollCount--; +#ifdef VERSAL_PLM + Xil_PlmStubHandler(); +#endif + usleep(1U); + } + if (PollCount == 0U) { + goto END; + } + EventAddr = va_arg(Event, volatile u32 *); + PollCount = Timeout; + } + +END: + if (LoopCnt == NumOfEvents) { + Status = XST_SUCCESS; + } + + va_end(Event); + return Status; +} + +/****************************************************************************/ +/** + * @brief + * Performs a Read Modify Write operation for a memory location by writing the + * 32 bit value to the the specified address and then reading it back to + * verify the value written in the register. + * + * @param Addr contains the address to perform the output operation + * @param Mask indicates the bits to be modified + * @param Value contains 32 bit Value to be written at the specified address + * + * @return + * XST_SUCCESS on success + * XST_FAILURE on failure + * + *****************************************************************************/ +s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value) +{ + s32 Status = XST_FAILURE; + u32 ReadReg; + u32 Val; + + Val = Xil_In32(Addr); + Val = (Val & (~Mask)) | (Mask & Value); + Xil_Out32(Addr, Val); + + /* verify value written to specified address */ + ReadReg = Xil_In32(Addr) & Mask; + + if (ReadReg == (Mask & Value)) { + Status = XST_SUCCESS; + } + + return Status; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_util.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xil_util.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xil_util.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.c new file mode 100644 index 0000000..bdb7c6a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.c @@ -0,0 +1,267 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xplatform_info.c +* @addtogroup common_platform_info Hardware Platform Information +* @{ +* This file contains information about hardware for which the code is built +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
+* 7.0	aru 03/15/19  Check for versal before aarch64 and armr5
+*		      in XGetPlatform_Info()
+* 7.2   adk 08/01/20  Added versal support for the XGetPSVersion_Info function.
+* 7.6   mus 08/23/21  Updated prototypes for functions which are not taking any
+*                     arguments with void keyword. This has been done to fix
+*                     compilation warnings with "-Wstrict-prototypes" flag.
+*                     It fixes CR#1108601.
+* 7.6    mus 08/30/21 Updated flag checking to fix compilation warnings
+*                     reported with "-Wundef" flag. It fixes CR#1108601.
+
+* 7.7    mus 11/02/21 Updated XGet_Zynq_UltraMp_Platform_info and
+*                     XGetPSVersion_Info to fix compilation warning
+*                     reported with "-Wundef" flag CR#1111453
+* 8.1    mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now
+*                     they are supported only for VERSAL_NET APU and RPU.
+* 9.0    mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be
+*                     used to identify type of boot (cold/warm).
+* 9.0    mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xplatform_info.h" +#if defined (__aarch64__) +#include "bspconfig.h" +#include "xil_smc.h" +#endif +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about platform +* +* @return The information about platform defined in xplatform_info.h +* +******************************************************************************/ +u32 XGetPlatform_Info(void) +{ +#if defined (versal) + return XPLAT_VERSAL; +#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) + return XPLAT_ZYNQ_ULTRA_MP; +#elif defined (__microblaze__) + return XPLAT_MICROBLAZE; +#else + return XPLAT_ZYNQ; +#endif +} + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about zynq ultrascale MP platform +* +* @return The information about zynq ultrascale MP platform defined in +* xplatform_info.h +* +******************************************************************************/ +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(void) +{ +#if defined (__aarch64__) && (EL1_NONSECURE == 1) + XSmc_OutVar reg; + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK); +#else + u32 reg; + reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT ) + & XPLAT_INFO_MASK); + return reg; +#endif +} +#endif + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about PS Silicon version +* +* @return The information about PS Silicon version. +* +******************************************************************************/ +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal) +u32 XGetPSVersion_Info(void) +{ +#if defined (__aarch64__) && (EL1_NONSECURE == 1) + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + XSmc_OutVar reg; + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >> + XPS_VERSION_INFO_SHIFT); +#else + u32 reg; + reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS) + & XPS_VERSION_INFO_MASK); + return (reg >> XPS_VERSION_INFO_SHIFT); +#endif +} +#endif + +#if ! defined(__microblaze__) && ! defined(__riscv) +/*****************************************************************************/ +/** +* +* @brief This API is used to provide infomation about core id of the +* CPU core from which it is executed. +* +* @return Core id of the core on which API is executed. +* +******************************************************************************/ +u8 XGetCoreId(void) +{ + UINTPTR CoreId; + +#if (defined (__aarch64__) && ! defined (VERSAL_NET)) + /* CortexA53 and CortexA72 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#elif (defined (__aarch64__) && defined (VERSAL_NET)) + /* CortexA78 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#else + /* CortexA9, CortexR5 and CortexR52 */ +#ifdef __GNUC__ + CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MULTI_PROC_AFFINITY, CoreId); + CoreId &= XREG_MPIDR_MASK; +#else + { + register u32 C15Reg __asm(XREG_CP15_MULTI_PROC_AFFINITY); + CoreId = C15Reg; + } + CoreId &= XREG_MPIDR_MASK; +#endif + + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#endif + + return (u8)CoreId; +} +#endif + +#if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) +/*****************************************************************************/ +/** +* +* @brief This API is used to provide infomation about cluster id of the +* CPU core from which it is executed. +* +* @return Cluster id of the core on which API is executed. +* +******************************************************************************/ +u8 XGetClusterId(void) +{ + u64 ClusterId = 0; + +#if defined (ARMR52) + ClusterId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); + ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY1_MASK) >> \ + XREG_MPIDR_AFFINITY1_SHIFT); +#else + ClusterId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY2_MASK) >> \ + XREG_MPIDR_AFFINITY2_SHIFT); +#endif + + return (u8)ClusterId; +} + +/*****************************************************************************/ +/** +* +* @brief This API returns boot status of core from which it is executed. +* 0th bit of CORE_X_PWRDWN/RPU_PCIL_X_PWRDWN register indicates boot type. +* +* @return - 0 for cold boot +* - 1 for warm boot +* +******************************************************************************/ +u8 XGetBootStatus(void) +{ + u32 Status; + UINTPTR Addr; + +#if (__aarch64__) + u8 CpuNum; + + CpuNum = XGetClusterId(); + CpuNum *= XPS_NUM_OF_CORES_PER_CLUSTER; + CpuNum += XGetCoreId(); + + Addr = XPS_CORE_X_PWRDWN_BASEADDR + (CpuNum * XPS_CORE_X_PWRDWN_OFFSET); + Status = Xil_In32(Addr); + + return (Status & XPS_CORE_X_PWRDWN_EN_MASK); +#else + Addr = (XPS_RPU_PCIL_CLUSTER_OFFSET * XGetClusterId()) + XPS_RPU_PCIL_A0_PWRDWN; + Addr += (XGetCoreId() * XPS_RPU_PCIL_CORE_OFFSET); + + Status = Xil_In32(Addr); + + return (Status & XPS_RPU_PCIL_X_PWRDWN_EN_MASK); +#endif + +} + +#endif + +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xplatform_info.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xplatform_info.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.c new file mode 100644 index 0000000..fca4d5e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.c @@ -0,0 +1,224 @@ +/****************************************************************************** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.c +* @addtogroup xpm_init xpm APIs +* +* This file contains the xpm node data and API's. +* @{ +* @details +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
    +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "bspconfig.h" +#if defined (XPM_SUPPORT) +#include "xil_assert.h" +#include "xparameters.h" +#include "pm_api_sys.h" +#include "xpm_nodeid.h" +#include "xstatus.h" +#include "xpm_init.h" + +/************************** Constant Definitions *****************************/ + +#define XPMU_IPI_CHANNEL_ID XPAR_XIPIPSU_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +static XIpiPsu IpiInst; +/************************** Function Prototypes ******************************/ + +/************************** Global Variables ********************************/ + +#ifdef VERSAL_NET +XpmNodeInfo XpmNodeData[] = { + /* { Base Address, Node ID, Reset ID } */ + { 0xF1B00000U, PM_DEV_USB_0, PM_RST_USB_0 }, /* USB_0 */ + { 0xF1C00000U, PM_DEV_USB_1, PM_RST_USB_1 }, /* USB_1 */ + { 0xF19E0000U, PM_DEV_GEM_0, PM_RST_GEM_0 }, /* GEM_0 */ + { 0xF19F0000U, PM_DEV_GEM_1, PM_RST_GEM_1 }, /* GEM_1 */ + { 0xF1960000U, PM_DEV_SPI_0, PM_RST_SPI_0 }, /* SPI_0 */ + { 0xF1970000U, PM_DEV_SPI_1, PM_RST_SPI_1 }, /* SPI_1 */ + { 0xF1940000U, PM_DEV_I2C_0, PM_RST_I2C_0 }, /* I2C_0 */ + { 0xF1950000U, PM_DEV_I2C_1, PM_RST_I2C_1 }, /* I2C_1 */ + { 0xF1980000U, PM_DEV_CAN_FD_0, PM_RST_CAN_FD_0 }, /* CAN_FD_0 */ + { 0xF1990000U, PM_DEV_CAN_FD_1, PM_RST_CAN_FD_1 }, /* CAN_FD_1 */ + { 0xF1920000U, PM_DEV_UART_0, PM_RST_UART_0 }, /* UART_0 */ + { 0xF1930000U, PM_DEV_UART_1, PM_RST_UART_1 }, /* UART_1 */ + { 0xF19D0000U, PM_DEV_GPIO, PM_RST_GPIO_LPD }, /* GPIO */ + { 0xF1DC0000U, PM_DEV_TTC_0, PM_RST_TTC_0 }, /* TTC_0 */ + { 0xF1DD0000U, PM_DEV_TTC_1, PM_RST_TTC_1 }, /* TTC_1 */ + { 0xF1DE0000U, PM_DEV_TTC_2, PM_RST_TTC_2 }, /* TTC_2 */ + { 0xF1DF0000U, PM_DEV_TTC_3, PM_RST_TTC_3 }, /* TTC_3 */ + { 0xEA420000U, PM_DEV_LPD_SWDT_0, PM_RST_SWDT_0 }, /* LPD_SWDT_0 */ + { 0xEA430000U, PM_DEV_LPD_SWDT_1, PM_RST_SWDT_1 }, /* LPD_SWDT_1 */ + { 0xECC10000U, PM_DEV_FPD_SWDT_0, PM_RST_FPD_SWDT_0 }, /* FPD_SWDT_0 */ + { 0xECD10000U, PM_DEV_FPD_SWDT_1, PM_RST_FPD_SWDT_1 }, /* FPD_SWDT_1 */ + { 0xECE10000U, PM_DEV_FPD_SWDT_2, PM_RST_FPD_SWDT_2 }, /* FPD_SWDT_2 */ + { 0xECF10000U, PM_DEV_FPD_SWDT_3, PM_RST_FPD_SWDT_3 }, /* FPD_SWDT_3 */ + { 0xF1010000U, PM_DEV_OSPI, PM_RST_OSPI }, /* OSPI */ + { 0xF1030000U, PM_DEV_QSPI, PM_RST_QSPI }, /* QSPI */ + { 0xF1020000U, PM_DEV_GPIO_PMC, PM_RST_GPIO_PMC }, /* GPIO_PMC */ + { 0xF1000000U, PM_DEV_I2C_PMC, PM_RST_I2C_PMC }, /* I2C_PMC */ + { 0xF1040000U, PM_DEV_SDIO_0, PM_RST_SDIO_0 }, /* SDIO_0 */ + { 0xF1050000U, PM_DEV_SDIO_1, PM_RST_SDIO_1 }, /* EMMC */ + { 0xEBD00000U, PM_DEV_ADMA_0, PM_RST_ADMA }, /* ADMA_0 */ + { 0xEBD10000U, PM_DEV_ADMA_1, PM_RST_ADMA }, /* ADMA_1 */ + { 0xEBD20000U, PM_DEV_ADMA_2, PM_RST_ADMA }, /* ADMA_2 */ + { 0xEBD30000U, PM_DEV_ADMA_3, PM_RST_ADMA }, /* ADMA_3 */ + { 0xEBD40000U, PM_DEV_ADMA_4, PM_RST_ADMA }, /* ADMA_4 */ + { 0xEBD50000U, PM_DEV_ADMA_5, PM_RST_ADMA }, /* ADMA_5 */ + { 0xEBD60000U, PM_DEV_ADMA_6, PM_RST_ADMA }, /* ADMA_6 */ + { 0xEBD70000U, PM_DEV_ADMA_7, PM_RST_ADMA }, /* ADMA_7 */ + { 0xEB300000U, PM_DEV_IPI_0, PM_RST_IPI }, /* IPI */ +}; +#elif defined(versal) +XpmNodeInfo XpmNodeData[] = { + /* { Base Address, Node ID, Reset ID } */ + { 0xFE200000U, PM_DEV_USB_0, PM_RST_USB_0 }, /* USB_0 */ + { 0xFF0C0000U, PM_DEV_GEM_0, PM_RST_GEM_0 }, /* GEM_0 */ + { 0xFF0D0000U, PM_DEV_GEM_1, PM_RST_GEM_1 }, /* GEM_1 */ + { 0xFF040000U, PM_DEV_SPI_0, PM_RST_SPI_0 }, /* SPI_0 */ + { 0xFF050000U, PM_DEV_SPI_1, PM_RST_SPI_1 }, /* SPI_1 */ + { 0xFF020000U, PM_DEV_I2C_0, PM_RST_I2C_0 }, /* I2C_0 */ + { 0xFF030000U, PM_DEV_I2C_1, PM_RST_I2C_1 }, /* I2C_1 */ + { 0xFF060000U, PM_DEV_CAN_FD_0, PM_RST_CAN_FD_0 }, /* CAN_FD_0 */ + { 0xFF070000U, PM_DEV_CAN_FD_1, PM_RST_CAN_FD_1 }, /* CAN_FD_1 */ + { 0xFF000000U, PM_DEV_UART_0, PM_RST_UART_0 }, /* UART_0 */ + { 0xFF010000U, PM_DEV_UART_1, PM_RST_UART_1 }, /* UART_1 */ + { 0xFF0B0000U, PM_DEV_GPIO, PM_RST_GPIO_LPD }, /* GPIO */ + { 0xFF0E0000U, PM_DEV_TTC_0, PM_RST_TTC_0 }, /* TTC_0 */ + { 0xFF0F0000U, PM_DEV_TTC_1, PM_RST_TTC_1 }, /* TTC_1 */ + { 0xFF100000U, PM_DEV_TTC_2, PM_RST_TTC_2 }, /* TTC_2 */ + { 0xFF110000U, PM_DEV_TTC_3, PM_RST_TTC_3 }, /* TTC_3 */ + { 0xFF120000U, PM_DEV_SWDT_LPD, PM_RST_SWDT_LPD }, /* SWDT_LPD */ + { 0xFD4D0000U, PM_DEV_SWDT_FPD, PM_RST_SWDT_FPD }, /* SWDT_FPD */ + { 0xF1010000U, PM_DEV_OSPI, PM_RST_OSPI }, /* OSPI */ + { 0xF1030000U, PM_DEV_QSPI, PM_RST_QSPI }, /* QSPI */ + { 0xF1020000U, PM_DEV_GPIO_PMC, PM_RST_GPIO_PMC }, /* GPIO_PMC */ + { 0xF1000000U, PM_DEV_I2C_PMC, PM_RST_I2C_PMC }, /* I2C_PMC */ + { 0xF1040000U, PM_DEV_SDIO_0, PM_RST_SDIO_0 }, /* SDIO_0 */ + { 0xF1050000U, PM_DEV_SDIO_1, PM_RST_SDIO_1 }, /* SDIO_1 */ + { 0xFFA80000U, PM_DEV_ADMA_0, PM_RST_ADMA }, /* ADMA_0 */ + { 0xFFA90000U, PM_DEV_ADMA_1, PM_RST_ADMA }, /* ADMA_1 */ + { 0xFFAA0000U, PM_DEV_ADMA_2, PM_RST_ADMA }, /* ADMA_2 */ + { 0xFFAB0000U, PM_DEV_ADMA_3, PM_RST_ADMA }, /* ADMA_3 */ + { 0xFFAC0000U, PM_DEV_ADMA_4, PM_RST_ADMA }, /* ADMA_4 */ + { 0xFFAD0000U, PM_DEV_ADMA_5, PM_RST_ADMA }, /* ADMA_5 */ + { 0xFFAE0000U, PM_DEV_ADMA_6, PM_RST_ADMA }, /* ADMA_6 */ + { 0xFFAF0000U, PM_DEV_ADMA_7, PM_RST_ADMA }, /* ADMA_7 */ + { 0xFF300000U, PM_DEV_IPI_0, PM_RST_IPI }, /* IPI */ +}; +#endif + +/****************************************************************************/ +/** + * * + * * @brief This API is used to provide the node id. + * * + * * @return Node ID if successful, otherwise XST_FAILURE. + * * + * * @note none + * * + * *****************************************************************************/ +UINTPTR XpmGetNodeId(UINTPTR BaseAddress) +{ + u32 id; + + for (id = 0; id < MAX_NODE_COUNT; id++) { + if (BaseAddress == XpmNodeData[id].BaseAddress) { + return XpmNodeData[id].NodeId; + } + } + return (UINTPTR)XST_FAILURE; +} + +/****************************************************************************/ +/** + * * + * * @brief This API is used to provide the reset id. + * * + * * @return Reset ID if successful, otherwise XST_FAILURE. + * * + * * @note none + * * + * *****************************************************************************/ +UINTPTR XpmGetResetId(UINTPTR BaseAddress) +{ + u32 id; + + for (id = 0; id < MAX_NODE_COUNT; id++) { + if (BaseAddress == XpmNodeData[id].BaseAddress) { + return XpmNodeData[id].ResetId; + } + } + return (UINTPTR)XST_FAILURE; +} + +static XStatus XpmIpiConfig(XIpiPsu *const IpiInst) +{ + XStatus status; + XIpiPsu_Config *IpiCfgPtr; + + Xil_AssertNonvoid(IpiInst != NULL); + + /* Look Up the config data */ + IpiCfgPtr = XIpiPsu_LookupConfig(XPMU_IPI_CHANNEL_ID); + if (NULL == IpiCfgPtr) { + status = XST_FAILURE; + xil_printf("%s ERROR in getting CfgPtr\n", __func__); + return status; + } + + /* Init with the Cfg Data */ + status = XIpiPsu_CfgInitialize(IpiInst, IpiCfgPtr, + IpiCfgPtr->BaseAddress); + if (XST_SUCCESS != status) { + xil_printf("%s ERROR #%d in configuring IPI\n", __func__, status); + } + return status; +} + +/****************************************************************************/ +/** + * * + * * This API initializes the ipi and xilpm through constructor. + * * + * * @return none + * * + * * @note none + * * + * *****************************************************************************/ +void __attribute__ ((constructor)) xpminit() +{ + XStatus status; + + status = XpmIpiConfig(&IpiInst); + if (XST_SUCCESS != status) { + xil_printf("IPI configuration failed.\n"); + } + + status = XPm_InitXilpm(&IpiInst); + if (XST_SUCCESS != status) { + xil_printf("Xilpm library initialization failed.\n"); + } +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.h new file mode 100644 index 0000000..f2856be --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xpm_init.h @@ -0,0 +1,46 @@ +/****************************************************************************** +*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +*SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.h +* @addtogroup xpm_init xpm_init APIs +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
    +******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xstatus.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/include/xstatus.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/common/xstatus.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make new file mode 100644 index 0000000..2668199 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/config.make @@ -0,0 +1,3 @@ +LIBSOURCES = *.c *.S +PROFILE_ARCH_OBJS = profile_mcount_arm.o +LIBS = standalone_libs diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpputest_time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpputest_time.c new file mode 100644 index 0000000..77ea3bc --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpputest_time.c @@ -0,0 +1,31 @@ +/****************************************************************************** +* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#ifndef UNDEFINE_FILE_OPS +#include +#include "xil_types.h" +#include +struct tms* tms; +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) clock_t _times(struct tms* tms); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) clock_t _times(struct tms* tms) +{ + (void)tms; + + errno = EIO; + return (-1); +} + + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpu_init.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpu_init.S new file mode 100644 index 0000000..48dcec3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/cpu_init.S @@ -0,0 +1,53 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file cpu_init.S +* +* This file contains CPU specific initialization. Invoked from main CRT +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0   pkp	12/16/14 removed incorrect initialization of TLB lockdown
+*			 register to fix CR#830580
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + + .text + .global __cpu_init + .align 2 +__cpu_init: + +/* Clear cp15 regs with unknown reset values */ + mov r0, #0x0 + mcr p15, 0, r0, c5, c0, 0 /* DFSR */ + mcr p15, 0, r0, c5, c0, 1 /* IFSR */ + mcr p15, 0, r0, c6, c0, 0 /* DFAR */ + mcr p15, 0, r0, c6, c0, 2 /* IFAR */ + mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */ + mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */ + mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */ + +/* Reset and start Cycle Counter */ + mov r2, #0x80000000 /* clear overflow */ + mcr p15, 0, r2, c9, c12, 3 + mov r2, #0xd /* D, C, E */ + mcr p15, 0, r2, c9, c12, 0 + mov r2, #0x80000000 /* enable cycle counter */ + mcr p15, 0, r2, c9, c12, 1 + + bx lr + +.end diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/errno.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/errno.c new file mode 100644 index 0000000..3d12021 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/errno.c @@ -0,0 +1,29 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/* The errno variable is stored in the reentrancy structure. This + function returns its address for use by the macro errno defined in + errno.h. */ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 * __errno (void); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) sint32 * +__errno (void) +{ + return &_REENT->_errno; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fcntl.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fcntl.c new file mode 100644 index 0000000..40e2729 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fcntl.c @@ -0,0 +1,22 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, LONG arg); + +/* + * fcntl -- Manipulate a file descriptor. + * We don't have a filesystem, so we do nothing. + */ +__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, LONG arg) +{ + (void)fd; + (void)cmd; + (void)arg; + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fstat.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fstat.c new file mode 100644 index 0000000..0faffb8 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/fstat.c @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf); + +#ifdef __cplusplus +} +#endif +/* + * fstat -- Since we have no file system, we just return an error. + */ +__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf) +{ + (void)fd; + buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ + + return (0); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getentropy.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getentropy.c new file mode 100644 index 0000000..344325c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getentropy.c @@ -0,0 +1,26 @@ +/****************************************************************************** +* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 getentropy(void *buffer, sint32 length); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) sint32 getentropy(void *buffer, sint32 length) +{ + (void)buffer; + (void)length; + + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getpid.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getpid.c new file mode 100644 index 0000000..c657e1c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/getpid.c @@ -0,0 +1,30 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include "xil_types.h" +/* + * getpid -- only one process, so just return 1. + */ +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _getpid(void); +__attribute__((weak)) s32 getpid(void); + +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) s32 getpid(void) +{ + return 1; +} + +__attribute__((weak)) s32 _getpid(void) +{ + return 1; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c new file mode 100644 index 0000000..0036459 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/inbyte.c @@ -0,0 +1,14 @@ +#include "xparameters.h" +#include "xuartps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif +char inbyte(void); +#ifdef __cplusplus +} +#endif + +char inbyte(void) { + return XUartPs_RecvByte(STDIN_BASEADDRESS); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/CMakeLists.txt new file mode 100644 index 0000000..755890f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT + + +set(INTC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../../../intc/src/") +set(SCUGIC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../../../scugic/src/") +find_package(INTC QUIET) +set(defs "") +list(APPEND defs "#ifndef XCOMMON_DRV_CONFIG_H_\n") +list(APPEND defs "#define XCOMMON_DRV_CONFIG_H_\n\n") +if ((EXISTS "${INTC_DIR}/INTCConfig.cmake") AND + DRIVER_INSTANCES) + list(APPEND defs "#define XPAR_AXI_INTC\n") +endif() + +find_package(SCUGIC QUIET) +if ((EXISTS "${SCUGIC_DIR}/SCUGICConfig.cmake") AND + DRIVER_INSTANCES) + list(APPEND defs "#define XPAR_SCUGIC\n") +endif() +list(APPEND defs "\n#endif") +file(WRITE ${CMAKE_CURRENT_SOURCE_DIR}/xcommon_drv_config.h ${defs}) +collect (PROJECT_LIB_SOURCES xinterrupt_wrap.c) +collect (PROJECT_LIB_HEADERS xinterrupt_wrap.h) +collect (PROJECT_LIB_HEADERS xcommon_drv_config.h) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.c new file mode 100644 index 0000000..10f339e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.c @@ -0,0 +1,455 @@ +/****************************************************************************** +* Copyright (c) 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xinterrupt_wrap.c +* +* The xinterrupt_wrap.c file contains interrupt related functions and macros. +* Contains wrapper functions for the scugic/axi intc Interrupt controller +* drivers. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2   mus  22/11/21 First release of xil interrupt support
+* 9.0   adk  17/04/23 Added support for system device-tree flow
+* 9.0   adk  27/04/23 Use XScuGic_LookupConfigBaseAddr() API for xsct flow
+*
    +* +******************************************************************************/ + +#include "xinterrupt_wrap.h" + +#ifdef XIL_INTERRUPT + +#if defined (XPAR_SCUGIC) /* available in xscugic.h */ +static XScuGic XScuGicInstance; +static int ScuGicInitialized; +#endif + +#if defined (XPAR_AXI_INTC) /* available in xintc.h */ +static XIntc XIntcInstance ; +#endif + +/*****************************************************************************/ +/** +* +* @brief Initializes the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConfigInterruptCntrl(UINTPTR IntcParent) +{ + int Status = XST_FAILURE; + UINTPTR BaseAddr = XGet_BaseAddr(IntcParent); + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Config *CfgPtr = NULL; + if (XScuGicInstance.IsReady != XIL_COMPONENT_IS_READY) { +#if defined(SDT) + CfgPtr = XScuGic_LookupConfig(BaseAddr); +#else + CfgPtr = XScuGic_LookupConfigBaseAddr(BaseAddr); +#endif + if (!ScuGicInitialized) { + Status = XScuGic_CfgInitialize(&XScuGicInstance, CfgPtr, 0); + } else { + Status = XST_SUCCESS; + } + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Initialize(&XIntcInstance, BaseAddr); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief connects to the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntrHandler: Interrupt handler. +* @param CallBackRef: Callback reference for handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent) +{ + int Status; + int Doconnect = FALSE; + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (ScuGicInitialized) { + Doconnect = 1; + } + if (Doconnect) { + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + Status = XScuGic_Connect(&XScuGicInstance, IntrNum, \ + (Xil_ExceptionHandler) IntrHandler, CallBackRef); + return Status; + } else { + return XST_SUCCESS; + } +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + Status = XIntc_Connect(&XIntcInstance, IntrNum, \ + (XInterruptHandler)IntrHandler, CallBackRef); + return Status; +#else + return XST_FAILURE; +#endif + + } +} + +/*****************************************************************************/ +/** +* +* @brief disconnects the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disconnect(&XScuGicInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Disconnect(&XIntcInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* @brief Starts the interrupt controller. +* +* @param Mode: Interrupt controller mode type. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent) +{ +#if defined (XPAR_AXI_INTC) + int Status = XST_FAILURE; +#else + (void) Mode; +#endif + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + /* + * For XPAR_SCUGIC, XConfigInterruptCntrl starts controller + * hence returning without doing anything + */ + return 0; + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Start(&XIntcInstance, Mode); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + + } + +} + +/*****************************************************************************/ +/** +* +* @brief Enable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XEnableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + IntrNum += Offset; + XScuGic_Enable(&XScuGicInstance, IntrNum); +#endif + + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Enable(&XIntcInstance, IntrNum); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief disable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDisableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disable(&XScuGicInstance, IntrNum); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Disable(&XIntcInstance, IntrId); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Configures the priority and trigger type. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent) +{ +#if defined (XPAR_SCUGIC) + u8 Trigger = (((XGet_TriggerType(IntrId) == 1) || + (XGet_TriggerType(IntrId) == 2)) ? XINTR_IS_EDGE_TRIGGERED + : XINTR_IS_LEVEL_TRIGGERED); + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + XScuGic_SetPriorityTriggerType(&XScuGicInstance, IntrNum, Priority, Trigger); + } +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Gets the priority of the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param Trigger: Trigger type of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_GetPriorityTriggerType(&XScuGicInstance, IntrId, Priority, Trigger); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief stops the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XStopInterruptCntrl( UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Stop(&XScuGicInstance); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Stop(&XIntcInstance); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief Registers the interrupt handler. +* +* @param IntrHandler: Interrupt handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XRegisterInterruptHandler(void *IntrHandler, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XScuGic_InterruptHandler, + &XScuGicInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XScuGicInstance); + + } +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XIntc_InterruptHandler, + &XIntcInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XIntcInstance); + } +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Setup the interrupt system. +* +* @param DriverInstance: Driver instance pointer. +* @param IntrHandler: Interrupt handler funtion pointer. +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* @param Priority: Interrupt priority. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent, u16 Priority) +{ + int Status; + + Status = XConfigInterruptCntrl(IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_SCUGIC) + ScuGicInitialized = TRUE; +#endif + XSetPriorityTriggerType( IntrId, Priority, IntcParent); + Status = XConnectToInterruptCntrl( IntrId, (Xil_ExceptionHandler) IntrHandler, \ + DriverInstance, IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_AXI_INTC) + XStartInterruptCntrl(XIN_REAL_MODE, IntcParent); +#endif + XRegisterInterruptHandler(NULL, IntcParent); + XEnableIntrId(IntrId, IntcParent); + Xil_ExceptionInit(); + Xil_ExceptionEnable(); + return XST_SUCCESS; +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/intr/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/common/intr/xinterrupt_wrap.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/intr/xinterrupt_wrap.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/isatty.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/isatty.c new file mode 100644 index 0000000..a513bf6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/isatty.c @@ -0,0 +1,34 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 _isatty(sint32 fd); + +#ifdef __cplusplus +} +#endif + +/* + * isatty -- returns 1 if connected to a terminal device, + * returns 0 if not. Since we're hooked up to a + * serial port, we'll say yes _AND return a 1. + */ +__attribute__((weak)) sint32 isatty(sint32 fd) +{ + (void)fd; + return (1); +} + +__attribute__((weak)) sint32 _isatty(sint32 fd) +{ + (void)fd; + return (1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/kill.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/kill.c new file mode 100644 index 0000000..5181c02 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/kill.c @@ -0,0 +1,38 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _kill(pid_t pid, s32 sig); + +#ifdef __cplusplus +} +#endif + +/* + * kill -- go out via exit... + */ + +__attribute__((weak)) int kill(pid_t pid, int sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} + +__attribute__((weak)) s32 _kill(pid_t pid, s32 sig) +{ + if(pid == 1) { + _exit(sig); + } + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/lseek.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/lseek.c new file mode 100644 index 0000000..7b2c126 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/lseek.c @@ -0,0 +1,40 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence); +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence); + +#ifdef __cplusplus +} +#endif +/* + * lseek -- Since a serial port is non-seekable, we return an error. + */ +__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} + +__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence) +{ + (void)fd; + (void)offset; + (void)whence; + errno = ESPIPE; + return ((off_t)-1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/_exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/_exit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/_exit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/_exit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/errno.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/errno.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/errno.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/errno.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/fcntl.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/fcntl.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/fcntl.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/fcntl.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/fsl.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/fsl.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/fsl.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/fsl.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/hw_exception_handler.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/hw_exception_handler.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/hw_exception_handler.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/hw_exception_handler.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/mb_interface.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/mb_interface.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/mb_interface.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/mb_interface.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_dcache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_dcache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_dcache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_dcache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_exceptions.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_exceptions.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_exceptions.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_exceptions.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_icache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_icache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_icache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_icache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_interrupts.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_interrupts.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_disable_interrupts.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_disable_interrupts.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_dcache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_dcache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_dcache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_dcache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_exceptions.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_exceptions.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_exceptions.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_exceptions.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_icache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_icache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_icache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_icache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_interrupts.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_interrupts.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_enable_interrupts.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_enable_interrupts.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_exception_handler.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_exception_handler.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_exception_handler.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_exception_handler.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_exceptions_g.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_exceptions_g.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_exceptions_g.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_exceptions_g.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_exceptions_i.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_exceptions_i.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_exceptions_i.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_exceptions_i.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_cache_ext.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_cache_ext.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_cache_ext.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_cache_ext.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_cache_ext_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_cache_ext_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_cache_ext_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_cache_ext_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_dcache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_dcache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_dcache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_dcache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_dcache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_dcache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_flush_dcache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_flush_dcache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_init_dcache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_init_dcache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_init_dcache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_init_dcache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_init_icache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_init_icache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_init_icache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_init_icache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_instructions.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_instructions.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_instructions.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_instructions.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_interrupt_handler.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_interrupt_handler.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_interrupt_handler.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_interrupt_handler.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_interrupts_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_interrupts_g.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_interrupts_g.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_interrupts_g.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_interrupts_i.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_interrupts_i.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_interrupts_i.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_interrupts_i.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_cache_ext.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_cache_ext.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_cache_ext.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_cache_ext.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_cache_ext_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_cache_ext_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_cache_ext_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_dcache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_dcache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_dcache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_dcache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_dcache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_dcache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_dcache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_dcache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_icache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_icache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_icache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_icache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_icache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_icache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_invalidate_icache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_invalidate_icache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_scrub.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_scrub.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_scrub.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_scrub.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_selftest.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_selftest.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_selftest.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_selftest.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_sleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_sleep.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_sleep.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_sleep.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_sleep.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_sleep.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_sleep.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_sleep.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_update_dcache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_update_dcache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_update_dcache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_update_dcache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_update_icache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_update_icache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/microblaze_update_icache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/microblaze_update_icache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/pvr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/pvr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/pvr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/pvr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/pvr.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/pvr.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/pvr.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/pvr.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_cache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_cache.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_cache.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_cache.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_exception.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xmicroblaze.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xmicroblaze.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xmicroblaze_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/microblaze/xmicroblaze_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/microblaze/xmicroblaze_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/open.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/open.c new file mode 100644 index 0000000..c5a33d7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/open.c @@ -0,0 +1,31 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#ifndef UNDEFINE_FILE_OPS +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode); + +#ifdef __cplusplus +} +#endif +/* + * open -- open a file descriptor. We don't have a filesystem, so + * we return an error. + */ +__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) +{ + (void)buf; + (void)flags; + (void)mode; + errno = EIO; + return (-1); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c new file mode 100644 index 0000000..8b56036 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/outbyte.c @@ -0,0 +1,15 @@ +#include "xparameters.h" +#include "xuartps_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif +void outbyte(char c); + +#ifdef __cplusplus +} +#endif + +void outbyte(char c) { + XUartPs_SendByte(STDOUT_BASEADDRESS, c); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h new file mode 100644 index 0000000..d5d2838 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/pm_api_version.h @@ -0,0 +1,269 @@ +/****************************************************************************** +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** + * @file pm_api_version.h + * + * @addtogroup xpm_versal_apis XilPM APIs + *****************************************************************************/ + + +#ifndef PM_API_VERSION_H_ +#define PM_API_VERSION_H_ + +/*****************************************************************************/ +/** + * @section EEMI_API_DETAIL XilPM EEMI API Version Detail + * + * This section provides details of EEMI API version and it's history for PM APIs of XilPM library. + * + * | NAME | ID | Platform | Version| Description | + * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------| + * | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API | + * | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device | + * | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality | + * | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event | + * | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem | + * | PM_SELF_SUSPEND | 0x7 | Both | 2 | V1 - The API is used to suspend a child subsystem | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node | + * | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem | + * | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem | + * | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source | + * | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system | + * | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device | + * | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 | + * | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use | + * | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device | + * | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device | + * | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state | + * | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices | + * | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip | + * | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin | + * | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin | + * | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function | + * | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function | + * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value | + * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value | + * | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality | + * | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 | + * | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately | + * | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 | + * | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality | + * | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock | + * | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock | + * | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state | + * | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock | + * | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider | + * | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock | + * | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent | + * | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock | + * | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock | + * | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock | + * | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock | + * | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory | + * | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP | + * | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API | + * | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail + * + * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|---------------------------------------| + * | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode | + * | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode | + * | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config | + * | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config | + * | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass | + * | IOCTL_SET_SGMII_MODE | 5 | ZynqMP | SGMII mode | + * | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset | + * | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay | + * | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode | + * | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode | + * | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data | + * | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data | + * | IOCTL_WRITE_GGS | 12 | Both | Write GGS | + * | IOCTL_READ_GGS | 13 | Both | Read GGS | + * | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS | + * | IOCTL_READ_PGGS | 15 | Both | Read PGGS | + * | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset | + * | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status | + * | IOCTL_AFI | 18 | ZynqMP | AFI | + * | IOCTL_PROBE_COUNTER_READ | 19 | Versal | Probe counter read | + * | IOCTL_PROBE_COUNTER_WRITE | 20 | Versal | Probe counter write | + * | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select | + * | IOCTL_USB_SET_STATE | 22 | Versal | USB set state | + * | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason | + * | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear | + * | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF | + * | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config | + * | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config | + * | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register | + * | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register | + * | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value | + * | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value | + * | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value | + * | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations | + * | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value | + * | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode | + * | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode | + * | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down | + * | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature | + * + *****************************************************************************/ + +/*****************************************************************************/ +/** + * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail + * + * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |--------------------------------------------|-------|---------------|---------------------------------------| + * | XPM_QID_INVALID | 0 | Both | Invalid Query ID | + * | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name | + * | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology | + * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter | + * | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources | + * | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes | + * | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions | + * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups | + * | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name | + * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups | + * | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups | + * | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks | + * | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor | + * | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent | + * | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes | + * + *****************************************************************************/ + + +/*****************************************************************************/ +/** + * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail + * + * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions. + * + * | Name | ID | Platform | Description | + * |------------------------------------|-------|---------------|-----------------------------------------------| + * | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power | + * | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature | + * | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency | + * + *****************************************************************************/ + + +/** + * PM API IDs + */ +typedef enum { + PM_API_MIN, /**< 0x0 */ + PM_GET_API_VERSION, /**< 0x1 */ + PM_SET_CONFIGURATION, /**< 0x2 */ + PM_GET_NODE_STATUS, /**< 0x3 */ + PM_GET_OP_CHARACTERISTIC, /**< 0x4 */ + PM_REGISTER_NOTIFIER, /**< 0x5 */ + PM_REQUEST_SUSPEND, /**< 0x6 */ + PM_SELF_SUSPEND, /**< 0x7 */ + PM_FORCE_POWERDOWN, /**< 0x8 */ + PM_ABORT_SUSPEND, /**< 0x9 */ + PM_REQUEST_WAKEUP, /**< 0xA */ + PM_SET_WAKEUP_SOURCE, /**< 0xB */ + PM_SYSTEM_SHUTDOWN, /**< 0xC */ + PM_REQUEST_NODE, /**< 0xD */ + PM_RELEASE_NODE, /**< 0xE */ + PM_SET_REQUIREMENT, /**< 0xF */ + PM_SET_MAX_LATENCY, /**< 0x10 */ + PM_RESET_ASSERT, /**< 0x11 */ + PM_RESET_GET_STATUS, /**< 0x12 */ + PM_MMIO_WRITE, /**< 0x13 */ + PM_MMIO_READ, /**< 0x14 */ + PM_INIT_FINALIZE, /**< 0x15 */ + PM_FPGA_LOAD, /**< 0x16 */ + PM_FPGA_GET_STATUS, /**< 0x17 */ + PM_GET_CHIPID, /**< 0x18 */ + PM_SECURE_RSA_AES, /**< 0x19 */ + PM_SECURE_SHA, /**< 0x1A */ + PM_SECURE_RSA, /**< 0x1B */ + PM_PINCTRL_REQUEST, /**< 0x1C */ + PM_PINCTRL_RELEASE, /**< 0x1D */ + PM_PINCTRL_GET_FUNCTION, /**< 0x1E */ + PM_PINCTRL_SET_FUNCTION, /**< 0x1F */ + PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */ + PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */ + PM_IOCTL, /**< 0x22 */ + PM_QUERY_DATA, /**< 0x23 */ + PM_CLOCK_ENABLE, /**< 0x24 */ + PM_CLOCK_DISABLE, /**< 0x25 */ + PM_CLOCK_GETSTATE, /**< 0x26 */ + PM_CLOCK_SETDIVIDER, /**< 0x27 */ + PM_CLOCK_GETDIVIDER, /**< 0x28 */ + PM_CLOCK_SETRATE, /**< 0x29 */ + PM_CLOCK_GETRATE, /**< 0x2A */ + PM_CLOCK_SETPARENT, /**< 0x2B */ + PM_CLOCK_GETPARENT, /**< 0x2C */ + PM_SECURE_IMAGE, /**< 0x2D */ + PM_FPGA_READ, /**< 0x2E */ + PM_SECURE_AES, /**< 0x2F */ + PM_PLL_SET_PARAMETER, /**< 0x30 */ + PM_PLL_GET_PARAMETER, /**< 0x31 */ + PM_PLL_SET_MODE, /**< 0x32 */ + PM_PLL_GET_MODE, /**< 0x33 */ + PM_REGISTER_ACCESS, /**< 0x34 */ + PM_EFUSE_ACCESS, /**< 0x35 */ + PM_ADD_SUBSYSTEM, /**< 0x36 */ + PM_DESTROY_SUBSYSTEM, /**< 0x37 */ + PM_DESCRIBE_NODES, /**< 0x38 */ + PM_ADD_NODE, /**< 0x39 */ + PM_ADD_NODE_PARENT, /**< 0x3A */ + PM_ADD_NODE_NAME, /**< 0x3B */ + PM_ADD_REQUIREMENT, /**< 0x3C */ + PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */ + PM_INIT_NODE, /**< 0x3E */ + PM_FEATURE_CHECK, /**< 0x3F */ + PM_ISO_CONTROL, /**< 0x40 */ + PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */ + PM_SET_NODE_ACCESS, /**< 0x42 */ + PM_BISR, /**< 0x43 */ + PM_APPLY_TRIM, /**< 0x44 */ + PM_NOC_CLOCK_ENABLE, /**< 0x45 */ + PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */ + PM_FORCE_HOUSECLEAN, /**< 0x47 */ + PM_FPGA_GET_VERSION, /**< 0x48 */ + PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */ + PM_API_MAX /**< 0x4A */ +} XPm_ApiId; + +#endif /* PM_API_VERSION_H_ */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/print.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/print.c new file mode 100644 index 0000000..cb66494 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/print.c @@ -0,0 +1,39 @@ +/* print.c -- print a string on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + *****************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_printf.h" + +/*****************************************************************************/ +/** +* print -- do a raw print of a string +* +******************************************************************************/ +void print(const char8 *ptr) +{ +#if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE) + XPVXenConsole_Write(ptr); +#else +#if defined(STDOUT_BASEADDRESS) || defined(SDT) + while (*ptr != (char8)0) { + outbyte (*ptr); + ptr++; + } +#else +(void)ptr; +#endif +#endif +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/_profile_clean.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_clean.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/_profile_clean.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_clean.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/_profile_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_init.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/_profile_init.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_init.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/_profile_timer_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_timer_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/_profile_timer_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_timer_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_timer_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_timer_hw.h new file mode 100644 index 0000000..b80c577 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/_profile_timer_hw.h @@ -0,0 +1,281 @@ +/****************************************************************************** +* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#ifndef PROFILE_TIMER_HW_H +#define PROFILE_TIMER_HW_H + +#include "profile.h" + +#ifdef PROC_PPC +#if defined __GNUC__ +# define SYNCHRONIZE_IO __asm__ volatile ("eieio") +#elif defined __DCC__ +# define SYNCHRONIZE_IO __asm volatile(" eieio") +#else +# define SYNCHRONIZE_IO +#endif +#endif + +#ifdef PROC_PPC +#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; } +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } +#else +#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); } +#endif + +#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ + ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (u32)(RegOffset)), (u32)(ValueToWrite)) + +#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ + ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset)) + +#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ + ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ + (RegisterValue)) + +#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ + ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PROC_PPC +#include "xexception_l.h" +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif /* TIMER_CONNECT_INTC */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +#ifdef PROC_CORTEXA9 +#include "xscutimer_hw.h" +#include "xscugic.h" +#endif + +extern u32 timer_clk_ticks ; + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_PPC + +#ifdef PPC_PIT_INTERRUPT +u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */ +#endif + +#ifdef PROC_PPC440 +#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE +#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS +#define XREG_SPR_PIT XREG_SPR_DEC +#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT +#endif + +/* -------------------------------------------------------------------- + * Disable the Timer - During Profiling + * + * For PIT Timer - + * 1. XTime_PITDisableInterrupt() ; + * 2. Store the remaining timer clk tick + * 3. Stop the PIT Timer + *-------------------------------------------------------------------- */ + +#ifdef PPC_PIT_INTERRUPT +#define disable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \ + timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ + mtspr(XREG_SPR_PIT, 0); \ + } +#else +#define disable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Enable the Timer + * + * For PIT Timer - + * 1. Load the remaining timer clk ticks + * 2. XTime_PITEnableInterrupt() ; + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define enable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ + mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ + } +#else +#define enable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + * For PIT Timer - + * 1. Load the timer clk ticks + * 2. Enable AutoReload and Interrupt + * 3. Clear PIT Timer Status bits + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define timer_ack() \ + { \ + u32 val; \ + mtspr(XREG_SPR_PIT, timer_clk_ticks); \ + mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ + } +#else +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ + ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + } +#endif + +/*-------------------------------------------------------------------- */ +#endif /* PROC_PPC */ +/* -------------------------------------------------------------------- */ + + + + +/* -------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_MICROBLAZE + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(Addr); \ + tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \ + u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \ + OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + OutAddr += (u32)XTC_TCSR_OFFSET; \ + ProfIo_Out32(OutAddr, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = (u32)ProfIo_In32(Addr); \ + tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \ + ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \ + } + +/*-------------------------------------------------------------------- */ +#endif /* PROC_MICROBLAZE */ +/*-------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_CORTEXA9 + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ +{ \ + Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \ + (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +/*-------------------------------------------------------------------- */ +#endif /* PROC_CORTEXA9 */ +/*-------------------------------------------------------------------- */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/dummy.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/dummy.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/dummy.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/dummy.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/mblaze_nt_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/mblaze_nt_types.h new file mode 100644 index 0000000..6b51ea9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/mblaze_nt_types.h @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + + +#ifndef _MBLAZE_NT_TYPES_H +#define _MBLAZE_NT_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef char byte; +typedef short half; +typedef int word; +typedef unsigned char ubyte; +typedef unsigned short uhalf; +typedef unsigned int uword; +typedef ubyte boolean; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile.h new file mode 100644 index 0000000..27b3df1 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#ifndef PROFILE_H +#define PROFILE_H 1 + +#include +#include "xil_types.h" +#include "profile_config.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void _system_init( void ) ; +void _system_clean( void ) ; +void mcount(u32 frompc, u32 selfpc); +void profile_intr_handler( void ) ; +void _profile_init( void ); + + + +/**************************************************************************** + * Profiling on hardware - Hash table maintained on hardware and data sent + * to xmd for gmon.out generation. + ****************************************************************************/ +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER u16 + +struct tostruct { + u32 selfpc; + s32 count; + s16 link; + u16 pad; +}; + +struct fromstruct { + u32 frompc ; + s16 link ; + u16 pad ; +} ; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + s32 state; + + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ + + /* Call-graph Information */ + struct fromstruct *froms; + u32 fromssize; + struct tostruct *tos; + u32 tossize; + + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ +}; +extern struct gmonparam *_gmonparam; +extern s32 n_gmon_sections; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +#ifdef __cplusplus +} +#endif + +#endif /* PROFILE_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_cg.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_cg.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_cg.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_cg.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_hist.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_hist.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_hist.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_hist.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_mcount_arm.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_mcount_arm.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_mcount_arm.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_mcount_arm.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_mcount_mb.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_mcount_mb.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_mcount_mb.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_mcount_mb.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_mcount_ppc.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_mcount_ppc.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/profile/profile_mcount_ppc.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/profile/profile_mcount_ppc.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/putnum.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/putnum.c new file mode 100644 index 0000000..3582ffe --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/putnum.c @@ -0,0 +1,56 @@ +/* putnum.c -- put a hex number on the output device. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + *****************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_printf.h" + +/************************** Function Prototypes ******************************/ +void putnum(u32 num); + +/*****************************************************************************/ +/** +* putnum -- print a 32 bit number in hex +* +******************************************************************************/ +void putnum(u32 num) +{ + char8 buf[9]; + s32 cnt, val=7; + s32 i; + char8 *ptr; + u32 digit; + for(i = 0; i<9; i++) { + buf[i] = '0'; + } + + ptr = buf; + for (cnt = 0 ; cnt <= 7 ; cnt++) { + digit = (num >> ((u32)val * 4U)) & 0x0000000fU; + + if (digit <= 9U) { + digit += (u32)'0'; + *ptr = ((char8) digit); + ptr += 1; + } else { + digit += ((u32)'a' - (u32)10); + *ptr = ((char8)digit); + ptr += 1; + } + val--; + } + + print (buf); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/read.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/read.c new file mode 100644 index 0000000..decf665 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/read.c @@ -0,0 +1,87 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/* read.c -- read bytes from a input device. + */ +#ifndef UNDEFINE_FILE_OPS +#include "xil_printf.h" +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes); +__attribute__((weak)) s32 read (s32 fd, char8* buf, s32 nbytes); + +#ifdef __cplusplus +} +#endif + +/* + * read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ +__attribute__((weak)) s32 +read (s32 fd, char8* buf, s32 nbytes) +{ +#if defined (STDIN_BASEADDRESS) || defined(SDT) + s32 i; + s32 numbytes = 0; + char8* LocalBuf = buf; + + (void)fd; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + LocalBuf[i] = inbyte(); + if ((LocalBuf[i] == '\n' )|| (LocalBuf[i] == '\r')) { + break; + } + } + } + + return numbytes; +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) s32 +_read (s32 fd, char8* buf, s32 nbytes) +{ +#if defined(STDIN_BASEADDRESS) || defined(SDT) + s32 i; + s32 numbytes = 0; + char8* LocalBuf = buf; + + (void)fd; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + LocalBuf[i] = inbyte(); + if ((LocalBuf[i] == '\n' )|| (LocalBuf[i] == '\r')) { + break; + } + } + } + + return numbytes; +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/_exit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/_exit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/_exit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/_exit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/_sbrk.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/_sbrk.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/_sbrk.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/_sbrk.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/boot.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/boot.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/boot.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/boot.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/errno.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/errno.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/errno.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/errno.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/fcntl.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/fcntl.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/fcntl.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/fcntl.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/fsl.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/fsl.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/fsl.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/fsl.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_disable_interrupts.S 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2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_interrupt_handler.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_interrupt_handler.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_dcache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_dcache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_dcache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_dcache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_dcache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_dcache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_dcache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_dcache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_icache.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_icache.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_icache.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_icache.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_icache_range.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_icache_range.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_invalidate_icache_range.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_invalidate_icache_range.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_scrub.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_scrub.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/riscv_scrub.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/riscv_scrub.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/trap_handler.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/trap_handler.S similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/trap_handler.S rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/trap_handler.S diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xil_exception.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xil_exception.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xil_exception.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xreg_riscv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xreg_riscv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/riscv/xreg_riscv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/riscv/xreg_riscv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sbrk.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sbrk.c new file mode 100644 index 0000000..fd00c99 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sbrk.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) char8 *sbrk (s32 nbytes); + +#ifdef __cplusplus +} +#endif + +extern u8 _heap_start[]; +extern u8 _heap_end[]; +extern char8 HeapBase[]; +extern char8 HeapLimit[]; + + + +__attribute__((weak)) char8 *sbrk (s32 nbytes) +{ + char8 *base; + static char8 *heap_ptr = HeapBase; + + base = heap_ptr; + if((heap_ptr != NULL) && ((heap_ptr + nbytes) <= ((char8 *)&HeapLimit + 1))) { + heap_ptr += nbytes; + return base; + } else { + errno = ENOMEM; + return ((char8 *)-1); + } +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.c new file mode 100644 index 0000000..d3e3d76 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.c @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/***************************************************************************** +* +* @file sleep.c +* +* This function provides a second delay using the Global Timer register in +* the ARM Cortex A9 MP core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6	srm      10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+* 9.0   ml       03/03/23 Add description to fix doxygen warnings.
+*
    +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" + +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + +/*****************************************************************************/ +/** +* +* This API is used to provide delays in seconds +* +* @param seconds requested +* +* @return 0 always +* +* @note None. +* +******************************************************************************/ +unsigned sleep_A9(unsigned int seconds) +{ +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); +#else + XTime tEnd, tCur; + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); +#endif + + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/sleep.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.h similarity index 52% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/sleep.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.h index fd70448..0d881b6 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/include/sleep.h +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/sleep.h @@ -1,25 +1,37 @@ /****************************************************************************** -* -* Copyright (C) 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. * SPDX-License-Identifier: MIT -* ******************************************************************************/ + /*****************************************************************************/ /** * @file sleep.h * -* This header file contains sleep related APIs. +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. * * 
     * MODIFICATION HISTORY :
 *
 * Ver   Who  Date	 Changes
 * ----- ---- -------- -------------------------------------------------------
-*  1.0  adk	 24/11/21 Initial release.
-*  1.2  adk	 22/12/22 Fixed doxygen style and indentation issues.
-*
+* 6.6   srm  11/02/17 Added processor specific sleep routines
+*								 function prototypes.
+* 7.7	sk   01/10/22 Typecast sleep declaration argument from unsigned int to
+* 		      u32 to fix misra_c_2012_directive_4_6 violation.
+* 7.7	sk   01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
+* 		      unsigned to void to fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk   03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
+*		      c_2012_directive_4_6 violation.
+* 8.0	sk   03/17/22 Modify the return type of usleep_MB from int to void and
+*		      sleep_MB from unsigned to void to fix misra_c_2012_rule_
+*		      17_7 violation.
+* 8.0	sk   03/17/22 Modify sleep_MB parameter type from unsigned int to
+*		      u32 and usleep_MB parameter type from unsigned long to
+*		      ULONG to fix misra_c_2012_rule_4_6 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
 *
    * ******************************************************************************/ @@ -51,9 +63,8 @@ extern "C" { * @param COND - Condition to checked (usually involves VALUE) * @param TIMEOUT_US - timeout in micro seconds * -* @return -* - 0 - when the condition is met -* - 1 - when the condition is not met till the timeout period +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period * * @note none * @@ -77,8 +88,19 @@ extern "C" { (timeout>0) ? 0 : -1; \ } ) -void usleep(unsigned long useconds); -void sleep(unsigned int seconds); +/************************** Function Prototypes ******************************/ +void usleep(ULONG useconds); +void sleep(u32 seconds); +void usleep_R5(ULONG useconds); +void sleep_R5(u32 seconds); +void usleep_MB(ULONG useconds); +void sleep_MB(u32 seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +/*****************************************************************************/ #ifdef __cplusplus } diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/smc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/smc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/smc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/smc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/time.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/time.c new file mode 100644 index 0000000..541b0e3 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/time.c @@ -0,0 +1,27 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) clock_t clock(void); + +#ifdef __cplusplus +} +#endif +/* + * clock -- It supposed to return processor time. We are not implementing + * this function, as timekeeping is tightly coupled with system, hence + * always returning 0. Users can override this with their system + * specific implementation. + * + */ +__attribute__((weak)) clock_t clock(void) +{ + return (0); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/translation_table.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/translation_table.S new file mode 100644 index 0000000..cd8e49f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/translation_table.S @@ -0,0 +1,213 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file translation_table.S +* +* @addtogroup a9_boot_code +* @{ +*

    translation_table.S

    +* The translation_table.S contains a static page table required by MMU for +* cortex-A9. This translation table is flat mapped (input address = output +* address) with default memory attributes defined for zynq architecture. It +* utilizes short descriptor translation table format with each section defining +* 1 MB of memory. +* +* The overview of translation table memory attributes is described below. +* +*| | Memory Range | Definition in Translation Table | +*|-----------------------|-------------------------|-----------------------------------| +*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable | +*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered | +*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned | +*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory | +*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned | +*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory | +*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable | +*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned | +*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned | +*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable | +*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned | +*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable | +* +* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB, +* region after DDR and before PL is marked as undefined/reserved in translation +* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 - +* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size +* of 1 MB, it is not possible to define separate regions for them. For region +* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB +* granual size, it is not possible to define separate region for it. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*		       instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2	pkp  09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+*			and  0xe0000000 - 0xe1ffffff is broken down into
+*			0xe0000000 - 0xe02fffff (memory mapped divides)
+*			0xe0300000 - 0xe0ffffff (reserved) and
+*			0xe1000000 - 0xe1ffffff (NAND)
+* 5.2	pkp  06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+*			if DDR is present or not and accordingly generate the
+*			translation table
+* 6.1	pkp  07/11/2016 Corrected comments for memory attributes
+* 6.8   mus  07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
+*			with the USE_AMP flag.
+*
    +* +* +******************************************************************************/ +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#else +#include "xmem_config.h" +#endif + .globl MMUTable + + .section .mmu_tbl,"a" + +MMUTable: + /* Each table entry occupies one 32-bit word and there are + * 4096 entries, so the entire table takes up 16KB. + * Each entry covers a 1MB section. + */ +.set SECT, 0 + +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR +.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR +.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 +#elif defined(XPAR_PS7_DDR_0_BASEADDRESS) +.set DDR_START, XPAR_PS7_DDR_0_BASEADDRESS +.set DDR_END, XPAR_PS7_DDR_0_HIGHADDRESS +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 +#else +.set DDR_REG, 0 +#endif + +.set UNDEF_REG, 0x3FF - DDR_REG + +#ifndef USE_AMP + /*0x00000000 - 0x00100000 (inner and outer cacheable )*/ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +#else + /*0x00000000 - 0x00100000 (inner cacheable )*/ +.word SECT + 0x14de6 /* S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1 */ +#endif +.set SECT, SECT+0x100000 + +.rept DDR_REG /* (DDR Cacheable) */ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept UNDEF_REG /* (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + + +.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices) + * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */ +.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and + 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of + 1MB, it is not possible to define separate regions for them */ + +.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */ + +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */ +.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of + 1MB, it is not possible to define separate region for it + + 0xfff00000 - 0xffffffff + 256K OCM when mapped to high address space + inner-cacheable */ +.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 + +.end +/** +* @} End of "addtogroup a9_boot_code". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/unlink.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/unlink.c new file mode 100644 index 0000000..5092095 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/unlink.c @@ -0,0 +1,28 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +#include +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 unlink(char8 *path); + +#ifdef __cplusplus +} +#endif +/* + * unlink -- since we have no file system, + * we just return an error. + */ +__attribute__((weak)) sint32 unlink(char8 *path) +{ + (void) path; + errno = EIO; + return (-1); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/usleep.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/usleep.c new file mode 100644 index 0000000..82f15ce --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/usleep.c @@ -0,0 +1,83 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file usleep.c +* +* This function provides a microsecond delay using the Global Timer register in +* the ARM Cortex A9 MP core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated micro sleep function to make use Global Timer
+* 4.2	pkp		 08/04/14 Removed unimplemented nanosleep routine as it is not
+*						  possible to generate timer in nanosecond due to
+*						  limited cpu frequency
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6	srm	 10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+* 9.0   ml       03/03/23 Added description to fix doxygen warnings.
+*
    +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "sleep.h" +#include "xtime_l.h" +#include "xparameters.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xreg_cortexa9.h" + +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + +/**************************** Constant Definitions ************************/ +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000) +#else +/**< Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U)) +#endif + +/*****************************************************************************/ +/** +* +* This API gives a delay in microseconds +* +* @param useconds requested +* +* @return 0 if the delay can be achieved, -1 if the requested delay +* is out of range +* +* @note None. +* +****************************************************************************/ +int usleep_A9(unsigned long useconds) +{ +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); +#else + XTime tEnd, tCur; + + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); +#endif + + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.c new file mode 100644 index 0000000..91ddaa9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.c @@ -0,0 +1,166 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file vectors.c +* +* This file contains the C level vectors for the ARM Cortex A9 core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
+* 8.0	sk   03/02/22 Move XExc_VectorTableEntry structure to xil_exception.h
+* 		      header file to fix misra_c_2012_rule_5_6 violation.
+* 8.0	sk   03/02/22 Move XExc_VectorTableEntry declaration to xil_exception.h
+* 		      header file to fix misra_c_2012_rule_8_4 violation.
+*
    +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xil_exception.h" +#include "vectors.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the FIQ interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void FIQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_FIQ_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the IRQ interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void IRQInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_IRQ_INT].Data); +} + +#if !defined (__aarch64__) +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Undefined exception called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void UndefinedException(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_UNDEFINED_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SW Interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void SWInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SWI_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the DataAbort Interrupt called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void DataAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the PrefetchAbort Interrupt called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void PrefetchAbortInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); +} +#else + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s +* file. +* +* @return None. +* +******************************************************************************/ +void SynchronousInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SYNC_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SError Interrupt called from the +* vectors.s file. +* +* @return None. +* +******************************************************************************/ +void SErrorInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data); +} + +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/vectors.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/vectors.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/vectors.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/CMakeLists.txt new file mode 100644 index 0000000..00f7985 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT +collect (PROJECT_LIB_HEADERS xil_error_node.h) +collect (PROJECT_LIB_HEADERS xil_hw.h) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_error_node.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_error_node.h new file mode 100644 index 0000000..7a15448 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_error_node.h @@ -0,0 +1,491 @@ +/****************************************************************************** +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_error_node.h +* +* This is the file which contains node IDs information for error events. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who 	 Date        Changes
+* ----- -------- -------- -----------------------------------------------------
+* 7.7   bsv      12/22/2021 Initial release
+*       ma       01/17/2022 Add PLM exceptions to SW errors list
+* 7.8   rama     06/28/2022 Add XilSem errors to SW error events
+* 7.9   rama     07/19/2023 Add STL errors to SW error events
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef XIL_ERROR_NODE_H +#define XIL_ERROR_NODE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/**@name Versal Event Node IDs + * @defgroup xileventnodes Event Node IDs + * @ingroup xilnodeids + * @{ + */ + +#define XIL_NODETYPE_EVENT_ERROR_ID_ENCODING (0x28100000U) + + /** + * Error Event Node Ids + */ +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR1 (0x28100000U) +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR2 (0x28104000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR1 (0x28108000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR2 (0x2810C000U) +#define XIL_NODETYPE_EVENT_ERROR_SW_ERR (0x28110000U) +/** + * @} + */ + +/**@name Versal Error event Mask + * @defgroup xilerroreventmask Error Event Mask + * @ingroup xilnodeids + * @{ + * @defgroup pmcerr1 Error Event Mask for PMC ERR1 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PMC ERR1 Node + */ + +/** Error event mask for PMC Boot Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_CR (0x00000001U) + +/** Error event mask for PMC Boot Non-Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_NCR (0x00000002U) + +/** Error event mask for PMC Firmware Boot Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_CR (0x00000004U) + +/** Error event mask for PMC Firmware Boot Non-Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_NCR (0x00000008U) + +/** Error event mask for General Software Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_CR (0x00000010U) + +/** Error event mask for General Software Non-Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_NCR (0x00000020U) + +/** Error event mask for CFU Error. */ +#define XIL_EVENT_ERROR_MASK_CFU (0x00000040U) + +/** Error event mask for CFRAME Error. */ +#define XIL_EVENT_ERROR_MASK_CFRAME (0x00000080U) + +/** Error event mask for PSM Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_CR (0x00000100U) + +/** Error event mask for PSM Non-Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_NCR (0x00000200U) + +/** Error event mask for DDRMC MB Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_CR (0x00000400U) + +/** Error event mask for DDRMC MB Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_NCR (0x00000800U) + +/** Error event mask for NoC Type1 Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_CR (0x00001000U) + +/** Error event mask for NoC Type1 Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_NCR (0x00002000U) + +/** Error event mask for NoC User Error. */ +#define XIL_EVENT_ERROR_MASK_NOCUSER (0x00004000U) + +/** Error event mask for MMCM Lock Error. */ +#define XIL_EVENT_ERROR_MASK_MMCM (0x00008000U) + +/** Error event mask for ME Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_CR (0x00010000U) + +/** Error event mask for ME Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_NCR (0x00020000U) + +/** Error event mask for DDRMC MC Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_CR (0x00040000U) + +/** Error event mask for DDRMC MC Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_NCR (0x00080000U) + +/** Error event mask for GT Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_CR (0x00100000U) + +/** Error event mask for GT Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_NCR (0x00200000U) + +/** Error event mask for PL Sysmon Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_CR (0x00400000U) + +/** Error event mask for PL Sysmon Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_NCR (0x00800000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL0 (0x01000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL1 (0x02000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL2 (0x04000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL3 (0x08000000U) + +/** Error event mask for NPI Root Error. */ +#define XIL_EVENT_ERROR_MASK_NPIROOT (0x10000000U) + +/** Error event mask for SSIT Error from Slave SLR1, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT3 (0x20000000U) + +/** Error event mask for SSIT Error from Slave SLR2, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT4 (0x40000000U) + +/** Error event mask for SSIT Error from Slave SLR3, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT5 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup pmcerr2 Error Event Mask for PMC ERR2 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PMC ERR2 Node + */ +/** Error event mask for General purpose PMC error, + * can be triggered by any of the following peripherals:, + * - PMC Global Regsiters,- PMC Clock & Reset (CRP),- PMC IOU Secure SLCR, + * - PMC IOU SLCR,- BBRAM Controller,- PMC Analog Control Registers, + * - RTC Control Registers. */ +#define XIL_EVENT_ERROR_MASK_PMCAPB (0x00000001U) + +/** Error event mask for PMC ROM Validation Error. */ +#define XIL_EVENT_ERROR_MASK_PMCROM (0x00000002U) + +/** Error event mask for PMC PPU0 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL0 (0x00000004U) + +/** Error event mask for PMC PPU1 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL1 (0x00000008U) + +/** Error event mask for PMC Switch and PMC IOU Parity Errors. */ +#define XIL_EVENT_ERROR_MASK_PMCPAR (0x00000010U) + +/** Error event mask for PMC Correctable Errors:, + * PPU0 RAM correctable error.,PPU1 instruction RAM correctable error., + * PPU1 data RAM correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_CR (0x00000020U) + +/** Error event mask for PMC Non-Correctable Errors: + * PPU0 RAM non-correctable error, PPU1 instruction RAM non-correctable error, + * PPU1 data RAM non-correctable error, PRAM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_NCR (0x00000040U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[0]. + * Indicates an alarm condition on any of SUPPLY0 to SUPPLY31. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON0 (0x00000080U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[1]. + * Indicates an alarm condition on any of SUPPLY32 to SUPPLY63. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON1 (0x00000100U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[2]. + * Indicates an alarm condition on any of SUPPLY64 to SUPPLY95. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON2 (0x00000200U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[3]. + * Indicates an alarm condition on any of SUPPLY96 to SUPPLY127. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON3 (0x00000400U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[4]. + * Indicates an alarm condition on any of SUPPLY128 to SUPPLY159. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON4 (0x00000800U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[8]. + * Indicates an over-temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON8 (0x00008000U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[9]. + * Indicates a device temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON9 (0x00010000U) + +/** Error event mask for CFI Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CFI (0x00020000U) + +/** Error event mask for CFRAME SEU CRC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUCRC (0x00040000U) + +/** Error event mask for CFRAME SEU ECC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUECC (0x00080000U) + +/** Error event mask for RTC Alarm Error. */ +#define XIL_EVENT_ERROR_MASK_RTCALARM (0x00400000U) + +/** Error event mask for PMC NPLL Lock Error, + * this error can be unmasked after the NPLL is locked to alert when the + * NPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_NPLL (0x00800000U) + +/** Error event mask for PMC PPLL Lock Error, + * this error can be unmasked after the PPLL is locked to alert when the + * PPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_PPLL (0x01000000U) + +/** Error event mask for Clock Monitor Errors, collected from CRP's + * CLKMON_STATUS register. */ +#define XIL_EVENT_ERROR_MASK_CLKMON (0x02000000U) + +/** Error event mask for PMC Interconnect Timeout Errors. + * Collected from: Interconnect mission interrupt status register, + * Interconnect latent status register, Timeout interrupt status register + * for SERBs. */ +#define XIL_EVENT_ERROR_MASK_PMCTO (0x04000000U) + +/** Error event mask for PMC XMPU Errors: Register access error on APB, + * Read permission violation, Write permission violation, Security violation. */ +#define XIL_EVENT_ERROR_MASK_PMCXMPU (0x08000000U) + +/** Error event mask for PMC XPPU Errors: Register access error on APB, + * Master ID not found, Read permission violation, Master ID parity error, + * Master ID access violation, TrustZone violation, Aperture parity error. */ +#define XIL_EVENT_ERROR_MASK_PMCXPPU (0x10000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR1, + * For Slave SLRs: SSIT Error0 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT0 (0x20000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR2, + * For Slave SLRs: SSIT Error1 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT1 (0x40000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR3, + * For Slave SLRs: SSIT Error2 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT2 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup psmerr1 Error Event Mask for PSM ERR1 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PSM ERR1 Node + */ +/** Error event mask for PS Software can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_CR (0x00000001U) + +/** Error event mask for PS Software can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_NCR (0x00000002U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_CR (0x00000004U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_NCR (0x00000008U) + +/** Error event mask for Or of MB Fatal1, Fatal2, Fatal3 Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL (0x00000010U) + +/** Error event mask for PSM Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_CR (0x00000020U) + +/** Error event mask for PSM Non-Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_NCR (0x00000040U) + +/** Error event mask for Non-Correctable ECC Error during an OCM access. */ +#define XIL_EVENT_ERROR_MASK_OCM_ECC (0x00000080U) + +/** Error event mask for Non-Correctable ECC Error during APU L2 Cache access. */ +#define XIL_EVENT_ERROR_MASK_L2_ECC (0x00000100U) + +/** Error event mask for ECC Errors during a RPU memory access. + * Floating-point operation exceptions. RPU REG APB error. */ +#define XIL_EVENT_ERROR_MASK_RPU_ECC (0x00000200U) + +/** Error event mask for RPU Lockstep Errors from R5_0. + * The Lockstep error is not initialized until RPU clock is enabled. + * Therefore the error outcomes are masked by default and are expected to be + * unmasked after processor clock is enabled and before its reset is released. */ +#define XIL_EVENT_ERROR_MASK_RPU_LS (0x00000400U) + +/** Error event mask for RPU Common Cause Failures ORed together. + * The CCF Error register with the masking capability has to reside in the RPU. */ +#define XIL_EVENT_ERROR_MASK_RPU_CCF (0x00000800U) + +/** Error event mask for APU GIC AXI Error by the AXI4 master port, + * such as SLVERR or DECERR. */ +#define XIL_EVENT_ERROR_MASK_GIC_AXI (0x00001000U) + +/** Error event mask for APU GIC ECC Error, + * a Non-Correctable ECC error occurred in any ECC-protected RAM. */ +#define XIL_EVENT_ERROR_MASK_GIC_ECC (0x00002000U) + +/** Error event mask for APLL Lock Errors. + * The error can be unmasked after the PLL is locked to alert when the + * PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_APLL_LOCK (0x00004000U) + +/** Error event mask for RPLL Lock Errors. + * The error can be unmasked after the PLL is locked to alert when the + * PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_RPLL_LOCK (0x00008000U) + +/** Error event mask for CPM Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CPM_CR (0x00010000U) + +/** Error event mask for CPM Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CPM_NCR (0x00020000U) + +/** Error event mask for LPD APB Errors from: IPI REG, USB2 REG, CRL REG, + * LPD AFIFM4 REG, LPD IOU REG, LPD IOU SECURE SLCR REG, LPD SLCR REG, + * LPD SLCR SECURE REG. */ +#define XIL_EVENT_ERROR_MASK_LPD_APB (0x00040000U) + +/** Error event mask for FPD APB Errors from: FPD AFIFM0 REG, FPD AFIFM2 REG, + * FPD SLCR REG,FPD SLCR SECURE REG, CRF REG. */ +#define XIL_EVENT_ERROR_MASK_FPD_APB (0x00080000U) + +/** Error event mask for Data parity errors from the interfaces connected + * to the LPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_LPD_PAR (0x00100000U) + +/** Error event mask for Data parity errors from the interfaces connected + * to the FPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_FPD_PAR (0x00200000U) + +/** Error event mask for LPD IO Peripheral Unit Parity Error. */ +#define XIL_EVENT_ERROR_MASK_IOU_PAR (0x00400000U) + +/** Error event mask for Data parity errors from the interfaces connected + * to the PSM interconnect. */ +#define XIL_EVENT_ERROR_MASK_PSM_PAR (0x00800000U) + +/** Error event mask for LPD Interconnect Timeout errors. + * Collected from: Timeout errors at the slaves connected to the LPD + * interconnect, Address decode error, Interconnect mission errors for + * the slaves connected to the LPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_LPD_TO (0x01000000U) + +/** Error event mask for FPD Interconnect Timeout errors. + * Collected from: Coresight debug trace alarms, Timeout errors at the + * slaves connected to the FPD interconnect, Address decode error, + * Data parity errors on the interfaces connected to the FPD interconnect. */ +#define XIL_EVENT_ERROR_MASK_FPD_TO (0x02000000U) + +/** Error event mask for PSM Interconnect Timeout Errors. + * Collected from: Interconnect mission errors for PSM_LOCAL slave or + * PSM_GLOBAL slave or MDM slave or LPD interconnect or PSM master, + * Interconnect latent errors for PSM_LOCAL slave or PSM_GLOBAL slave or + * MDM slave or LPD interconnect or PSM master, Timeout errors at the slaves + * connected to the PSM interconnect. */ +#define XIL_EVENT_ERROR_MASK_PSM_TO (0x04000000U) + +/** Error event mask for XRAM Correctable error. + * Only applicable in devices that have XRAM. */ +#define XIL_EVENT_ERROR_MASK_XRAM_CR (0x08000000U) + +/** Error event mask for XRAM Non-Correctable error. + * Only applicable in devices that have XRAM. */ +#define XIL_EVENT_ERROR_MASK_XRAM_NCR (0x10000000U) +/** + * @} + */ + +/** + * @defgroup psmerr2 Error Event Mask for PSM ERR2 + * @ingroup xilerroreventmask + * @brief Error Events belong to PSM ERR2 Node + * @{ + */ +/** Error event mask for Error from Watchdog Timer in the LPD Subsystem. */ +#define XIL_EVENT_ERROR_MASK_LPD_SWDT (0x00000001U) + +/** Error event mask for Error from Watchdog Timer in the FPD Subsystem. */ +#define XIL_EVENT_ERROR_MASK_FPD_SWDT (0x00000002U) + +/** Error event mask for LPD XMPU Errors: Register access error on APB, + * Read permission violation, Write permission violation, Security violation. */ +#define XIL_EVENT_ERROR_MASK_LPD_XMPU (0x00040000U) + +/** Error event mask for LPD XPPU Errors: Register access error on APB, + * Master ID not found, Read permission violation, Master ID parity error, + * Master ID access violation, TrustZone violation, Aperture parity error. */ +#define XIL_EVENT_ERROR_MASK_LPD_XPPU (0x00080000U) + +/** Error event mask for FPD XMPU Errors: Register access error on APB, + * Read permission violation, Write permission violation, Security violation. */ +#define XIL_EVENT_ERROR_MASK_FPD_XMPU (0x00100000U) +/** + * @} + */ + +/** + * @defgroup swerr Error Event Mask for Software error events + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to SW ERR Node + */ +/** Error event mask for Software error events */ +/** Health Boot Monitoring errors */ +#define XIL_EVENT_ERROR_MASK_HB_MON_0 (0x00000001U) +#define XIL_EVENT_ERROR_MASK_HB_MON_1 (0x00000002U) +#define XIL_EVENT_ERROR_MASK_HB_MON_2 (0x00000004U) +#define XIL_EVENT_ERROR_MASK_HB_MON_3 (0x00000008U) +#define XIL_EVENT_ERROR_MASK_PLM_EXCEPTION (0x00000010U) +/** XilSem errors */ +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_CE (0x00000020U) +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_UE (0x00000040U) +#define XIL_EVENT_ERROR_MASK_XSEM_NPI_UE (0x00000080U) +/** STL errors */ +#define XIL_EVENT_ERROR_MASK_XSTL_UE (0x00000100U) +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* XIL_ERROR_NODE_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_hw.h new file mode 100644 index 0000000..cf288bf --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal/xil_hw.h @@ -0,0 +1,98 @@ +/****************************************************************************** +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** +* +* @file xil_hw.h +* +* This is the header file which contains definitions for the hardware +* registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date        Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.7   bsv   02/21/2017 Initial release
+* 7.8   skd   03/09/2022 Compilation warning fix
+* 8.0   bm    07/06/2022 Refactor versal and versal_net code
+*       bsv   07/19/2022 Moved PCSR_LOCK macros to standalone from xilpm
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HW_H +#define XIL_HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/**@cond xil_internal + * @{ + */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +/* + * PMC_GLOBAL Base Address + */ +#define PMC_GLOBAL_BASEADDR (0XF1110000U) + +/* + * Register: PMC_GLOBAL_DOMAIN_ISO_CNTRL + */ +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL (PMC_GLOBAL_BASEADDR + 0X00010000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_MASK (0X00000400U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_MASK (0X00000800U) + +/* + * Definitions required from pmc_tap.h + */ +#define PMC_TAP_BASEADDR (0XF11A0000U) +#define PMC_TAP_IDCODE (PMC_TAP_BASEADDR + 0X00000000U) +#define PMC_TAP_VERSION (PMC_TAP_BASEADDR + 0X00000004U) +#define PMC_TAP_VERSION_PMC_VERSION_MASK (0X000000FFU) +/* + * Definitions required from crp.h + */ +#define CRP_BASEADDR (0XF1260000U) +#define CRP_RESET_REASON (CRP_BASEADDR + 0X00000220U) +#define CRP_RST_NONPS (CRP_BASEADDR + 0X00000320U) +#define CRP_RST_NONPS_NPI_RESET_MASK (0X10U) +/* + * Register: CRP_RST_PS + */ +#define CRP_RST_PS (CRP_BASEADDR + 0x0000031CU) +/* + * Register: PMC_IOU_SLCR + */ +#define PMC_IOU_SLCR_BASEADDR (0XF1060000U) + +#define IPI_BASEADDR (0xFF300000U) + +#define PCSR_UNLOCK_VAL (0xF9E8D7C6U) +#define PCSR_LOCK_VAL (0U) + +/** + * @} + * @endcond + */ + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_HW_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/CMakeLists.txt new file mode 100644 index 0000000..00f7985 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +# SPDX-License-Identifier: MIT +collect (PROJECT_LIB_HEADERS xil_error_node.h) +collect (PROJECT_LIB_HEADERS xil_hw.h) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_error_node.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_error_node.h new file mode 100644 index 0000000..01bc5f0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_error_node.h @@ -0,0 +1,735 @@ +/****************************************************************************** +* Copyright (c) 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_error_node.h +* +* This is the file which contains node IDs information for versal net error events. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who 	 Date        Changes
+* ----- -------- -------- -----------------------------------------------------
+* 8.0   bm       07/06/2022 Initial release
+*       dc       07/12/2022 Added XIL_EVENT_ERROR_MASK_DEV_STATE_CHANGE
+* 8.1   kal      01/05/2023 Added XIL_EVENT_ERROR_PCR_LOG_UPDATE
+*       rama     01/19/2023 Add XilSem errors to SW error events
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef XIL_ERROR_NODE_H +#define XIL_ERROR_NODE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/**@name Versalnet Event Node IDs + * @defgroup xileventnodes Event Node IDs + * @ingroup xilnodeids + * @{ + */ + +#define XIL_NODETYPE_EVENT_ERROR_ID_ENCODING (0x28100000U) + + /** + * Error Event Node Ids + */ +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR1 (0x28100000U) +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR2 (0x28104000U) +#define XIL_NODETYPE_EVENT_ERROR_PMC_ERR3 (0x28108000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR1 (0x2810C000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR2 (0x28110000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR3 (0x28114000U) +#define XIL_NODETYPE_EVENT_ERROR_PSM_ERR4 (0x28118000U) +#define XIL_NODETYPE_EVENT_ERROR_SW_ERR (0x2811C000U) +/** + * @} + */ + +/**@name Versalnet Error event Mask + * @defgroup xilerroreventmask Error Event Mask + * @ingroup xilnodeids + * @{ + * @defgroup pmcerr1 Error Event Mask for PMC ERR1 + * @ingroup xilerroreventmask + * @{ + * @brief Error Events belong to PMC ERR1 Node + */ + +/** Error event mask for PMC Boot Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_CR (0x00000001U) + +/** Error event mask for PMC Boot Non-Correctable Error. + * Set by ROM code during ROM execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_BOOT_NCR (0x00000002U) + +/** Error event mask for PMC Firmware Boot Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_CR (0x00000004U) + +/** Error event mask for PMC Firmware Boot Non-Correctable Error. + * Set by PLM during firmware execution during Boot. */ +#define XIL_EVENT_ERROR_MASK_FW_NCR (0x00000008U) + +/** Error event mask for General Software Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_CR (0x00000010U) + +/** Error event mask for General Software Non-Correctable Error. + * Set by any processors after Boot. */ +#define XIL_EVENT_ERROR_MASK_GSW_NCR (0x00000020U) + +/** Error event mask for CFU Error. */ +#define XIL_EVENT_ERROR_MASK_CFU (0x00000040U) + +/** Error event mask for CFRAME Error. */ +#define XIL_EVENT_ERROR_MASK_CFRAME (0x00000080U) + +/** Error event mask for PSM Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_CR (0x00000100U) + +/** Error event mask for PSM Non-Correctable Error, + * Summary from PSM Error Management. */ +#define XIL_EVENT_ERROR_MASK_PMC_PSM_NCR (0x00000200U) + +/** Error event mask for DDRMC MB Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_CR (0x00000400U) + +/** Error event mask for DDRMC MB Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMB_NCR (0x00000800U) + +/** Error event mask for NoC Type1 Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_CR (0x00001000U) + +/** Error event mask for NoC Type1 Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_NOCTYPE1_NCR (0x00002000U) + +/** Error event mask for NoC User Error. */ +#define XIL_EVENT_ERROR_MASK_NOCUSER (0x00004000U) + +/** Error event mask for MMCM Lock Error. */ +#define XIL_EVENT_ERROR_MASK_MMCM (0x00008000U) + +/** Error event mask for ME Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_CR (0x00010000U) + +/** Error event mask for ME Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_AIE_NCR (0x00020000U) + +/** Error event mask for DDRMC MC Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_CR (0x00040000U) + +/** Error event mask for DDRMC MC Non-Correctable ECC Error. */ +#define XIL_EVENT_ERROR_MASK_DDRMC_NCR (0x00080000U) + +/** Error event mask for GT Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_CR (0x00100000U) + +/** Error event mask for GT Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_GT_NCR (0x00200000U) + +/** Error event mask for PL Sysmon Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_CR (0x00400000U) + +/** Error event mask for PL Sysmon Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PLSMON_NCR (0x00800000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL0 (0x01000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL1 (0x02000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL2 (0x04000000U) + +/** Error event mask for User defined PL generic error. */ +#define XIL_EVENT_ERROR_MASK_PL3 (0x08000000U) + +/** Error event mask for NPI Root Error. */ +#define XIL_EVENT_ERROR_MASK_NPIROOT (0x10000000U) + +/** Error event mask for SSIT Error from Slave SLR1, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT3 (0x20000000U) + +/** Error event mask for SSIT Error from Slave SLR2, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT4 (0x40000000U) + +/** Error event mask for SSIT Error from Slave SLR3, + * Only used in Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT5 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup pmcerr2 Error Event Mask for PMC ERR2 + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to PMC ERR2 Node + */ +/** Error event mask for General purpose PMC error, + * can be triggered by any of the following peripherals:, + * - PMC Global Regsiters,- PMC Clock & Reset (CRP),- PMC IOU Secure SLCR, + * - PMC IOU SLCR,- BBRAM Controller,- PMC Analog Control Registers, + * - RTC Control Registers. */ +#define XIL_EVENT_ERROR_MASK_PMCAPB (0x00000001U) + +/** Error event mask for PMC ROM Validation Error. */ +#define XIL_EVENT_ERROR_MASK_PMCROM (0x00000002U) + +/** Error event mask for PMC PPU0 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL0 (0x00000004U) + +/** Error event mask for PMC PPU1 MB TMR Fatal Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL1 (0x00000008U) + +/** Error event mask for PMC Correctable Errors:, + * PPU0 RAM correctable error.,PPU1 instruction RAM correctable error., + * PPU1 data RAM correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_CR (0x00000020U) + +/** Error event mask for PMC Non-Correctable Errors:, + * PPU0 RAM non-correctable error.,PPU1 instruction RAM non-correctable error., + * PPU1 data RAM non-correctable error.,PRAM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_PMC_NCR (0x00000040U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[0]. + * Indicates an alarm condition on any of SUPPLY0 to SUPPLY31. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON0 (0x00000080U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[1]. + * Indicates an alarm condition on any of SUPPLY32 to SUPPLY63. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON1 (0x00000100U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[2]. + * Indicates an alarm condition on any of SUPPLY64 to SUPPLY95. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON2 (0x00000200U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[3]. + * Indicates an alarm condition on any of SUPPLY96 to SUPPLY127. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON3 (0x00000400U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[4]. + * Indicates an alarm condition on any of SUPPLY128 to SUPPLY159. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON4 (0x00000800U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[8]. + * Indicates an over-temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON8 (0x00008000U) + +/** Error event mask for PMC Temperature Shutdown Alert and Power Supply + * Failure Detection Errors from PMC Sysmon alarm[9]. + * Indicates a device temperature alarm. */ +#define XIL_EVENT_ERROR_MASK_PMCSMON9 (0x00010000U) + +/** Error event mask for CFI Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_CFI (0x00020000U) + +/** Error event mask for CFRAME SEU CRC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUCRC (0x00040000U) + +/** Error event mask for CFRAME SEU ECC Error. */ +#define XIL_EVENT_ERROR_MASK_SEUECC (0x00080000U) + +/** Error event mask for PMX WDT Error. */ +#define XIL_EVENT_ERROR_MASK_PMX_WWDT (0x00100000U) + +/** Error event mask for RTC Alarm Error. */ +#define XIL_EVENT_ERROR_MASK_RTCALARM (0x00400000U) + +/** Error event mask for PMC NPLL Lock Error, + * This error can be unmasked after the NPLL is locked to alert when the + * NPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_NPLL (0x00800000U) + +/** Error event mask for PMC PPLL Lock Error, + * This error can be unmasked after the PPLL is locked to alert when the + * PPLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_PPLL (0x01000000U) + +/** Error event mask for Clock Monitor Errors., + * Collected from CRP's CLKMON_STATUS register. */ +#define XIL_EVENT_ERROR_MASK_CLKMON (0x02000000U) + +/** Error event mask for PMC interconnect correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PMX_CORR_ERR (0x08000000U) + +/** Error event mask for PMC interconnect uncorrectable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PMX_UNCORR_ERR (0x10000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR1., + * For Slave SLRs: SSIT Error0 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT0 (0x20000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR2., + * For Slave SLRs: SSIT Error1 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT1 (0x40000000U) + +/** Error event mask for For Master SLR: SSIT Error from Slave SLR3., + * For Slave SLRs: SSIT Error2 from Master SLR. */ +#define XIL_EVENT_ERROR_MASK_SSIT2 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup pmcerr3 Error Event Mask for PMC ERR3 + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to PMC ERR3 Node + */ +/** Error event mask for PMC IOU correctable error. */ +#define XIL_EVENT_ERROR_MASK_IOU_CR (0x00000001U) + +/** Error event mask for PMC IOU uncorrectable error. */ +#define XIL_EVENT_ERROR_MASK_IOU_NCR (0x00000002U) + +/** Error event mask for DFX unexpected activation. */ +#define XIL_EVENT_ERROR_MASK_DFX_UXPT_ACT (0x00000004U) + +/** Error event mask for DICE CDI SEED parity. */ +#define XIL_EVENT_ERROR_MASK_DICE_CDI_PAR (0x00000008U) + +/** Error event mask for Device identity private key parity. */ +#define XIL_EVENT_ERROR_MASK_DEVIK_PRIV (0x00000010U) + +/** Error event mask for Next SW CDI SEED parity. */ +#define XIL_EVENT_ERROR_MASK_NXTSW_CDI_PAR (0x00000020U) + +/** Error event mask for Device attestation private key parity. */ +#define XIL_EVENT_ERROR_MASK_DEVAK_PRIV (0x00000040U) + +/** Error event mask for DME public key X component's parity. */ +#define XIL_EVENT_ERROR_MASK_DME_PUB_X (0x00000080U) + +/** Error event mask for DME public key Y component's parity. */ +#define XIL_EVENT_ERROR_MASK_DME_PUB_Y (0x00000100U) + +/** Error event mask for DEVAK public key X component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVAK_PUB_X (0x00000200U) + +/** Error event mask for DEVAK public key Y component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVAK_PUB_Y (0x00000400U) + +/** Error event mask for DEVIK public key X component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVIK_PUB_X (0x00000800U) + +/** Error event mask for DEVIK public key Y component's parity. */ +#define XIL_EVENT_ERROR_MASK_DEVIK_PUB_Y (0x00001000U) + +/** Error event mask for PCR parity. */ +#define XIL_EVENT_ERROR_MASK_PCR_PAR (0x00002000U) +/** + * @} + */ + +/** + * @defgroup psmerr1 Error Event Mask for PSM ERR1 + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to PSM ERR1 Node + */ +/** Error event mask for PS Software can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_CR (0x00000001U) + +/** Error event mask for PS Software can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PS_SW_NCR (0x00000002U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_CR (0x00000004U) + +/** Error event mask for PSM Firmware can write to trigger register to + * generate this Non-Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_PSM_B_NCR (0x00000008U) + +/** Error event mask for Or of MB Fatal1, Fatal2, Fatal3 Error. */ +#define XIL_EVENT_ERROR_MASK_MB_FATAL (0x00000010U) + +/** Error event mask for PSM Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_CR (0x00000020U) + +/** Error event mask for PSM Non-Correctable. */ +#define XIL_EVENT_ERROR_MASK_PSM_NCR (0x00000040U) + +/** Error event mask for PSMX CHK error. */ +#define XIL_EVENT_ERROR_MASK_PSMX_CHK (0x00000080U) + +/** Error event mask for APLL1 lock error. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_APLL1_LOCK (0x00000100U) + +/** Error event mask for APLL2 lock error. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_APLL2_LOCK (0x00000200U) + +/** Error event mask for RPLL Lock Errors. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_RPLL_LOCK (0x00000400U) + +/** Error event mask for FLXPLL Lock Errors. The error can be unmasked + * after the PLL is locked to alert when the PLL loses lock. */ +#define XIL_EVENT_ERROR_MASK_FLXPLL_LOCK (0x00000800U) + +/** Error event mask for INT_PSM correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PSM_CR (0x00001000U) + +/** Error event mask for INT_PSM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_PSM_NCR (0x00002000U) + +/** Error event mask for Consolidated Error from the two USB2 blocks. */ +#define XIL_EVENT_ERROR_MASK_USB2 (0x00004000U) + +/** Error event mask for LPX unexpected dfx activation error. */ +#define XIL_EVENT_ERROR_MASK_LPX_UXPT_ACT (0x00008000U) + +/** Error event mask for INT_LPD correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_LPD_CR (0x00020000U) + +/** Error event mask for INT_LPD non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_LPD_NCR (0x00040000U) + +/** Error event mask for INT_OCM correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_OCM_CR (0x00080000U) + +/** Error event mask for INT_OCM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_OCM_NCR (0x00100000U) + +/** Error event mask for INT_FPD correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_FPD_CR (0x00200000U) + +/** Error event mask for INT_FPD non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_INT_FPD_NCR (0x00400000U) + +/** Error event mask for INT_IOU correctable Error. */ +#define XIL_EVENT_ERROR_MASK_INT_IOU_CR (0x00800000U) + +/** Error event mask for INT_IOU non-correctable Error. */ +#define XIL_EVENT_ERROR_MASK_INT_IOU_NCR (0x01000000U) + +/** Error event mask for RPU lockstep error for ClusterA. */ +#define XIL_EVENT_ERROR_MASK_RPUA_LOCKSTEP (0x02000000U) + +/** Error event mask for RPU lockstep error for ClusterB. */ +#define XIL_EVENT_ERROR_MASK_RPUB_LOCKSTEP (0x04000000U) + +/** Error event mask for APU GIC AXI error (slverr, decerr). */ +#define XIL_EVENT_ERROR_MASK_APU_GIC_AXI (0x08000000U) + +/** Error event mask for APU GIC ECC error. */ +#define XIL_EVENT_ERROR_MASK_APU_GIC_ECC (0x10000000U) + +/** Error event mask for CPM correctable error. */ +#define XIL_EVENT_ERROR_MASK_CPM_CR (0x20000000U) + +/** Error event mask for CPM non-correctable error. */ +#define XIL_EVENT_ERROR_MASK_CPM_NCR (0x40000000U) + +/** Error event mask for CPI error. */ +#define XIL_EVENT_ERROR_MASK_CPI (0x80000000U) +/** + * @} + */ + + +/** + * @defgroup psmerr2 Error Event Mask for PSM ERR2 + * @ingroup xilpmerroreventmask + * @brief Error Events belong to PSM ERR2 Node + * @{ + */ +/** Error event mask for FPD WDT0 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT0 (0x00000001U) + +/** Error event mask for FPD WDT1 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT1 (0x00000002U) + +/** Error event mask for FPD WDT2 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT2 (0x00000004U) + +/** Error event mask for FPD WDT3 error. */ +#define XIL_EVENT_ERROR_MASK_FPD_WDT3 (0x00000008U) + +/** Error event mask for Memory Errors for Splitter0. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER0 (0x00000010U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter0. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER0 (0x00000020U) + +/** Error event mask for Memory Errors for Splitter1. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER1 (0x00000040U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter1. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER1 (0x00000080U) + +/** Error event mask for Memory Errors for Splitter2. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER2 (0x00000100U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter2. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER2 (0x00000200U) + +/** Error event mask for Memory Errors for Splitter3. */ +#define XIL_EVENT_ERROR_MASK_MEM_SPLITTER3 (0x00000400U) + +/** Error event mask for Consolidated Errror indicating AXI parity Error for Splitter3. */ +#define XIL_EVENT_ERROR_MASK_AXI_PAR_SPLITTER3 (0x00000800U) + +/** Error event mask for APU Cluster 0 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER0 (0x00001000U) + +/** Error event mask for APU Cluster 1 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER1 (0x00002000U) + +/** Error event mask for APU Cluster 2 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER2 (0x00004000U) + +/** Error event mask for APU Cluster 3 error. */ +#define XIL_EVENT_ERROR_MASK_APU_CLUSTER3 (0x00008000U) + +/** Error event mask for WWDT0 LPX Error. */ +#define XIL_EVENT_ERROR_MASK_LPD_WWDT0 (0x00010000U) + +/** Error event mask for WWDT0 LPX Error. */ +#define XIL_EVENT_ERROR_MASK_LPD_WWDT1 (0x00020000U) + +/** Error event mask for ADMA Lockstep Error. */ +#define XIL_EVENT_ERROR_MASK_ADMA_LOCKSTEP (0x00040000U) + +/** Error event mask for IPI Error */ +#define XIL_EVENT_ERROR_MASK_IPI (0x00080000U) + +/** Error event mask for OCM Bank0 Corr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK0_CR (0x00100000U) + +/** Error event mask for OCM Bank1 Corr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK1_CR (0x00200000U) + +/** Error event mask for OCM Bank0 UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK0_NCR (0x00400000U) + +/** Error event mask for OCM Bank1 UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_OCM_BANK1_NCR (0x00800000U) + +/** Error event mask for LPXAFIFS Corr Error. */ +#define XIL_EVENT_ERROR_MASK_LPXAFIFS_CR (0x01000000U) + +/** Error event mask for LPXAFIFS UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_LPXAFIFS_NCR (0x02000000U) + +/** Error event mask for LPX Glitch Detector0 glitch detected. */ +#define XIL_EVENT_ERROR_MASK_LPX_GLITCH_DETECT0 (0x04000000U) + +/** Error event mask for LPX Glitch Detector1 glitch detected. */ +#define XIL_EVENT_ERROR_MASK_LPX_GLITCH_DETECT1 (0x08000000U) + +/** Error event mask for Firewall write errors from NOC NMUs. */ +#define XIL_EVENT_ERROR_MASK_FWALL_WR_NOC_NMU (0x10000000U) + +/** Error event mask for Firewall read error from NOC NMU. */ +#define XIL_EVENT_ERROR_MASK_FWALL_RD_NOC_NMU (0x20000000U) + +/** Error event mask for Firewall error from NOC NSU. */ +#define XIL_EVENT_ERROR_MASK_FWALL_NOC_NSU (0x40000000U) + +/** Error event mask for Bit[18] from R52 Core A0, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_A0 (0x80000000U) +/** + * @} + */ + +/** + * @defgroup psmerr3 Error Event Mask for PSM ERR3 + * @ingroup xilpmerroreventmask + * @brief Error Events belong to PSM ERR3 Node + * @{ + */ +/** Error event mask for Bit[18] from R52 Core A1, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_A1 (0x00000001U) + +/** Error event mask for Bit[18] from R52 Core B0, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_B0 (0x00000002U) + +/** Error event mask for Bit[18] from R52 Core B1, Err event. */ +#define XIL_EVENT_ERROR_MASK_B18_R52_B1 (0x00000004U) + +/** Error event mask for R52 A0 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A0_CR (0x00000008U) + +/** Error event mask for R52 A0 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A0_TFATAL (0x00000010U) + +/** Error event mask for R52 A0 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A0_TIMEOUT (0x00000020U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUA0. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUA0 (0x00000040U) + +/** Error event mask for Bit[25] of ERREVNT for RPUA0. */ +#define XIL_EVENT_ERROR_MASK_B25_RPUA0 (0x00000080U) + +/** Error event mask for R52 A1 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A1_CR (0x00000100U) + +/** Error event mask for R52 A1 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A1_TFATAL (0x00000200U) + +/** Error event mask for R52 A1 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_A1_TIMEOUT (0x00000400U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUA1. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUA1 (0x00000800U) + +/** Error event mask for Bit[25] of ERREVNT for RPUA1. */ +#define XIL_EVENT_ERROR_MASK_B25_RPUA1 (0x00001000U) + +/** Error event mask for R52 A1 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B0_CR (0x00002000U) + +/** Error event mask for R52 A1 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B0_TFATAL (0x00004000U) + +/** Error event mask for R52 A1 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B0_TIMEOUT (0x00008000U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUB0. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUB0 (0x00010000U) + +/** Error event mask for Bit[25] of ERREVNT for RPUB0. */ +#define XIL_EVENT_ERROR_MASK_B25_RPUB0 (0x00020000U) + +/** Error event mask for R52 A1 Core Correctable Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B1_CR (0x00040000U) + +/** Error event mask for R52 A1 Core TFatal Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B1_TFATAL (0x00080000U) + +/** Error event mask for R52 A1 Core Timeout Error. */ +#define XIL_EVENT_ERROR_MASK_R52_B1_TIMEOUT (0x00100000U) + +/** Error event mask for Bit[24:20] pf ERREVNT for RPUB1. */ +#define XIL_EVENT_ERROR_MASK_B24_B20_RPUB1 (0x00200000U) + +/** Error event mask for Bit[25] of ERREVNT for RPUB1.*/ +#define XIL_EVENT_ERROR_MASK_B25_RPUB1 (0x00400000U) + +/** Error event mask for PCIL ERR FOR RPU Clusters. */ +#define XIL_EVENT_ERROR_MASK_PCIL_RPU (0x01000000U) + +/** Error event mask for FPXAFIFS Corr Error. */ +#define XIL_EVENT_ERROR_MASK_FPXAFIFS_CR (0x02000000U) + +/** Error event mask for FPXAFIFS UnCorr Error. */ +#define XIL_EVENT_ERROR_MASK_FPXAFIFS_NCR (0x04000000U) + +/** Error event mask for PSX_CMN_1 PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CMN_1 (0x08000000U) + +/** Error event mask for PSX_CMN_2 PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CMN_2 (0x10000000U) + +/** Error event mask for PSX_CMN_3 PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CMN_3 (0x20000000U) + +/** Error event mask for PSX_CML PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_PSX_CML (0x40000000U) + +/** Error event mask for FPD_INT_WRAP PD block consolidated ERROR. */ +#define XIL_EVENT_ERROR_MASK_FPD_INT_WRAP (0x80000000U) +/** + * @} + */ + +/** + * @defgroup psmerr4 Error Event Mask for PSM ERR4 + * @ingroup xilpmerroreventmask + * @brief Error Events belong to PSM ERR4 Node + * @{ + */ +/** Error event mask for FPD Reset Monitor ERROR. */ +#define XIL_EVENT_ERROR_MASK_FPD_RST_MON (0x00000001U) + +/** Error event mask for LPD reset and Clock Monitor Error. */ +#define XIL_EVENT_ERROR_MASK_LPD_RST_CLK_MON (0x00000002U) + +/** Error event mask for Fatal Error from all AFI FM. */ +#define XIL_EVENT_ERROR_MASK_FATAL_AFI_FM (0x00000004U) + +/** Error event mask for Non Fatal Error from AFI FM in LPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM_LPX (0x00000008U) + +/** Error event mask for Non Fatal Error from AFI FM0 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM0_FPX (0x00000010U) + +/** Error event mask for Non Fatal Error from AFI FM1 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM1_FPX (0x00000020U) + +/** Error event mask for Non Fatal Error from AFI FM2 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM2_FPX (0x00000040U) + +/** Error event mask for Non Fatal Error from AFI FM3 in FPX. */ +#define XIL_EVENT_ERROR_MASK_NFATAL_AFI_FM3_FPX (0x00000080U) + +/** Error event mask for Errors from RPU cluster A. */ +#define XIL_EVENT_ERROR_MASK_RPU_CLUSTERA (0x00000100U) + +/** Error event mask for Errors from RPU cluster B. */ +#define XIL_EVENT_ERROR_MASK_RPU_CLUSTERB (0x00000200U) +/** + * @} + */ + +/** + * @defgroup swerr Error Event Mask for Software error events + * @ingroup xilpmerroreventmask + * @{ + * @brief Error Events belong to SW ERR Node + */ +/** Error event mask for Software error events */ +/** Health Boot Monitoring errors */ +#define XIL_EVENT_ERROR_MASK_HB_MON_0 (0x00000001U) +#define XIL_EVENT_ERROR_MASK_HB_MON_1 (0x00000002U) +#define XIL_EVENT_ERROR_MASK_HB_MON_2 (0x00000004U) +#define XIL_EVENT_ERROR_MASK_HB_MON_3 (0x00000008U) +#define XIL_EVENT_ERROR_MASK_PLM_EXCEPTION (0x00000010U) +#define XIL_EVENT_ERROR_MASK_DEV_STATE_CHANGE (0x00000020U) +#define XIL_EVENT_ERROR_PCR_LOG_UPDATE (0x00000040U) +/** XilSem errors */ +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_CE (0x00000080U) +#define XIL_EVENT_ERROR_MASK_XSEM_CRAM_UE (0x00000100U) +#define XIL_EVENT_ERROR_MASK_XSEM_NPI_UE (0x00000200U) +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* XIL_ERROR_NODE_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_hw.h new file mode 100644 index 0000000..42a7947 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/versal_net/xil_hw.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* Copyright (c) 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** +* +* @file xil_hw.h +* +* This is the header file which contains definitions for the hardware +* registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date        Changes
+* ----- ---- -------- -------------------------------------------------------
+* 8.0   bm   07/06/2022 Initial release
+*       bsv  07/19/2022 Moved PCSR_LOCK macros to standalone from xilpm
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HW_H +#define XIL_HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/**@cond xil_internal + * @{ + */ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +/* + * PMC_GLOBAL Base Address + */ +#define PMC_GLOBAL_BASEADDR (0XF1110000U) + +/* + * Register: PMC_GLOBAL_DOMAIN_ISO_CNTRL + */ +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL (PMC_GLOBAL_BASEADDR + 0X00010000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_VCCRAM_MASK (0x00040000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCRAM_SOC_MASK (0x00020000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_VCCAUX_SOC_MASK (0x00010000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PL_SOC_MASK (0x00008000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_MASK (0x00004000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_SOC_NPI_MASK (0x00002000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_MASK (0x00001000U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_TEST_MASK (0x00000800U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_PL_CFRAME_MASK (0X00000400U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_MASK (0x00000200U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_PMC_LPD_DFX_MASK (0x00000100U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_SOC_MASK (0x00000080U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_MASK (0x00000040U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_PL_TEST_MASK (0x00000020U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_MASK (0x00000010U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_LPD_CPM_DFX_MASK (0x00000008U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_SOC_MASK (0x00000004U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_MASK (0x00000002U) +#define PMC_GLOBAL_DOMAIN_ISO_CNTRL_FPD_PL_TEST_MASK (0x00000001U) +/* + * Definitions required from pmc_tap.h + */ +#define PMC_TAP_BASEADDR (0XF11A0000U) +#define PMC_TAP_IDCODE (PMC_TAP_BASEADDR + 0X00000000U) +#define PMC_TAP_VERSION (PMC_TAP_BASEADDR + 0X00000004U) +#define PMC_TAP_VERSION_PMC_VERSION_MASK (0X000000FFU) +/* + * Definitions required from crp.h + */ +#define CRP_BASEADDR (0XF1260000U) +#define CRP_RESET_REASON (CRP_BASEADDR + 0X00000220U) +#define CRP_RST_NONPS (CRP_BASEADDR + 0X00000320U) +#define CRP_RST_NONPS_NPI_RESET_MASK (0X10U) +/* + * Register: CRP_RST_PS + */ +#define CRP_RST_PS (CRP_BASEADDR + 0x0000031CU) +/* + * Register: PMC_IOU_SLCR + */ +#define PMC_IOU_SLCR_BASEADDR (0XF1060000U) + +#define IPI_BASEADDR (0xEB300000U) + +#define PCSR_UNLOCK_VAL (0xF9E8D7C6U) +#define PCSR_LOCK_VAL (0U) + +/** + * @} + * @endcond + */ + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_HW_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/write.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/write.c new file mode 100644 index 0000000..279a0cd --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/write.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/* write.c -- write bytes to an output device. + */ +#ifndef UNDEFINE_FILE_OPS +#include "xil_printf.h" +#include "bspconfig.h" +#ifndef SDT +#include "xparameters.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes); +__attribute__((weak)) sint32 write (sint32 fd, char8* buf, sint32 nbytes); + +#ifdef __cplusplus +} +#endif + +/* + * write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ +__attribute__((weak)) sint32 +write (sint32 fd, char8* buf, sint32 nbytes) + +{ +#if defined(STDOUT_BASEADDRESS) || defined(SDT) + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +} + +__attribute__((weak)) sint32 +_write (sint32 fd, char8* buf, sint32 nbytes) +{ +#if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE) + sint32 length; + + (void)fd; + (void)nbytes; + length = XPVXenConsole_Write(buf); + return length; +#else +#if defined(STDOUT_BASEADDRESS) || defined(SDT) + s32 i; + char8* LocalBuf = buf; + + (void)fd; + for (i = 0; i < nbytes; i++) { + if(LocalBuf != NULL) { + LocalBuf += i; + } + if(LocalBuf != NULL) { + if (*LocalBuf == '\n') { + outbyte ('\r'); + } + outbyte (*LocalBuf); + } + if(LocalBuf != NULL) { + LocalBuf -= i; + } + } + return (nbytes); +#else + (void)fd; + (void)buf; + (void)nbytes; + return 0; +#endif +#endif +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xbasic_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xbasic_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xbasic_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xbasic_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xcortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xcortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xcortexa9_config.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9_config.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xcortexa9_config.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xcortexa9_config.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xdebug.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xdebug.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xdebug.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xdebug.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xenv.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xenv.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xenv_standalone.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv_standalone.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xenv_standalone.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xenv_standalone.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil-crt0.S b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil-crt0.S new file mode 100644 index 0000000..a560286 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil-crt0.S @@ -0,0 +1,136 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil-crt0.S +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.05a sdm  02/02/12 Added code for profiling
+* 3.06a sgd  05/16/12 Added global constructors and cleanup code
+*                     Uart initialization based on compiler flag
+* 3.07a sgd  07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2	pkp  08/04/14 Removed PEEP board related code which contained
+*		      initialization of uart smc nor and sram
+* 5.3	pkp  10/07/15 Added support for OpenAMP by not initializing global
+*		      timer when USE_AMP flag is defined
+* 6.6   srm  10/18/17 Added timer configuration using XTime_StartTTCTimer API.
+*		      Now the TTC instance as specified by the user will be
+*		      started.
+* 7.7   adk  11/30/21 Added support for xiltimer library.
+*
    +* +* @note +* +* None. +* +******************************************************************************/ +#include "bspconfig.h" +#include "xparameters.h" + + .file "xil-crt0.S" + .section ".got2","aw" + .align 2 + + .text +.Lsbss_start: + .long __sbss_start + +.Lsbss_end: + .long __sbss_end + +.Lbss_start: + .long __bss_start + +.Lbss_end: + .long __bss_end + +.Lstack: + .long __stack + + + .globl _start +_start: + bl __cpu_init /* Initialize the CPU first (BSP provides this) */ + + mov r0, #0 + + /* clear sbss */ + ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ + ldr r2,.Lsbss_end /* calculate end of the SBSS */ + +.Lloop_sbss: + cmp r1,r2 + bge .Lenclsbss /* If no SBSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_sbss + +.Lenclsbss: + /* clear bss */ + ldr r1,.Lbss_start /* calculate beginning of the BSS */ + ldr r2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp r1,r2 + bge .Lenclbss /* If no BSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_bss + +.Lenclbss: + + /* set stack pointer */ + ldr r13,.Lstack /* stack address */ + + /* Reset and start Global Timer */ + mov r0, #0x0 + mov r1, #0x0 + + /* Reset and start Triple Timer Counter */ + #if defined SLEEP_TIMER_BASEADDR + bl XTime_StartTTCTimer + #endif + +#ifndef XPAR_XILTIMER_ENABLED +#if USE_AMP != 1 + bl XTime_SetTime +#endif +#endif + +#ifdef PROFILING /* defined in Makefile */ + /* Setup profiling stuff */ + bl _profile_init +#endif /* PROFILING */ + + /* run global constructors */ + bl __libc_init_array + + /* make sure argc and argv are valid */ + mov r0, #0 + mov r1, #0 + + /* Let her rip */ + bl main + + /* Cleanup global constructors */ + bl __libc_fini_array + +#ifdef PROFILING + /* Cleanup profiling stuff */ + bl _profile_clean +#endif /* PROFILING */ + + /* All done */ + bl exit + +.Lexit: /* should never get here */ + b .Lexit + +.Lstart: + .size _start,.Lstart-_start diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/xbasic_types.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.c similarity index 55% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/xbasic_types.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.c index 67d02ae..b3dd7e9 100644 --- a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/common/src/xbasic_types.c +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.c @@ -1,33 +1,32 @@ /****************************************************************************** -* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved. -* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /*****************************************************************************/ /** * -* @file xbasic_types.c -* @addtogroup common Overview +* @file xil_assert.c +* @addtogroup common_assert_apis Assert APIs and Macros * @{ * -* This file contains basic functions for Xilinx software IP. +* This file contains basic assert related functions for Xilinx software IP. * * 
     * MODIFICATION HISTORY:
 *
 * Ver   Who    Date   Changes
 * ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
-* 1.00a xd   11/03/04 Improved support for doxygen.
-* 1.00a bss  13/01/12 Removed a compiler warning in XNullHandler;
+* 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
 *
    * ******************************************************************************/ /***************************** Include Files *********************************/ -#include "xbasic_types.h" +#include "xil_types.h" +#include "xil_assert.h" /************************** Constant Definitions *****************************/ @@ -38,80 +37,80 @@ /************************** Variable Definitions *****************************/ /** - * This variable allows testing to be done easier with asserts. An assert + * @brief This variable allows testing to be done easier with asserts. An assert * sets this variable such that a driver can evaluate this variable * to determine if an assert occurred. */ -unsigned int XAssertStatus; +u32 Xil_AssertStatus; /** - * This variable allows the assert functionality to be changed for testing + * @brief This variable allows the assert functionality to be changed for testing * such that it does not wait infinitely. Use the debugger to disable the * waiting during testing of asserts. */ -int XWaitInAssert = TRUE; +s32 Xil_AssertWait = 1; /* The callback function to be invoked when an assert is taken */ -static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL; +static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; /************************** Function Prototypes ******************************/ /*****************************************************************************/ /** * -* Implements assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the XWaitInAssert variable. +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. * -* @param File is the name of the filename of the source -* @param Line is the linenumber within File +* @param File: filename of the source +* @param Line: linenumber within File * * @return None. * * @note None. * ******************************************************************************/ -void XAssert(char *File, int Line) +void Xil_Assert(const char8 *File, s32 Line) { /* if the callback has been set then invoke it */ - if (XAssertCallbackRoutine != NULL) { - (*XAssertCallbackRoutine) (File, Line); + if (Xil_AssertCallbackRoutine != 0) { + (*Xil_AssertCallbackRoutine)(File, Line); } /* if specified, wait indefinitely such that the assert will show up * in testing */ - while (XWaitInAssert) { + while (Xil_AssertWait != 0) { } } /*****************************************************************************/ /** * -* Sets up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. * -* @param Routine is the callback to be invoked when an assert is taken +* @param Routine: callback to be invoked when an assert is taken * * @return None. * * @note This function has no effect if NDEBUG is set * ******************************************************************************/ -void XAssertSetCallback(XAssertCallback Routine) +void Xil_AssertSetCallback(Xil_AssertCallback Routine) { - XAssertCallbackRoutine = Routine; + Xil_AssertCallbackRoutine = Routine; } - /*****************************************************************************/ /** * -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. * -* @param NullParameter is an arbitrary void pointer and not used. +* @param NullParameter: arbitrary void pointer and not used. * * @return None. * @@ -120,6 +119,8 @@ void XAssertSetCallback(XAssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void) NullParameter; + (void) NullParameter; } -/** @} */ +/** +* @} End of "addtogroup common_assert_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_assert.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_assert.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_assert.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.c new file mode 100644 index 0000000..0f6b14f --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.c @@ -0,0 +1,1535 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_cache.c +* +* Contains required functions for the ARM cache functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      		  to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      		  L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      		  at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      		  APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      		  'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  		  operation was being done with L1 Data cache disabled. This is
+*			  		  fixed so that L2 cache disable operation happens independent of
+*			  		  L1 cache disable operation. This fixes CR #706464.
+*			  		  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  		  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 		  Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 		  relevant cache APIs to disable and enable back the interrupts.
+*			 		  This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 		  out that for L2 cache flush/clean/invalidation by cache lines
+*			 		  does not need a cache sync as these are atomic nature. Similarly
+*			 		  figured out that for complete L2 cache flush/invalidation by way
+*			 		  we need to wait for some more time in a loop till the status
+*			 		  shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 		  cache lines were missed to invalidate when unaligned address
+*			 		  invalidation was accommodated. That fixes CR #766768.
+*			 		  Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 		  stack memory which contains return address was invalidated. So
+*			 		  stack memory was flushed first and then L1D cache is invalidated.
+*			 		  This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02	 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+*					  explanation of CR#785243
+* 5.00   kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+*					  has stack memory which has return address. Before invalidating
+*					  cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01	 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+*					  to remove unnecessary dsb in the APIs. Instead of using dsb
+*					  for L2 Cache, L2CacheSync has been used for each L2 cache line
+*					  and single dsb has been used for L1 cache. Also L2CacheSync is
+*					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+*					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
+*					  stack instead of just System Stack
+* 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+*					  application(when USE_AMP flag is defined for BSP) as master CPU
+*					  would be utilizing L2 cache for its operation
+* 6.6    mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+*                     version r0p2, which is present in zynq. So,removed the handling
+*                     related to same.It fixes CR#989132.
+* 6.6    asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+*					  routines to ensure the stack data flushed only when the respective
+*					  caches are enabled. This fixes CR-992023.
+* 7.5    mus 01/19/21 Implement workaround for errata#588369 in Xil_DCacheFlushRange.
+*					  It fixes CR#1086022.
+* 8.0    asa 05/25/22 Fix issues in cache maintenance APIs Xil_DCacheFlushRange
+*                     and Xil_DCacheInvalidateRange to ensure that clean and
+*                     invalidation of outer cache (L2 cache) is separated out and
+*                     is independent from inner cache (L1 cache). This is inline
+*                     with recommendations and implementations available in open
+*                     source. It fixes CR#1130368.
+*                     Minimize use of barriers (dsb) as per guidances.
+*                     Remove the use of XREG_CP15_CACHE_SIZE_SEL register as it is
+*                     not needed for Zynq architecture.
+*                     Replace dsb with Xil_L2CacheSync as applicable as the latter
+*                     is more efficient while handling L2 cache maintenance.
+* 8.1    asa 02/13/23 The existing Xil_DCacheInvalidateRange has a bug where
+*                     the last cache line will not get invalidated under certain
+*                     scenarios. Changes are made to fix the same.
+* 9.0    ml  03/03/23 Added description to fix doxygen warnings.
+*        mus 09/21/23 Fix infinite loop in Xil_DCacheInvalidateRange when
+*                     USE_AMP=1.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xil_cache_l.h" +#include "xil_io.h" +#include "xpseudo_asm.h" +#include "xparameters.h" +#include "xreg_cortexa9.h" +#include "xl2cc.h" +#include "xil_errata.h" +#include "xil_exception.h" + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#define IRQ_FIQ_MASK 0xC0U /**< Mask IRQ and FIQ interrupts in cpsr */ + +#ifdef __GNUC__ + extern s32 _stack_end; + extern s32 __undef_stack; +#endif + +#ifndef USE_AMP +/***************************************************************************/ +/** +* +* Access L2 Debug Control Register. +* +* @param Value, value to be written to Debug Control Register. +* +* @return None. +* +****************************************************************************/ +#ifdef __GNUC__ +static inline void Xil_L2WriteDebugCtrl(u32 Value) +#else +static void Xil_L2WriteDebugCtrl(u32 Value) +#endif +{ +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value); +#else + (void)(Value); +#endif +} + +/***************************************************************************/ +/** +* +* Perform L2 Cache Sync Operation. +* +* @return None. +* +****************************************************************************/ +#ifdef __GNUC__ +static inline void Xil_L2CacheSync(void) +#else +static void Xil_L2CacheSync(void) +#endif +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U); +} +#endif +/****************************************************************************/ +/** +* @brief Enable the Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheEnable(void) +{ + Xil_L1DCacheEnable(); +#ifndef USE_AMP + Xil_L2CacheEnable(); +#endif +} + +/****************************************************************************/ +/** +* @brief Disable the Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheDisable(void) +{ +#ifndef USE_AMP + Xil_L2CacheDisable(); +#endif + Xil_L1DCacheDisable(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the entire Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidate(); +#endif + Xil_L1DCacheInvalidate(); + + mtcpsr(currmask); +} + +/*****************************************************************************/ +/** +* @brief Invalidate a Data cache line. If the byte specified by the address +* (adr) is cached by the Data cache, the cacheline containing that +* byte is invalidated. If the cacheline is modified (dirty), the +* modified contents are lost and are NOT written to the system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheInvalidateLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidateLine(adr); +#endif + Xil_L1DCacheInvalidateLine(adr); + + mtcpsr(currmask); +} + + +/*****************************************************************************/ +/** +* Invalidate the Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If +* the cachelines are modified (dirty), the modified contents are lost +* and NOT written to the system memory before the lines are +* invalidated. +* +* In this function, if start address or end address is not aligned to +* cache-line, particular cache-line containing unaligned start or end +* address is flush first and then invalidated the others as +* invalidating the same unaligned cache line may result into loss of +* data. This issue raises few possibilities. +* +* If the address to be invalidated is not cache-line aligned, the +* following choices are available: +* 1. Invalidate the cache line when required and do not bother much +* for the side effects. Though it sounds good, it can result in +* hard-to-debug issues. The problem is, if some other variable are +* allocated in the same cache line and had been recently updated +* (in cache), the invalidation would result in loss of data. +* 2. Flush the cache line first. This will ensure that if any other +* variable present in the same cache line and updated recently are +* flushed out to memory. Then it can safely be invalidated. Again it +* sounds good, but this can result in issues. For example, when the +* invalidation happens in a typical ISR (after a DMA transfer has +* updated the memory), then flushing the cache line means, losing +* data that were updated recently before the ISR got invoked. +* +* Linux prefers the second one. To have uniform implementation +* (across standalone and Linux), the second option is implemented. +* This being the case, following needs to be taken care of: +* 1. Whenever possible, the addresses must be cache line aligned. +* Please nore that, not just start address, even the end address must +* be cache line aligned. If that is taken care of, this will always +* work. +* 2. Avoid situations where invalidation has to be done after the +* data is updated by peripheral/DMA directly into the memory. It is +* not tough to achieve (may be a bit risky). The common use case to +* do invalidation is when a DMA happens. Generally for such use +* cases, buffers can be allocated first and then start the DMA. The +* practice that needs to be followed here is, immediately after +* buffer allocation and before starting the DMA, do the invalidation. +* With this approach, invalidation need not to be done after the DMA +* transfer is over. +* +* This is going to always work if done carefully. +* However, the concern is, there is no guarantee that invalidate has +* not needed to be done after DMA is complete. For example, because +* of some reasons if the first cache line or last cache line +* (assuming the buffer in question comprises of multiple cache lines) +* are brought into cache (between the time it is invalidated and DMA +* completes) because of some speculative prefetching or reading data +* for a variable present in the same cache line, then we will have to +* invalidate the cache after DMA is complete. +* +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + INTPTR tempadr; + INTPTR opendaddr; + INTPTR endaddr; + u32 currmask; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + opendaddr = adr + len; + endaddr = opendaddr; + + if ((adr & (cacheline-1U)) != 0U) { + adr &= (~(cacheline - 1U)); + + Xil_L1DCacheFlushLine(adr); +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + Xil_L2CacheFlushLine(adr); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); +#endif + adr += cacheline; + } + if ((opendaddr & (cacheline-1U)) != 0U) { + opendaddr &= (~(cacheline - 1U)); + + if (opendaddr != adr) { + Xil_L1DCacheFlushLine(opendaddr); +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + Xil_L2CacheFlushLine(opendaddr); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + Xil_L2CacheSync(); +#endif + } + } + + tempadr = adr; + +#ifndef USE_AMP + while (tempadr < endaddr) { + /* Invalidate L2 cache line */ + *L2CCOffset = tempadr; + Xil_L2CacheSync(); + tempadr += cacheline; + } +#endif + + while (adr < endaddr) { + /* Invalidate L1 Data cache line */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_dc_line_mva_poc(adr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); + Reg = adr; } +#endif + adr += cacheline; + } + /* Wait for L1 cache invalidation to complete */ + dsb(); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the entire Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheFlush(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L1DCacheFlush(); +#ifndef USE_AMP + Xil_L2CacheFlush(); +#endif + mtcpsr(currmask); +} + + +/****************************************************************************/ +/** +* @brief Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. +* +* @param adr: 32bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheFlushLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + Xil_L1DCacheFlushLine(adr); +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + Xil_L2CacheFlushLine(adr); + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); +#endif + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address range are cached by the +* data cache, the cachelines containing those bytes are invalidated. +* If the cachelines are modified (dirty), they are written to the +* system memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_DCacheFlushRange(INTPTR adr, u32 len) +{ + const u32 cacheline = 32U; + u32 opendadr; + u32 currmask; + u32 tempadr; + + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + opendadr = adr + len; + adr &= ~(cacheline - 1U); + + tempadr = adr; + + while (tempadr < opendadr) { + /* Flush L1 Data cache line */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_clean_inval_dc_line_mva_poc(tempadr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); + Reg = tempadr; } +#endif + tempadr += cacheline; + } + /* Wait for L1 cache clean and invalidation to complete */ + dsb(); + +#ifndef USE_AMP + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + while ((u32)adr < opendadr) { + /* Flush L2 cache line */ + *L2CCOffset = adr; + Xil_L2CacheSync(); + adr += cacheline; + } + Xil_L2WriteDebugCtrl(0x0U); +#endif + } + mtcpsr(currmask); +} +/****************************************************************************/ +/** +* @brief Store a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). +* +* @param adr: 32bit address of the data to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_DCacheStoreLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + Xil_L1DCacheStoreLine(adr); +#ifndef USE_AMP + Xil_L2CacheStoreLine(adr); +#endif + mtcpsr(currmask); +} + +/***************************************************************************/ +/** +* @brief Enable the instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheEnable(void) +{ + Xil_L1ICacheEnable(); +#ifndef USE_AMP + Xil_L2CacheEnable(); +#endif +} + +/***************************************************************************/ +/** +* @brief Disable the instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheDisable(void) +{ +#ifndef USE_AMP + Xil_L2CacheDisable(); +#endif + Xil_L1ICacheDisable(); +} + + +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheInvalidate(void) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidate(); +#endif + Xil_L1ICacheInvalidate(); + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate an instruction cache line. If the instruction specified +* by the address is cached by the instruction cache, the cacheline +* containing that instruction is invalidated. +* +* @param adr: 32bit address of the instruction to be invalidated. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_ICacheInvalidateLine(u32 adr) +{ + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); +#ifndef USE_AMP + Xil_L2CacheInvalidateLine(adr); +#endif + Xil_L1ICacheInvalidateLine(adr); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the instructions specified by the address range are cached by +* the instrunction cache, the cachelines containing those +* instructions are invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { +#ifndef USE_AMP + /* Invalidate L2 cache line */ + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); +#endif + + /* Invalidate L1 I-cache line */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_ic_line_mva_pou(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + /* Wait for L1 I cache invalidation to complete */ + dsb(); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Enable the level 1 Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { + return; + } + + /* clean and invalidate the Data cache */ + Xil_L1DCacheInvalidate(); + + /* enable the Data cache */ + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/***************************************************************************/ +/** +* @brief Disable the level 1 Data cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheDisable(void) +{ + register u32 CtrlReg; + + /* clean and invalidate the Data cache */ + Xil_L1DCacheFlush(); + +#ifdef __GNUC__ + /* disable the Data cache */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 1 Data cache. +* +* @return None. +* +* @note In Cortex A9, there is no cp instruction for invalidating +* the whole D-cache. This function invalidates each line by +* set/way. +* +****************************************************************************/ +void Xil_L1DCacheInvalidate(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way, WayIndex, Set, SetIndex, NumSet; + u32 currmask; + +#ifdef __GNUC__ + u32 stack_start,stack_end,stack_size; + register u32 CtrlReg; +#endif + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + +#ifdef __GNUC__ + stack_end = (u32)&_stack_end; + stack_start = (u32)&__undef_stack; + stack_size=stack_start-stack_end; + + /* Check for the cache status. If cache is enabled, then only + * flush stack memory to save return address. If cache is disabled, + * don't flush anything as it might result in flushing stale date into + * memory which is undesirable. + * */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { + Xil_DCacheFlushRange(stack_end, stack_size); + } +#endif + +#ifdef __GNUC__ + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); + CsidReg = Reg; } +#endif + /* Determine Cache Size */ + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x07U) + 4U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + + /* Invalidate by Set/Way */ +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_dc_line_sw(C7Reg); +#else + /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */ + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_SW); + Reg = C7Reg; } +#endif + Set += (0x00000001U << LineSize); + } + Set=0U; + Way += 0x40000000U; + } + + /* Wait for L1 invalidate to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Invalidate a level 1 Data cache line. If the byte specified by the +* address (Addr) is cached by the Data cache, the cacheline +* containing that byte is invalidated. If the cacheline is modified +* (dirty), the modified contents are lost and are NOT written to +* system memory before the line is invalidated. +* +* @param adr: 32bit address of the data to be invalidated. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheInvalidateLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 1 Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If the +* cachelines are modified (dirty), the modified contents are lost and +* NOT written to the system memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_dc_line_mva_poc(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + + /* Wait for L1 cache invalidation to complete */ + dsb(); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the level 1 Data cache. +* +* @return None. +* +* @note In Cortex A9, there is no cp instruction for flushing +* the whole D-cache. Need to flush each line. +* +****************************************************************************/ +void Xil_L1DCacheFlush(void) +{ + register u32 CsidReg, C7Reg; + u32 CacheSize, LineSize, NumWays; + u32 Way; + u32 WayIndex, Set, SetIndex, NumSet; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + +#ifdef __GNUC__ + CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID); + CsidReg = Reg; } +#endif + + /* Determine Cache Size */ + + CacheSize = (CsidReg >> 13U) & 0x1FFU; + CacheSize +=1U; + CacheSize *=128U; /* to get number of bytes */ + + /* Number of Ways */ + NumWays = (CsidReg & 0x3ffU) >> 3U; + NumWays += 1U; + + /* Get the cacheline size, way size, index size from csidr */ + LineSize = (CsidReg & 0x07U) + 4U; + + NumSet = CacheSize/NumWays; + NumSet /= (0x00000001U << LineSize); + + Way = 0U; + Set = 0U; + + /* Invalidate all the cachelines */ + for (WayIndex =0U; WayIndex < NumWays; WayIndex++) { + for (SetIndex =0U; SetIndex < NumSet; SetIndex++) { + C7Reg = Way | Set; + /* Flush by Set/Way */ + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_clean_inval_dc_line_sw(C7Reg); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW); + Reg = C7Reg; } +#endif + Set += (0x00000001U << LineSize); + } + Set = 0U; + Way += 0x40000000U; + } + + /* Wait for L1 flush to complete */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush a level 1 Data cache line. If the byte specified by the +* address (adr) is cached by the Data cache, the cacheline containing +* that byte is invalidated. If the cacheline is modified (dirty), the +* entire contents of the cacheline are written to system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data to be flushed. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheFlushLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 flush to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Flush the level 1 Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), they are written to system memory +* before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L1DCacheFlushRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + + /* Wait for L1 cache clean and invalidation to complete */ + dsb(); + } + + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Store a level 1 Data cache line. If the byte specified by the +* address (adr) is cached by the Data cache and the cacheline is +* modified (dirty), the entire contents of the cacheline are written +* to system memory. After the store completes, the cacheline is +* marked as unmodified (not dirty). +* +* @param adr: Address to be stored. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1DCacheStoreLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU))); + + /* Wait for L1 store to complete */ + dsb(); +} + + +/****************************************************************************/ +/** +* @brief Enable the level 1 instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheEnable(void) +{ + register u32 CtrlReg; + + /* enable caches only if they are disabled */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) { + return; + } + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* enable the instruction cache */ + CtrlReg |= (XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/****************************************************************************/ +/** +* @brief Disable level 1 the instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheDisable(void) +{ + register u32 CtrlReg; + + dsb(); + + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* disable the instruction cache */ +#ifdef __GNUC__ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#else + { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL); + CtrlReg = Reg; } +#endif + CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); + + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); +} + +/****************************************************************************/ +/** +* @brief Invalidate the entire level 1 instruction cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheInvalidate(void) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + /* invalidate the instruction cache */ + mtcp(XREG_CP15_INVAL_IC_POU, 0U); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate a level 1 instruction cache line. If the instruction +* specified by the address is cached by the instruction cache, the +* cacheline containing that instruction is invalidated. +* +* @param adr: 32bit address of the instruction to be invalidated. +* +* @return None. +* +* @note The bottom 5 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L1ICacheInvalidateLine(u32 adr) +{ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU))); + + /* Wait for L1 invalidate to complete */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 1 instruction cache for the given address +* range. If the instrucions specified by the address range are cached +* by the instruction cache, the cacheline containing those bytes are +* invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + while (LocalAddr < end) { + +#if defined (__GNUC__) || defined (__ICCARM__) + asm_cp15_inval_ic_line_mva_pou(LocalAddr); +#else + { volatile register u32 Reg + __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); + Reg = LocalAddr; } +#endif + LocalAddr += cacheline; + } + + /* Wait for L1 cache invalidation to complete */ + dsb(); + } + + mtcpsr(currmask); +} + +#ifndef USE_AMP +/****************************************************************************/ +/** +* @brief Enable the L2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheEnable(void) +{ + register u32 L2CCReg; + + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + + /* only enable if L2CC is currently disabled */ + if ((L2CCReg & 0x01U) == 0U) { + /* set up the way size and latencies */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_AUX_CNTRL_OFFSET); + L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK; + L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK; + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET, + L2CCReg); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET, + XPS_L2CC_TAG_RAM_DEFAULT_MASK); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET, + XPS_L2CC_DATA_RAM_DEFAULT_MASK); + + /* Clear the pending interrupts */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_ISR_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg); + + Xil_L2CacheInvalidate(); + /* Enable the L2CC */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + + XPS_L2CC_CNTRL_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, + (L2CCReg | (0x01U))); + + Xil_L2CacheSync(); + /* synchronize the processor */ + dsb(); + + } +} + +/****************************************************************************/ +/** +* @brief Disable the L2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheDisable(void) +{ + register u32 L2CCReg; + + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + + if((L2CCReg & 0x1U) != 0U) { + + /* Clean and Invalidate L2 Cache */ + Xil_L2CacheFlush(); + + /* Disable the L2CC */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, + (L2CCReg & (~0x01U))); + /* Wait for the cache operations to complete */ + + dsb(); + } +} + +/*****************************************************************************/ +/** +* @brief Invalidate the entire level 2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheInvalidate(void) +{ + #ifdef __GNUC__ + u32 stack_start,stack_end,stack_size; + register u32 L2CCReg; + stack_end = (u32)&_stack_end; + stack_start = (u32)&__undef_stack; + stack_size=stack_start-stack_end; + + /* Check for the cache status. If cache is enabled, then only + * flush stack memory to save return address. If cache is disabled, + * don't flush anything as it might result in flushing stale date into + * memory which is undesirable. + */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + if ((L2CCReg & 0x01U) != 0U) { + /*Flush stack memory to save return address*/ + Xil_DCacheFlushRange(stack_end, stack_size); + } + + #endif + u32 ResultDCache; + /* Invalidate the caches */ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET, + 0x0000FFFFU); + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + while(ResultDCache != (u32)0U) { + ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET) + & 0x0000FFFFU; + } + + /* Wait for the invalidate to complete */ + Xil_L2CacheSync(); + + /* synchronize the processor */ + dsb(); +} + +/*****************************************************************************/ +/** +* @brief Invalidate a level 2 cache line. If the byte specified by the +* address (adr) is cached by the Data cache, the cacheline containing +* that byte is invalidated. If the cacheline is modified (dirty), +* the modified contents are lost and are NOT written to system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data/instruction to be invalidated. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheInvalidateLine(u32 adr) +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr); + /* synchronize the processor */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Invalidate the level 2 cache for the given address range. +* If the bytes specified by the address range are cached by the L2 +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), the modified contents are lost and +* are NOT written to system memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheInvalidateRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INVLD_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + } + + /* synchronize the processor */ + dsb(); + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Flush the entire level 2 cache. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheFlush(void) +{ + u32 ResultL2Cache; + + /* Flush the caches */ + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET, + 0x0000FFFFU); + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + + while(ResultL2Cache != (u32)0U) { + ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET) + & 0x0000FFFFU; + } + + Xil_L2CacheSync(); + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + + /* synchronize the processor */ + dsb(); +} + +/****************************************************************************/ +/** +* @brief Flush a level 2 cache line. If the byte specified by the address +* (adr) is cached by the L2 cache, the cacheline containing that +* byte is invalidated. If the cacheline is modified (dirty), the +* entire contents of the cacheline are written to system memory +* before the line is invalidated. +* +* @param adr: 32bit address of the data/instruction to be flushed. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheFlushLine(u32 adr) +{ +#ifdef CONFIG_PL310_ERRATA_588369 + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr); +#else + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr); +#endif + Xil_L2CacheSync(); +} + +/****************************************************************************/ +/** +* @brief Flush the level 2 cache for the given address range. +* If the bytes specified by the address range are cached by the L2 +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), they are written to the system +* memory before the lines are invalidated. +* +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. +* +* @return None. +* +****************************************************************************/ +void Xil_L2CacheFlushRange(u32 adr, u32 len) +{ + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR + + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); + + u32 currmask; + + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); + + /* Disable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x3U); + + while (LocalAddr < end) { + *L2CCOffset = LocalAddr; + Xil_L2CacheSync(); + LocalAddr += cacheline; + } + + /* Enable Write-back and line fills */ + Xil_L2WriteDebugCtrl(0x0U); + } + mtcpsr(currmask); +} + +/****************************************************************************/ +/** +* @brief Store a level 2 cache line. If the byte specified by the address +* (adr) is cached by the L2 cache and the cacheline is modified +* (dirty), the entire contents of the cacheline are written to +* system memory. After the store completes, the cacheline is marked +* as unmodified (not dirty). +* +* @param adr: 32bit address of the data/instruction to be stored. +* +* @return None. +* +* @note The bottom 4 bits are set to 0, forced by architecture. +* +****************************************************************************/ +void Xil_L2CacheStoreLine(u32 adr) +{ + Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); + Xil_L2CacheSync(); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cache_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_l.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cache_l.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_l.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cache_vxworks.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_vxworks.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cache_vxworks.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cache_vxworks.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c new file mode 100644 index 0000000..421de02 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.c @@ -0,0 +1,256 @@ +/****************************************************************************** +* Copyright (C) 2020 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.c +* +* The xil_clocking.c file contains clocking related functions and macros. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  02/06/20 First release of clocking
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 9.0 ml  03/03/23 Add description to fix doxygen warnings.
+*
    +* +******************************************************************************/ + +#include "xil_clocking.h" +/************************** Variable Definitions *****************************/ + +#if (defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR)) && defined (XCLOCKING) +XClock ClockInstance; /* Instance of clock Controller */ +XClockPs_Config *ConfigPtr; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This API initialize the Clock controller driver. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockInit(void) +{ + XStatus Status = XST_FAILURE; + + /* Lookup clock configurations */ +#ifndef SDT + ConfigPtr = XClock_LookupConfig(XPAR_XCLOCKPS_DEVICE_ID); +#else + ConfigPtr = XClock_LookupConfig(XPAR_PSU_CRL_APB_BASEADDR); +#endif + + /* Initialize the Clock controller driver */ + Status = XClock_CfgInitialize(&ClockInstance, ConfigPtr); + return Status; +} + +/*****************************************************************************/ +/** +* +* This function enables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockEnable(XClock_OutputClks ClockId) +{ + + XStatus Status = XST_FAILURE; + + Status = XClock_EnableClock(ClockId); + return Status; +} + +/*****************************************************************************/ +/** +* +* This function disables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockDisable(XClock_OutputClks ClockId) +{ + XStatus Status = XST_FAILURE; + + Status = XClock_DisableClock(ClockId); + return Status; +} + +/*****************************************************************************/ +/** +* +* This function is used to fetch rate of output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is a pointer to variable storing rate. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate) +{ + XStatus Status = XST_FAILURE; + + Xil_AssertNonvoid(Rate != NULL); + + Status = XClock_GetRate(ClockId, Rate); + if (XST_SUCCESS == Status) { + xdbg_printf(XDBG_DEBUG_GENERAL, "Operating rate = %lx\n",*Rate); + } else { + xdbg_printf(XDBG_DEBUG_ERROR, "Failed: Fetching rate\r\n"); + } + return Status; +} +/*****************************************************************************/ +/** +* +* This function is used to set rate for output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is the clock rate to set. +* @param SetRate is a pointer to variable holding rate that is set. +* +* @return Status to indicate success/failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, + XClockRate *SetRate) +{ + XStatus Status = XST_FAILURE; + + Xil_AssertNonvoid(SetRate != NULL); + + if (Rate == 0) { + return XST_FAILURE; + } + Status = XClock_SetRate(ClockId, Rate, SetRate); + if (XST_SUCCESS != Status) { + xdbg_printf(XDBG_DEBUG_ERROR, "Failed Setting rate\n"); + } + return Status; +} + +#else + +/*****************************************************************************/ +/** +* +* This function is used to fetch rate of output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is pointer to variable storing rate. +* +* @return XST_FAILURE to indicate failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate) +{ + (void) ClockId; + (void) Rate; + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* +* This function is used to set rate for output clock. +* +* @param ClockId is the identifier for output clock. +* @param Rate is the clock rate to set. +* @param SetRate is a pointer to variable holding rate that is set. +* +* @return XST_FAILURE to indicate failure. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, + XClockRate *SetRate) { + (void) ClockId; + (void) Rate; + (void) SetRate; + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* +* This API initialize the Clock controller driver. +* +* @return XST_SUCCESS to indicate success. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockInit(void) +{ + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function enables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return XST_SUCCESS to indicate success. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockEnable(XClock_OutputClks ClockId) +{ + (void) ClockId; + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables output clock based on clock ID. +* +* @param ClockId is the identifier for output clock. +* +* @return XST_SUCCESS to indicate success. +* +* @note None. +* +******************************************************************************/ +XStatus Xil_ClockDisable(XClock_OutputClks ClockId) +{ + (void) ClockId; + return XST_SUCCESS; +} + +#endif /* XCLOCKING */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h new file mode 100644 index 0000000..d40a6f7 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_clocking.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_clocking.h +* +* The xil_clocking.h file contains clocking related functions and macros. +* certain conditions. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  12/11/19 First release
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 7.7 sk  01/10/22 Add function prototype for Xil_ClockGetRate to fix
+* 		   misra_c_2012_rule_8_4 violation.
+* 9.0 ml  03/03/23 Added description to fix doxygen warnings.
+*
    +* +******************************************************************************/ + +#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */ +#define XIL_CLOCKING_H /**< by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xdebug.h" +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xparameters.h" +#include "xstatus.h" +#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR) +#include "xclockps.h" +#else +typedef u32 XClock_OutputClks; +typedef u64 XClockRate; +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + + +XStatus Xil_ClockDisable(XClock_OutputClks ClockId); +XStatus Xil_ClockEnable(XClock_OutputClks ClockId); +XStatus Xil_ClockInit(void); +XStatus Xil_ClockGet(void); +XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate); +XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cryptoalginfo.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cryptoalginfo.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_cryptoalginfo.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_cryptoalginfo.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_errata.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_errata.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_errata.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_errata.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.c new file mode 100644 index 0000000..e08ecb9 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.c @@ -0,0 +1,863 @@ +/****************************************************************************** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xil_exception.c +* +* This file contains low-level driver functions for the Cortex A53,A9,R5 exception +* Handler. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
+* 6.7   mna      26/04/18 Add an API to obtain a corresponding
+*                         Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7  asa       18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+* 7.0  mus       07/03/19 Tweak Xil_ExceptionRegisterHandler and
+*                         Xil_GetExceptionRegisterHandler to support legacy
+*                         examples for Cortexa72 EL3 exception level.
+* 7.3  mus       07/27/20 Updated Xil_ExceptionRegisterHandler and
+*                         Xil_GetExceptionRegisterHandler to ignore
+*                         Exception_id, only if its pointing to IRQ.
+*                         It fixes CR#1069524
+* 8.0  mus       02/24/22 Updated Xil_ExceptionRegisterHandler and
+*                         Xil_GetExceptionRegisterHandler to support legacy
+*                         driver examples for CortexR52. This is needed, as
+*                         by default scugic driver configures interrupts as
+*                         group0, and CortexR52 GIC triggers FIQ for group0
+*                         interrupts.
+* 8.0  sk	 03/02/22 Move XExc_VectorTableEntry structure to header
+* 			  file to fix misra_c_2012_rule_5_6 violation.
+* 8.1  asa       02/12/23 Updated data abort and prefetch abort fault
+*                         status reporting for ARMv7.
+*			  Updated Sync and SError fault status reporting
+*			  for ARMv8.
+* 9.0  ml        03/03/23 Add description to fix doxygen warnings.
+* 9.0  ml	 14/04/23 Add comment to default case in switch statement to fix
+*                         misra-c violation.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xdebug.h" +#include "bspconfig.h" +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ +#ifdef DEBUG +#if defined (__aarch64__) +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u64 FaultStatus); +static void DecodeSyncAbortWithIss(u32 Type, u64 IssVal); +static void DecodeSErrorWithIss(u64 IssVal); +#else +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u32 FaultStatus); +#endif +#endif +/************************** Function Prototypes *****************************/ +static void Xil_ExceptionNullHandler(void *Data); +#if defined (__aarch64__) +static void Xil_SyncErrorHandler(void *CallBackRef); +static void Xil_SErrorHandler(void *CallBackRef); +#else +static void Xil_DataAbortHandler(void *CallBackRef); +static void Xil_PrefetchAbortHandler(void *CallBackRef); +static void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif +/************************** Variable Definitions *****************************/ +/* + * Exception vector table to store handlers for each exception vector. + */ +#if defined (__aarch64__) +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_SyncErrorHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_SErrorHandler, NULL}, + +}; +#else +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_UndefinedExceptionHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_PrefetchAbortHandler, NULL}, + {Xil_DataAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, +}; +#endif /* #if defined (__aarch64__) */ +#if !defined (__aarch64__) +u32 DataAbortAddr; /* Address of instruction causing data abort */ +u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ +u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined + exception */ +#endif + +/*****************************************************************************/ + +/****************************************************************************/ +/** +* +* This function is a stub Handler that is the default Handler that gets called +* if the application has not setup a Handler for a specific exception. The +* function interface has to match the interface specified for a Handler even +* though none of the arguments are used. +* +* @param Data is unused by this function. +* +* @return None. +* +*****************************************************************************/ +static void Xil_ExceptionNullHandler(void *Data) +{ + (void) Data; +DieLoop: goto DieLoop; +} + +/****************************************************************************/ +/** +* @brief The function is a common API used to initialize exception handlers +* across all supported arm processors. For ARM Cortex-A53, Cortex-R5, +* and Cortex-A9, the exception handlers are being initialized +* statically and this function does not do anything. +* However, it is still present to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to +* initialize exception handlers). +* +* @return None. +* +*****************************************************************************/ +void Xil_ExceptionInit(void) +{ + return; +} + +/*****************************************************************************/ +/** +* @brief Register a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. +* +* @param Exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +****************************************************************************/ +void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data) +{ +#if (defined (versal) && !defined(ARMR5) && EL3) + if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id ) + { + /* + * Cortexa72 processor in versal is coupled with GIC-500, and + * GIC-500 supports only FIQ at EL3. Hence, tweaking this API + * to act on IRQ, if Exception_id is pointing to IRQ + */ + Exception_id = XIL_EXCEPTION_ID_FIQ_INT; + } +#endif + XExc_VectorTable[Exception_id].Handler = Handler; + XExc_VectorTable[Exception_id].Data = Data; +} + +/*****************************************************************************/ +/** +* @brief Get a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. +* +* @param Exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* @param Handler to the Handler for that exception. +* @param Data is a reference to Data that will be passed to the +* Handler when it gets called. +* +* @return None. +* +****************************************************************************/ +void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, + void **Data) +{ +#if (defined (versal) && !defined(ARMR5) && EL3) + if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id ) + { + /* + * Cortexa72 processor in versal is coupled with GIC-500, and + * GIC-500 supports only FIQ at EL3. Hence, tweaking this API + * to act on IRQ, if Exception_id is pointing to IRQ + */ + + Exception_id = XIL_EXCEPTION_ID_FIQ_INT; + } +#endif + + *Handler = XExc_VectorTable[Exception_id].Handler; + *Data = XExc_VectorTable[Exception_id].Data; +} + +/*****************************************************************************/ +/** +* +* @brief Removes the Handler for a specific exception id. The stub Handler +* is then registered for this exception id. +* +* @param Exception_id contains the ID of the exception source and should +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* +* @return None. +* +****************************************************************************/ +void Xil_ExceptionRemoveHandler(u32 Exception_id) +{ + Xil_ExceptionRegisterHandler(Exception_id, + Xil_ExceptionNullHandler, + NULL); +} + +#if defined (__aarch64__) +/*****************************************************************************/ +/** +* +* Default Synchronous abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @return None. +* +****************************************************************************/ + +static void Xil_SyncErrorHandler(void *CallBackRef){ + (void) CallBackRef; + +#ifdef __GNUC__ +#ifdef DEBUG + volatile u64 EsrVal; + volatile u64 ElrVal; + volatile u64 FarVal; + u32 Far_Status; +#if (EL3 == 1) + EsrVal = mfesrel3(); + ElrVal = mfelrel3(); +#else + EsrVal = mfesrel1(); + ElrVal = mfelrel1(); +#endif + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + Far_Status = NotifyFaultStatusDetails(ARMV8_SYNC_ERROR, EsrVal); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Instruction causing Sync error is: 0x%lx\n", ElrVal); + if (Far_Status) { +#if (EL3 == 1) + FarVal = mffarel3(); +#else + FarVal = mffarel1(); +#endif + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Memory whose access caused the Sync Error is: 0x%lx\n", + FarVal); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#endif +#else + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous Error \n"); +#endif + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default SError abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @return None. +* +****************************************************************************/ +static void Xil_SErrorHandler(void *CallBackRef){ + (void) CallBackRef; + +#ifdef __GNUC__ +#ifdef DEBUG + volatile u64 EsrVal; +#if (EL3 == 1) + EsrVal = mfesrel3(); +#else + EsrVal = mfesrel1(); +#endif + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + (void)NotifyFaultStatusDetails(ARMV8_SERROR, EsrVal); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#endif +#else + xdbg_printf(XDBG_DEBUG_ERROR, "Asynchronous SError \n"); +#endif + + while(1) { + ; + } +} + +#if defined (__aarch64__) +#ifdef DEBUG +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u64 EsrVal) +{ + u32 Far_Status = 0x0; + u64 EcVal = ARMV8_EXTRACT_ESR_EC(EsrVal); + u64 IssVal = ARMV8_EXTRACT_ESR_ISS(EsrVal); + + if (Fault_Type == ARMV8_SYNC_ERROR) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Sync Error with ESR = 0x%lx, EC = 0x%lx, ISS = 0x%lx \n", + EsrVal, EcVal, IssVal); + + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Type based on Exception Class (EC val) : "); + switch (EcVal) { + case ARMV8_ESR_EC_UNKNOWN_ERR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Unknown Error\n"); + break; + case ARMV8_ESR_EC_FP_ASIMD: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access to ASIMD or floating point functionality based " + "on CPACR_EL1 FPEN configuration\n"); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_DATA_ABORT_LOWER: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Data Abort From a Lower " + "Exception Level\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_DATA_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_DATA_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Data Abort \n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_DATA_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_INS_ABORT_LOWER: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Instruction Abort Taken From a Lower Exception Level\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_INS_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_INS_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Instruction Abort\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details based on Instruction Specific Syndrome " + "(ISS val) : "); + DecodeSyncAbortWithIss(ARMV8_ESR_EC_INS_ABORT, IssVal); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_PC_ALIGNMENT_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "PC Alignment Fault\n"); + Far_Status = ARMV8_FAR_VALUE_VALID; + break; + case ARMV8_ESR_EC_SP_ALIGNMENT_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "SP Alignment Fault\n"); + break; + case ARMV8_ESR_ILL_EXECUTION_STATE: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Illegal Execution State\n"); + break; + default: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Other error\n"); + break; + } + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Asynchronous SError with ESR = 0x%lx, EC = 0x%lx, ISS = 0x%lx \n", + EsrVal, EcVal, IssVal); + + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Exception Details (based on Instruction Specific Syndrome " + "(ISS val) : "); + + DecodeSErrorWithIss(IssVal); + } + return Far_Status; +} + +static void DecodeSyncAbortWithIss(u32 Type, u64 IssVal) +{ + u64 FscVal; + + FscVal = IssVal & ARMV8_ESR_ISS_FSC; + switch (FscVal) { + case ARMV8_LEVEL_0_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_ADDR_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address Size fault at Level 3 translation \n"); + break; + case ARMV8_LEVEL_0_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_TRANS_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Translation fault at Level 3 translation \n"); + break; + case ARMV8_LEVEL_0_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_ACCS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Access Flag Fault at Level 3 translation \n"); + break; + case ARMV8_LEVEL_0_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 0 translation \n"); + break; + case ARMV8_LEVEL_1_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 1 translation \n"); + break; + case ARMV8_LEVEL_2_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 2 translation \n"); + break; + case ARMV8_LEVEL_3_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Permission Fault at Level 3 translation \n"); + break; + + case ARMV8_SYNC_EXT_ABORT_NOT_ON_TTW: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort, not on translation table walk or " + "hw update of translation table \n"); + break; + case ARMV8_LEVEL_0_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 0 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_LEVEL_1_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 1 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_LEVEL_2_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 2 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_LEVEL_3_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort at Level 3 translation on " + "translation table walk or hw update of translation table \n"); + break; + case ARMV8_SYNC_PAR_OR_ECC_ERROR_NOT_ON_TTW: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "not on translation table walk \n"); + break; + case ARMV8_LEVEL_0_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 0 translation \n"); + break; + case ARMV8_LEVEL_1_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 1 translation \n"); + break; + case ARMV8_LEVEL_2_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 2 translation \n"); + break; + case ARMV8_LEVEL_3_SYNC_PAR_OR_ECC_ERROR: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity or ECC error for memory access, " + "for level 3 translation \n"); + break; + case ARMV8_ALIGNMENT_FAULT: + if (Type == ARMV8_ESR_EC_DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Alignment Fault \n"); + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Unknown fault \n"); + } + break; + case ARMV8_TLB_CONFLICT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "TLB Conflict Abort \n"); + break; + default: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Unknown fault \n"); + } + + if (Type == ARMV8_ESR_EC_DATA_ABORT) { + if (IssVal & ARMV8_ESR_ISS_WNR_MASK) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data abort caused by instruction writing to a memory location.\n "); + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data abort caused by instruction reading from a memory location.\n"); + } + if (IssVal & ARMV8_ESR_ISS_CM_MASK) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data abort caused by a cache maintenance instruction \n"); + } + } +} + +static void DecodeSErrorWithIss(u64 IssVal) +{ + u64 FscVal; + u64 MaskVal; + + FscVal = IssVal & ARMV8_ESR_ISS_FSC; + if (FscVal == ARMV8_ASYNC_SEEROR_INTERRUPT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "SError caused by Asynchronous Serror Interrupt \n "); + + MaskVal = IssVal & ARMV8_ESR_ISS_AET_MASK; + switch (MaskVal) { + case ARMV8_ESR_ISS_AET_UC: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Uncontainable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_UEU: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Unrecoverable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_UEO: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Restartable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_UER: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Recoverable Error State \n "); + break; + case ARMV8_ESR_ISS_AET_CE: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Corrected Error State \n "); + break; + default: + break; + + } + + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "SError caused by uncategorized error \n "); + } +} + + +#endif /* #ifdef DEBUG */ +#endif /* #if defined (__aarch64__) */ + +#else /* #if defined (__aarch64__) */ +/*****************************************************************************/ +/** +* +* Default Data abort handler which prints data fault status register through +* which information about data fault can be acquired +* +* @return None. +* +****************************************************************************/ + +static void Xil_DataAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + u32 FaultStatus; +#ifdef __GNUC__ + u32 DataAbortMemAddr; + u32 DfarStatus; +#endif + +#ifdef __GNUC__ + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); +#else + { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); + FaultStatus = Reg; } +#endif /* #ifdef __GNUC__ */ + +#ifdef __GNUC__ + DfarStatus = NotifyFaultStatusDetails(DATA_ABORT, FaultStatus); + if (DfarStatus) { + DataAbortMemAddr = mfcp(XREG_CP15_DATA_FAULT_ADDRESS); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Instruction causing data abort is: 0x%lx\n", + DataAbortAddr); + if (DfarStatus) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Memory whose access caused the data abort is: 0x%lx\n", + DataAbortMemAddr); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#else + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr); +#endif +#endif /* #ifdef DEBUG */ + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default Prefetch abort handler which prints prefetch fault status register through +* which information about instruction prefetch fault can be acquired +* +* @return None. +* +****************************************************************************/ +static void Xil_PrefetchAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + u32 FaultStatus; +#ifdef __GNUC__ + u32 IfarStatus; +#endif + +#ifdef __GNUC__ + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); + FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); +#else + { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); + FaultStatus = Reg; } +#endif /* #ifdef __GNUC__ */ + +#ifdef __GNUC__ + IfarStatus = NotifyFaultStatusDetails(INS_PREFETCH_ABORT, FaultStatus); + if (IfarStatus) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of Instruction Causing Prefetch Abort is: 0x%lx\n", + PrefetchAbortAddr); + } + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "-------------------------------------------------------------\n"); +#else + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr); +#endif +#endif /* #ifdef DEBUG */ + while(1) { + ; + } +} + +/*****************************************************************************/ +/** +* +* Default undefined exception handler which prints address of the undefined +* instruction if debug prints are enabled +* +* @return None. +* +****************************************************************************/ +static void Xil_UndefinedExceptionHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Address of the undefined instruction 0x%lx\n", + UndefinedExceptionAddr); +#endif + while(1) { + ; + } +} + +#ifdef DEBUG +static u32 NotifyFaultStatusDetails(u32 Fault_Type, u32 FaultStatus) +{ + u32 Far_Status = 0x0; + + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Data Abort with Fault Status Register (DFSR) = 0x%lx\n", + FaultStatus); + } else { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Instruction Prefetch Abort with Fault Status Register (IFSR) = 0x%lx\n", + FaultStatus); + } + + /* Extract bit 10 and bits 3:0 to form the 5 bit error identifier */ + + FaultStatus = EXTRACT_BITS_10_AND_3_TO_0(FaultStatus); + + switch (FaultStatus) { +#if defined(ARMR5) + case ARMV7_BACKGROUND_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Background Fault\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + case ARMV7_ALIGNMENT_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Alignment Fault\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; + case ARMV7_DEBUG_EVENT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Debug Event\n"); + break; +#if !defined(ARMR5) + case ARMV7_ACCESS_FLAG_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Debug Event\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; + case ARMV7_ICACHE_MAINTENANCE_FAULT: + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Fault on Instruction Cache Maintenance\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + } + break; + case ARMV7_TRANSLATION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Translation Fault\n"); + break; + case ARMV7_DOMAIN_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Domain Fault\n"); + break; + case ARMV7_SYNC_ABORT_TRANSTAB_WALK: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous External Abort on Translation Table Walk\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + case ARMV7_PERMISSION_FAULT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Permission Fault\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#if !defined(ARMR5) + case ARMV7_TLB_CONFLICT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "TLB Conflict Abort\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + case ARMV7_ASYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Asynchronous External Abort\n"); + break; + case ARMV7_SYNC_EXT_ABORT: + xdbg_exception_printf(XDBG_DEBUG_ERROR, "Synchronous External Abort\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; + case ARMV7_MEM_ACS_SYNC_PAR_ERR: + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity Error on Memory Access\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + } + break; + case ARMV7_MEM_ACS_ASYNC_PAR_ERR: + if (Fault_Type == DATA_ABORT) { + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Asynchronous Parity Error on Memory Access\n"); + } + break; +#if !defined(ARMR5) + case ARMV7_SYNCPAR_ERR_TRANSTAB_WALK: + xdbg_exception_printf(XDBG_DEBUG_ERROR, + "Synchronous Parity Error on Translation Table Walk\n"); + Far_Status = ARMV7_DFAR_VALUE_VALID; + break; +#endif + default: + /* if above cases doesn't match, then + default case will execute and terminate a statement sequence */ + break; + } + + return Far_Status; +} +#endif /* #ifdef DEBUG */ +#endif /* #if defined (__aarch64__) */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_exception.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_exception.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_exception.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_hal.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_hal.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_hal.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_hal.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_io.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_io.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_io.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_io.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_macroback.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_macroback.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_macroback.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_macroback.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.c new file mode 100644 index 0000000..44e7d9a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.c @@ -0,0 +1,70 @@ +/******************************************************************************/ +/** +* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_mem.c +* +* This file contains xil mem copy function to use in case of word aligned +* data copies. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+* 7.7	sk	 01/10/22 Update Xil_MemCpy functions variables typecast
+* 			  from int to s32 to fix misra_c_2012_directive_4_6
+* 			  violations.
+* 7.7	sk	 01/10/22 Include xil_mem.h header file to fix Xil_MemCpy
+* 			  prototype misra_c_2012_rule_8_4 violation.
+*
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_mem.h" + +/***************** Inline Functions Definitions ********************/ +/*****************************************************************************/ +/** +* @brief This function copies memory from once location to other. +* +* @param dst: pointer pointing to destination memory +* +* @param src: pointer pointing to source memory +* +* @param cnt: 32 bit length of bytes to be copied +* +*****************************************************************************/ +void Xil_MemCpy(void* dst, const void* src, u32 cnt) +{ + char *d = (char*)(void *)dst; + const char *s = src; + + while (cnt >= sizeof (s32)) { + *(s32*)d = *(s32*)s; + d += sizeof (s32); + s += sizeof (s32); + cnt -= sizeof (s32); + } + while (cnt >= sizeof (u16)) { + *(u16*)d = *(u16*)s; + d += sizeof (u16); + s += sizeof (u16); + cnt -= sizeof (u16); + } + while ((cnt) > 0U){ + *d = *s; + d += 1U; + s += 1U; + cnt -= 1U; + } +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_mem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_mem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.c new file mode 100644 index 0000000..10366fb --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.c @@ -0,0 +1,436 @@ +/****************************************************************************** +* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_misc_psreset_api.c +* +* This file contains the implementation of the reset sequence for various +* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset +* sequence provided to the interfaces is based on the provision in +* slcr reset functional block. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 5.4	pkp	  09/11/15 Change the description for XOcm_Remap function
+*
    +* +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_misc_psreset_api.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/*****************************************************************************/ +/** +* This function contains the implementation for ddr reset. +* +* +* @return N/A. +* +******************************************************************************/ +void XDdr_ResetHw(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert and deassert the ddr softreset bit */ + RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); + RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK); + Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for remapping the ocm memory region +* to postbootrom state. +* +* @return N/A. +* +******************************************************************************/ +void XOcm_Remap(void) +{ + u32 RegVal; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Map the ocm region to postbootrom state */ + RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); + RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL; + Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for SMC reset sequence +* +* @param BaseAddress of the interface +* +* @return N/A. +* +******************************************************************************/ +void XSmc_ResetHw(u32 BaseAddress) +{ + u32 RegVal; + + /* Clear the interuupts */ + RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); + RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK; + Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); + /* Clear the idle counter registers */ + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U); + Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U); + /* Update the ecc registers with reset values */ + Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, + XSMC_ECC_MEMCFG1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET, + XSMC_ECC_MEMCMD1_RESET_VAL); + Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET, + XSMC_ECC_MEMCMD2_RESET_VAL); + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr mio registers +* with reset values +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_MioWriteResetValues(void) +{ + u32 i; + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Update all the MIO registers with reset values */ + for (i=0U; i<=1U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + for (; i<=8U;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_02_RESET_VAL); + } + for (; i<=53U ;i++) + { + Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)), + XSLCR_MIO_PIN_00_RESET_VAL); + } + + +} + +/*****************************************************************************/ +/** +* This function contains the implementation for updating the slcr pll registers +* with reset values +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_PllWriteResetValues(void) +{ + + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + + /* update the pll control registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL); + /* update the pll config registers with reset values */ + Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL); + Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL); + /* update the clock control registers with reset values */ + Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL); + Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for disabling the level shifters +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_DisableLevelShifters(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Disable the level shifters */ + RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); + RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK); + Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); + +} +/*****************************************************************************/ +/** +* This function contains the implementation for OCM software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_OcmReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL); + Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for Ethernet software reset from +* the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_EmacPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL); + Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); +} + +/*****************************************************************************/ +/** +* This function contains the implementation for USB software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_UsbPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL); + Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for QSPI software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_QspiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SPI software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_SpiPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL); + Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for i2c software reset from the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_I2cPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL); + Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for UART software reset from the +* slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_UartPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL); + Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for CAN software reset from slcr +* registers +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_CanPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL); + Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for SMC software reset from the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_SmcPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL); + Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for DMA controller software reset +* from the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_DmaPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL); + Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); +} +/*****************************************************************************/ +/** +* This function contains the implementation for Gpio AMBA software reset from +* the slcr +* +* @return N/A. +* +******************************************************************************/ +void XSlcr_GpioPsReset(void) +{ + u32 RegVal; + /* Unlock the slcr register access lock */ + Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); + /* Assert the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); + /* Release the reset */ + RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); + RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL); + Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_misc_psreset_api.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_misc_psreset_api.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_misc_psreset_api.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.c new file mode 100644 index 0000000..9e15c6a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.c @@ -0,0 +1,208 @@ +/****************************************************************************** +* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xil_mmu.c +* +* This file provides APIs for enabling/disabling MMU and setting the memory +* attributes for sections, in the MMU translation table. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
+*                     It fixes CR#1008309.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mmu.h" +#include "xil_errata.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024 /**< Each TTB descriptor + * covers a 1MB region */ +#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL)) +/**< Mask off lower bits of addr */ + +/************************** Variable Definitions *****************************/ + +extern u32 MMUTable; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* @brief This function sets the memory attributes for a section covering 1MB +* of memory in the translation table. +* +* @param Addr 32-bit address for which memory attributes need to be set. +* @param attrib Attribute for the given memory region. xil_mmu.h contains +* definitions of commonly used memory attributes which can be +* utilized for this function. +* +* +* @return None. +* +* @note The MMU or D-cache does not need to be disabled before changing a +* translation table entry. +* +******************************************************************************/ +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib) +{ + u32 *ptr; + u32 section; + + section = Addr / 0x100000U; + ptr = &MMUTable; + ptr += section; + if(ptr != NULL) { + *ptr = (Addr & 0xFFF00000U) | attrib; + } + + Xil_DCacheFlush(); + + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + /* Invalidate all branch predictors */ + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); + + dsb(); /* ensure completion of the BP and TLB invalidation */ + isb(); /* synchronize context on this processor */ +} + +/*****************************************************************************/ +/** +* @brief Enable MMU for cortex A9 processor. This function invalidates the +* instruction and data caches, and then enables MMU. +* +* @return None. +* +******************************************************************************/ +void Xil_EnableMMU(void) +{ + u32 Reg; + Xil_DCacheInvalidate(); + Xil_ICacheInvalidate(); + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, Reg); +#else + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + Reg = Cp15Reg; } +#endif + Reg |= (u32)0x05U; + mtcp(XREG_CP15_SYS_CONTROL, Reg); + + dsb(); + isb(); +} + +/*****************************************************************************/ +/** +* @brief Disable MMU for Cortex A9 processors. This function invalidates +* the TLBs, Branch Predictor Array and flushed the D Caches before +* disabling the MMU. +* +* @return None. +* +* @note When the MMU is disabled, all the memory accesses are treated as +* strongly ordered. +******************************************************************************/ +void Xil_DisableMMU(void) +{ + u32 Reg; + + mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U); + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U); + Xil_DCacheFlush(); + +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, Reg); +#else + { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL); + Reg = Cp15Reg; } +#endif + Reg &= (u32)(~0x05U); +#ifdef CONFIG_ARM_ERRATA_794073 + /* Disable Branch Prediction */ + Reg &= (u32)(~0x800U); +#endif + mtcp(XREG_CP15_SYS_CONTROL, Reg); +} + +/*****************************************************************************/ +/** +* @brief Memory mapping for Cortex A9 processor. +* +* @param PhysAddr is physical address. +* @param size is size of region. +* @param flags is flags used to set translation table. +* +* @return Pointer to virtual address. +* +* @note: Previously this was implemented in libmetal. Move to embeddedsw as this +* functionality is specific to A9 processor. +* +******************************************************************************/ +void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags) +{ + u32 Sectionoffset; + u32 Ttbaddr; + + if (!flags) + return (void*)PhysAddr; + + /* Ensure alignment on a section boundary */ + PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK; + + /* Loop through entire region of memory (one MMU section at a time). + Each section requires a TTB entry. */ + for (Sectionoffset = 0; Sectionoffset < size; + Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) { + /* Calculate translation table entry for this memory section */ + Ttbaddr = (PhysAddr + Sectionoffset); + + /* Write translation table entry value to entry address */ + Xil_SetTlbAttributes(Ttbaddr, flags); + } + return (void*)PhysAddr; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_mmu.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_mmu.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_mmu.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.c new file mode 100644 index 0000000..c116a15 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.c @@ -0,0 +1,461 @@ +/****************************************************************************** +* Copyright (C) 1995 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +*******************************************************************************/ +/*---------------------------------------------------*/ +/* Modified from : */ +/* Public Domain version of printf */ +/* Rud Merriam, Compsult, Inc. Houston, Tx. */ +/* For Embedded Systems Programming, 1991 */ +/* */ +/*---------------------------------------------------*/ +#include "xil_printf.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "bspconfig.h" +#include +#include +#include + +/************************** Function Prototypes ******************************/ + +static void padding( const s32 l_flag,const struct params_s *par); +static void outs(const charptr lp, struct params_s *par); +static s32 getnum( charptr* linep); + +/**************************** Type Definitions *******************************/ + +typedef struct params_s { + s32 len; /**< length */ + s32 num1; /**< number 1 */ + s32 num2; /**< number 2 */ + char8 pad_character; /**< pad character */ + s32 do_padding; /**< do padding */ + s32 left_flag; /**< left flag */ + s32 unsigned_flag; /**< unsigned flag */ +} params_t; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + + + +/*****************************************************************************/ +/** +* This routine puts pad characters into the output buffer. +* +******************************************************************************/ +static void padding( const s32 l_flag, const struct params_s *par) +{ + s32 i; + + if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) { + i=(par->len); + for (; i<(par->num1); i++) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( par->pad_character); +#endif + } + } +} + +/******************************************************************************/ +/** +* This routine moves a string to the output buffer +* as directed by the padding and positioning flags. +* +*******************************************************************************/ +static void outs(const charptr lp, struct params_s *par) +{ + charptr LocalPtr; + LocalPtr = lp; + /* pad on left if needed */ + if(LocalPtr != NULL) { + par->len = (s32)strlen( LocalPtr); + padding( !(par->left_flag), par); + /* Move string to the buffer */ + while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) { + (par->num2)--; +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte(*LocalPtr); +#endif + LocalPtr += 1; + } +} + + /* Pad on right if needed */ + /* CR 439175 - elided next stmt. Seemed bogus. */ + padding( par->left_flag, par); +} + +/*****************************************************************************/ +/** +* +* This routine moves a number to the output buffer +* as directed by the padding and positioning flags. +* +******************************************************************************/ +static void outnum( const s32 n, const s32 base, struct params_s *par) +{ + s32 negative; + s32 i; + char8 outbuf[32]; + const char8 digits[] = "0123456789ABCDEF"; + u32 num; + for(i = 0; i<32; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = n; + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % (u32)base)]; + i++; + num /= base; + } while (num > 0U); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = '\0'; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( outbuf[i] ); +#endif + i--; +} + padding( par->left_flag, par); +} +/*---------------------------------------------------*/ +/* */ +/* This routine moves a 64-bit number to the output */ +/* buffer as directed by the padding and positioning */ +/* flags. */ +/* */ +#if defined (__aarch64__) || defined (__arch64__) +static void outnum1( const s64 n, const s32 base, params_t *par) +{ + s32 negative; + s32 i; + char8 outbuf[64]; + const char8 digits[] = "0123456789ABCDEF"; + u64 num; + for(i = 0; i<64; i++) { + outbuf[i] = '0'; + } + + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = (n); + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = '\0'; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); + i--; +} + padding( par->left_flag, par); +} +#endif + +/*****************************************************************************/ +/** +* +* This routine gets a number from the format string. +* +******************************************************************************/ +static s32 getnum(charptr* linep) +{ + s32 n = 0; + s32 ResultIsDigit = 0; + charptr cptr = *linep; + + while (cptr != NULL) { + ResultIsDigit = isdigit(((u8)*cptr)); + if (ResultIsDigit == 0) { + break; + } + n = ((n*10) + (((s32)*cptr) - (s32)'0')); + cptr += 1; + } + + *linep = ((charptr)(cptr)); + return(n); +} + +/*****************************************************************************/ +/** +* This routine operates just like a printf/sprintf +* routine. It outputs a set of data under the +* control of a formatting string. Not all of the +* standard C format control are supported. The ones +* provided are primarily those needed for embedded +* systems work. Primarily the floating point +* routines are omitted. Other formats could be +* added easily by following the examples shown for +* the supported formats. +* void esp_printf( const func_ptr f_ptr, +* const charptr ctrl1, ...) +* +*******************************************************************************/ +#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +void xil_printf( const char8 *ctrl1, ...){ + XPVXenConsole_Printf(ctrl1); +} +#else +void xil_printf( const char8 *ctrl1, ...) +{ + va_list argp; + + va_start(argp, ctrl1); + + xil_vprintf(ctrl1, argp); + + va_end(argp); +} +#endif + +/*****************************************************************************/ +/** +* This routine is equivalent to vprintf routine +******************************************************************************/ +void xil_vprintf(const char8 *ctrl1, va_list argp) +{ + s32 Check; +#if defined (__aarch64__) || defined (__arch64__) + s32 long_flag; +#endif + s32 dot_flag; + + params_t par; + + u8 ch; + char8 *ctrl = (char8 *)ctrl1; + + while ((ctrl != NULL) && (*ctrl != (char8)0)) { + + /* move format string chars to buffer until a */ + /* format control is found. */ + if (*ctrl != '%') { +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte(*ctrl); +#endif + ctrl += 1; + continue; + } + + /* initialize all the flags for this format. */ + dot_flag = 0; +#if defined (__aarch64__) || defined (__arch64__) + long_flag = 0; +#endif + par.unsigned_flag = 0; + par.left_flag = 0; + par.do_padding = 0; + par.pad_character = ' '; + par.num2=32767; + par.num1=0; + par.len=0; + + try_next: + if(ctrl != NULL) { + ctrl += 1; + } + if(ctrl != NULL) { + ch = (u8)*ctrl; + } else { + break; + } + + if (isdigit(ch) != 0) { + if (dot_flag != 0) { + par.num2 = getnum(&ctrl); + } + else { + if (ch == (u8)'0') { + par.pad_character = '0'; + } + if(ctrl != NULL) { + par.num1 = getnum(&ctrl); + } + par.do_padding = 1; + } + if(ctrl != NULL) { + ctrl -= 1; + } + goto try_next; + } + + switch (tolower(ch)) { + case '%': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( '%'); +#endif + Check = 1; + break; + + case '-': + par.left_flag = 1; + Check = 0; + break; + + case '.': + dot_flag = 1; + Check = 0; + break; + + case 'l': + #if defined (__aarch64__) || defined (__arch64__) + long_flag = 1; + #endif + Check = 0; + break; + + case 'u': + par.unsigned_flag = 1; + /* fall through */ + case 'i': + case 'd': + #if defined (__aarch64__) || defined (__arch64__) + if (long_flag != 0){ + outnum1((s64)va_arg(argp, s64), 10L, &par); + } + else { + outnum( va_arg(argp, s32), 10L, &par); + } + #else + outnum( va_arg(argp, s32), 10L, &par); + #endif + Check = 1; + break; + case 'p': + #if defined (__aarch64__) || defined (__arch64__) + par.unsigned_flag = 1; + outnum1((s64)va_arg(argp, s64), 16L, &par); + Check = 1; + break; + #endif + case 'X': + case 'x': + par.unsigned_flag = 1; + #if defined (__aarch64__) || defined (__arch64__) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 16L, &par); + } + else { + outnum((s32)va_arg(argp, s32), 16L, &par); + } + #else + outnum((s32)va_arg(argp, s32), 16L, &par); + #endif + Check = 1; + break; + + case 's': + outs( va_arg( argp, char *), &par); + Check = 1; + break; + + case 'c': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( (char8)va_arg( argp, s32)); +#endif + Check = 1; + break; + + case '\\': + switch (*ctrl) { + case 'a': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x07)); +#endif + break; + case 'h': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x08)); +#endif + break; + case 'r': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); +#endif + break; + case 'n': +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( ((char8)0x0D)); + outbyte( ((char8)0x0A)); +#endif + break; + default: +#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT) + outbyte( *ctrl); +#endif + break; + } + ctrl += 1; + Check = 0; + break; + + default: + Check = 1; + break; + } + if(Check == 1) { + if(ctrl != NULL) { + ctrl += 1; + } + continue; + } + goto try_next; + } +} +/*---------------------------------------------------*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_printf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_printf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_printf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleepcommon.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleepcommon.c new file mode 100644 index 0000000..aba3a08 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleepcommon.c @@ -0,0 +1,85 @@ +/****************************************************************************** +* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +*@file xil_sleepcommon.c +* +* This file contains the sleep API's +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 	srm  	 11/02/17 First release
+* 7.7	sk	 01/10/22 Typecast sleep function argument from unsigned
+* 			  int to u32 to fix misra_c_2012_directive_4_6
+* 			  violation.
+* 8.0	sk	 03/02/22 Update usleep argument type to fix misra_c_2012_
+* 			  directive_4_6 violation.
+*
    +******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "sleep.h" + +/**************************** Constant Definitions *************************/ + + +/*****************************************************************************/ +/** +* +* This API gives delay in sec +* +* @param seconds - delay time in seconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void sleep(u32 seconds) + { +#if defined (ARMR5) + sleep_R5(seconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + sleep_A53(seconds); +#elif defined (__MICROBLAZE__) + sleep_MB(seconds); +#else + sleep_A9(seconds); +#endif + + } + +/****************************************************************************/ +/** +* +* This API gives delay in usec +* +* @param useconds - delay time in useconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void usleep(ULONG useconds) + { +#if defined (ARMR5) + usleep_R5(useconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + usleep_A53(useconds); +#elif defined (__MICROBLAZE__) + usleep_MB(useconds); +#else + usleep_A9(useconds); +#endif + + } diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.c new file mode 100644 index 0000000..2d3df6c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.c @@ -0,0 +1,152 @@ +/****************************************************************************** +* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.c +* +* This file provides the common helper routines for the sleep API's +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 6.6   srm  04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+* 7.0   mus  03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
+*                     space access, if processor is nonsecure and IOU slcr
+*                     address space is secure. CR#1015725.
+* 7.7	sk   01/10/22 Update values from signed to unsigned to fix
+* 		      misra_c_2012_rule_10_4 violation.
+* 7.7	sk   01/10/22 Add explicit parentheses for EL3==1 to fix
+* 		      misra_c_2012_rule_12_1 violation.
+* 7.7	sk   01/10/22 Add void argument to XTime_StartTTCTimer function to
+* 		      fix misra_c_2012_rule_8_2 violation.
+* 7.7	sk   01/10/22 Add braces for the if statement to make it a compound
+* 		      statement and fix misra_c_2012_rule_15_6 violation.
+*
+*
    +*****************************************************************************/ + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xil_sleeptimer.h" +#include "xtime_l.h" + +/**************************** Constant Definitions *************************/ + + +/* Function definitions are applicable only when TTC3 is present*/ +#if defined (SLEEP_TIMER_BASEADDR) +/****************************************************************************/ +/** +* +* This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec +* +* @param delay - delay time in seconds/micro seconds +* +* @param frequency - Number of counts per second/micro second +* +* @return none +* +* @note none +* +*****************************************************************************/ +void Xil_SleepTTCCommon(u32 delay, u64 frequency) +{ + u64 tEnd = 0U; + u64 tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + + TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency); + do + { + TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (u64)TimeLowVal2; + }while (tCur < tEnd); +} + + +/*****************************************************************************/ +/** +* +* This API starts the Triple Timer Counter +* +* @param none +* +* @return none +* +* @note none +* +*****************************************************************************/ +void XTime_StartTTCTimer(void) +{ + u32 TimerPrescalar; + u32 TimerCntrl; + +#if (defined (__aarch64__) && (EL3==1)) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32) + u32 LpdRst; + +#if defined (versal) + u32 RstAddr = CRL_TTC_RST; + u32 RstMask = CRL_TTC_BASE_RST_MASK << XSLEEP_TTC_INSTANCE; +#else + u32 RstAddr = RST_LPD_IOU2; + u32 RstMask = RST_LPD_IOU2_TTC_BASE_RESET_MASK << XSLEEP_TTC_INSTANCE; +#endif + /* check if the timer is reset */ + LpdRst = XSleep_ReadCounterVal(RstAddr); + if ((LpdRst & RstMask) != 0U ) { + LpdRst = LpdRst & (~RstMask); + Xil_Out32(RstAddr, LpdRst); + } else { +#endif + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + /* check if Timer is disabled */ + if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0U) { + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + /* check if Timer is configured with proper functionalty for sleep */ + if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0U) { + return; + } + } +#if (defined (__aarch64__) && (EL3==1)) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32) + } +#endif + /* Disable the timer to configure */ + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK; + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); + /* Disable the prescalar */ + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET, + TimerPrescalar); + /* Enable the Timer */ + TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h new file mode 100644 index 0000000..adcb7e6 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_sleeptimer.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 7.0   mus  01/07/19 Add cpp extern macro
+* 7.7	sk   01/10/22 Add explicit parentheses for EL3==1 to fix
+* 		      misra_c_2012_rule_12_1 violation.
+* 7.7	sk   01/10/22 Add void to XTime_StartTTCTimer function declaration
+* 		      to fix misra_c_2012_rule_8_2 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
    +*****************************************************************************/ + +/** + *@cond nocomments + */ +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && (EL3==1)) || defined (ARMA53_32) +#if defined (versal) +#define CRL_TTC_RST 0xFF5E0344U +#define CRL_TTC_BASE_RST_MASK 0x1U +#else +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ +/** + *@endcond + */ +/************************** Function Prototypes ******************************/ + +/**< This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec */ +void Xil_SleepTTCCommon(u32 delay, u64 frequency); + +void XTime_StartTTCTimer(void); /**< This API starts the Triple + * Timer Counter */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_SLEEPTIMER_H */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.c new file mode 100644 index 0000000..e1b5240 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.c @@ -0,0 +1,368 @@ +/****************************************************************************** +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_spinlock.c +* +* Implements a spinlocking mechanism using ARM load-exclusive and +* store-exclusive instructions. +* +* spinlocks in baremetal world are useful mainly for AMP kind of use cases +* where different applications run in different CPUs in a CPU cluster and +* they have a common resource to work with. +* A simple yet common example is: +* R5-0 and R5-1 have separate applications and at runtime they try to access a +* shared register space (GIC) or shared memory space. Mutual exclusion is +* really needed for such use cases. +* Similar use case applies for Zynq CortexA9-0 and CortesA9-1. +* +* The spinlock mechanism provided with this file is very simple to cater to +* baremetal world requirements. +* +* A) Unlike OS type of use cases, at any point of time, only a single lock +* can be used. There is no way in BM world we can support multiple locks +* at the same time. +* B) The spinlocking is available for ARM v7 (Cortex-R5 and Cortex-A9). +* C) Users need to provide a lock (essentially a shared address), and a flag +* (also a shared address) for spinlocking to work. These shared addresses +* must be agreed upon by apps running on both CPUs. Needless to say, +* the linker scripts must change accordingly so that apps running on both +* CPUs can have a shared DDR region from which address can be used for +* spinlocking. +* D) The address that is used for spinlocking and the address that is used +* as flag address must be in a memory region that is strongly-ordered +* or device memory. +* E) Like any similar standard use cases, one application running in any +* of the CPUs must create the spinlock address. It is advisable that the +* the same application must destroy or release the spinlock address, +* though nothing stops the other CPU in destroying and releasing the +* spinlock addresses. There has to be understanding between applications +* running on both the CPUs to ensure that correct ordering is followed. +* Once a spinlock is released, it spinlock APIs cannot be used anymore. +* F) Once a spinlock address is created it can be used any number of times +* to protect critical sections as long as a certain set of rules are +* followed and a certain set of sequences are followed. More about the +* sequences later in this description. +* G) To re-iterate, the spinlocking mechanism provided through this file is +* pretty rudimentary. Users can always improvise. The use case that +* the whole mechanism is trying to solve is: common register space +* being accesses in an AMP scenario by independent applications running +* at multiple CPUs. +* +* The usage of APIs provided in this file are summarized below. +* A) Applications running at both the CPUs ensure that they allocate shared +* memory space to be used for locking and flag maintenance. +* B) The memory allocated as shared should be of minimum size 1 MB. This +* limitation is because the way translation tables/memory map is setup +* for R5 or A9. In future, this limitation can be brought down 4 KB. +* C) The spinlock and the flag address must be uncached. Users need to c +* all Xilinx provided API Xil_SetTlbAttributes to mark the shared +* 1 MB memory space as strongly ordered or device memory. +* D) Both the applications must call the API Xil_InitializeSpinLock with +* the spinlock address, flag address and flag value to be used. Currently +* only one flag value is supported (i.e. XIL_SPINLOCK_ENABLE with +* a value of 1). +* Only if the Xil_InitializeSpinLock returns success, should they +* proceed to use Xil_SpinLock and Xil_SpinUnlock. +* F) Afterwards applications can start using the APIs Xil_SpinLock() and +* Xil_SpinUnlock() to protect the critical sections. +* G) It is highly suggested to use Xil_IsSpinLockEnabled() as a check +* before using Xil_SpinLock() or Xil_SpinUnlock(). Refer to the code +* snippet below. +* H) If spinlock is no more needed by an application, they can use the API +* Xil_ReleaseSpinLock(). +* I) Once a spinlock is created it can be used as many numbers of time as +* needed. +* +* A typical code snippet with R5 as an example and lock address falling +* in the 1 MB memory region (0x300000 to 0x400000) is given below. +* +* Code snippet for R5-0 (that runs first): +* int main() +* { +* u32 *sharedlockaddr = (int *)0x300008; +* u32 *sharedlockflagaddr = int *)0x30000C; +* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); +* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr, +* XIL_SPINLOCK_ENABLE); +* .... +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinLock(); +* // Critical Section +* .... +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinUnlock(); +* ..... +* ..... +* Xil_ReleaseSpinLock(); +* } // End of main +* +* * Code snippet for R5-1 (that runs second): +* int main() +* { +* u32 *sharedlockaddr = (int *)0x300008; +* u32 *sharedlockflagaddr = int *)0x30000C; +* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); +* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr, +* XIL_SPINLOCK_ENABLE); +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinLock(); +* // Critical Section +* .... +* .... +* if (Xil_IsSpinLockEnabled()) +* Xil_SpinUnlock(); +* ..... +* ..... +* Xil_ReleaseSpinLock(); +* } // End of main +* +* Xil_SpinLock() and Xil_SpinLock() return XST_FAILURE if the spinlock +* is initialized. Instead of calling Xil_IsSpinLockEnabled before using +* Xil_SpinLock() or Xil_SpinLock(), users can also check the return +* value of Xil_SpinLock and Xil_SpinLock. If a lock is not initialized, +* Xil_SpinLock will just return failure and not perform load-exclusive +* operations. +* +* Guidelines on when to use the spinlocking mechanism in Xilinx baremetal +* environment: +* A) Spinlocking mechanism can only be used for Cortex-R5s (split mode) +* and Cortex-A9s (Zynq). +* B) In Cortex-R5 split mode or Cortex-A9 cluster, applications running on +* both the CPUs, by design should never be sharing the same peripheral. +* It is impossible to support such use cases reliably. +* Hence none of the peripheral drivers (except GIC driver) have +* spinlocking support added into their APIs. +* C) GIC register space is shared by both the CPUs (R5 split mode, A9s). +* The GIC driver APIs have spinlocking mechanism added to the relevant +* APIs. Users need to follow the guidelines stated earlier to enable +* the spinlocks and use them. +* It is really advisable to use spinlock mechanism for use cases where +* applications running on multiple CPUs can simultaneously access +* GIC register space through driver APIs. +* D) The spinlock mechanism can be used to protect any critical region +* implemented through shared memory space. +* +* IMPORTANT NOTE: Circular spinlocks are not allowed (as expected). +* Use case where an application calls Xil_SpinLock back to back without +* calling Xil_SpinUnlock in between will/may result in a deadlock +* condition. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 7.5 	asa      02/23/21 First release
+* 7.5   asa      04/28/21 Fixed bug Xil_IsSpinLockEnabled to avoid
+*                         dereferencing to address zero.
+* 7.7	sk	 01/10/22 Update values from signed to unsigned to fix
+* 			  misra_c_2012_rule_10_4 violation.
+*
    +* +******************************************************************************/ + + +/***************************** Include Files ********************************/ +#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__) +#include "xil_spinlock.h" + + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + + + +/************************** Variable Definitions ****************************/ +static UINTPTR Xil_Spinlock_Addr = 0x0; +static UINTPTR Xil_Spinlock_Flag_Addr = 0x0; + +/************************** Function Prototypes *****************************/ + +/****************************************************************************/ +/** +* +* @brief Used at the beginning of a critical section. This API takes the +* lock using load-exclusive and store-exclusive operations. In +* case the lock is not available (being held by an application +* running at the other CPU and doing operations inside the +* critical section, the control will never go out from the API +* till the other CPU releases the lock. +* +* @param None. +* +* @return XST_FAILURE: If spinlock is not properly initialized. +* XST_SUCCESS: If the lock was successfully obtained. +* +* @note None. +* +*****************************************************************************/ +u32 Xil_SpinLock(void) +{ + UINTPTR lockaddr = Xil_Spinlock_Addr; + u32 LockTempVar; + + if (Xil_Spinlock_Addr == 0U) { + return XST_FAILURE; + } + + __asm__ __volatile__( + "1: ldrex %0, [%1] \n" + " teq %0, %3 \n" + " strexeq %0, %2, [%1] \n" + " teqeq %0, #0 \n" + " bne 1b \n" + " dmb \n" + : "=&r" (LockTempVar) + : "r" (lockaddr), "r"(XIL_SPINLOCK_LOCKVAL), "r"(XIL_SPINLOCK_RESETVAL) + : "cc"); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* @brief Used to release a lock previously held by calling Xil_SpinLock. +* +* @param None. +* +* @return XST_FAILURE: If spinlock is not properly initialized. +* XST_SUCCESS: If the lock was successfully obtained. +* +* @note None. +* +*****************************************************************************/ +u32 Xil_SpinUnlock(void) +{ + UINTPTR lockaddr = Xil_Spinlock_Addr; + + if (Xil_Spinlock_Addr == 0U) { + return XST_FAILURE; + } + __asm__ __volatile__( + "dmb \n" + "str %1, [%0] \n" + : + : "r" (lockaddr), "r" (XIL_SPINLOCK_RESETVAL) + : "cc"); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* @brief Used to initialize a spinlock. +* +* @param lockaddr: Address of the lock variable. The address must be in +* a shared memory region. +* lockflagaddr: Address of the flag variable. The address must be +* in a shared memory region. +* lockflag: The value of the flag. Currently only one value +* is supported, which is XIL_SPINLOCK_ENABLE. +* +* @return XST_SUCCESS, if the initialization succeeded. +* XST_FAILURE, if the initialization failed +* +* @note None. +* +*****************************************************************************/ +u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr, + u32 lockflag) +{ + if (Xil_Spinlock_Flag_Addr == 0U) { + Xil_Spinlock_Flag_Addr = lockflagaddr; + if (*(u32 *)Xil_Spinlock_Flag_Addr == XIL_SPINLOCK_ENABLED) { + /* + * spinlock is already initialized by one of the CPUs, just update + * the local variable Xil_Spinlock_Addr with the passed address + * and dont write to the lock value as it might be currently + * getting used. + */ + /* + * Ensure to update the global variable Xil_Spinlock_Addr only + * if it is zero. A non-zero value may mean that there is something + * wrong. + */ + if (Xil_Spinlock_Addr == 0U) { + Xil_Spinlock_Addr = lockaddr; + } else { + /* + * May be spinlock is already initialized and the user has not + * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock. + */ + return XST_FAILURE; + } + } else { + /* All good, do the necessary initializations */ + Xil_Spinlock_Addr = lockaddr; + *(u32 *)(Xil_Spinlock_Addr) = XIL_SPINLOCK_RESETVAL; + *(u32 *)(Xil_Spinlock_Flag_Addr) = lockflag; + } + return XST_SUCCESS; + } else { + /* + * Most probably spinlock is already initialized and the user has not + * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock. + */ + return XST_FAILURE; + } +} + + +/****************************************************************************/ +/** +* @brief Used to release the spinlock. Typically called by the application +* once spinlock feature is no more required. +* +* @param None. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void Xil_ReleaseSpinLock(void) +{ + Xil_Spinlock_Addr = 0; + Xil_Spinlock_Flag_Addr = 0; +} + +/****************************************************************************/ +/** +* @brief Used to know if the spinlock feature has been enabled. To ensure +* that spinlock feature does not break use cases where lock is +* not initialized, the application must call this API first to know +* if it can use spinlock. If this API returns non-zero value, an +* application should then use Xil_SpinLock or Xil_SpinUnlock. +* +* @param None +* +* @return Non-zero, if spinlock is already initialized and can be used. +* Zero, if spinlock is not initialized. +* +* @note +* +*****************************************************************************/ +u32 Xil_IsSpinLockEnabled(void) +{ + u32 retVal = FALSE; + + if (Xil_Spinlock_Flag_Addr != 0U) { + if (*(u32 *)(Xil_Spinlock_Flag_Addr) == XIL_SPINLOCK_ENABLED) { + retVal = TRUE; + } + } + return retVal; +} +#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_spinlock.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_spinlock.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_spinlock.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.c new file mode 100644 index 0000000..f101c14 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.c @@ -0,0 +1,341 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testcache.c +* @addtogroup common_test_utils +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+*
    +* +******************************************************************************/ +#ifdef __ARM__ +#include "xil_cache.h" +#include "xil_testcache.h" +#include "xil_types.h" +#include "xpseudo_asm.h" +#ifdef __aarch64__ +#include "xreg_cortexa53.h" +#else +#include "xreg_cortexr5.h" +#endif + +#include "xil_types.h" + +extern void xil_printf(const char8 *ctrl1, ...); + +#define DATA_LENGTH 128 + +#ifdef __aarch64__ +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); +#else +static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); +#endif + + +/*****************************************************************************/ +/** +* +* @brief Perform DCache range related API test such as Xil_DCacheFlushRange +* and Xil_DCacheInvalidateRange. This test function writes a constant +* value to the Data array, flushes the range, writes a new value, then +* invalidates the corresponding range. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestDCacheRange(void) +{ + s32 Index; + s32 Status = 0; + u32 CtrlReg; + INTPTR Value; + + xil_printf("-- Cache Range Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A00505; + + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" flush range done\r\n"); + + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A00505) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush worked\r\n"); + } + else { + xil_printf("Error: flush dcache range not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0C505; + + + + Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR)); + + xil_printf(" invalidate dcache range done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0xA0A0A05; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0xA0A0A05) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + + if (!Status) { + xil_printf(" Invalidate worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache range not working\r\n"); + } + xil_printf("-- Cache Range Test Complete --\r\n"); + return Status; + +} + +/*****************************************************************************/ +/** +* @brief Perform DCache all related API test such as Xil_DCacheFlush and +* Xil_DCacheInvalidate. This test function writes a constant value +* to the Data array, flushes the DCache, writes a new value, +* then invalidates the DCache. +* +* @return +* - 0 is returned for a pass +* - -1 is returned for a failure +*****************************************************************************/ +s32 Xil_TestDCacheAll(void) +{ + s32 Index; + s32 Status; + INTPTR Value; + u32 CtrlReg; + + xil_printf("-- Cache All Test --\n\r"); + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50500A0A; + xil_printf(" initialize Data done:\r\n"); + + Xil_DCacheFlush(); + xil_printf(" flush all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + + if (Value != 0x50500A0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Flush all worked\r\n"); + } + else { + xil_printf("Error: Flush dcache all not working\r\n"); + } + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x505FFA0A; + + Xil_DCacheFlush(); + + + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = Index + 3; + + Xil_DCacheInvalidate(); + + xil_printf(" invalidate all done\r\n"); + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + for (Index = 0; Index < DATA_LENGTH; Index++) + Data[Index] = 0x50CFA0A; + dsb(); + #ifdef __aarch64__ + CtrlReg = mfcp(SCTLR_EL3); + CtrlReg |= (XREG_CONTROL_DCACHE_BIT); + mtcp(SCTLR_EL3,CtrlReg); + #else + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg |= (XREG_CP15_CONTROL_C_BIT); + mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); + #endif + dsb(); + Status = 0; + + for (Index = 0; Index < DATA_LENGTH; Index++) { + Value = Data[Index]; + if (Value != 0x50CFA0A) { + Status = -1; + xil_printf("Data[%d] = %x\r\n", Index, Value); + break; + } + } + + if (!Status) { + xil_printf(" Invalidate all worked\r\n"); + } + else { + xil_printf("Error: Invalidate dcache all not working\r\n"); + } + + xil_printf("-- DCache all Test Complete --\n\r"); + + return Status; +} + +/*****************************************************************************/ +/** +* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers. +* +* @return +* - 0 is returned for a pass +* +* @note The function will hang if it fails. +*****************************************************************************/ +s32 Xil_TestICacheRange(void) +{ + + Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024); + Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024); + + xil_printf("-- Invalidate icache range done --\r\n"); + + return 0; +} + +/*****************************************************************************/ +/** +* @brief Perform Xil_ICacheInvalidate() on a few function pointers. +* +* @return +* - 0 is returned for a pass +* +* @note The function will hang if it fails. +*****************************************************************************/ +s32 Xil_TestICacheAll(void) +{ + Xil_ICacheInvalidate(); + xil_printf("-- Invalidate icache all done --\r\n"); + return 0; +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_testcache.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_testcache.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testcache.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.c new file mode 100644 index 0000000..0fe1204 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.c @@ -0,0 +1,279 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testio.c +* @addtogroup common_test_utils +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 9.00  ml   04/26/23 Updated code to fix sizeof_mismatch coverity warnings.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testio.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + + + +/** + * + * Endian swap a 16-bit word. + * @param Data is the 16-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u16 Swap16(u16 Data) +{ + return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U); +} + +/** + * + * Endian swap a 32-bit word. + * @param Data is the 32-bit word to be swapped. + * @return The endian swapped value. + * + */ +static u32 Swap32(u32 Data) +{ + u16 Lo16; + u16 Hi16; + + u16 Swap16Lo; + u16 Swap16Hi; + + Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU); + Lo16 = (u16)(Data & 0x0000FFFFU); + + Swap16Lo = Swap16(Lo16); + Swap16Hi = Swap16(Hi16); + + return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi); +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide register IO test where the +* register is accessed using Xil_Out8 and Xil_In8, and comparing +* the written values by reading them back. +* +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writing the memory. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) +{ + u8 ValueIn; + s32 Index; + s32 Status = 0; + + for (Index = 0; Index < Length; Index++) { + Xil_Out8((UINTPTR)Addr, Value); + + ValueIn = Xil_In8((UINTPTR)Addr); + + if ((Value != ValueIn) && (Status == 0)) { + Status = -1; + break; + } + } + return Status; + +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide register IO test. Each location +* is tested by sequentially writing a 16-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register +* IO, and big-endian register IO. When testing little/big-endian IO, +* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE, +* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE, +* Compare In-Out values. Whether to swap the read-in value before +* comparing is controlled by the 5th argument. +* +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writing the memory. +* @param Kind: Type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ + +s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) +{ + u16 *TempAddr16; + u16 ValueIn = 0U; + s32 Index; + u32 Size_16; + TempAddr16 = Addr; + Xil_AssertNonvoid(TempAddr16 != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out16LE((UINTPTR)TempAddr16, Value); + break; + case XIL_TESTIO_BE: + Xil_Out16BE((UINTPTR)TempAddr16, Value); + break; + default: + Xil_Out16((UINTPTR)TempAddr16, Value); + break; + } + + ValueIn = Xil_In16((UINTPTR)TempAddr16); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out16((UINTPTR)TempAddr16, Value); + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In16LE((UINTPTR)TempAddr16); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In16BE((UINTPTR)TempAddr16); + break; + default: + ValueIn = Xil_In16((UINTPTR)TempAddr16); + break; + } + + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap16(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + Size_16 = sizeof(u16); + TempAddr16 += Size_16; + } + return 0; +} + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide register IO test. Each location +* is tested by sequentially writing a 32-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register IO, +* and big-endian register IO. When testing little/big-endian IO, +* the function perform the following sequence, Xil_Out32LE/ +* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. +* Whether to swap the read-in value *before comparing is controlled +* by the 5th argument. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writing the memory. +* @param Kind: type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +*****************************************************************************/ +s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) +{ + u32 *TempAddr; + u32 ValueIn = 0U; + s32 Index; + u32 Size_32; + TempAddr = Addr; + Xil_AssertNonvoid(TempAddr != NULL); + + for (Index = 0; Index < Length; Index++) { + switch (Kind) { + case XIL_TESTIO_LE: + Xil_Out32LE((UINTPTR)TempAddr, Value); + break; + case XIL_TESTIO_BE: + Xil_Out32BE((UINTPTR)TempAddr, Value); + break; + default: + Xil_Out32((UINTPTR)TempAddr, Value); + break; + } + + ValueIn = Xil_In32((UINTPTR)TempAddr); + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + + /* second round */ + Xil_Out32((UINTPTR)TempAddr, Value); + + + switch (Kind) { + case XIL_TESTIO_LE: + ValueIn = Xil_In32LE((UINTPTR)TempAddr); + break; + case XIL_TESTIO_BE: + ValueIn = Xil_In32BE((UINTPTR)TempAddr); + break; + default: + ValueIn = Xil_In32((UINTPTR)TempAddr); + break; + } + + if ((Kind != 0) && (Swap != 0)) { + ValueIn = Swap32(ValueIn); + } + + if (Value != ValueIn) { + return -1; + } + Size_32 = sizeof(u32); + TempAddr += Size_32; + } + return 0; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_testio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_testio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.c new file mode 100644 index 0000000..aaa0617 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.c @@ -0,0 +1,1575 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_testmem.c +* @addtogroup common_test_utils +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 7.5   mus  03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
+*                     Xil_TestMem8 APIs to support memory test for memory
+*                     regions mapped at extended addresses
+*                     (addresses > 4 GB). These new set of APIs would be
+*                     compiled only for 32 bit Microblaze processor, if
+*                     XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
+*                     It fixes CR#1089129.
+* 7.6   mus  07/29/21 Updated Xil_TestMem8 to fix issues reported by static
+*                     analysis tool. It fixes CR#1105956.
+* 7.7	sk   01/10/22 Remove commented macro to fix misra_c_2012_directive_4_4
+* 		      violation.
+* 7.7	sk   01/10/22 Modify operands to fix misra_c_2012_rule_10_1 violation.
+* 7.7	sk   01/10/22 Typecast to make the both left and right sides expressions
+* 		      of same type and fix misra_c_2012_rule_10_6 violation.
+* 7.7	sk   01/10/22 Modify varaiable name from I to i to fix misra_c_2012_rule_
+* 		      21_2 violation.
+* 7.7	sk   01/10/22 Remove arithematic operations on pointer varaible to fix
+* 		      misra_c_2012_rule_18_4 violation.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xil_testmem.h" +#include "xil_io.h" +#include "xil_assert.h" + +/************************** Constant Definitions ****************************/ +/************************** Function Prototypes *****************************/ + +static u32 RotateLeft(u32 Input, u8 Width); + +/* define ROTATE_RIGHT to give access to this functionality */ +#ifdef ROTATE_RIGHT +static u32 RotateRight(u32 Input, u8 Width); +#endif /* ROTATE_RIGHT */ + +#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32) + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide memory test. +* +* @param Addrlow: lower 32 bit address of memory to be tested. +* @param Addrhigh: upper 32 bit address of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u8 Val; + u8 WordMem8; + s32 Status = 0; + u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * select the proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from XIL_TESTMEM_INIT_VALUE + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + sbea(Addr+I, Val); + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = XIL_TESTMEM_INIT_VALUE; + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + Val = (u8)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* write memory location */ + sbea(Addr+I, Val); + Val = (u8)RotateLeft(Val, 8U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val = (u8)RotateLeft(Val, NUM_OF_BITS_IN_BYTE); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking zeros test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) { + /* + * Generate an initial value for walking ones test to test + * for bad data bits + */ + Val = (u8) (~(1U << j)); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* write memory location */ + sbea(Addr+I, Val); + Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8) (~(1U << j)); + /* Read the values from each location that was written */ + for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + + Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE)); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + Val = (u8) (~((INTPTR) (Addr + I))); + sbea(Addr+I, Val); + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + Val = (u8) (~((INTPTR) (Addr+I))); + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u8)0) { + Val = 0xA5U; + } + else { + Val = Pattern; + } + /* + * Fill the memory with fixed Pattern + */ + for (I = 0U; I < Words; I++) { + /* write memory location */ + sbea(Addr+I, Val); + } + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < Words; I++) { + /* read memory location */ + WordMem8 = lbuea(Addr+I); + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide memory test. +* +* @param Addrlow: lower 32 bit address of memory to be tested. +* @param Addrhigh: upper 32 bit address of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant Pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u16 Val; + u16 WordMem16; + s32 Status = 0; + u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * selectthe proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'XIL_TESTMEM_INIT_VALUE' + */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* write memory location */ + shea(Addr+I, Val); + Val++; + I = I + NUM_OF_BYTES_IN_HW; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference val + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* read memory location */ + WordMem16 = lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val++; + I = I + NUM_OF_BYTES_IN_HW; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking ones test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (u16)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { + /* write memory location */ + shea(Addr+I,Val); + Val = (u16)RotateLeft(Val, 16U); + I = I + NUM_OF_BYTES_IN_HW; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16)((u32)1 << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { + /* read memory location */ + WordMem16 = lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = (u16)RotateLeft(Val, NUM_OF_BITS_IN_HW); + I = I + NUM_OF_BYTES_IN_HW; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking zeros test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) { + /* + * Generate an initial value for walking ones + * test to test for bad + * data bits + */ + + Val = ~(1U << j); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) { + shea(Addr+I, Val); + Val = ~((u16)RotateLeft(~Val, 16U)); + I = I + NUM_OF_BYTES_IN_HW; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = ~(1U << j); + /* Read the values from each location that was written */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) { + WordMem16= lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u16)RotateLeft(~Val, NUM_OF_BITS_IN_HW)); + I = I + NUM_OF_BYTES_IN_HW; + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* write memory location */ + Val = (u16) (~((INTPTR)((Addr+I)))); + shea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_HW; + } + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) { + /* read memory location */ + WordMem16 = lhuea(Addr+I); + Val = (u16) (~((INTPTR) ((Addr+I)))); + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_HW; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + if (Pattern == (u16)0) { + Val = 0xDEADU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed pattern + */ + + for (I = 0U; I < (2*Words);) { + /* write memory location */ + shea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_HW; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed pattern + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) { + /* read memory location */ + WordMem16=lhuea(Addr+I); + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_HW; + } + } +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide memory test. +* +* @param Addrlow: lower 32 bit address of memory to be tested. +* @param Addrhigh: upper 32 bit address of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: test type selected. See xil_testmem.h for possible +* values. +* +* @return +* - 0 is returned for a pass +* - 1 is returned for a failure +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest) +{ + u32 I; + u32 j; + u32 Val; + u32 WordMem32; + s32 Status = 0; + u64 Addr = (Addrlow + ((u64)Addrhigh << 32)); + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'XIL_TESTMEM_INIT_VALUE' + */ + for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) { + swea(Addr+I, Val); + Val++; + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = XIL_TESTMEM_INIT_VALUE; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) { + WordMem32 = lwea(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val++; + I = I + NUM_OF_BYTES_IN_WORD; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (1U << j); + + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) { + /* write memory location */ + swea(Addr+I, Val); + Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Restore the reference 'val' to the + * initial value + */ + Val = 1U << j; + + /* Read the values from each location that was + * written */ + for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) { + /* read memory location */ + + WordMem32 = lwea(Addr+I); + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val = (u32)RotateLeft(Val, NUM_OF_BITS_IN_WORD); + I = I + NUM_OF_BYTES_IN_WORD; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible + * initial test Patterns for walking zeros test + */ + + for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) { + + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = ~(1U << j); + + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { + /* write memory location */ + swea(Addr+I, Val); + Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD)); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + + Val = ~(1U << j); + + /* Read the values from each location that was + * written */ + for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) { + /* read memory location */ + WordMem32 = lwea(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD)); + I = I + NUM_OF_BYTES_IN_WORD; + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + /* write memory location */ + Val = (u32) (~((INTPTR) (Addr+I))); + swea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + /* Read the location */ + WordMem32 = lwea(Addr+I); + Val = (u32) (~((INTPTR) (Addr+I))); + + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_WORD; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed Pattern + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + /* write memory location */ + swea(Addr+I, Val); + I = I + NUM_OF_BYTES_IN_WORD; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) { + + /* read memory location */ + + WordMem32 = lwea(Addr+I); + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + I = I + NUM_OF_BYTES_IN_WORD; + } + } + +End_Label: + return Status; +} + +#else +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 32-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: test type selected. See xil_testmem.h for possible +* values. +* +* @return +* - 0 is returned for a pass +* - 1 is returned for a failure +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) +{ + u32 i; + u32 j; + u32 Val; + u32 FirtVal; + u32 WordMem32; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (i = 0U; i < Words; i++) { + Addr[i] = Val; + Val++; + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (i = 0U; i < Words; i++) { + WordMem32 = Addr[i]; + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)32; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (1UL << j); + + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)32; i++) { + /* write memory location */ + Addr[i] = Val; + Val = (u32) RotateLeft(Val, 32U); + } + + /* + * Restore the reference 'val' to the + * initial value + */ + Val = 1UL << j; + + /* Read the values from each location that was + * written */ + for (i = 0U; i < (u32)32; i++) { + /* read memory location */ + + WordMem32 = Addr[i]; + + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + + Val = (u32)RotateLeft(Val, 32U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible + * initial test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)32; j++) { + + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = ~(1UL << j); + + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)32; i++) { + /* write memory location */ + Addr[i] = Val; + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + /* + * Restore the reference 'Val' to the + * initial value + */ + + Val = ~(1UL << j); + + /* Read the values from each location that was + * written */ + for (i = 0U; i < (u32)32; i++) { + /* read memory location */ + WordMem32 = Addr[i]; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u32)RotateLeft(~Val, 32U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Val = ~(u32) (UINTPTR) &Addr[i]; + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (i = 0U; i < Words; i++) { + /* Read the location */ + WordMem32 = Addr[i]; + Val = ~(u32) (UINTPTR) &Addr[i]; + + if ((WordMem32 ^ Val) != 0x00000000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u32)0) { + Val = 0xDEADBEEFU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed Pattern + */ + + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (i = 0U; i < Words; i++) { + + /* read memory location */ + + WordMem32 = Addr[i]; + if (WordMem32 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 16-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant Pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) +{ + u32 i; + u32 j; + u16 Val; + u16 FirtVal; + u16 WordMem16; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * selectthe proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference val + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking ones test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + + Val = (u16)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)16; i++) { + /* write memory location */ + Addr[i] = Val; + Val = (u16)RotateLeft(Val, 16U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16)((u32)1 << j); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)16; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = (u16)RotateLeft(Val, 16U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)16; j++) { + /* + * Generate an initial value for walking ones + * test to test for bad + * data bits + */ + + Val = (u16) (~((u16)1U << j)); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + + for (i = 0U; i < (u32)16; i++) { + /* write memory location */ + Addr[i] = Val; + Val = ~((u16)RotateLeft(~((u32)Val), 16U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u16) (~((u16)1U << j)); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)16; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + Val = ~((u16)RotateLeft(~((u32)Val), 16U)); + } + + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Val = ~(u16) (UINTPTR) &Addr[i]; + Addr[i] = Val; + } + /* + * Check every word within the words + * of tested memory + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + Val = ~(u16) (UINTPTR) &Addr[i]; + if ((WordMem16 ^ Val) != 0x0000U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + if (Pattern == (u16)0) { + Val = 0xDEADU; + } + else { + Val = Pattern; + } + + /* + * Fill the memory with fixed pattern + */ + + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed pattern + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem16 = Addr[i]; + if (WordMem16 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} + + +/*****************************************************************************/ +/** +* +* @brief Perform a destructive 8-bit wide memory test. +* +* @param Addr: pointer to the region of memory to be tested. +* @param Words: length of the block. +* @param Pattern: constant used for the constant pattern test, if 0, +* 0xDEADBEEF is used. +* @param Subtest: type of test selected. See xil_testmem.h for possible +* values. +* +* @return +* - -1 is returned for a failure +* - 0 is returned for a pass +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** Width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundary of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +*****************************************************************************/ +s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) +{ + u32 i; + u32 j; + u8 Val; + u8 FirtVal; + u8 WordMem8; + s32 Status = 0; + + Xil_AssertNonvoid(Words != (u32)0); + Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); + + /* + * variable initialization + */ + Val = XIL_TESTMEM_INIT_VALUE; + FirtVal = XIL_TESTMEM_INIT_VALUE; + + /* + * select the proper Subtest(s) + */ + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) { + /* + * Fill the memory with incrementing + * values starting from 'FirtVal' + */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + Val++; + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = FirtVal; + /* + * Check every word within the words + * of tested memory and compare it + * with the incrementing reference + * Val + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val++; + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) { + /* + * set up to cycle through all possible initial + * test Patterns for walking ones test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test + * to test for bad data bits + */ + Val = (u8)((u32)1 << j); + /* + * START walking ones test + * Write a one to each data bit indifferent locations + */ + for (i = 0U; i < (u32)8; i++) { + /* write memory location */ + Addr[i] = Val; + Val = (u8)RotateLeft(Val, 8U); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8)((u32)1 << j); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)8; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + Val = (u8)RotateLeft(Val, 8U); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) { + /* + * set up to cycle through all possible initial test + * Patterns for walking zeros test + */ + + for (j = 0U; j < (u32)8; j++) { + /* + * Generate an initial value for walking ones test to test + * for bad data bits + */ + Val = (u8) (~(1U << j)); + /* + * START walking zeros test + * Write a one to each data bit indifferent locations + */ + for (i = 0U; i < (u32)8; i++) { + /* write memory location */ + Addr[i] = Val; + Val = ~((u8)RotateLeft(~((u32)Val), 8U)); + } + /* + * Restore the reference 'Val' to the + * initial value + */ + Val = (u8) (~(1U << j)); + /* Read the values from each location that was written */ + for (i = 0U; i < (u32)8; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + + Val = ~((u8)RotateLeft(~((u32)Val), 8U)); + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) { + /* Fill the memory with inverse of address */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Val = ~(u8) (UINTPTR) &Addr[i]; + Addr[i] = Val; + } + + /* + * Check every word within the words + * of tested memory + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + Val = ~(u8) (UINTPTR) &Addr[i]; + if ((WordMem8 ^ Val) != 0x00U) { + Status = -1; + goto End_Label; + } + } + } + + if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) { + /* + * Generate an initial value for + * memory testing + */ + + if (Pattern == (u8)0) { + Val = 0xA5U; + } + else { + Val = Pattern; + } + /* + * Fill the memory with fixed Pattern + */ + for (i = 0U; i < Words; i++) { + /* write memory location */ + Addr[i] = Val; + } + /* + * Check every word within the words + * of tested memory and compare it + * with the fixed Pattern + */ + + for (i = 0U; i < Words; i++) { + /* read memory location */ + WordMem8 = Addr[i]; + if (WordMem8 != Val) { + Status = -1; + goto End_Label; + } + } + } + +End_Label: + return Status; +} +#endif + +/*****************************************************************************/ +/** +* +* @brief Rotates the provided value to the left one bit position +* +* @param Input is value to be rotated to the left +* @param Width is the number of bits in the input data +* +* @return The resulting unsigned long value of the rotate left +* +* +*****************************************************************************/ +static u32 RotateLeft(u32 Input, u8 Width) +{ + u32 Msb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1UL << (Width - 1U); + + WidthMask = (MsbMask << (u32)1) - (u32)1; + + /* + * set the Width of the Input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + Msb = LocalInput & MsbMask; + + ReturnVal = LocalInput << 1U; + + if (Msb != 0x00000000U) { + ReturnVal = ReturnVal | (u32)0x00000001; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} + +#ifdef ROTATE_RIGHT +/*****************************************************************************/ +/** +* +* @brief Rotates the provided value to the right one bit position +* +* @param Input: value to be rotated to the right +* @param Width: number of bits in the input data +* +* @return +* The resulting u32 value of the rotate right +* +*****************************************************************************/ +static u32 RotateRight(u32 Input, u8 Width) +{ + u32 Lsb; + u32 ReturnVal; + u32 WidthMask; + u32 MsbMask; + u32 LocalInput = Input; + /* + * set up the WidthMask and the MsbMask + */ + + MsbMask = 1U << (Width - 1U); + + WidthMask = (MsbMask << 1U) - 1U; + + /* + * set the width of the input to the correct width + */ + + LocalInput = LocalInput & WidthMask; + + ReturnVal = LocalInput >> 1U; + + Lsb = LocalInput & 0x00000001U; + + if (Lsb != 0x00000000U) { + ReturnVal = ReturnVal | MsbMask; + } + + ReturnVal = ReturnVal & WidthMask; + + return ReturnVal; + +} +#endif /* ROTATE_RIGHT */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_testmem.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_testmem.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_testmem.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_types.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_types.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_types.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_types.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.c new file mode 100644 index 0000000..89c6d16 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.c @@ -0,0 +1,1361 @@ +/******************************************************************************/ +/** +* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* @file xil_util.c +* +* xil_util.c file contains xil utility functions +* Except few functions, most of these functions are wrappers to standard functions. +* The standard string functions do not validate the input and that results into +* buffer overflows. To avoid it, the wrapper function validates the input and +* then passed to standard function. There are few constant time functions +* ( xxx_CT() ) which are used to compare the data in constant time. +* The constant time functions should be used while comparing secure data +* like password, keys which prevent disclosing of the data using +* timing analysis. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.4   mmd      04/21/19 First release.
+* 7.2   nava     08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
+*                         API to use microsecond timeout instead of a free
+*                         counter.
+* 7.3   kal      06/30/20 Converted Xil_Ceil macro to API.
+*       rpo      08/19/20 Added function for read,modify,write
+*       kal      09/22/20 Changed the param type from const char to const char*
+*                         to avoid copying key onto stack
+*       td       10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
+*                         Xil_MemCmp functions
+* 7.4   am       11/26/20 Added Xil_StrCpyRange function
+* 7.6   kpt      07/15/21 Added Xil_SecureZeroize function
+* 7.7   kpt      11/09/21 Added Xil_SMemCmp, Xil_SMemCmp_CT, Xil_SMemCpy,
+*                         Xil_SMemSet, Xil_SStrCat, Xil_SStrCmp, Xil_SStrCmp_CT
+*                         Xil_SStrCpy functions
+*       kpt      11/25/21 Added strnlen function to fix ARMCC compilation
+*                         failure
+* 7.7	sk	 01/10/22 Update functions return type and update RetVal variable
+* 			  data type to fix misra_c_2012_directive_4_6 misrac
+* 			  violations.
+* 7.7	sk	 01/10/22 Update values from signed to unsigned to fix
+* 			  misra_c_2012_rule_10_4 violation.
+* 7.7	sk	 01/10/22 Add explicit parentheses to fix misra_c_2012_rule_12_1
+* 			  violation.
+* 7.7	sk	 01/10/22 Typecast character strings to u8 to fix misra_c_2012_rule_
+* 			  10_3 violation.
+* 7.7	sk	 01/10/22 Modify the code to reduce multiple break statements
+* 			  and fix misra_c_2012_rule_15_4 violation.
+* 7.7	sk	 01/10/22 Modify Xil_SMemCmp_CT and Xil_SMemCmp function argument
+* 			  type to fix misra_c_2012_rule_8_3 violation.
+* 7.7	sk	 01/10/22 Update conditional expression to fix misra_c_2012_rule_14_4
+* 			  violation.
+*       bm       01/20/22 Fix compilation warnings in Xil_SMemCpy
+*       mmd      02/28/22 Added Xil_SMemMove function
+* 8.0	sk	 03/02/22 Add explicit parentheses to fix misra_c_2012_rule_12_1
+* 			  violation.
+* 8.0	sk	 03/02/22 Add const qualifier to varaibles to fix misra_c_2012_rule_
+* 			  11_8 violation.
+* 8.0	sk	 03/02/22 Typecast expression with unsigned int to fix
+* 			  misra_c_2012_rule_10_7 violation.
+* 8.0	sk	 03/02/22 Typecast variables with unsigned or signed to fix misra_c
+* 			  _2012_rule_10_3 violation.
+* 8.0	sk	 03/02/22 Add const to unmodified variable to fix misra_c_2012
+* 			  _rule_8_13 violation.
+* 8.0	sk	 03/02/22 Typecast the function with void as return type is
+* 			  not used and fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk	 03/02/22 Remove increment operations during comparision to
+* 			  fix misra_c_2012_rule_13_3 violation.
+* 8.0	sk	 03/02/22 Update values from signed to unsigned to fix
+* 			  misra_c_2012_rule_10_4 violation.
+* 8.0	sk	 03/17/22 Add const to unmodified pointer variable to fix misra_c
+*			  _2012_rule_8_13 violation.
+* 8.0   adk      04/18/22 Added Xil_WaitForEventSet function.
+*       adk	 07/15/22 Updated the Xil_WaitForEventSet() API to
+*			  support variable number of events.
+*	ssc	 08/25/22 Added Xil_SecureRMW32 API
+* 8.1	sa       09/29/22 Change the type of first argument passed to Xil_WaitForEvent
+*			  API from u32 to UINTPTR for supporting 64 bit addressing.
+* 8.1   sa       10/20/22 Change the type of first argument passed to Xil_WaitForEvents
+*                         API from u32 to UINTPTR for supporting 64 bit addressing.
+* 8.1   akm      01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs.
+* 9.0   ml       03/03/23 Add description to fix doxygen warnings.
+* 9.0   ml       04/26/23 Updated code to fix DC.STRING BUFFER and VARARGS coverity warnings.
+* 9.0   ml       09/13/23 Replaced numerical types (int) with proper typedefs(s32) to
+*                         fix MISRA-C violations for Rule 4.6
+*
    +* +*****************************************************************************/ + +/****************************** Include Files *********************************/ +#include "xil_util.h" +#include "sleep.h" + +/************************** Constant Definitions ****************************/ +#define MAX_NIBBLES 8U /**< maximum nibbles */ + +/************************** Function Prototypes *****************************/ +void (*fptr)(void) = NULL; + +#ifdef __ARMCC_VERSION +/******************************************************************************/ +/** + * + * This API returns the length of the input string + * + * @param StartPtr is the pointer to the input string + * @param StrSize is the maximum length of the input string + * + * @return Returns the length of the input string + * + ******************************************************************************/ +static size_t strnlen (const char *StartPtr, size_t StrSize) +{ + const char *EndPtr = StartPtr; + size_t StrLen = 0U; + + EndPtr = memchr(StartPtr, '\0', StrSize); + if (EndPtr == NULL) { + StrLen = StrSize; + } else { + StrLen = (size_t) (EndPtr - StartPtr); + } + + return StrLen; +} +#endif + +/******************************************************************************/ +/** +* This API ceils the provided float value. +* +* @param Value is a float variable which has to ceiled to nearest +* integer. +* +* @return Returns ceiled value. +* +*******************************************************************************/ +s32 Xil_Ceil(float Value) +{ + s32 Result = Value; + + if (Value > Result) { + Result = Result + 1; + } + + return Result; +} + +/****************************************************************************/ +/** + * Converts the char into the equivalent nibble. + * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9 + * + * @param InChar - Input character to be converted to nibble. + * Valid characters are between 0-9, a-f, A-F + * @param Num - Memory location where nibble is to be stored + * + * @return + * XST_SUCCESS - Character converted to nibble + * XST_FAILURE - Invalid input character + * + * @note None. + * + *****************************************************************************/ + +u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num) +{ + u32 Status; + + /* Convert the char to nibble */ + if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) { + *Num = InChar - (u8)'0'; + Status = XST_SUCCESS; + } else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) { + *Num = InChar - (u8)'a' + 10U; + Status = XST_SUCCESS; + } else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) { + *Num = InChar - (u8)'A' + 10U; + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + return Status; +} + +/****************************************************************************/ +/* + * Converts the string into the equivalent Hex buffer. + * Ex: "abc123" -> {0xab, 0xc1, 0x23} + * + * @param Str - Pointer to string to be converted to Hex. + * Accepted characters in string are between 0-9, a-f and A-F + * @param Buf - Pointer to memory location where converted hex values are to + * be stored. + * @param Len - Length of input string + * + * @return + * XST_SUCCESS - Input string is converted to hex + * XST_FAILURE - Invalid character in inpit string + * + * @note None. + * + *****************************************************************************/ +u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len) +{ + u32 Status = XST_FAILURE; + u8 ConvertedLen = 0U, index = 0U; + u8 Nibble[MAX_NIBBLES] = {0U}; + u8 i; + + while (ConvertedLen < Len) { + for (i = 0U; i < MAX_NIBBLES; i++) { + Status = Xil_ConvertCharToNibble((u8)Str[ConvertedLen], + &Nibble[i]); + ConvertedLen = ConvertedLen + 1U; + if (Status != XST_SUCCESS) { + /* Error converting char to nibble */ + goto END; + } + } + + buf[index] = (((u32)Nibble[0] << (u8)28U) | ((u32)Nibble[1] << (u8)24U) | + ((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) | + ((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) | + ((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]); + index++; + } +END: + return Status; +} + +#ifdef VERSAL_PLM +/****************************************************************************/ +/* + * Register PLM Alive Handler. + * + * @param PlmAlive - Pointer to PlmAlive API. + * + * @return None. + * + *****************************************************************************/ +void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) +{ + fptr = PlmAlive; +} + +/****************************************************************************/ +/* + * PLM Stub Handler called while waiting for event. + * + * @param None. + * + * @return None. + * + *****************************************************************************/ +void Xil_PlmStubHandler(void) +{ + if (fptr != NULL) { + fptr(); + } +} +#endif + +/****************************************************************************/ +/* + * Waits for the event + * + * @param RegAddr - Address of register to be checked for event(s) occurrence + * @param EventMask - Mask indicating event(s) to be checked + * @param Event - Specific event(s) value to be checked + * @param Timeout - Max number of microseconds to wait for an event(s). + * + * @return + * XST_SUCCESS - On occurrence of the event(s). + * XST_FAILURE - Event did not occur before counter reaches 0 + * + * @note None. + * + *****************************************************************************/ +u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout) +{ + u32 EventStatus; + u32 PollCount = Timeout; + u32 Status = XST_FAILURE; + + while (PollCount > 0U) { + EventStatus = Xil_In32(RegAddr) & EventMask; + if (EventStatus == Event) { + Status = XST_SUCCESS; + break; + } + PollCount--; +#ifdef VERSAL_PLM + Xil_PlmStubHandler(); +#endif + usleep(1U); + } + + return Status; +} + + +/******************************************************************************/ +/** + * Waits for the events. Returns on occurrence of first event / timeout. + * + * @param EventsRegAddr - Address of register to be checked for event(s) + * occurrence + * @param EventsMask - Mask indicating event(s) to be checked + * @param WaitEvents - Specific event(s) to be checked + * @param Timeout - Max number of microseconds to wait for an event(s). + * @param Events - Mask of Events occurred returned in memory pointed by + * this variable + * + * @return + * XST_SUCCESS - On occurrence of the event(s). + * XST_FAILURE - Event did not occur before counter reaches 0 + * + ******************************************************************************/ +u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents, + u32 Timeout, u32 *Events) +{ + u32 EventStatus; + u32 PollCount = Timeout; + u32 Status = XST_TIMEOUT; + + *Events = 0x00; + do { + EventStatus = Xil_In32(EventsRegAddr); + EventStatus &= EventsMask; + if ((EventStatus & WaitEvents) != 0U) { + Status = XST_SUCCESS; + *Events = EventStatus; + break; + } + PollCount--; +#ifdef VERSAL_PLM + Xil_PlmStubHandler(); +#endif + usleep(1U); + } while (PollCount > 0U); + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether the passed character is a valid hex digit + * + * @param Ch - Pointer to the input character + * + * @return + * XST_SUCCESS - on valid hex digit + * XST_FAILURE - on invalid hex digit + * + * @note None. + * + ******************************************************************************/ +u32 Xil_IsValidHexChar(const char *Ch) +{ + u32 Status = XST_FAILURE; + + if (NULL == Ch) { + goto END; + } + if (((*Ch >= '0') && (*Ch <= '9')) || + ((*Ch >= 'a') && (*Ch <= 'f')) || + ((*Ch >= 'A') && (*Ch <= 'F'))) { + + Status = XST_SUCCESS; + } +END: + return Status; +} + +/******************************************************************************/ +/** + * Validate the input string contains only hexadecimal characters + * + * @param HexStr - Pointer to string to be validated + * + * @return + * XST_SUCCESS - On valid input hex string + * XST_INVALID_PARAM - On invalid length of the input string + * XST_FAILURE - On non hexadecimal character in string + * + * @note None + * + ******************************************************************************/ +u32 Xil_ValidateHexStr(const char *HexStr) +{ + u32 Idx; + u32 Len; + u32 Status = XST_INVALID_PARAM; + + if (NULL == HexStr) { + goto END; + } + + Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U); + if (Len > XIL_MAX_HEX_STR_LEN) { + goto END; + } + + for (Idx = 0U; Idx < Len; Idx++) { + Status = Xil_IsValidHexChar(&HexStr[Idx]); + if (Status != XST_SUCCESS) { + break; + } + } + +END: + return Status; +} + +/****************************************************************************/ +/** + * Converts the string into the equivalent Hex buffer. + * Ex: "abc123" -> {0xab, 0xc1, 0x23} + * + * @param Str is a Input String. Will support the lower and upper case values. + * Value should be between 0-9, a-f and A-F + * @param Buf is Output buffer. + * @param Len of the input string. Should have even values + * + * @return + * - XST_SUCCESS no errors occurred. + * - XST_FAILURE an error when input parameters are not valid + * - an error when input buffer has invalid values + * + * TDD Test Cases: + * ---Initialization--- + * Len is odd + * Len is zero + * Str is NULL + * Buf is NULL + * ---Functionality--- + * Str input with only numbers + * Str input with All values in A-F + * Str input with All values in a-f + * Str input with values in a-f, 0-9, A-F + * Str input with values in a-z, 0-9, A-Z + * Boundary Cases + * Memory Bounds of buffer checking + * ****************************************************************************/ +u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len) +{ + u32 ConvertedLen; + u8 LowerNibble = 0U; + u8 UpperNibble = 0U; + u32 Status = (u32)XST_FAILURE; + + if ((Str == NULL) || (Buf == NULL)) { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + + if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + + ConvertedLen = 0U; + while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), &UpperNibble) + == (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == (u32)XST_SUCCESS)) { + Buf[ConvertedLen / 2U] = + (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | + LowerNibble; + } else { + Status = (u32)XST_INVALID_PARAM; + goto END; + } + ConvertedLen += 2U; + } + Status = (u32)XST_SUCCESS; +END: + return Status; +} + +/******************************************************************************/ +/** + * Converts the string into the equivalent Hex buffer. + * Ex: "abc123" -> {0x23, 0xc1, 0xab} + * + * @param Str - Input String to be converted to hex number in little + * endian format. Valid characters of input strin are between + * 0-9, a-f and A-F + * @param Buf - Pointer to memory location where converted hex numbers are to + * be stored. + * @param Len - Expected number of output bits + * + * @return + * XST_SUCCESS - Input string is converted to hex number(s) + * XST_FAILURE - Invalid input character detected in input string + * + * @note + * + ******************************************************************************/ +u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len) +{ + u32 ConvertedLen; + u8 LowerNibble = 0U; + u8 UpperNibble = 0U; + u32 StrIndex; + u32 Status = XST_FAILURE; + + if ((NULL == Str) || (NULL == Buf)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) { + Status = XST_INVALID_PARAM; + goto END; + } + + StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U; + ConvertedLen = 0U; + while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) { + if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), + &UpperNibble) == XST_SUCCESS) && + (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]), + &LowerNibble) == XST_SUCCESS)) { + Buf[StrIndex] = + (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) | + LowerNibble; + StrIndex = StrIndex - 1U; + } else { + Status = XST_INVALID_PARAM; + goto END; + } + ConvertedLen += 2U; + } + + Status = XST_SUCCESS; +END: + return Status; +} + +/******************************************************************************/ +/** + * Returns the length of input string. + * + * @param Str - Input string + * @param MaxLen - Maximum expected length of the input string + * + * @return + * Returns length of the input string if length is less than MaxLen. + * Returns MaxLen if the length of the input string is >= MaxLen. + * + * @note + * + ******************************************************************************/ +u32 Xil_Strnlen(const char *Str, u32 MaxLen) +{ + const char *InStr = Str; + u32 StrLen = 0U; + + if (NULL == Str) { + goto END; + } + + while (StrLen < MaxLen) { + if ('\0' == *InStr) { + break; + } + StrLen++; + InStr++; + } + +END: + return StrLen; +} + +/*****************************************************************************/ +/** + * @brief This function will Read, Modify and Write to an address. + * + * @param Addr denotes Address + * @param Mask denotes the bits to be modified + * @param Value is the value to be written to the address + * + * @return None + * + *****************************************************************************/ +void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value) +{ + u32 Val; + + Val = Xil_In32(Addr); + Val = (Val & (~Mask)) | (Mask & Value); + Xil_Out32(Addr, Val); +} + +/*****************************************************************************/ +/** + * @brief This functions copies source string to destination string. This + * function is a safe version of strcpy + * + * @param DestPtr is pointer to destination string + * @param SrcPtr is pointer to source string + * @param Size is the maximum number of bytes of the source string + * to be copied + * + * @return XST_SUCCESS on success and error code on failure + * + ******************************************************************************/ +s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size) +{ + int Status = XST_FAILURE; + u32 Count; + + if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) { + goto END; + } + + for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) { + DestPtr[Count] = SrcPtr[Count]; + } + if (Count == Size) { + DestPtr[0U] = '\0'; + goto END; + } + DestPtr[Count] = '\0'; + Status = XST_SUCCESS; + +END: + return Status; +} + +/****************************************************************************/ +/** + * @brief Copies specified range from source string to destination string + * + * @param Src is a pointer to source string + * @param Dest is a pointer to destination string + * @param From is 0 based index from where string copy starts + * @param To is 0 based index till which string is copied + * @param MaxSrcLen is the maximum length of source string + * @param MaxDstLen is the maximum length of destination string + * + * @return XST_SUCCESS on success + * XST_FAILURE on failure + * + * @note None + * + ****************************************************************************/ +s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen, + u32 MaxDstLen) +{ + int Status = XST_FAILURE; + u32 SrcLength; + u32 Index; + + if ((Src == NULL) || (Dest == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if ((To >= MaxSrcLen) || (To < From)) { + Status = XST_INVALID_PARAM; + goto END; + } + + if ((To - From + 1U) >= MaxDstLen) { + Status = XST_INVALID_PARAM; + goto END; + } + + SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen); + if (To >= SrcLength) { + Status = XST_INVALID_PARAM; + goto END; + } + + for (Index = From; (Index <= To) && (Src[Index] != (u8)'\0'); Index++) { + Dest[Index - From] = Src[Index]; + } + + Dest[Index - From] = (u8)'\0'; + Status = XST_SUCCESS; + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function appends string2 to string1. This function is a safe + * version of strcat + * + * @param Str1Ptr is pointer to string1 + * @param Str2Ptr is pointer to string2 + * @param Size is the maximum number of bytes Str1 can hold + * + * @return XST_SUCCESS on success and error code on failure + * + ******************************************************************************/ +s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size) +{ + int Status = XST_FAILURE; + u32 Count = 0U; + u32 CountTmp = 0U; + + if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) { + goto END; + } + + while ((Count < Size) && (Str1Ptr[Count] != '\0')) { + Count++; + } + + while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) { + Str1Ptr[Count] = Str2Ptr[CountTmp]; + Count++; + CountTmp++; + } + if (Count == Size) { + Str1Ptr[0U] = '\0'; + goto END; + } + Str1Ptr[Count] = '\0'; + Status = XST_SUCCESS; + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function copies Len bytes from source memory to destination + * memory. If Len is greater than DestPtrLen, then DestPtr is also + * filled with 0s till DestPtrLen bytes and is considered as a failure. + * This function is a secure implementation of memcpy + * + * @param DestPtr is pointer to destination address + * @param DestPtrLen is the memory alloted to the destination buffer + * @param SrcPtr is pointer to source address + * @param Len is number of bytes to be copied + * + * @return XST_SUCCESS on success and error code on failure + * + ******************************************************************************/ +s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len) +{ + int Status = XST_FAILURE; + u8 *Dest = (u8 *)DestPtr; + const u8 *Src = (const u8 *)SrcPtr; + + if ((DestPtr == NULL) || (SrcPtr == NULL)) { + goto END; + } + + if (Len > DestPtrLen) { + while (DestPtrLen != 0U) { + *Dest = 0U; + Dest++; + DestPtrLen--; + } + goto END; + } + + /* Loop and copy. */ + while (Len != 0U) { + *Dest = *Src; + Dest++; + Src++; + Len--; + } + Status = XST_SUCCESS; + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares Len bytes from memory1 and memory2. This + * function is a secure implementation of memcmp + * + * @param Buf1Ptr is pointer to memory1 + * @param Buf2Ptr is pointer to memory2 + * @param Len is number of byets to be compared + * + * @return 0 if contents of both the memory regions are same, + * -1 if first non-matching character has lower value in Buf1Ptr + * 1 if first non-matching character is greater value in Buf1Ptr + * + ******************************************************************************/ +s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len) +{ + volatile int RetVal = 1; + const u8 *Buf1 = Buf1Ptr; + const u8 *Buf2 = Buf2Ptr; + u32 Size = Len; + + /* Assert validates the input arguments */ + if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) { + goto END; + } + + /* Loop and compare */ + while (Size != 0U) { + if (*Buf1 > *Buf2) { + RetVal = 1; + goto END; + } else if (*Buf1 < *Buf2) { + RetVal = -1; + goto END; + } else { + Buf1++; + Buf2++; + Size--; + } + } + + /* Make sure size is zero to know the whole of data is compared */ + if (Size == 0U) { + RetVal = 0; + } + +END: + return RetVal; +} + +/*****************************************************************************/ +/** + * @brief This function is used to zeroize the memory + * + * @param DataPtr Pointer to the memory which need to be zeroized. + * @param Length Length of the data in bytes. + * + * @return + * - XST_SUCCESS: If Zeroization is successful. + * - XST_FAILURE: If Zeroization is not successful. + ********************************************************************************/ +s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length) +{ + u32 Index; + int Status = XST_FAILURE; + + /* Clear the data */ + (void)memset(DataPtr, 0, Length); + + /* Read it back to verify */ + for (Index = 0U; Index < Length; Index++) { + if (DataPtr[Index] != 0x00U) { + goto END; + } + } + if (Index == Length) { + Status = XST_SUCCESS; + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares two memory regions for specified number + * of bytes. This function takes size of two memory regions to + * make sure not to read from or write to out of bound memory + * region. + * + * @param Src1 - Pointer to first memory range + * @param Src1Size - Maximum size of first memory range + * @param Src2 - Pointer to second memory range + * @param Src2Size - Maximum size of second memory range + * @param CmpLen - Number of bytes to be compared + * + * @return + * XST_SUCCESS - If specified number of bytes matches + * XST_FAILURE - If there is a mistmatch found during comparison + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemCmp(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) +{ + int Status = XST_FAILURE; + + if ((Src1 == NULL) || (Src2 == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + Status = XST_INVALID_PARAM; + } else { + Status = memcmp (Src1, Src2, CmpLen); + if (Status != 0) { + Status = XST_FAILURE; + } + } + + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares two memory regions for specified number + * of bytes. This function takes size of two memory regions to + * make sure not to read from or write to out of bound memory + * region. + * Note that this function compares till end to make it execute + * in constant time irrespective of the content of input memory. + * + * @param Src1 - Pointer to first memory range + * @param Src1Size - Maximum size of first memory range + * @param Src2 - Pointer to second memory range + * @param Src2Size - Maximum size of second memory range + * @param CmpLen - Number of bytes to be compared + * + * @return + * XST_SUCCESS - If specified number of bytes matches + * XST_FAILURE - If mistmatch + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size, + const void *Src2, const u32 Src2Size, const u32 CmpLen) +{ + volatile int Status = XST_FAILURE; + volatile int StatusRedundant = XST_FAILURE; + volatile u32 Data = 0U; + volatile u32 DataRedundant = 0xFFFFFFFFU; + u32 Cnt = CmpLen; + const u8 *Src_1 = (const u8 *)Src1; + const u8 *Src_2 = (const u8 *)Src2; + + + if ((Src1 == NULL) || (Src2 == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) { + Status = XST_INVALID_PARAM; + } else { + while (Cnt >= sizeof(u32)) { + Data |= (*(const u32 *)Src_1 ^ * (const u32 *)Src_2); + DataRedundant &= ~Data; + Src_1 += sizeof(u32); + Src_2 += sizeof(u32); + Cnt -= sizeof(u32); + } + + while (Cnt > 0U) { + Data |= (u32)(*Src_1 ^ *Src_2); + DataRedundant &= ~Data; + Src_1++; + Src_2++; + Cnt--; + } + + if ((Data == 0U) && (DataRedundant == 0xFFFFFFFFU)) { + Status = XST_SUCCESS; + StatusRedundant = XST_SUCCESS; + } + } + + return (Status | StatusRedundant); +} + +/*****************************************************************************/ +/** + * @brief This is wrapper function to memcpy function. This function + * takes size of two memory regions to make sure not read from + * or write to out of bound memory region. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Src - Pointer to source memory + * @param SrcSize - Maximum data that can be copied from source + * @param CopyLen - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemCpy(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) +{ + int Status = XST_FAILURE; + const u8 *Src8 = (const u8 *) Src; + const u8 *Dst8 = (u8 *) Dest; + void *volatile DestTemp = Dest; + const void *volatile SrcTemp = Src; + + if ((Dest == NULL) || (Src == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + Status = XST_INVALID_PARAM; + } + /* Return error for overlap string */ + else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) { + Status = XST_INVALID_PARAM; + } else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) { + Status = XST_INVALID_PARAM; + } else { + (void)memcpy(DestTemp, SrcTemp, CopyLen); + Status = XST_SUCCESS; + } + + return Status; +} + +/*****************************************************************************/ +/** + * @brief This is wrapper function to memset function. This function + * writes specified byte to destination specified number of times. + * This function also takes maximum string size that destination + * holds to make sure not to write out of bound area. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Data - Any value from 0 to 255 + * @param Len - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemSet(void *Dest, const u32 DestSize, + const u8 Data, const u32 Len) +{ + int Status = XST_FAILURE; + + if ((Dest == NULL) || (DestSize < Len) || (Len == 0U)) { + Status = XST_INVALID_PARAM; + } else { + (void)memset(Dest, (s32)Data, Len); + Status = XST_SUCCESS; + } + + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function concatenates two strings. This function + * takes size of both strings to make sure not to read from / + * write to out of bound area. + * + * @param DestStr - Pointer to destination string + * @param DestSize - Maximum string size that detination can hold + * @param SrcStr - Pointer to source string + * @param SrcSize - Maximum string size that source can hold + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) +{ + int Status = XST_FAILURE; + u32 SrcLen; + u32 DstLen; + u32 Length; + + if ((DestStr == NULL) || (SrcStr == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + SrcLen = strnlen((const char *)SrcStr, SrcSize); + DstLen = strnlen((const char *)DestStr, DestSize); + Length = SrcLen + DstLen; + + if ((DestSize <= DstLen) || (SrcSize <= SrcLen)) { + Status = XST_INVALID_PARAM; + } else if (DestSize <= Length) { + Status = XST_INVALID_PARAM; + } else { + (void)strncat((char *)DestStr, (const char *)SrcStr, Length); + Status = XST_SUCCESS; + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function compares two strings. It also takes maximum string + * size that Src1 and Src2 can hold to make sure not to read out of + * bound data for comparison. + * + * @param Str1 - Pointer to first string + * @param Str1Size - Maximum string size that Str1 can hold + * @param Str2 - Pointer to second string + * @param Str2Size - Maximum string size that Str2 can hold + * + * @return + * XST_SUCCESS - If both strings are same + * XST_FAILURE - If there is difference between two strings + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCmp(const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) +{ + int Status = XST_FAILURE; + u32 Str1Len = 0U; + u32 Str2Len = 0U; + + if ((Str1 == NULL) || (Str2 == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); + + if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { + Status = XST_INVALID_PARAM; + } else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) { + Status = XST_FAILURE; + } else { + Status = memcmp(Str1, Str2, Str1Len); + if (Status != 0) { + Status = XST_FAILURE; + } + } + +END: + return Status; +} + + +/*****************************************************************************/ +/** + * @brief This function compares two strings. It also takes maximum string + * size that Src1 and Src2 can hold to make sure not to read out of + * bound data for comparison. This function compares each character + * of the strings so that execution time of the function is not + * dependent on the content of two input strings. The execution + * time is constant when string size are same. + * + * @param Str1 - Pointer to first string + * @param Str1Size - Maximum string size that Str1 can hold + * @param Str2 - Pointer to second string + * @param Str2Size - Maximum string size that Str2 can hold + * + * @return + * XST_SUCCESS - If both strings are same + * XST_FAILURE - If there is difference between two strings + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size, + const u8 *Str2, const u32 Str2Size) +{ + int Status = XST_FAILURE; + u32 Str1Len = 0U; + u32 Str2Len = 0U; + + if ((Str1 == NULL) || (Str2 == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + Str1Len = strnlen((const char *)Str1, Str1Size); + Str2Len = strnlen((const char *)Str2, Str2Size); + + if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) { + Status = XST_INVALID_PARAM; + } else if (Str1Len != Str2Len) { + Status = XST_FAILURE; + } else { + Status = Xil_SMemCmp_CT (Str1, Str1Size, Str2, Str2Size, Str1Len); + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This function copies one string to other. This function + * takes size of both strings to make sure not to read from / + * write to out of bound area. + * + * @param DestStr - Pointer to destination string + * @param DestSize - Maximum string size that detination can hold + * @param SrcStr - Pointer to source string + * @param SrcSize - Maximum string size that source can hold + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SStrCpy(u8 *DestStr, const u32 DestSize, + const u8 *SrcStr, const u32 SrcSize) +{ + int Status = XST_FAILURE; + u32 SrcLen = 0U; + + if ((DestStr == NULL) || (SrcStr == NULL)) { + Status = XST_INVALID_PARAM; + goto END; + } + + SrcLen = strnlen((const char *)SrcStr, SrcSize); + + if ((DestSize <= SrcLen) || (SrcSize <= SrcLen)) { + Status = XST_INVALID_PARAM; + } else { + (void)memcpy(DestStr, SrcStr, SrcLen + 1U); + Status = XST_SUCCESS; + } + +END: + return Status; +} + +/*****************************************************************************/ +/** + * @brief This is wrapper function to memmove function. This function + * takes size of two memory regions to avoid out of bound memory region. + * + * @param Dest - Pointer to destination memory + * @param DestSize - Memory available at destination + * @param Src - Pointer to source memory + * @param SrcSize - Maximum data that can be copied from source + * @param CopyLen - Number of bytes to be copied + * + * @return + * XST_SUCCESS - Copy is successful + * XST_INVALID_PARAM - Invalid inputs + * + *****************************************************************************/ +s32 Xil_SMemMove(void *Dest, const u32 DestSize, + const void *Src, const u32 SrcSize, const u32 CopyLen) +{ + volatile int Status = XST_FAILURE; + const void *Output = NULL; + + if ((Dest == NULL) || (Src == NULL)) { + Status = XST_INVALID_PARAM; + } else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) { + Status = XST_INVALID_PARAM; + } else { + Output = memmove(Dest, Src, CopyLen); + if (Output != NULL) { + Status = XST_SUCCESS; + } + } + + return Status; +} + +/****************************************************************************/ +/* + * Waits for the event to be set with in timeout and returns error incase + * event was not set in specified time out. + * + * @param Timeout - Max number of microseconds to wait for an event, + * It should be maximum timeout needed among the + * events specified. + * @param NumOfEvents - Number of event(s) to be checked. + * @param EventAddr - Pointer to address of event(s) to be set. + * + * @return + * XST_SUCCESS - On occurrence of the event(s). + * XST_FAILURE - Event(s) did not occur before counter reaches 0 + * + * @note None. + * + *****************************************************************************/ +u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...) +{ + u32 PollCount = Timeout; + u32 Status = XST_FAILURE; + u32 LoopCnt = 0, i; + va_list Event; + + va_start(Event, EventAddr); + /* wait for all events to complete */ + for (i = 0; i < NumOfEvents; i++) { + while (PollCount > 0U) { + if (Xil_In32((UINTPTR)EventAddr)) { + LoopCnt++; + break; + } + PollCount--; +#ifdef VERSAL_PLM + Xil_PlmStubHandler(); +#endif + usleep(1U); + } + if (PollCount == 0U) { + goto END; + } + EventAddr = va_arg(Event, volatile u32 *); + PollCount = Timeout; + } + +END: + if (LoopCnt == NumOfEvents) { + Status = XST_SUCCESS; + } + + va_end(Event); + return Status; +} + +/****************************************************************************/ +/** + * @brief + * Performs a Read Modify Write operation for a memory location by writing the + * 32 bit value to the the specified address and then reading it back to + * verify the value written in the register. + * + * @param Addr contains the address to perform the output operation + * @param Mask indicates the bits to be modified + * @param Value contains 32 bit Value to be written at the specified address + * + * @return + * XST_SUCCESS on success + * XST_FAILURE on failure + * + *****************************************************************************/ +s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value) +{ + s32 Status = XST_FAILURE; + u32 ReadReg; + u32 Val; + + Val = Xil_In32(Addr); + Val = (Val & (~Mask)) | (Mask & Value); + Xil_Out32(Addr, Val); + + /* verify value written to specified address */ + ReadReg = Xil_In32(Addr) & Mask; + + if (ReadReg == (Mask & Value)) { + Status = XST_SUCCESS; + } + + return Status; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_util.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xil_util.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xil_util.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/xilstandalone.cmake b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xilstandalone.cmake similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/standalone/src/xilstandalone.cmake rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xilstandalone.cmake diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c new file mode 100644 index 0000000..10f339e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.c @@ -0,0 +1,455 @@ +/****************************************************************************** +* Copyright (c) 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xinterrupt_wrap.c +* +* The xinterrupt_wrap.c file contains interrupt related functions and macros. +* Contains wrapper functions for the scugic/axi intc Interrupt controller +* drivers. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2   mus  22/11/21 First release of xil interrupt support
+* 9.0   adk  17/04/23 Added support for system device-tree flow
+* 9.0   adk  27/04/23 Use XScuGic_LookupConfigBaseAddr() API for xsct flow
+*
    +* +******************************************************************************/ + +#include "xinterrupt_wrap.h" + +#ifdef XIL_INTERRUPT + +#if defined (XPAR_SCUGIC) /* available in xscugic.h */ +static XScuGic XScuGicInstance; +static int ScuGicInitialized; +#endif + +#if defined (XPAR_AXI_INTC) /* available in xintc.h */ +static XIntc XIntcInstance ; +#endif + +/*****************************************************************************/ +/** +* +* @brief Initializes the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConfigInterruptCntrl(UINTPTR IntcParent) +{ + int Status = XST_FAILURE; + UINTPTR BaseAddr = XGet_BaseAddr(IntcParent); + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Config *CfgPtr = NULL; + if (XScuGicInstance.IsReady != XIL_COMPONENT_IS_READY) { +#if defined(SDT) + CfgPtr = XScuGic_LookupConfig(BaseAddr); +#else + CfgPtr = XScuGic_LookupConfigBaseAddr(BaseAddr); +#endif + if (!ScuGicInitialized) { + Status = XScuGic_CfgInitialize(&XScuGicInstance, CfgPtr, 0); + } else { + Status = XST_SUCCESS; + } + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Initialize(&XIntcInstance, BaseAddr); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief connects to the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntrHandler: Interrupt handler. +* @param CallBackRef: Callback reference for handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent) +{ + int Status; + int Doconnect = FALSE; + + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (ScuGicInitialized) { + Doconnect = 1; + } + if (Doconnect) { + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + Status = XScuGic_Connect(&XScuGicInstance, IntrNum, \ + (Xil_ExceptionHandler) IntrHandler, CallBackRef); + return Status; + } else { + return XST_SUCCESS; + } +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + Status = XIntc_Connect(&XIntcInstance, IntrNum, \ + (XInterruptHandler)IntrHandler, CallBackRef); + return Status; +#else + return XST_FAILURE; +#endif + + } +} + +/*****************************************************************************/ +/** +* +* @brief disconnects the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disconnect(&XScuGicInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Disconnect(&XIntcInstance, IntrNum); +#else + return XST_FAILURE; +#endif + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* @brief Starts the interrupt controller. +* +* @param Mode: Interrupt controller mode type. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent) +{ +#if defined (XPAR_AXI_INTC) + int Status = XST_FAILURE; +#else + (void) Mode; +#endif + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + /* + * For XPAR_SCUGIC, XConfigInterruptCntrl starts controller + * hence returning without doing anything + */ + return 0; + } else { +#if defined (XPAR_AXI_INTC) + if (XIntcInstance.IsStarted != XIL_COMPONENT_IS_STARTED) { + Status = XIntc_Start(&XIntcInstance, Mode); + } else { + Status = XST_SUCCESS; + } + return Status; +#else + return XST_FAILURE; +#endif + + } + +} + +/*****************************************************************************/ +/** +* +* @brief Enable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XEnableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + IntrNum += Offset; + XScuGic_Enable(&XScuGicInstance, IntrNum); +#endif + + } else { +#if defined (XPAR_AXI_INTC) + u16 IntrNum = XGet_IntrId(IntrId); + XIntc_Enable(&XIntcInstance, IntrNum); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief disable the interrupt id. +* +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDisableIntrId( u32 IntrId, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + XScuGic_Disable(&XScuGicInstance, IntrNum); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Disable(&XIntcInstance, IntrId); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Configures the priority and trigger type. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent) +{ +#if defined (XPAR_SCUGIC) + u8 Trigger = (((XGet_TriggerType(IntrId) == 1) || + (XGet_TriggerType(IntrId) == 2)) ? XINTR_IS_EDGE_TRIGGERED + : XINTR_IS_LEVEL_TRIGGERED); + u16 IntrNum = XGet_IntrId(IntrId); + u16 Offset = XGet_IntrOffset(IntrId); + + IntrNum += Offset; + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { + XScuGic_SetPriorityTriggerType(&XScuGicInstance, IntrNum, Priority, Trigger); + } +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Gets the priority of the interrupt controller. +* +* @param IntrId: Interrupt Id. +* @param Priority: Priority of the interrupt +* @param Trigger: Trigger type of the interrupt +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_GetPriorityTriggerType(&XScuGicInstance, IntrId, Priority, Trigger); +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief stops the interrupt controller. +* +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XStopInterruptCntrl( UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + XScuGic_Stop(&XScuGicInstance); +#endif + } else { +#if defined (XPAR_AXI_INTC) + XIntc_Stop(&XIntcInstance); +#endif + } + +} + +/*****************************************************************************/ +/** +* +* @brief Registers the interrupt handler. +* +* @param IntrHandler: Interrupt handler. +* @param IntcParent: Interrupt controller baseaddress and type. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XRegisterInterruptHandler(void *IntrHandler, UINTPTR IntcParent) +{ + if (XGet_IntcType(IntcParent) == XINTC_TYPE_IS_SCUGIC) { +#if defined (XPAR_SCUGIC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XScuGic_InterruptHandler, + &XScuGicInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XScuGicInstance); + + } +#endif + } else { +#if defined (XPAR_AXI_INTC) + if (IntrHandler == NULL) { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) XIntc_InterruptHandler, + &XIntcInstance); + } else { + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, \ + (Xil_ExceptionHandler) IntrHandler, + &XIntcInstance); + } +#endif + } +} + +/*****************************************************************************/ +/** +* +* @brief Setup the interrupt system. +* +* @param DriverInstance: Driver instance pointer. +* @param IntrHandler: Interrupt handler funtion pointer. +* @param IntrId: Interrupt Id. +* @param IntcParent: Interrupt controller baseaddress and type. +* @param Priority: Interrupt priority. +* +* @return XST_SUCCESS if initialization was successful +* XST_FAILURE in case of failure +* +* @note None. +* +******************************************************************************/ +int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent, u16 Priority) +{ + int Status; + + Status = XConfigInterruptCntrl(IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_SCUGIC) + ScuGicInitialized = TRUE; +#endif + XSetPriorityTriggerType( IntrId, Priority, IntcParent); + Status = XConnectToInterruptCntrl( IntrId, (Xil_ExceptionHandler) IntrHandler, \ + DriverInstance, IntcParent); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } +#if defined (XPAR_AXI_INTC) + XStartInterruptCntrl(XIN_REAL_MODE, IntcParent); +#endif + XRegisterInterruptHandler(NULL, IntcParent); + XEnableIntrId(IntrId, IntcParent); + Xil_ExceptionInit(); + Xil_ExceptionEnable(); + return XST_SUCCESS; +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.h new file mode 100644 index 0000000..423aa0e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xinterrupt_wrap.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xinterrupt_wrap.h +* +* The xinterrupt_wrap.h file contains interrupt related functions and macros. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2   mus  22/11/21 First release of xil interrupt support
+* 8.0	sk   03/17/22 Update XINTC_BASEADDR_MASK macro to unsigned to
+* 		      fix misra_c_2012_rule_7_2 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+*
    +* +******************************************************************************/ + +#ifndef XINTERRUPT_WRAP_H /**< prevent circular inclusions */ +#define XINTERRUPT_WRAP_H /**< by using protection macros */ + +#include "xil_types.h" +#include "xstatus.h" + +#ifdef XIL_INTERRUPT +#ifdef SDT +#include "xcommon_drv_config.h" +#else +#include "xparameters.h" +#endif +#include "xil_exception.h" + +#if defined(XPAR_AXI_INTC) +#include "xintc.h" +#endif + +#if defined(XPAR_SCUGIC) +#include "xscugic.h" +#define XSPI_INTR_OFFSET 32U +#endif + +#define XINTERRUPT_DEFAULT_PRIORITY 0xA0U /* AXI INTC doesnt support priority setting, it is default priority for GIC interrupts */ +#define XINTC_TYPE_IS_SCUGIC 0U +#define XINTC_TYPE_IS_INTC 1U +#define XINTR_IS_EDGE_TRIGGERED 3U +#define XINTR_IS_LEVEL_TRIGGERED 1U + +#define XINTC_TYPE_MASK 0x1 +#define XINTC_INTR_TYPE_MASK 0x100000 +#define XINTC_BASEADDR_MASK 0xFFFFFFFFFFFFFFFEU +#define XINTC_INTRID_MASK 0xFFF +#define XINTC_TRIGGER_MASK 0xF000 +#define XINTC_TRIGGER_SHIFT 12 +#define XINTC_INTR_TYPE_SHIFT 20U +#define XGet_IntcType(IntParent) (IntParent & XINTC_TYPE_MASK) +#define XGet_IntrType(IntId) ((IntId & XINTC_INTR_TYPE_MASK) >> XINTC_INTR_TYPE_SHIFT) +#define XGet_BaseAddr(IntParent) (IntParent & XINTC_BASEADDR_MASK) +#define XGet_IntrId(IntId) (IntId & XINTC_INTRID_MASK) +#define XGet_TriggerType(IntId) ((IntId & XINTC_TRIGGER_MASK) >> XINTC_TRIGGER_SHIFT) +#define XGet_IntrOffset(IntId) (( XGet_IntrType(IntId) == 1) ? 16 : 32) /* For PPI offset is 16 and for SPI it is 32 */ + +extern int XConfigInterruptCntrl(UINTPTR IntcParent); +extern int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent); +extern int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent); +extern int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent); +extern void XEnableIntrId( u32 IntrId, UINTPTR IntcParent); +extern void XDisableIntrId( u32 IntrId, UINTPTR IntcParent); +extern void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent); +extern void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent); +extern void XStopInterruptCntrl( UINTPTR IntcParent); +extern void XRegisterInterruptHandler( void *IntrHandler, UINTPTR IntcParent); +extern int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent, + u16 Priority); +#endif + +#endif /* end of protection macro */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xl2cc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xl2cc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.c new file mode 100644 index 0000000..ea3a08c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.c @@ -0,0 +1,133 @@ +/****************************************************************************** +* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.c +* +* This file contains APIs for configuring and controlling the event counters +* in PL310 L2 cache controller. For more information about the event counters, +* see xl2cc_counter.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include +#include "xparameters_ps.h" +#include "xl2cc_counter.h" +#include "xl2cc.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XL2cc_EventCtrReset(void); + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* @brief This function initializes the event counters in L2 Cache controller +* with a set of event codes specified by the user. +* +* @param Event0: Event code for counter 0. +* @param Event1: Event code for counter 1. +* +* @return None. +* +* @note The definitions for event codes XL2CC_* can be found in +* xl2cc_counter.h. +* +*****************************************************************************/ +void XL2cc_EventCtrInit(s32 Event0, s32 Event1) +{ + + /* Write event code into cnt1 cfg reg */ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2); + + /* Write event code into cnt0 cfg reg */ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2); + + /* Reset counters */ + XL2cc_EventCtrReset(); +} + + +/****************************************************************************/ +/** +* +* @brief This function starts the event counters in L2 Cache controller. +* +* @return None. +* +*****************************************************************************/ +void XL2cc_EventCtrStart(void) +{ + u32 *LocalPtr; + LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET); + XL2cc_EventCtrReset(); + + /* Enable counter */ + /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */ + *LocalPtr = (u32)1; +} + +/****************************************************************************/ +/** +* +* @brief This function disables the event counters in L2 Cache controller, +* saves the counter values and resets the counters. +* +* @param EveCtr0: Output parameter which is used to return the value +* in event counter 0. +* @param EveCtr1: Output parameter which is used to return the value +* in event counter 1. +* +* @return None. +* +*****************************************************************************/ +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1) +{ + /* Disable counter */ + *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U; + + /* Save counter values */ + *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET)); + *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET)); + + XL2cc_EventCtrReset(); +} + +/****************************************************************************/ +/** +* +* @brief This function resets the event counters in L2 Cache controller. +* +* @return None. +* +*****************************************************************************/ +void XL2cc_EventCtrReset(void) +{ + *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xl2cc_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xl2cc_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xl2cc_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xparameters_ps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xparameters_ps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xparameters_ps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xparameters_ps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.c new file mode 100644 index 0000000..bdb7c6a --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.c @@ -0,0 +1,267 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xplatform_info.c +* @addtogroup common_platform_info Hardware Platform Information +* @{ +* This file contains information about hardware for which the code is built +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
+* 7.0	aru 03/15/19  Check for versal before aarch64 and armr5
+*		      in XGetPlatform_Info()
+* 7.2   adk 08/01/20  Added versal support for the XGetPSVersion_Info function.
+* 7.6   mus 08/23/21  Updated prototypes for functions which are not taking any
+*                     arguments with void keyword. This has been done to fix
+*                     compilation warnings with "-Wstrict-prototypes" flag.
+*                     It fixes CR#1108601.
+* 7.6    mus 08/30/21 Updated flag checking to fix compilation warnings
+*                     reported with "-Wundef" flag. It fixes CR#1108601.
+
+* 7.7    mus 11/02/21 Updated XGet_Zynq_UltraMp_Platform_info and
+*                     XGetPSVersion_Info to fix compilation warning
+*                     reported with "-Wundef" flag CR#1111453
+* 8.1    mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now
+*                     they are supported only for VERSAL_NET APU and RPU.
+* 9.0    mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be
+*                     used to identify type of boot (cold/warm).
+* 9.0    mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xplatform_info.h" +#if defined (__aarch64__) +#include "bspconfig.h" +#include "xil_smc.h" +#endif +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about platform +* +* @return The information about platform defined in xplatform_info.h +* +******************************************************************************/ +u32 XGetPlatform_Info(void) +{ +#if defined (versal) + return XPLAT_VERSAL; +#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) + return XPLAT_ZYNQ_ULTRA_MP; +#elif defined (__microblaze__) + return XPLAT_MICROBLAZE; +#else + return XPLAT_ZYNQ; +#endif +} + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about zynq ultrascale MP platform +* +* @return The information about zynq ultrascale MP platform defined in +* xplatform_info.h +* +******************************************************************************/ +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(void) +{ +#if defined (__aarch64__) && (EL1_NONSECURE == 1) + XSmc_OutVar reg; + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK); +#else + u32 reg; + reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT ) + & XPLAT_INFO_MASK); + return reg; +#endif +} +#endif + +/*****************************************************************************/ +/** +* +* @brief This API is used to provide information about PS Silicon version +* +* @return The information about PS Silicon version. +* +******************************************************************************/ +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal) +u32 XGetPSVersion_Info(void) +{ +#if defined (__aarch64__) && (EL1_NONSECURE == 1) + /* + * This SMC call will return, + * idcode - upper 32 bits of reg.Arg0 + * version - lower 32 bits of reg.Arg1 + */ + XSmc_OutVar reg; + reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0); + return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >> + XPS_VERSION_INFO_SHIFT); +#else + u32 reg; + reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS) + & XPS_VERSION_INFO_MASK); + return (reg >> XPS_VERSION_INFO_SHIFT); +#endif +} +#endif + +#if ! defined(__microblaze__) && ! defined(__riscv) +/*****************************************************************************/ +/** +* +* @brief This API is used to provide infomation about core id of the +* CPU core from which it is executed. +* +* @return Core id of the core on which API is executed. +* +******************************************************************************/ +u8 XGetCoreId(void) +{ + UINTPTR CoreId; + +#if (defined (__aarch64__) && ! defined (VERSAL_NET)) + /* CortexA53 and CortexA72 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#elif (defined (__aarch64__) && defined (VERSAL_NET)) + /* CortexA78 */ + CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#else + /* CortexA9, CortexR5 and CortexR52 */ +#ifdef __GNUC__ + CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MULTI_PROC_AFFINITY, CoreId); + CoreId &= XREG_MPIDR_MASK; +#else + { + register u32 C15Reg __asm(XREG_CP15_MULTI_PROC_AFFINITY); + CoreId = C15Reg; + } + CoreId &= XREG_MPIDR_MASK; +#endif + + CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \ + XREG_MPIDR_AFFINITY0_SHIFT); +#endif + + return (u8)CoreId; +} +#endif + +#if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52) +/*****************************************************************************/ +/** +* +* @brief This API is used to provide infomation about cluster id of the +* CPU core from which it is executed. +* +* @return Cluster id of the core on which API is executed. +* +******************************************************************************/ +u8 XGetClusterId(void) +{ + u64 ClusterId = 0; + +#if defined (ARMR52) + ClusterId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK); + ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY1_MASK) >> \ + XREG_MPIDR_AFFINITY1_SHIFT); +#else + ClusterId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK); + ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY2_MASK) >> \ + XREG_MPIDR_AFFINITY2_SHIFT); +#endif + + return (u8)ClusterId; +} + +/*****************************************************************************/ +/** +* +* @brief This API returns boot status of core from which it is executed. +* 0th bit of CORE_X_PWRDWN/RPU_PCIL_X_PWRDWN register indicates boot type. +* +* @return - 0 for cold boot +* - 1 for warm boot +* +******************************************************************************/ +u8 XGetBootStatus(void) +{ + u32 Status; + UINTPTR Addr; + +#if (__aarch64__) + u8 CpuNum; + + CpuNum = XGetClusterId(); + CpuNum *= XPS_NUM_OF_CORES_PER_CLUSTER; + CpuNum += XGetCoreId(); + + Addr = XPS_CORE_X_PWRDWN_BASEADDR + (CpuNum * XPS_CORE_X_PWRDWN_OFFSET); + Status = Xil_In32(Addr); + + return (Status & XPS_CORE_X_PWRDWN_EN_MASK); +#else + Addr = (XPS_RPU_PCIL_CLUSTER_OFFSET * XGetClusterId()) + XPS_RPU_PCIL_A0_PWRDWN; + Addr += (XGetCoreId() * XPS_RPU_PCIL_CORE_OFFSET); + + Status = Xil_In32(Addr); + + return (Status & XPS_RPU_PCIL_X_PWRDWN_EN_MASK); +#endif + +} + +#endif + +/** @} */ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xplatform_info.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xplatform_info.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xplatform_info.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.c new file mode 100644 index 0000000..70156c4 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.c @@ -0,0 +1,621 @@ +/****************************************************************************** +* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_counter.c +* +* This file contains APIs for configuring and controlling the Performance +* Monitor Events for ARM based processors supported by standalone BSP. +* For more information about the event counters, see xpm_counter.h. +* The file contains APIs to setup an event, return the event counter value, +* disable event(s), enable events, reset event counters. +* It also provides a helper function: Xpm_SleepPerfCounter that is used to +* implement sleep routines in non-OS environment. +* It also contains two APIs which are being deprecated. Users are advised +* not to use them. +* On usage of these APIs, please refer to xpm_conter_example.c file which can +* be found at standalone example folder. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 8.00  mus  07/07/22 Initial version
+* 8.00  mus  07/14/22 Existing PMU APIs dont have support for CortexA53 32
+*                     bit processor, added check to skip PMU APIs
+*                     compilation in case of CortexA53 32 bit BSP.
+* 8.2   asa  02/23/23 Add instruction sync barrier as mandated by ARM specs.
+*                     Do other clean ups.
+*                     Remove xil_printfs for failure cases where we return
+*                     appropriate error return value. It is expected that
+*                     callers of the APIs would check for return value to
+*                     know the cause of the error.
+* 8.2   asa  03/09/23 Xpm_SetEvents and Xpm_GetEventCounters are deprecated
+*                     APIs. They need not be supported for Versal Net.
+* 8.2   adk  03/13/23 Include xstatus.h when xiltimer is enabled.
+* 9.0   ml   14/04/23 Add U to numericals to fix misra-c violation
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#if !defined(ARMA53_32) +#include "xpm_counter.h" +#if !defined(XPAR_XILTIMER_ENABLED) && !defined(SDT) +#include "xil_sleeptimer.h" +#include "xtime_l.h" +#else +#include "xstatus.h" +#endif + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ +typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT]; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions *****************************/ + + +/******************************************************************************/ + +/****************************************************************************/ +/** +* +* @brief This function disables the event counters. +* +* @return None. +* +*****************************************************************************/ +void Xpm_DisableEventCounters(void) +{ + u32 RegVal; + +#if defined(__aarch64__) + RegVal = mfcp(PMCNTENCLR_EL0); +#else + /* Disable the event counters */ +#ifdef __GNUC__ + RegVal = mfcp(XREG_CP15_COUNT_ENABLE_CLR); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR); + RegVal = C15Reg; } +#endif +#endif + + RegVal &= 0x7FFFFFFFU; + RegVal |= XPM_EVENT_CNTRS_MASK; +#if defined(__aarch64__) + mtcp(PMCNTENCLR_EL0, RegVal); +#else + mtcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal); +#endif +} + +/****************************************************************************/ +/** +* +* @brief This function enables the event counters. +* +* @return None. +* +*****************************************************************************/ +void Xpm_EnableEventCounters(void) +{ + u32 RegVal; + +#if defined(__aarch64__) + RegVal = mfcp(PMCNTENSET_EL0); +#else + /* Enable the event counters */ +#ifdef __GNUC__ + RegVal = mfcp(XREG_CP15_COUNT_ENABLE_SET); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_SET, RegVal); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET); + RegVal = C15Reg; } +#endif +#endif + RegVal |= XPM_EVENT_CNTRS_MASK; +#if defined(__aarch64__) + mtcp(PMCNTENSET_EL0, RegVal); +#if defined(VERSAL_NET) + RegVal = mfcp(MDCR_EL3); + mtcp(MDCR_EL3, RegVal | XPM_MDCR_EL3_SPME_MASK); +#endif +#else + mtcp(XREG_CP15_COUNT_ENABLE_SET, RegVal); +#endif +} + +/****************************************************************************/ +/** +* +* @brief This function resets the event counters. +* +* @return None. +* +*****************************************************************************/ +void Xpm_ResetEventCounters(void) +{ + u32 Reg; + +#if defined(__aarch64__) + Reg = mfcp(PMCR_EL0); +#else +#ifdef __GNUC__ + Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); + Reg = C15Reg; } +#endif +#endif + + Reg |= (1U << 1U); /* reset event counters */ + +#if defined(__aarch64__) + mtcp(PMCR_EL0, Reg); +#else + mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); +#endif + isb(); +} + +/*****************************************************************************/ +/** + * + * Disables the requested event counter. + * + * + * @param EventCntrId: Event Counter ID. The counter ID is the same that + * was earlier returned through a call to Xpm_SetUpAnEvent. + * + * @return + * - XST_SUCCESS if successful. + * - XST_FAILURE if the passed Counter ID is invalid + * + ******************************************************************************/ +u32 Xpm_DisableEvent(u32 EventCntrId) +{ + u32 Counters; + u32 CntrMask = 0x1U; + + if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) { + return XST_FAILURE; + } else { + CntrMask = CntrMask << EventCntrId; +#if defined(__aarch64__) + Counters = mfcp(PMCNTENCLR_EL0); +#else +#ifdef __GNUC__ + Counters = mfcp(XREG_CP15_COUNT_ENABLE_CLR); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_CLR, Counters); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR); + Counters = C15Reg; } +#endif +#endif + Counters &= ~CntrMask; +#if defined(__aarch64__) + mtcp(PMCNTENCLR_EL0, Counters); +#else + mtcp(XREG_CP15_COUNT_ENABLE_CLR, Counters); +#endif + return XST_SUCCESS; + } +} + +/*****************************************************************************/ +/** + * + * Sets up one of the event counters to count events based on the Event ID + * passed. For supported Event IDs please refer xpm_counter.h. + * Upon invoked, the API searches for an available counter. After finding + * one, it sets up the counter to count events for the requested event. + * + * + * @param EventID: For valid values, please refer xpm_counter.h. + * + * @return + * - Counter Number if successful. For Cortex-R5, valid return values are + * 0, 1, or 2, and for others valid values are 0 to 5 + * - XPM_NO_COUNTERS_AVAILABLE (0xFF) if all counters are being used + * + ******************************************************************************/ +u32 Xpm_SetUpAnEvent(u32 EventID) +{ + u32 Counters; + u32 OriginalCounters; + u32 Index; + +#if defined(__aarch64__) + OriginalCounters = mfcp(PMCNTENSET_EL0); +#else +#ifdef __GNUC__ + OriginalCounters = mfcp(XREG_CP15_COUNT_ENABLE_SET); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters); +#else + { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET); + OriginalCounters = C15Reg; } +#endif +#endif + + OriginalCounters &= XPM_EVENT_CNTRS_BIT_MASK; + Counters = OriginalCounters; + if (Counters == XPM_ALL_EVENT_CNTRS_IN_USE) { + return XPM_NO_COUNTERS_AVAILABLE; + } else { + for(Index = 0U; Index < XPM_CTRCOUNT; Index++) { + if ((Counters & 0x1U) == 0x0U) { + break; + } else { + Counters = Counters >> 0x1U; + } + } + } + +#if defined(__aarch64__) + /* Select event counter */ + mtcp(PMSELR_EL0, Index); + isb(); + /* Set the event */ + mtcp( PMXEVTYPER_EL0, EventID); + /* Enable event counter */ + mtcp(PMCNTENSET_EL0, OriginalCounters | (1U << Index)); +#else + /* Select event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Index); + isb(); + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, EventID); + /* Enable event counter */ + mtcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters | ((u32)1U << Index)); +#endif + return Index; +} + +/*****************************************************************************/ +/** + * + * Reads the counter value for the requested counter ID. This is used to read + * the number of events that has been counted for the requsted event ID. + * This can only be called after a call to Xpm_SetUpAnEvent. + * + * + * @param EventCntrId: The counter ID is the same that was earlier + * returned through a call to Xpm_SetUpAnEvent. + * Cortex-R5 supports only 3 counters. The valid values are 0, 1, + * or 2 for other processors valid values are 0 to 5. + * @param CntVal: Pointer to a 32 bit unsigned int type. This is used to return + * the event counter value. + * + * @return + * - XST_SUCCESS if successful. + * - XST_FAILURE if the passed Counter ID is invalid + * + ******************************************************************************/ +u32 Xpm_GetEventCounter(u32 EventCntrId, u32 *CntVal) +{ + if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) { + return XST_FAILURE; + } else { +#if defined(__aarch64__) + mtcp(PMSELR_EL0, EventCntrId); + isb(); + *CntVal = mfcp(PMXEVCNTR_EL0); +#else + mtcp(XREG_CP15_EVENT_CNTR_SEL, EventCntrId); + isb(); +#ifdef __GNUC__ + *CntVal = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, (*CntVal)); +#else + { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + *CntVal = C15Reg; } +#endif +#endif + return XST_SUCCESS; + } +} + +/****************************************************************************/ +/** +* +* @brief This is helper function used by sleep/usleep APIs to generate +* delay in sec/usec +* +* @param delay - delay time in sec/usec +* @param frequency - Number of countes in second/micro second +* +* @return None. +* +*****************************************************************************/ +#ifndef XPAR_XILTIMER_ENABLED +void Xpm_SleepPerfCounter(u32 delay, u64 frequency) +{ + u64 tEnd = 0U; + u64 tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + +#if defined (__GNUC__) + TimeLowVal1 = Xpm_ReadCycleCounterVal(); +#elif defined (__ICCARM__) + Xpm_ReadCycleCounterVal(TimeLowVal1); +#endif + tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency); + do { +#if defined (__GNUC__) + TimeLowVal2 = Xpm_ReadCycleCounterVal(); +#elif defined (__ICCARM__) + Xpm_ReadCycleCounterVal(TimeLowVal2); +#endif + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (u64)TimeLowVal2; + }while (tCur < tEnd); +} +#endif +#if !defined(__aarch64__) && !defined(VERSAL_NET) +/****************************************************************************/ +/** +* +* @brief This function configures the event counters controller, +* with the event codes, in a configuration selected by the user and +* enables the counters. +* +* @param PmcrCfg: Configuration value based on which the event counters +* are configured.XPM_CNTRCFG* values defined in xpm_counter.h can +* be utilized for setting configuration +* +* @return None. +* +*****************************************************************************/ +void Xpm_SetEvents(s32 PmcrCfg) +{ + u32 Counter; + static PmcrEventCfg32 PmcrEvents[] = { + +#if defined(ARMR5) + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSTRCACHEMISS, + XPM_EVENT_DATACACHEMISS + }, + { + XPM_EVENT_DATACACHEACCESS, + XPM_EVENT_DATAREAD, + XPM_EVENT_DATAWRITE + }, + { + XPM_EVENT_INSTR, + XPM_EVENT_DUALINSTR, + XPM_EVENT_EXCEPTION + }, + { + XPM_EVENT_EXCEPTIONRET, + XPM_EVENT_CHANGETOCONTEXID, + XPM_EVENT_SWCHANGE + }, + { + XPM_EVENT_IMMEDIATEINSTR, + XPM_EVENT_PROCEDURERET, + XPM_EVENT_UNALIGNACCESS + }, + { + XPM_EVENT_BRANCHMISPREDICT, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT + }, + { + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL, + XPM_EVENT_DATACACHEWRITE + }, + { + XPM_EVENT_EXTERNALMEMREQ, + XPM_EVENT_LSUSTALL, + XPM_EVENT_FORCEDRAINSTORE + }, + { + XPM_EVENT_INSTRTAGPARITY, + XPM_EVENT_INSTRDATAPARITY, + XPM_EVENT_DATATAGPARITY + }, + { + XPM_EVENT_DATADATAPARITY, + XPM_EVENT_TCMERRORPREFETCH, + XPM_EVENT_TCMERRORSTORE + }, + { + XPM_EVENT_INSTRCACHEACCESS, + XPM_EVENT_DUALISSUEA, + XPM_EVENT_DUALISSUEB + }, + { + XPM_EVENT_DUALISSUEOTHER, + XPM_EVENT_FPA, + XPM_EVENT_DATACACHEDATAERROR + }, + { + XPM_EVENT_DATACACHETAGERROR, + XPM_EVENT_PROCESSORLIVELOCK, + XPM_EVENT_ATCMMULTIBITERROR + }, + { + XPM_EVENT_B0TCMMULTIBITERROR, + XPM_EVENT_B1TCMMULTIBITERROR, + XPM_EVENT_ATCMSINGLEBITERROR + }, + { + XPM_EVENT_B0TCMSINGLEBITERROR, + XPM_EVENT_B1TCMSINGLEBITERROR, + XPM_EVENT_TCMERRORLSU + }, + { + XPM_EVENT_TCMERRORPFU, + XPM_EVENT_TCMFATALERRORAXI, + XPM_EVENT_TCMERRORAXI + }, +#else + { + XPM_EVENT_SOFTINCR, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, + { + XPM_EVENT_DATA_READS, + XPM_EVENT_DATA_WRITE, + XPM_EVENT_EXCEPTION, + XPM_EVENT_EXCEPRETURN, + XPM_EVENT_CHANGECONTEXT, + XPM_EVENT_SW_CHANGEPC + }, + { + XPM_EVENT_IMMEDBRANCH, + XPM_EVENT_UNALIGNEDACCESS, + XPM_EVENT_BRANCHMISS, + XPM_EVENT_CLOCKCYCLES, + XPM_EVENT_BRANCHPREDICT, + XPM_EVENT_JAVABYTECODE + }, + { + XPM_EVENT_SWJAVABYTECODE, + XPM_EVENT_JAVABACKBRANCH, + XPM_EVENT_COHERLINEMISS, + XPM_EVENT_COHERLINEHIT, + XPM_EVENT_INSTRSTALL, + XPM_EVENT_DATASTALL + }, + { + XPM_EVENT_MAINTLBSTALL, + XPM_EVENT_STREXPASS, + XPM_EVENT_STREXFAIL, + XPM_EVENT_DATAEVICT, + XPM_EVENT_NODISPATCH, + XPM_EVENT_ISSUEEMPTY + }, + { + XPM_EVENT_INSTRRENAME, + XPM_EVENT_PREDICTFUNCRET, + XPM_EVENT_MAINEXEC, + XPM_EVENT_SECEXEC, + XPM_EVENT_LDRSTR, + XPM_EVENT_FLOATRENAME + }, + { + XPM_EVENT_NEONRENAME, + XPM_EVENT_PLDSTALL, + XPM_EVENT_WRITESTALL, + XPM_EVENT_INSTRTLBSTALL, + XPM_EVENT_DATATLBSTALL, + XPM_EVENT_INSTR_uTLBSTALL + }, + { + XPM_EVENT_DATA_uTLBSTALL, + XPM_EVENT_DMB_STALL, + XPM_EVENT_INT_CLKEN, + XPM_EVENT_DE_CLKEN, + XPM_EVENT_INSTRISB, + XPM_EVENT_INSTRDSB + }, + { + XPM_EVENT_INSTRDMB, + XPM_EVENT_EXTINT, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_PLE_OVFL, + XPM_EVENT_PLE_PROG, + XPM_EVENT_PLE_LRC, + XPM_EVENT_PLE_LRS, + XPM_EVENT_PLE_FLUSH, + XPM_EVENT_PLE_CMPL + }, + { + XPM_EVENT_DATASTALL, + XPM_EVENT_INSRFETCH_CACHEREFILL, + XPM_EVENT_INSTRFECT_TLBREFILL, + XPM_EVENT_DATA_CACHEREFILL, + XPM_EVENT_DATA_CACHEACCESS, + XPM_EVENT_DATA_TLBREFILL + }, +#endif + }; + const u32 *ptr = PmcrEvents[PmcrCfg]; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + /* Select event counter */ + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + + /* Set the event */ + mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]); + } + + Xpm_ResetEventCounters(); + Xpm_EnableEventCounters(); +} + +/****************************************************************************/ +/** +* +* @brief This function disables the event counters and returns the counter +* values. +* +* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. +* +* @return None. +* +*****************************************************************************/ +void Xpm_GetEventCounters(u32 *PmCtrValue) +{ + u32 Counter; + + Xpm_DisableEventCounters(); + + for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) { + + mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); + +#ifdef __GNUC__ + PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); +#else + { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); + PmCtrValue[Counter] = Cp15Reg; } +#endif + } +} +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xpm_counter.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xpm_counter.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_counter.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.c new file mode 100644 index 0000000..fca4d5e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.c @@ -0,0 +1,224 @@ +/****************************************************************************** +* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.c +* @addtogroup xpm_init xpm APIs +* +* This file contains the xpm node data and API's. +* @{ +* @details +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
    +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "bspconfig.h" +#if defined (XPM_SUPPORT) +#include "xil_assert.h" +#include "xparameters.h" +#include "pm_api_sys.h" +#include "xpm_nodeid.h" +#include "xstatus.h" +#include "xpm_init.h" + +/************************** Constant Definitions *****************************/ + +#define XPMU_IPI_CHANNEL_ID XPAR_XIPIPSU_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +static XIpiPsu IpiInst; +/************************** Function Prototypes ******************************/ + +/************************** Global Variables ********************************/ + +#ifdef VERSAL_NET +XpmNodeInfo XpmNodeData[] = { + /* { Base Address, Node ID, Reset ID } */ + { 0xF1B00000U, PM_DEV_USB_0, PM_RST_USB_0 }, /* USB_0 */ + { 0xF1C00000U, PM_DEV_USB_1, PM_RST_USB_1 }, /* USB_1 */ + { 0xF19E0000U, PM_DEV_GEM_0, PM_RST_GEM_0 }, /* GEM_0 */ + { 0xF19F0000U, PM_DEV_GEM_1, PM_RST_GEM_1 }, /* GEM_1 */ + { 0xF1960000U, PM_DEV_SPI_0, PM_RST_SPI_0 }, /* SPI_0 */ + { 0xF1970000U, PM_DEV_SPI_1, PM_RST_SPI_1 }, /* SPI_1 */ + { 0xF1940000U, PM_DEV_I2C_0, PM_RST_I2C_0 }, /* I2C_0 */ + { 0xF1950000U, PM_DEV_I2C_1, PM_RST_I2C_1 }, /* I2C_1 */ + { 0xF1980000U, PM_DEV_CAN_FD_0, PM_RST_CAN_FD_0 }, /* CAN_FD_0 */ + { 0xF1990000U, PM_DEV_CAN_FD_1, PM_RST_CAN_FD_1 }, /* CAN_FD_1 */ + { 0xF1920000U, PM_DEV_UART_0, PM_RST_UART_0 }, /* UART_0 */ + { 0xF1930000U, PM_DEV_UART_1, PM_RST_UART_1 }, /* UART_1 */ + { 0xF19D0000U, PM_DEV_GPIO, PM_RST_GPIO_LPD }, /* GPIO */ + { 0xF1DC0000U, PM_DEV_TTC_0, PM_RST_TTC_0 }, /* TTC_0 */ + { 0xF1DD0000U, PM_DEV_TTC_1, PM_RST_TTC_1 }, /* TTC_1 */ + { 0xF1DE0000U, PM_DEV_TTC_2, PM_RST_TTC_2 }, /* TTC_2 */ + { 0xF1DF0000U, PM_DEV_TTC_3, PM_RST_TTC_3 }, /* TTC_3 */ + { 0xEA420000U, PM_DEV_LPD_SWDT_0, PM_RST_SWDT_0 }, /* LPD_SWDT_0 */ + { 0xEA430000U, PM_DEV_LPD_SWDT_1, PM_RST_SWDT_1 }, /* LPD_SWDT_1 */ + { 0xECC10000U, PM_DEV_FPD_SWDT_0, PM_RST_FPD_SWDT_0 }, /* FPD_SWDT_0 */ + { 0xECD10000U, PM_DEV_FPD_SWDT_1, PM_RST_FPD_SWDT_1 }, /* FPD_SWDT_1 */ + { 0xECE10000U, PM_DEV_FPD_SWDT_2, PM_RST_FPD_SWDT_2 }, /* FPD_SWDT_2 */ + { 0xECF10000U, PM_DEV_FPD_SWDT_3, PM_RST_FPD_SWDT_3 }, /* FPD_SWDT_3 */ + { 0xF1010000U, PM_DEV_OSPI, PM_RST_OSPI }, /* OSPI */ + { 0xF1030000U, PM_DEV_QSPI, PM_RST_QSPI }, /* QSPI */ + { 0xF1020000U, PM_DEV_GPIO_PMC, PM_RST_GPIO_PMC }, /* GPIO_PMC */ + { 0xF1000000U, PM_DEV_I2C_PMC, PM_RST_I2C_PMC }, /* I2C_PMC */ + { 0xF1040000U, PM_DEV_SDIO_0, PM_RST_SDIO_0 }, /* SDIO_0 */ + { 0xF1050000U, PM_DEV_SDIO_1, PM_RST_SDIO_1 }, /* EMMC */ + { 0xEBD00000U, PM_DEV_ADMA_0, PM_RST_ADMA }, /* ADMA_0 */ + { 0xEBD10000U, PM_DEV_ADMA_1, PM_RST_ADMA }, /* ADMA_1 */ + { 0xEBD20000U, PM_DEV_ADMA_2, PM_RST_ADMA }, /* ADMA_2 */ + { 0xEBD30000U, PM_DEV_ADMA_3, PM_RST_ADMA }, /* ADMA_3 */ + { 0xEBD40000U, PM_DEV_ADMA_4, PM_RST_ADMA }, /* ADMA_4 */ + { 0xEBD50000U, PM_DEV_ADMA_5, PM_RST_ADMA }, /* ADMA_5 */ + { 0xEBD60000U, PM_DEV_ADMA_6, PM_RST_ADMA }, /* ADMA_6 */ + { 0xEBD70000U, PM_DEV_ADMA_7, PM_RST_ADMA }, /* ADMA_7 */ + { 0xEB300000U, PM_DEV_IPI_0, PM_RST_IPI }, /* IPI */ +}; +#elif defined(versal) +XpmNodeInfo XpmNodeData[] = { + /* { Base Address, Node ID, Reset ID } */ + { 0xFE200000U, PM_DEV_USB_0, PM_RST_USB_0 }, /* USB_0 */ + { 0xFF0C0000U, PM_DEV_GEM_0, PM_RST_GEM_0 }, /* GEM_0 */ + { 0xFF0D0000U, PM_DEV_GEM_1, PM_RST_GEM_1 }, /* GEM_1 */ + { 0xFF040000U, PM_DEV_SPI_0, PM_RST_SPI_0 }, /* SPI_0 */ + { 0xFF050000U, PM_DEV_SPI_1, PM_RST_SPI_1 }, /* SPI_1 */ + { 0xFF020000U, PM_DEV_I2C_0, PM_RST_I2C_0 }, /* I2C_0 */ + { 0xFF030000U, PM_DEV_I2C_1, PM_RST_I2C_1 }, /* I2C_1 */ + { 0xFF060000U, PM_DEV_CAN_FD_0, PM_RST_CAN_FD_0 }, /* CAN_FD_0 */ + { 0xFF070000U, PM_DEV_CAN_FD_1, PM_RST_CAN_FD_1 }, /* CAN_FD_1 */ + { 0xFF000000U, PM_DEV_UART_0, PM_RST_UART_0 }, /* UART_0 */ + { 0xFF010000U, PM_DEV_UART_1, PM_RST_UART_1 }, /* UART_1 */ + { 0xFF0B0000U, PM_DEV_GPIO, PM_RST_GPIO_LPD }, /* GPIO */ + { 0xFF0E0000U, PM_DEV_TTC_0, PM_RST_TTC_0 }, /* TTC_0 */ + { 0xFF0F0000U, PM_DEV_TTC_1, PM_RST_TTC_1 }, /* TTC_1 */ + { 0xFF100000U, PM_DEV_TTC_2, PM_RST_TTC_2 }, /* TTC_2 */ + { 0xFF110000U, PM_DEV_TTC_3, PM_RST_TTC_3 }, /* TTC_3 */ + { 0xFF120000U, PM_DEV_SWDT_LPD, PM_RST_SWDT_LPD }, /* SWDT_LPD */ + { 0xFD4D0000U, PM_DEV_SWDT_FPD, PM_RST_SWDT_FPD }, /* SWDT_FPD */ + { 0xF1010000U, PM_DEV_OSPI, PM_RST_OSPI }, /* OSPI */ + { 0xF1030000U, PM_DEV_QSPI, PM_RST_QSPI }, /* QSPI */ + { 0xF1020000U, PM_DEV_GPIO_PMC, PM_RST_GPIO_PMC }, /* GPIO_PMC */ + { 0xF1000000U, PM_DEV_I2C_PMC, PM_RST_I2C_PMC }, /* I2C_PMC */ + { 0xF1040000U, PM_DEV_SDIO_0, PM_RST_SDIO_0 }, /* SDIO_0 */ + { 0xF1050000U, PM_DEV_SDIO_1, PM_RST_SDIO_1 }, /* SDIO_1 */ + { 0xFFA80000U, PM_DEV_ADMA_0, PM_RST_ADMA }, /* ADMA_0 */ + { 0xFFA90000U, PM_DEV_ADMA_1, PM_RST_ADMA }, /* ADMA_1 */ + { 0xFFAA0000U, PM_DEV_ADMA_2, PM_RST_ADMA }, /* ADMA_2 */ + { 0xFFAB0000U, PM_DEV_ADMA_3, PM_RST_ADMA }, /* ADMA_3 */ + { 0xFFAC0000U, PM_DEV_ADMA_4, PM_RST_ADMA }, /* ADMA_4 */ + { 0xFFAD0000U, PM_DEV_ADMA_5, PM_RST_ADMA }, /* ADMA_5 */ + { 0xFFAE0000U, PM_DEV_ADMA_6, PM_RST_ADMA }, /* ADMA_6 */ + { 0xFFAF0000U, PM_DEV_ADMA_7, PM_RST_ADMA }, /* ADMA_7 */ + { 0xFF300000U, PM_DEV_IPI_0, PM_RST_IPI }, /* IPI */ +}; +#endif + +/****************************************************************************/ +/** + * * + * * @brief This API is used to provide the node id. + * * + * * @return Node ID if successful, otherwise XST_FAILURE. + * * + * * @note none + * * + * *****************************************************************************/ +UINTPTR XpmGetNodeId(UINTPTR BaseAddress) +{ + u32 id; + + for (id = 0; id < MAX_NODE_COUNT; id++) { + if (BaseAddress == XpmNodeData[id].BaseAddress) { + return XpmNodeData[id].NodeId; + } + } + return (UINTPTR)XST_FAILURE; +} + +/****************************************************************************/ +/** + * * + * * @brief This API is used to provide the reset id. + * * + * * @return Reset ID if successful, otherwise XST_FAILURE. + * * + * * @note none + * * + * *****************************************************************************/ +UINTPTR XpmGetResetId(UINTPTR BaseAddress) +{ + u32 id; + + for (id = 0; id < MAX_NODE_COUNT; id++) { + if (BaseAddress == XpmNodeData[id].BaseAddress) { + return XpmNodeData[id].ResetId; + } + } + return (UINTPTR)XST_FAILURE; +} + +static XStatus XpmIpiConfig(XIpiPsu *const IpiInst) +{ + XStatus status; + XIpiPsu_Config *IpiCfgPtr; + + Xil_AssertNonvoid(IpiInst != NULL); + + /* Look Up the config data */ + IpiCfgPtr = XIpiPsu_LookupConfig(XPMU_IPI_CHANNEL_ID); + if (NULL == IpiCfgPtr) { + status = XST_FAILURE; + xil_printf("%s ERROR in getting CfgPtr\n", __func__); + return status; + } + + /* Init with the Cfg Data */ + status = XIpiPsu_CfgInitialize(IpiInst, IpiCfgPtr, + IpiCfgPtr->BaseAddress); + if (XST_SUCCESS != status) { + xil_printf("%s ERROR #%d in configuring IPI\n", __func__, status); + } + return status; +} + +/****************************************************************************/ +/** + * * + * * This API initializes the ipi and xilpm through constructor. + * * + * * @return none + * * + * * @note none + * * + * *****************************************************************************/ +void __attribute__ ((constructor)) xpminit() +{ + XStatus status; + + status = XpmIpiConfig(&IpiInst); + if (XST_SUCCESS != status) { + xil_printf("IPI configuration failed.\n"); + } + + status = XPm_InitXilpm(&IpiInst); + if (XST_SUCCESS != status) { + xil_printf("Xilpm library initialization failed.\n"); + } +} +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h new file mode 100644 index 0000000..f2856be --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpm_init.h @@ -0,0 +1,46 @@ +/****************************************************************************** +*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +*SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xpm_init.h +* @addtogroup xpm_init xpm_init APIs +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+*  1.0  gm      14/06/23 Initial release.
+*
    +******************************************************************************/ + +#ifndef XPM_INIT_H +#define XPM_INIT_H + +/************************** Constant Definitions *****************************/ + +#if defined (XPM_SUPPORT) +#ifdef VERSAL_NET +#define MAX_NODE_COUNT 38 +#elif defined(versal) +#define MAX_NODE_COUNT 33 +#endif + +/**************************** Type Definitions *******************************/ + +typedef struct { + UINTPTR BaseAddress; + UINTPTR NodeId; + UINTPTR ResetId; +} XpmNodeInfo; + +/************************** Function Prototypes ******************************/ + +UINTPTR XpmGetNodeId(UINTPTR BaseAddress); +UINTPTR XpmGetResetId(UINTPTR BaseAddress); + +#endif +#endif diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm_gcc.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm_gcc.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xpseudo_asm_gcc.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xpseudo_asm_gcc.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xreg_cortexa9.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xreg_cortexa9.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xreg_cortexa9.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xreg_cortexa9.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xstatus.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xstatus.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xstatus.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xstatus.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.c new file mode 100644 index 0000000..a2443fe --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.c +* +* This file contains low level functions to get/set time from the Global Timer +* register in the ARM Cortex A9 MP core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Updated get/set time functions to make use Global Timer
+* 7.5   mus    04/30/21  Moved pragma message from xtime_l.h to xtime_l.c, to avoid
+*                        displaying same warnings multiple times. It fixes CR#1090562.
+*
    +* +* @note None. +* +******************************************************************************/ +/***************************** Include Files *********************************/ + +#include "xtime_l.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) +#pragma message ("For the sleep routines, Global timer is being used") +#endif +/****************************************************************************/ +/** +* @brief Set the time in the Global Timer Counter Register. +* +* @param Xtime_Global: 64-bit Value to be written to the Global Timer +* Counter Register. +* +* @return None. +* +* @note When this function is called by any one processor in a multi- +* processor environment, reference time will reset/lost for all +* processors. +* +****************************************************************************/ +void XTime_SetTime(XTime Xtime_Global) +{ + /* Disable Global Timer */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0); + + /* Updating Global Timer Counter Register */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global); + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET, + (u32)((u32)(Xtime_Global>>32U))); + + /* Enable Global Timer */ + Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1); +} + +/****************************************************************************/ +/** +* @brief Get the time from the Global Timer Counter Register. +* +* @param Xtime_Global: Pointer to the 64-bit location which will be +* updated with the current timer value. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XTime_GetTime(XTime *Xtime_Global) +{ + u32 low; + u32 high; + + /* Reading Global Timer Counter Register */ + do + { + high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET); + low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET); + } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high); + + *Xtime_Global = (((XTime) high) << 32U) | (XTime) low; +} diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h new file mode 100644 index 0000000..9d17f5c --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_0/src/xtime_l.h @@ -0,0 +1,86 @@ +/****************************************************************************** +* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Updated get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Updated get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
+* 6.8   aru  09/06/18 Removed compilation warnings for ARMCC toolchain.
+* 7.5   mus    04/30/21  Moved pragma message from xtime_l.h to xtime_l.c, to avoid
+*                        displaying same warnings multiple times. It fixes CR#1090562.
+*
    +* +******************************************************************************/ + +/** +*@cond nocomments +*/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +#endif +/************************** Variable Definitions *****************************/ + +/** +*@endcond +*/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/Makefile new file mode 100644 index 0000000..5feeb49 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/Makefile @@ -0,0 +1,39 @@ +DRIVER_LIB_VERSION = 1.0 +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib/ +INCLUDEDIR=../../../include/ +INCLUDES=-I./. -I$(INCLUDEDIR) + +SRCFILES:=$(wildcard *.c) + +OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c)))) + +libs: $(OBJECTS) + +DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d) + +include $(wildcard $(DEPFILES)) + +include $(wildcard ../../../../dep.mk) + +$(RELEASEDIR)%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@ + +.PHONY: include +include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) + +$(INCLUDEDIR)%.h: %.h + $(CP) $< $@ + +clean: + rm -rf ${OBJECTS} + rm -rf $(DEPFILES) diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c new file mode 100644 index 0000000..6872364 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_g.c @@ -0,0 +1,33 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xuartps.h" + +/* +* The configuration table for devices +*/ + +XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_UART_1_DEVICE_ID, + XPAR_PS7_UART_1_BASEADDR, + XPAR_PS7_UART_1_UART_CLK_FREQ_HZ, + XPAR_PS7_UART_1_HAS_MODEM + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_hw.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_hw.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/uartps/src/xuartps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_options.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_options.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_options.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_options.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/uartps/src/xuartps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_13/src/xuartps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/CMakeLists.txt old mode 100755 new mode 100644 similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c new file mode 100644 index 0000000..197994e --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: 2023.2 +* DO NOT EDIT. +* +* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xadcps.h" + +/* +* The configuration table for devices +*/ + +XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_XADC_0_DEVICE_ID, + XPAR_PS7_XADC_0_BASEADDR + } +}; + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_hw.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_hw.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/libsrc/xadcps/src/xadcps_hw.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_hw.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps_intr.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_intr.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps_intr.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_intr.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps_selftest.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_selftest.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps_selftest.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_selftest.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps_sinit.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_sinit.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xadcps/src/xadcps_sinit.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_sinit.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/diskio.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/diskio.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/diskio.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/diskio.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/ff.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/ff.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/ff.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/ff.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/ffsystem.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/ffsystem.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/ffsystem.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/ffsystem.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/ffunicode.c b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/ffunicode.c similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/ffunicode.c rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/ffunicode.c diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/include/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/include/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/diskio.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/diskio.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/diskio.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/diskio.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/ff.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/ff.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/ff.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/ff.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/ffconf.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/ffconf.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/ffconf.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/include/ffconf.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/xilffs.cmake b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/xilffs.cmake similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/xilffs.cmake rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/xilffs.cmake diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/xilffs_config.h.in b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/xilffs_config.h.in similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilffs/src/xilffs_config.h.in rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_1/src/xilffs_config.h.in diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilrsa/src/CMakeLists.txt b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/CMakeLists.txt similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilrsa/src/CMakeLists.txt rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/CMakeLists.txt diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilrsa/src/Makefile b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/Makefile similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/xilrsa/src/Makefile rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/Makefile diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xilrsa.h b/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/include/xilrsa.h similarity index 100% rename from 2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard_bsp/zynq_fsbl/zynq_fsbl_bsp/libsrc/build_configs/gen_bsp/include/xilrsa.h rename to 2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/include/xilrsa.h diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.cproject b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.cproject new file mode 100644 index 0000000..0f37da0 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.cproject @@ -0,0 +1,352 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.gitignore b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.gitignore new file mode 100644 index 0000000..ac01e66 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.gitignore @@ -0,0 +1,2 @@ +/Debug/ +/Release/ diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.project b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.project new file mode 100644 index 0000000..dc1c437 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/.project @@ -0,0 +1,27 @@ + + + NewInstrCalBoard + Created by Vitis v2023.2 + + NewInstCal_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.xilinx.sdx.sdk.core.SdkProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/NewInstrCalBoard.prj b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/NewInstrCalBoard.prj new file mode 100644 index 0000000..cae92f5 --- /dev/null +++ b/2.FW/Zynq/proj_cal/Vitis/NewInstrCalBoard/NewInstrCalBoard.prj @@ -0,0 +1,11 @@ + + + + + + + + + +