yuysh/NewInstrCalBoard
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add PMU DC Control part

Browse Source
This commit is contained in:
Jeremy Shen
2026-05-20 10:05:48 +08:00
parent 79d5a810dc
commit 248a54b777
1 changed files with 126 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
2.FW/CPLD1/CPLD_Con.v
+122 -12
View File
@@ -22,12 +22,17 @@ module CPLD_Con (
output o_IO_RC1, output o_IO_RC1,
output [4:0]o_RC_Tx, output [4:0]o_RC_Tx,
output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 ,
output [31:0]o_PMU_OC_3 ,
output [31:0]o_PMU_OC_4 ,
// DMM Mode Sel // DMM Mode Sel
output o_RC_VSel; output o_RC_VSel,
output o_RC_ISel; output o_RC_ISel,
// Output RLoad Sel // Output RLoad Sel
output [17:0]o_RC_RLSel; output [17:0]o_RC_RLSel,
// FLAGs // FLAGs
output o_con_done, output o_con_done,
@@ -42,6 +47,13 @@ module CPLD_Con (
reg[4:0]RC_Tx; reg[4:0]RC_Tx;
reg io_RC; reg io_RC;
reg RC_VISel;
reg [17:0]RC_RLSel ;
reg [31:0]PMU_OC_1 ;
reg [31:0]PMU_OC_2 ;
reg [31:0]PMU_OC_3 ;
reg [31:0]PMU_OC_4 ;
//Condition Tester //Condition Tester
reg [15:0]en_t ; reg [15:0]en_t ;
reg freq_t; reg freq_t;
@@ -96,22 +108,29 @@ module CPLD_Con (
OC_x01 <= 'd0; OC_x01 <= 'd0;
OC_x17 <= 'd0; OC_x17 <= 'd0;
io_RC <= 'd0;
o_RC_VSel <='d0; DMM_en <= 'd0;
o_RC_ISel <='d0;
o_RC_RLSel <='d0; RC_VISel <='d0;
RC_RLSel <='d0;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
done_flag <= 'd1; done_flag <= 'd1;
end end
else begin else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
exec_flag <= 1'b1;
done_flag <= 1'b0;
//To DO: More Sanity Check? //To DO: More Sanity Check?
if (en_t > 'd1) begin //Only ONE Enable bit should be set! if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1; err_flag <= 1'b1;
end end
else begin else begin
exec_flag <= 1'b1;
done_flag <= 1'b0;
err_flag <= 1'b0;
freq_slot_flag[0] <= i_freq_relay1[0]; freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0]; freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0]; freq_slot_flag[2] <= i_freq_relay3[0];
@@ -228,21 +247,102 @@ module CPLD_Con (
else if (dc_t == 1'b1) begin else if (dc_t == 1'b1) begin
case (dc_slot_flag) case (dc_slot_flag)
4'b0001: begin 4'b0001: begin
if (i_DC_Con1[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1);
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
end
end
end end
4'b0010: begin 4'b0010: begin
if (i_DC_Con2[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1);
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
end
end
end end
4'b0100:begin 4'b0100:begin
if (i_DC_Con3[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1);
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
end
end
end end
4'b1000:begin 4'b1000:begin
if (i_DC_Con4[22] == 1'b1) begin
RC_VISel <= 1'b1; //Select Current
end
else begin
RC_VISel <= 1'b0; //Select Voltage
end
//Sanity Check
if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
err_flag <= 1'b1;
end
else begin
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
end
end
end end
default:begin // You Should NOT be HERE default:begin // You Should NOT be HERE
o_RC_VSel <='d0; RC_VISel <='d0;
o_RC_ISel <='d0; RC_RLSel <='d0;
o_RC_RLSel <='d0;
PMU_OC_1 <= 'd0 ;
PMU_OC_2 <= 'd0 ;
PMU_OC_3 <= 'd0 ;
PMU_OC_4 <= 'd0 ;
DMM_en <= 'd0;
end end
endcase endcase
end end
@@ -262,5 +362,15 @@ module CPLD_Con (
assign o_err = err_flag; assign o_err = err_flag;
assign o_RC_Tx = RC_Tx; assign o_RC_Tx = RC_Tx;
assign o_RC_ISel = (RC_VISel==1'b1)?1:0;
assign o_RC_VSel = (RC_VISel==1'b1)?0:1;
assign o_RC_RLSel = RC_RLSel;
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2 = PMU_OC_2;
assign o_PMU_OC_3 = PMU_OC_3;
assign o_PMU_OC_4 = PMU_OC_4;
endmodule endmodule