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Increase the version of CPLD1

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This commit is contained in:
Jeremy Shen
2026-05-21 11:33:20 +08:00
parent 7096f94f47
commit 13611d20a0
3 changed files with 47 additions and 40 deletions
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2.FW/CPLD1/.spreadsheet_view.ini
+1 -1
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@@ -6,7 +6,7 @@ sig_sort_ascending=true
active_Sheet=Port Assignments active_Sheet=Port Assignments
[Port%20Assignments] [Port%20Assignments]
Name="216,0" Name="207,0"
Group%20By="118,1" Group%20By="118,1"
Pin="71,2" Pin="71,2"
BANK="91,3" BANK="91,3"
2.FW/CPLD1/Reg_file.v
+1 -1
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@@ -35,7 +35,7 @@ module Reg_file (
// --- Parameters --- // --- Parameters ---
localparam REG_COUNT = 16; localparam REG_COUNT = 16;
localparam [23:0] localparam [23:0]
IDENT = 24'h200000 || 12'b0001_0000_0000, //CPLD1==1,version=1.0.0 IDENT = 24'h200000 | 12'b0001_0001_0000, //CPLD1==1,version=1.1.0
STATE_INIT = 24'h800000; STATE_INIT = 24'h800000;
// State Machine Definition // State Machine Definition
3.FW_Docs/CPLD_Firmware_Architecture.md
+45 -38
View File
@@ -95,8 +95,8 @@ IDLE → CMD_SENT → DONE → IDLE
**Register Map:** **Register Map:**
| Addr | Name | R/W | Description | | Addr | Name | R/W | Description |
|------|------|-----|-------------| |------|------|-----|-------------|
| 0 | IDENT | R/W | Identity: `24'h200000` (CPLD3=0, CPLD2=0, CPLD1=1, Major=2, Minor=0, Rev=0) | | 0 | IDENT | R/W | Identity: CPLD3=0, CPLD2=0, CPLD1=1, Major=1, Minor=0, Rev=0 |
| 1 | STATE | R/W | State/Execution control. Bit 0 = EXEC trigger, Bit 23 = RDY, Bits 22:20 = Level | | 1 | STATE | R/W | State/Execution control. Bit 0 = EXEC trigger, Bit 23 = RDY, Bits 22:1 = Reserved |
| 2 | Freq_Slot1 | R/W | Frequency slot 1 relay control | | 2 | Freq_Slot1 | R/W | Frequency slot 1 relay control |
| 3 | Freq_Slot2 | R/W | Frequency slot 2 relay control | | 3 | Freq_Slot2 | R/W | Frequency slot 2 relay control |
| 4 | Freq_Slot3 | R/W | Frequency slot 3 relay control | | 4 | Freq_Slot3 | R/W | Frequency slot 3 relay control |
@@ -111,21 +111,12 @@ IDLE → CMD_SENT → DONE → IDLE
**Freq_Slot N (Addr 2-5):** **Freq_Slot N (Addr 2-5):**
``` ```
Bit 23:8: Per Relay_Control (1=Switch, 0=Not Switch) Bit 23:10: Per Relay_Control (1=Switch, 0=Not Switch) — 14 bits, one per relay
Bit 17:12: RC_Tx (for Slot 4 only) — 6 bits (T27-T32), updated from [14:10] Bit 9:1: Channel_Number (1-256) — 9 bits
Bit 9:1: Channel_Number (1-256)
Bit 0: Slot_EN (1=Enable) Bit 0: Slot_EN (1=Enable)
``` ```
**Relay Control Bits per Slot (from Excel Freq_CPLD sheet):** **RC_Tx Mapping (Slot 4 only, part of Per Relay_Control bits 17:12):**
| Slot | RC_F | RC_S | RC_T |
|------|------|------|------|
| 1 | RC_F1, RC_F2 | RC_S1-RC_S4 | RC_T1-RC_T8 |
| 2 | RC_F3, RC_F4 | RC_S5-RC_S8 | RC_T9-RC_T16 |
| 3 | RC_F5, RC_F6 | RC_S9-RC_S12 | RC_T17-RC_T24 |
| 4 | RC_F7, RC_F8 | RC_S13-RC_S16 | RC_T25-RC_T32 |
**RC_Tx Mapping (CPLD1):**
| RC_Tx Bit | Output Pin | | RC_Tx Bit | Output Pin |
|-----------|-----------| |-----------|-----------|
| [5] | o_RC_T27 | | [5] | o_RC_T27 |
@@ -135,15 +126,23 @@ Bit 0: Slot_EN (1=Enable)
| [1] | o_RC_T31 | | [1] | o_RC_T31 |
| [0] | o_RC_T32 | | [0] | o_RC_T32 |
**Source:** `i_freq_relay4[17:12]` → `RC_Tx[5:0]` (updated from [14:10] in old version) **Source:** `i_freq_relay4[17:12]` → `RC_Tx[5:0]` (part of Per Relay_Control field)
**Relay Control Bits per Slot (from Excel Freq_CPLD sheet):**
| Slot | RC_F | RC_S | RC_T |
|------|------|------|------|
| 1 | RC_F1, RC_F2 | RC_S1-RC_S4 | RC_T1-RC_T8 |
| 2 | RC_F3, RC_F4 | RC_S5-RC_S8 | RC_T9-RC_T16 |
| 3 | RC_F5, RC_F6 | RC_S9-RC_S12 | RC_T17-RC_T24 |
| 4 | RC_F7, RC_F8 | RC_S13-RC_S16 | RC_T25-RC_T32 |
**DC_Slot N (Addr 6-9):** **DC_Slot N (Addr 6-9):**
``` ```
Bit 23: PMU(0)/DPS(1) — PMU or DPS mode select Bit 23: PMU(0)/DPS(1) — PMU or DPS mode select
Bit 22: V(0)/I(1) — Voltage or Current select Bit 22: V(0)/I(1) — Voltage or Current select
Bit 21:17: Rload_Sel (0-31) — Resistor selection (5-bit, 0-31 range) Bit 21:17: Rload_Sel (0-31) — Resistor selection (5-bit, 0-31 range)
Bit 16: Reserved Bit 16:10: Reserved (7 bits)
Bit 9:1: Channel_Number (1-256) Bit 9:1: Channel_Number (1-256) — 9 bits
Bit 0: Slot_EN (1=Enable) Bit 0: Slot_EN (1=Enable)
``` ```
@@ -208,21 +207,21 @@ IDLE → BUSY → EXEC_ACK → EXEC_WAIT → IDLE
|--------|-------|-------------| |--------|-------|-------------|
| `o_OC_x01` | 4:0 | OC relay selector (CPLD1: 4-bit, CPLD2: 4-bit) | | `o_OC_x01` | 4:0 | OC relay selector (CPLD1: 4-bit, CPLD2: 4-bit) |
| `o_OC_x17` | 4:0 | OC relay selector (CPLD1: 4-bit, CPLD2: 4-bit) | | `o_OC_x17` | 4:0 | OC relay selector (CPLD1: 4-bit, CPLD2: 4-bit) |
| `o_RC_F[7:0]` | 8:0 | RC_F relays (CPLD2 only) | | `o_RC_F[7:0]` | 8 | RC_F relays (CPLD2 only) |
| `o_RC_S[15:0]` | 16:0 | RC_S relays (CPLD2 only) | | `o_RC_S[15:0]` | 16 | RC_S relays (CPLD2 only) |
| `o_RC_T[5:0]` | 6:0 | RC_T relays (CPLD1: 6 bits T27-T32, CPLD2: 26 bits) | | `o_RC_T[5:0]` | 6 | RC_T relays (CPLD1: 6 bits T27-T32, CPLD2: 26 bits) |
| `o_RC_T27-T32` | 6:0 | RC_T relays (CPLD1 only, expanded from 5 bits) | | `o_RC_T27-T32` | 6 | RC_T relays (CPLD1 only, expanded from 5 bits) |
| `o_RC_RLSel[17:0]` | 18:0 | Resistor load select (CPLD1 only) | | `o_RC_RLSel[17:0]` | 18 | Resistor load select (CPLD1 only) |
| `o_RC_VSel` | 1:0 | Voltage select (CPLD1 only) | | `o_RC_VSel` | 1 | Voltage select (CPLD1 only) |
| `o_RC_ISel` | 1:0 | Current select (CPLD1 only) | | `o_RC_ISel` | 1 | Current select (CPLD1 only) |
| `o_RC_LOF[1:0]` | 2:0 | DMM_N port relay LOF (CPLD1 only) | | `o_RC_LOF[1:0]` | 2 | DMM_N port relay LOF (CPLD1 only) |
| `o_RC_LOS[1:0]` | 2:0 | DMM_N port relay LOS (CPLD1 only) | | `o_RC_LOS[1:0]` | 2 | DMM_N port relay LOS (CPLD1 only) |
| `o_PMU_OC_[1-4][31:0]` | 32:0 | PMU output channel (CPLD1 only) | | `o_PMU_OC_[1-4][31:0]` | 32 | PMU output channel (CPLD1 only) |
| `o_PMU_RC[3:0]` | 4:0 | PMU relay control (CPLD3 only) | | `o_PMU_RC[3:0]` | 4 | PMU relay control (CPLD3 only) |
| `o_DMM_EN[18:0]` | 19:0 | DMM enable signals (CPLD1 only) | | `o_DMM_EN[18:0]` | 19 | DMM enable signals (CPLD1 only) |
| `o_IO_RC1` | 1:0 | IO relay control (CPLD1 only) | | `o_IO_RC1` | 1 | IO relay control (CPLD1 only) |
| `o_con_done` | 1:0 | Execution done flag | | `o_con_done` | 1 | Execution done flag |
| `o_err` | 1:0 | Error flag | | `o_err` | 1 | Error flag |
--- ---
@@ -384,32 +383,40 @@ Zynq FCLK_CLK0 → clk_wiz_0 → clk_out1 (100MHz) → CPLD SPI_Con IP
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPLD3 CPLD2 CPLD1 Reserved Major Version Minor Version Reversion CPLD3 CPLD2 CPLD1 Reserved Major Version Minor Version Reversion
``` ```
- CPLD3, CPLD2, CPLD1: Board identity flags (CPLD1=1 means board has CPLD1) - CPLD3, CPLD2, CPLD1: Board identity flags (CPLD1=1 means the CPLD communicating to IDENTIFY itself as CPLD1)
- Major Version: 2 - Major Version: 1
- Minor Version: 0 - Minor Version: 0
- Reversion: 0 - Reversion: 0
### Freq_Slot Register (Addr 2-5) ### Freq_Slot Register (Addr 2-5)
``` ```
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Per Relay_Control (1=Switch, 0=Not Switch) Reserved Channel_Number Slot_EN Per Relay_Control (1=Switch, 0=Not Switch) Channel_Number Slot_EN
``` ```
- Bits 23:10: Per Relay_Control (14 bits, one per relay per slot)
- Bits 9:1: Channel_Number (9 bits)
- Bit 0: Slot_EN (1=Enable)
### DC_Slot Register (Addr 6-9) ### DC_Slot Register (Addr 6-9)
``` ```
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPS V/I Rload_Sel (0-31) Reserved Channel_Number Slot_EN DPS V/I Rload_Sel (0-31) Reserved Channel_Number Slot_EN
``` ```
- Bit 23: DPS (0=PMU, 1=DPS)
- Bit 22: V/I (0=Voltage, 1=Current)
- Bits 21:17: Rload_Sel (0-31, 5-bit resistor selection)
- Bits 16:10: Reserved (7 bits)
- Bits 9:1: Channel_Number (9 bits)
- Bit 0: Slot_EN (1=Enable)
### STATE Register (Addr 1) ### STATE Register (Addr 1)
``` ```
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY Reserved EXEC Level1 Level2 Level3 RDY Reserved EXEC
``` ```
- Bit 23: RDY (ready flag) - Bit 23: RDY (ready flag)
- Bits 22:20: Reserved - Bits 22:1: Reserved (22 bits)
- Bit 0: EXEC (1=start execution) - Bit 0: EXEC (1=start execution)
- Bits 2:0: Level (Level1=MSB, Level2, Level3=LSB)
--- ---