
`timescale 1 ns / 1 ps

	module SPI_Con_v1_0 #
	(
		// Users to add parameters here

		// User parameters ends
		// Do not modify the parameters beyond this line


		// Parameters of Axi Slave Bus Interface S00_AXI
		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 7
	)
	(
		// Users to add ports here
		input  wire i_miso,
		output wire o_sclk,
		output wire o_cs,
		output wire o_mosi,


		// User ports ends
		// Do not modify the ports beyond this line


		// Ports of Axi Slave Bus Interface S00_AXI
		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);
// Public Reg
		reg [6:0]spi_addr ;
		reg [23:0]spi_data;
		reg w_req;
		reg r_req;
		reg spi_done;


// Instantiation of Axi Bus Interface S00_AXI
// This inst will handle actul AXI commiuncation and register read/write
	SPI_Con_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) SPI_Con_v1_0_S00_AXI_inst (
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready),
		.i_spi_data(spi_data),
		.i_spi_done(spi_done),
		.o_wreq(w_req),
		.o_spi_addr(spi_addr),
		.o_rreq(r_req)
	);

	// Add user logic here
	//SPI Reg
	reg mosi_reg;
	reg miso_reg;
	reg sclk_reg;
	reg cs_reg;
	
	//Flag reg
	reg busy_flag;


	always @(posedge s00_axi_aclk) begin
		if (s00_axi_aresetn == 1'b0) begin
			mosi_reg	<= 		1'b0;
			miso_reg	<= 		1'b0;
			sclk_reg	<= 		1'b0;
			cs_reg		<= 		1'b1;
			spi_done 	<=		1'b1;
		end
		else begin
			if ((w_req == 1'b1) | (r_req == 1'b1)) begin
				spi_done <= 1'b0;

			end
			else begin
				
			end
		end
	end

	assign o_cs = cs_reg;
	assign o_sclk = sclk_reg;
	assign o_mosi = mosi_reg;
	// User logic ends

	endmodule
