{
  "schema": "xilinx.com:schema:json_instance:1.0",
  "ip_inst": {
    "xci_name": "NewExtInst_TOP_proc_sys_reset_0_0",
    "cell_name": "proc_sys_reset_0",
    "component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
    "ip_revision": "14",
    "gen_directory": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0",
    "parameters": {
      "component_parameters": {
        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
        "Component_Name": [ { "value": "NewExtInst_TOP_proc_sys_reset_0_0", "resolve_type": "user", "usage": "all" } ],
        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
      },
      "model_parameters": {
        "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
      },
      "project_parameters": {
        "ARCHITECTURE": [ { "value": "zynq" } ],
        "BASE_BOARD_PART": [ { "value": "" } ],
        "BOARD_CONNECTIONS": [ { "value": "" } ],
        "DEVICE": [ { "value": "xc7z035" } ],
        "PACKAGE": [ { "value": "ffg676" } ],
        "PREFHDL": [ { "value": "VERILOG" } ],
        "SILICON_REVISION": [ { "value": "" } ],
        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
        "SPEEDGRADE": [ { "value": "-2" } ],
        "STATIC_POWER": [ { "value": "" } ],
        "TEMPERATURE_GRADE": [ { "value": "" } ],
        "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
        "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
      },
      "runtime_parameters": {
        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
        "IPREVISION": [ { "value": "14" } ],
        "MANAGED": [ { "value": "TRUE" } ],
        "OUTPUTDIR": [ { "value": "../../../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_proc_sys_reset_0_0" } ],
        "SELECTEDSIMMODEL": [ { "value": "" } ],
        "SHAREDDIR": [ { "value": "../../ipshared" } ],
        "SWVERSION": [ { "value": "2023.2" } ],
        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
      }
    },
    "boundary": {
      "ports": {
        "slowest_sync_clk": [ { "direction": "in" } ],
        "ext_reset_in": [ { "direction": "in" } ],
        "aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
        "mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
        "dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
        "mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
        "bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
        "peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
        "interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
        "peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
      },
      "interfaces": {
        "clock": {
          "vlnv": "xilinx.com:signal:clock:1.0",
          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "FREQ_HZ": [ { "value": "25000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
            "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
            "CLK_DOMAIN": [ { "value": "NewExtInst_TOP_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "CLK": [ { "physical_name": "slowest_sync_clk" } ]
          }
        },
        "ext_reset": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "ext_reset_in" } ]
          }
        },
        "aux_reset": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "aux_reset_in" } ]
          }
        },
        "dbg_reset": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "slave",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "mb_debug_sys_rst" } ]
          }
        },
        "mb_rst": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "master",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "mb_reset" } ]
          }
        },
        "bus_struct_reset": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "master",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "bus_struct_reset" } ]
          }
        },
        "interconnect_low_rst": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "master",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "interconnect_aresetn" } ]
          }
        },
        "peripheral_high_rst": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "master",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "peripheral_reset" } ]
          }
        },
        "peripheral_low_rst": {
          "vlnv": "xilinx.com:signal:reset:1.0",
          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
          "mode": "master",
          "parameters": {
            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "RST": [ { "physical_name": "peripheral_aresetn" } ]
          }
        }
      }
    }
  }
}