verilog xil_defaultlib --include "/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" --include "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ec67/hdl" --include "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/6b2b/hdl" --include "../../../../NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/c2c6" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_processing_system7_0_0/sim/NewExtInst_TOP_processing_system7_0_0.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0_clk_wiz.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_clk_wiz_0_0/NewExtInst_TOP_clk_wiz_0_0.v" \
"../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0_S00_AXI.v" \
"../../../bd/NewExtInst_TOP/ipshared/8878/hdl/SPI_Con_v1_0.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_0/sim/NewExtInst_TOP_SPI_Con_0_0.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_1/sim/NewExtInst_TOP_SPI_Con_0_1.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_SPI_Con_0_2/sim/NewExtInst_TOP_SPI_Con_0_2.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_xbar_0/sim/NewExtInst_TOP_xbar_0.v" \
"../../../bd/NewExtInst_TOP/ip/NewExtInst_TOP_auto_pc_0/sim/NewExtInst_TOP_auto_pc_0.v" \
"../../../bd/NewExtInst_TOP/sim/NewExtInst_TOP.v" \

verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort
