#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Fri May 15 15:26:41 2026
# Process ID: 123451
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1
# Command line: vivado -log NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vds
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/vivado.jou
# Running On: mkb, OS: Linux, CPU Frequency: 4998.693 MHz, CPU Physical cores: 32, Host memory: 134145 MB
#-----------------------------------------------------------
source NewExtInst_TOP_rst_clk_wiz_0_100M_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/ly0kos/work/Zynq/ip_repo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: NewExtInst_TOP_rst_clk_wiz_0_100M_0
Command: synth_design -top NewExtInst_TOP_rst_clk_wiz_0_100M_0 -part xc7z035ffg676-2 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
INFO: [Device 21-403] Loading part xc7z035ffg676-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 123548
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Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2112.535 ; gain = 402.715 ; free physical = 32328 ; free virtual = 94154
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INFO: [Synth 8-638] synthesizing module 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:74]
	Parameter C_FAMILY bound to: zynq - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b1 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:129]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
INFO: [Synth 8-256] done synthesizing module 'NewExtInst_TOP_rst_clk_wiz_0_100M_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/synth/NewExtInst_TOP_rst_clk_wiz_0_100M_0.vhd:74]
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
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Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2191.504 ; gain = 481.684 ; free physical = 31641 ; free virtual = 93467
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2206.348 ; gain = 496.527 ; free physical = 31623 ; free virtual = 93451
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2206.348 ; gain = 496.527 ; free physical = 31623 ; free virtual = 93451
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2212.285 ; gain = 0.000 ; free physical = 31616 ; free virtual = 93444
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_ooc.xdc] for cell 'U0'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] for cell 'U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0_board.xdc] for cell 'U0'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] for cell 'U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc] for cell 'U0'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.gen/sources_1/bd/NewExtInst_TOP/ip/NewExtInst_TOP_rst_clk_wiz_0_100M_0/NewExtInst_TOP_rst_clk_wiz_0_100M_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/NewExtInst_TOP_rst_clk_wiz_0_100M_0_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/NewExtInst_TOP_rst_clk_wiz_0_100M_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.098 ; gain = 0.000 ; free physical = 31382 ; free virtual = 93210
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 13 instances were transformed.
  FDR => FDRE: 12 instances
  SRL16 => SRL16E: 1 instance 

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31381 ; free virtual = 93209
INFO: [Designutils 20-5008] Incremental synthesis strategy off
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Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077
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Start Loading Part and Timing Information
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Loading part: xc7z035ffg676-2
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077
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Start Applying 'set_property' XDC Constraints
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Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file  /home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/dont_touch.xdc, line 9).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31246 ; free virtual = 93077
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31243 ; free virtual = 93075
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Start RTL Component Statistics 
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Detailed RTL Component Info : 
+---Adders : 
	   2 Input    6 Bit       Adders := 1     
+---Registers : 
	                6 Bit    Registers := 1     
	                3 Bit    Registers := 3     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input    6 Bit        Muxes := 1     
	   2 Input    1 Bit        Muxes := 1     
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Finished RTL Component Statistics 
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Start Part Resource Summary
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Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31257 ; free virtual = 93092
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31284 ; free virtual = 93120
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31284 ; free virtual = 93120
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31262 ; free virtual = 93097
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
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Start Writing Synthesis Report
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Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+------+------+
|      |Cell  |Count |
+------+------+------+
|1     |LUT1  |     5|
|2     |LUT2  |     9|
|3     |LUT3  |     1|
|4     |LUT4  |     6|
|5     |LUT5  |     3|
|6     |LUT6  |     1|
|7     |SRL16 |     1|
|8     |FDR   |     8|
|9     |FDRE  |    28|
|10    |FDSE  |     4|
+------+------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31144 ; free virtual = 92979
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2351.133 ; gain = 496.527 ; free physical = 31392 ; free virtual = 93228
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2351.133 ; gain = 641.312 ; free physical = 31392 ; free virtual = 93228
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31392 ; free virtual = 93228
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.133 ; gain = 0.000 ; free physical = 31675 ; free virtual = 93510
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 9 instances were transformed.
  FDR => FDRE: 8 instances
  SRL16 => SRL16E: 1 instance 

Synth Design complete | Checksum: 2497e3b9
INFO: [Common 17-83] Releasing license: Synthesis
49 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 2351.133 ; gain = 1058.770 ; free physical = 31968 ; free virtual = 93804
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1679.910; main = 1379.216; forked = 307.635
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3321.746; main = 2351.102; forked = 1002.660
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2375.109 ; gain = 0.000 ; free physical = 31968 ; free virtual = 93804
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP NewExtInst_TOP_rst_clk_wiz_0_100M_0, cache-ID = 2e8c33c5e53a7d6d
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2375.109 ; gain = 0.000 ; free physical = 31970 ; free virtual = 93804
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/NewExtInst_Debug/NewExtInst_Debug.runs/NewExtInst_TOP_rst_clk_wiz_0_100M_0_synth_1/NewExtInst_TOP_rst_clk_wiz_0_100M_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.rpt -pb NewExtInst_TOP_rst_clk_wiz_0_100M_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri May 15 15:26:59 2026...
