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Formal_NewInstrCalBoard_Zynq/.gitignore
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2026-06-17 09:48:54 +08:00

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# =============================================================================
# .gitignore — Xilinx Vitis Embedded Project (Zynq-7000)
# Workspace: Cal_Net/
#
# Strategy:
# IGNORE: build outputs, IDE workspace state, BSP (regenerated).
# TRACK: source (.c/.h/.ld), project config, hardware outputs
# (.xsa/.bit/.elf/.bin), wizard files (.spr/.sprj), Tcl scripts.
# =============================================================================
# ----- BSP (ignore generated, keep project config for regeneration) -----
NewExtInst_bsp/*
!NewExtInst_bsp/.project
!NewExtInst_bsp/.cproject
!NewExtInst_bsp/platform.spr
!NewExtInst_bsp/platform.tcl
# ----- Build Output Directories (contents only) -----
# Using "/*" instead of "/" so negation rules can un-ignore deliverables.
*/Debug/*
*/Release/*
# ----- Object & Dependency Files -----
*.o
*.d
# ----- Logs -----
*.log
*.jou
IDE.log
# ----- IDE / Eclipse Workspace State -----
.metadata/
.analytics
RemoteSystemsTempFiles/
# ----- Xilinx Tool Caches -----
.Xil/
*/_ide/*
!*/_ide/bitstream/
# ----- OS / Editor Files -----
.DS_Store
Thumbs.db
*.swp
*~
*.bak
*.swo
# ----- Python Cache -----
__pycache__/
*.pyc
# =============================================================================
# Deliverables — explicitly tracked
# (negation rules override the ignore patterns above)
# =============================================================================
!*/Debug/*.elf
!*/Debug/sd_card/
!*/_ide/bitstream/*.bit