Init commit
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,352 @@
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<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1694882736;xilinx.gnu.armv7.exe.release.1694882736.;xilinx.gnu.armv7.c.toolchain.compiler.release.554812800;xilinx.gnu.armv7.c.compiler.input.1545730065">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.969390879;xilinx.gnu.armv7.exe.debug.969390879.;xilinx.gnu.armv7.c.toolchain.compiler.debug.1541541655;xilinx.gnu.armv7.c.compiler.input.6848140">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1694882736;xilinx.gnu.armv7.exe.release.1694882736.">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.969390879;xilinx.gnu.armv7.exe.debug.969390879.">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
|
||||
</cproject>
|
||||
@@ -0,0 +1,3 @@
|
||||
/Debug/*
|
||||
/Release/*
|
||||
!/Debug/*.elf
|
||||
@@ -0,0 +1,27 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>NewExtInst_Zynq_Net</name>
|
||||
<comment>Created by Vitis v2023.2</comment>
|
||||
<projects>
|
||||
<project>NewExtInst_bsp</project>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.xilinx.sdx.sdk.core.SdkProjectNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
BIN
Binary file not shown.
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="NewExtInst_Zynq_Net" location="/data/work/prj/New_CalBoard/2.FW/Zynq/Cal_Net/NewExtInst_Zynq_Net" platform="/data/work/prj/New_CalBoard/2.FW/Zynq/Cal_Net/NewExtInst_bsp/export/NewExtInst_bsp/NewExtInst_bsp.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="NewExtInst_Zynq_Net_system" sysConfig="NewExtInst_bsp" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="ff8a910e349ea3dc17a7c935b1743124">
|
||||
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.969390879">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
</configuration>
|
||||
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.1694882736" dirty="true">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
</configuration>
|
||||
<template appTemplateName="empty_application"/>
|
||||
</sdkproject:SdkProject>
|
||||
Binary file not shown.
@@ -0,0 +1,77 @@
|
||||
#include "CPLD_Con.h"
|
||||
|
||||
int CPLD_Write(u8 addr,u32 data)
|
||||
{
|
||||
u16 reg_addr = addr | 0x80; //Write bit set to 1'b1
|
||||
u8 reg_data[dat_width] = {0};
|
||||
//Data Sanity Check
|
||||
if ((data >> 24) > 0)
|
||||
{
|
||||
|
||||
xil_printf("[E] CPLD data length should within 24 bits!\r\n");
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
reg_data[0] = (u8)(data >> 16);
|
||||
reg_data[1] = (u8)(((data)&0xff00)>>8);
|
||||
reg_data[2] = (u8)data;
|
||||
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U3);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data)
|
||||
{
|
||||
switch (CPLDSel)
|
||||
{
|
||||
case 1:
|
||||
{
|
||||
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
|
||||
break;
|
||||
}
|
||||
case 3:
|
||||
{
|
||||
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
xil_printf("[E] CPLD Select Num Error (Range 1-3)\r\n");
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int CPLD_Read_ALL(u8 reg_addr, u32* reg_data)
|
||||
{
|
||||
//TODO:Sanity Check
|
||||
reg_data[0]=uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
|
||||
reg_data[1]=uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
|
||||
reg_data[2]=uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
|
||||
|
||||
//TODO:SUCCESS Check
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
int CPLD_exec()
|
||||
{
|
||||
u8 reg_addr = 0x01;
|
||||
u8 sw_config_data[3] = {0x00,0x00,0x00};
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
|
||||
reg_addr = reg_addr | 0x80;
|
||||
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
#ifndef CPLD_CON_H_
|
||||
#define CPLD_CON_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <xstatus.h>
|
||||
#include <xparameters.h>
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
|
||||
#define dat_width 3
|
||||
|
||||
int CPLD_Write(u8 addr,u32 data);
|
||||
int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data);
|
||||
int CPLD_Read_ALL(u8 reg_addr, u32* reg_data);
|
||||
|
||||
int CPLD_exec();
|
||||
|
||||
|
||||
#endif /* CPLD_CON_H_ */
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
#include "xil_printf.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
int EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_XGPIOPS_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
{
|
||||
xil_printf("[E] PS GPIO LookupConfig failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
else
|
||||
{
|
||||
xil_printf("[D] Successfully Find PS GPIO!\r\n");
|
||||
}
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
{
|
||||
xil_printf("[E] PS GPIO INIT FAILED \n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 0);//79---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 1);//80---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
xil_printf("[I] PS GPIO Init Done!\r\n");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* GPIO_Driv.h
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_GPIO_DRIV_H_
|
||||
#define SRC_GPIO_DRIV_H_
|
||||
|
||||
#include "stdio.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
|
||||
extern u32 CPLD_U1[11];
|
||||
extern u32 CPLD_U2[11];
|
||||
extern u32 CPLD_U3[11];
|
||||
|
||||
int EMIO_config(void);
|
||||
|
||||
#endif /* SRC_GPIO_DRIV_H_ */
|
||||
@@ -0,0 +1 @@
|
||||
Empty application. Add your own sources.
|
||||
@@ -0,0 +1,626 @@
|
||||
/*
|
||||
* SPI_Driv.c
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "SPI_Driv.h"
|
||||
|
||||
extern XGpioPs psGpioInstancePtr; //端口
|
||||
extern XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
|
||||
|
||||
extern u32 K7_U0[16];
|
||||
extern u32 molex_4_bank_3[4];
|
||||
extern u32 cs_en_bank_3[4];
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void interface_initial(u32* device,u32 num_wire)
|
||||
* Description : interface initial
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void interface_initial(u32* device) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void rst_CPLD(u32* device,u32 num_wire)
|
||||
* Description : CPLD reset
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 rst_n = *(device+num_wire);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
usleep(2);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
|
||||
* Description : spi onewire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device)
|
||||
{
|
||||
char temp_addr = 0;
|
||||
//u32 temp_data = 0;
|
||||
u32 temp_data = 0;
|
||||
char i = 0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
|
||||
temp_addr = addr;
|
||||
///temp_data = data;
|
||||
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0;j<width;j++)
|
||||
{
|
||||
temp_data = *(data+j);
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_data <<= 1;
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
|
||||
* Description : spi onewire read
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void //??????
|
||||
******************************************************************************/
|
||||
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
|
||||
{
|
||||
char temp_addr=0;
|
||||
u32 temp_data=0;
|
||||
char i=0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
u32 sdo= *(device+3);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0; j<width; j++)
|
||||
{
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
|
||||
temp_data = temp_data| 0x00000001;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
read_data[0] = (u8)(temp_data>>16);
|
||||
read_data[1] = (u8)(temp_data>>8);
|
||||
read_data[0] = (u8)(temp_data);
|
||||
return temp_data;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u32 uspi_read_onewire(char addr, char width, u32* device)
|
||||
* Description : spi onewire read
|
||||
* Parameter : addr -- 地址
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : u32 reg_data
|
||||
******************************************************************************/
|
||||
u32 uspi_read_onewire(char addr, char width, u32* device)
|
||||
{
|
||||
char temp_addr=0;
|
||||
u32 temp_data=0;
|
||||
char i=0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
u32 sdo= *(device+3);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0; j<width; j++)
|
||||
{
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
|
||||
temp_data = temp_data| 0x00000001;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
return temp_data;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
* Description : forwire write to reg
|
||||
* Parameter : txdata--数据
|
||||
* sdi0,sdi1,sdi2,sdi3--IO
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
{
|
||||
switch(txdata & 0x0F)
|
||||
{
|
||||
case 0x00:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x01:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x05:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x06:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x07:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x08:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x09:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0A:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0B:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0C:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0D:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0E:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0F:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
* Description : spi fourwire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdi0 = *(device+2);
|
||||
u32 sdi1 = *(device+3);
|
||||
u32 sdi2 = *(device+4);
|
||||
u32 sdi3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
|
||||
{
|
||||
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
* Description : forwire read from reg
|
||||
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
|
||||
* Return : rxdata--数据
|
||||
******************************************************************************/
|
||||
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
{
|
||||
u32 GPIO_PIN[4];
|
||||
u16 rdata[4];
|
||||
u16 rxdata = 0;
|
||||
|
||||
GPIO_PIN[0] = sdo0;
|
||||
GPIO_PIN[1] = sdo1;
|
||||
GPIO_PIN[2] = sdo2;
|
||||
GPIO_PIN[3] = sdo3;
|
||||
|
||||
for(u8 i = 0; i < 4 ; i++)
|
||||
{
|
||||
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
|
||||
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
|
||||
rxdata = ((rdata[i])<<i) + rxdata ;
|
||||
}
|
||||
return rxdata;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
|
||||
* Description : spi fourwire read
|
||||
* Parameter : addr -- 地址
|
||||
* rxdata -- 数据
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i = 0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdio0 = *(device+2);
|
||||
u32 sdio1 = *(device+3);
|
||||
u32 sdio2 = *(device+4);
|
||||
u32 sdio3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
split_addr[0] = (temp_addr >> 4)&0x0F;
|
||||
split_addr[1] = (temp_addr)&0x0F;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
temp_data = temp_data<<4;
|
||||
temp_data = temp_data + split_data[i];
|
||||
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
|
||||
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
|
||||
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
|
||||
*rxdata = temp_data;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void GPIO_dir_set(u32* device,char dir)
|
||||
* Description : change GPIO direction
|
||||
* Parameter : device -- CPLD
|
||||
* dir -- GPIO_OUT/GPIO_IN
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void GPIO_dir_set_16(u32* device,char dir)
|
||||
{
|
||||
u32 sdio[16] = {0};
|
||||
u8 i;
|
||||
|
||||
for(i = 0; i < 16;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
|
||||
{
|
||||
u32 sdio[4] = {0};
|
||||
u8 i;
|
||||
u8 dir_temp = 0;
|
||||
|
||||
for(i = 0; i < 4;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
dir_temp = (((dir >> (3-i))) & 0x01);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void rst(char *d)
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
|
||||
usleep(20);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
}
|
||||
|
||||
|
||||
void func_test(void)
|
||||
{
|
||||
|
||||
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
|
||||
}
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPI_Driv.h
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_SPI_DRIV_H_
|
||||
#define SRC_SPI_DRIV_H_
|
||||
|
||||
#include "sleep.h"
|
||||
#include "stdio.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
#define wr_flag 1
|
||||
#define rd_flag 0
|
||||
|
||||
#define GPIO_OUT 1
|
||||
#define GPIO_IN 0
|
||||
|
||||
#define NUM_SCK_CMD 4
|
||||
#define NUM_SCK_ADDR 8
|
||||
#define NUM_SCK_LENGTH 4
|
||||
#define NUM_SCK_ENABLE 8
|
||||
#define NUM_SCK_BYTE 2
|
||||
|
||||
void interface_initial(u32* device);
|
||||
void rst_CPLD(u32* device,u32 num_wire);
|
||||
|
||||
void rst(char *d);
|
||||
|
||||
void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device);
|
||||
u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
|
||||
|
||||
u32 uspi_read_onewire(char addr, char width, u32* device);
|
||||
|
||||
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
|
||||
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
|
||||
void spi_write_fourwire(char addr,u16 data,u32* device);
|
||||
void spi_read_fourwire(char addr,u16* rxdata,u32* device);
|
||||
|
||||
void GPIO_dir_set_16(u32* device,char dir);
|
||||
void GPIO_dir_set_cs_enable(u32* device,u8 dir);
|
||||
|
||||
#endif /* SRC_SPI_DRIV_H_ */
|
||||
@@ -0,0 +1,2 @@
|
||||
*startfile:
|
||||
crti%O%s crtbegin%O%s
|
||||
@@ -0,0 +1,524 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023年7月19日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
|
||||
int Command_Parser(u8* recvbuffer, u8 len)
|
||||
{
|
||||
switch (recvbuffer[0])
|
||||
{
|
||||
case 0x00:
|
||||
{
|
||||
xil_printf("[D] Match Command CPLD Read\r\n");
|
||||
if (len != CPLD_SPI_READ + 1)
|
||||
{
|
||||
xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Read Format: \"00 [CPLD] [REG Addr]\"\r\n");
|
||||
}
|
||||
u32 reg_data = 0x0;
|
||||
reg_data = CPLD_Read(recvbuffer + 1, recvbuffer + 2, reg_data);
|
||||
xil_printf("[I] CPLD #%d: REG Addr #0x%01X: Data=0x%03X\r\n",recvbuffer + 1, recvbuffer + 2, reg_data);
|
||||
break;
|
||||
}
|
||||
case 0x01:
|
||||
{
|
||||
xil_printf("[D] Match Command CPLD Write\r\n");
|
||||
if (len != CPLD_SPI_WRITE + 1)
|
||||
{
|
||||
xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Write Format: \"01 [CPLD] [REG Addr] [Data]\"\r\n");
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
|
||||
xil_printf("[D] TBD!\r\n");
|
||||
break;
|
||||
}
|
||||
case 0xA0:
|
||||
{
|
||||
xil_printf("[D] Matched Command Reset\r\n");
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
rst_CPLD(CPLD_U3,4);
|
||||
xil_printf("[I] CPLD RST Done\r\n");
|
||||
break;
|
||||
}
|
||||
case 0xA1: //DC Cal
|
||||
{
|
||||
xil_printf("[D] Matched Command DC Cal\r\n");
|
||||
//Command Len Sanity Check
|
||||
if (len != DC_CMD_LEN + 1) //Do NOT forget the command header
|
||||
{
|
||||
xil_printf("[E] Command Length Mismatch!\r\n[I] DC Cal Format: \"A1 [01-04:SLOT] [01:PMU/02:DPS] [0001-0100:Channel_Num] [01:V/02:I] [01-12:RLoad]\"\r\n");
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
DC_Control(recvbuffer + 1); //Op-out the command header
|
||||
break;
|
||||
}
|
||||
case 0xA2: //Freq Cal
|
||||
{
|
||||
xil_printf("[D] Matched Command Freq Cal\r\n");
|
||||
if (len > Freq_CMD_LEN + 1) //Do NOT forget the command header
|
||||
{
|
||||
//TODO: ADD Freq Command Format Hint
|
||||
xil_printf("[E] Command Length Mismatch!\r\n[I] Freq Cal Format: TBD\r\n");
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
sw_config(recvbuffer + 1); //Op-out the command header
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
xil_printf("[E] Command Header No Match! \r\n[D] Received Command Header:0x%02X Check Command!\r\n",recvbuffer[0]);
|
||||
return XST_NO_FEATURE;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
int DC_Control(u8* idata)
|
||||
{
|
||||
//Comannd Parse Variables
|
||||
u8 u_slot = 0x0;
|
||||
u8 u_m_fun = 0x0; //PMU/DPS Sel
|
||||
u16 u_ch_Num = 0x0;
|
||||
u8 u_vi_Sel = 0x0; //DMM Connection Config
|
||||
u8 u_rLoad = 0x0; //rLoadSel
|
||||
|
||||
//CPLD Variables
|
||||
u8 reg_addr = 0x0;
|
||||
u32 reg_data = 0x0;
|
||||
|
||||
//Flags
|
||||
int Status = -255;
|
||||
int cmdValid = 1;
|
||||
|
||||
//We already did length check, so no need to do again here
|
||||
|
||||
u_slot = idata[0]; //1-4
|
||||
u_m_fun = idata[1]; //1:PMU/2:DPS
|
||||
u_ch_Num = (((u16)(idata[2])) << 8) | idata[3];
|
||||
u_vi_Sel = idata[4]; //1:V/2:I
|
||||
u_rLoad = idata[5]; //1~18: Refer to SCH/Protocol
|
||||
|
||||
//Let's do some sanity check
|
||||
//Slot
|
||||
if ((u_slot > 4) || (u_slot == 0))
|
||||
{
|
||||
xil_printf("[E] Illege Slot Num check Command! (Slot:1-4)\r\n");
|
||||
cmdValid = -1;
|
||||
}
|
||||
//Dev Sel
|
||||
if ((u_m_fun > 2) || (u_m_fun == 0))
|
||||
{
|
||||
xil_printf("[E] Illege Dev Select check Command! (1:PMU/2:DPS)\r\n");
|
||||
cmdValid = -2;
|
||||
}
|
||||
//Channel
|
||||
if (u_m_fun == 1) //PMU
|
||||
{
|
||||
|
||||
if ((u_ch_Num < 1) || (u_ch_Num > 256))
|
||||
{
|
||||
|
||||
xil_printf("[E] Illege Channel! (PMU Ch:0x0001-0x0100)\r\n");
|
||||
cmdValid = -2;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((u_ch_Num < 1) || (u_ch_Num > 64))
|
||||
{
|
||||
|
||||
xil_printf("[E] Illege Channel! (PMU Ch:0x0001-0x0040)\r\n");
|
||||
cmdValid = -3;
|
||||
}
|
||||
}
|
||||
|
||||
//V/I Sel
|
||||
if ((u_vi_Sel > 2) || (u_vi_Sel == 0))
|
||||
{
|
||||
xil_printf("[E] Illege V/I Config check Command! (1:V/2:I)\r\n");
|
||||
cmdValid = -5;
|
||||
}
|
||||
//RLoad Sel
|
||||
if ((u_rLoad > 18) || (u_rLoad == 0))
|
||||
{
|
||||
xil_printf("[E] Illege RLoad Select check Command! (RLoad:0x01-0x12)\r\n");
|
||||
cmdValid = -6;
|
||||
}
|
||||
if (cmdValid != 1)
|
||||
{
|
||||
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
|
||||
//DEBUG Printout
|
||||
xil_printf("[D] We Got:\r\n[-]\tSlot: #%d\r\n",u_slot);
|
||||
if (u_m_fun == 1)
|
||||
{
|
||||
|
||||
xil_printf("[-]\tDevice Select: PMU\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
xil_printf("[-]\tDevice Select: DPS\r\n");
|
||||
}
|
||||
xil_printf("[-]\tChannel Select: #%d\r\n",u_ch_Num);
|
||||
if (u_vi_Sel == 1)
|
||||
{
|
||||
|
||||
xil_printf("[-]\tDMM Measure Select: Voltage\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
xil_printf("[-]\tDMM Measure Select: Current\r\n");
|
||||
}
|
||||
xil_printf("[-]\tRLoad Select: #%d\r\n",u_rLoad);
|
||||
|
||||
//Sanity Check Done
|
||||
//Let's format the CPLD Reg Data
|
||||
|
||||
//As the structure of DC regs are the same, we can format the data uniformly
|
||||
//Dev Sel
|
||||
if (u_m_fun == 0x2)
|
||||
{
|
||||
reg_data = 0x800000; //1:DPS/0:PMU
|
||||
|
||||
}
|
||||
//V/I Sel
|
||||
if (u_vi_Sel == 0x2)
|
||||
{
|
||||
|
||||
reg_data = reg_data | 0x400000; //1:I/0:V
|
||||
}
|
||||
//RLoad Sel
|
||||
reg_data = reg_data | (((u32)u_rLoad)<<17);
|
||||
//Channel Sel
|
||||
reg_data = reg_data |((u32)(u_ch_Num)<<1) | 0x1; //0x1:Slot_EN
|
||||
|
||||
//We should clear out other slot's enable flag to prevent error
|
||||
Status = 0;
|
||||
//Note here as the CPLD_Write() will smartly set the R/W bit to 1'b1, so no need to handle that here, addr is addr
|
||||
switch (u_slot)
|
||||
{
|
||||
case 1:
|
||||
{
|
||||
|
||||
Status = Status + CPLD_Write(0x07, 0x0);
|
||||
Status = Status + CPLD_Write(0x08, 0x0);
|
||||
Status = Status + CPLD_Write(0x09, 0x0);
|
||||
reg_addr = 0x06;
|
||||
Status = Status + CPLD_Write(reg_addr, reg_data);
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
Status = Status + CPLD_Write(0x06, 0x0);
|
||||
Status = Status + CPLD_Write(0x08, 0x0);
|
||||
Status = Status + CPLD_Write(0x09, 0x0);
|
||||
reg_addr = 0x07;
|
||||
Status = Status + CPLD_Write(reg_addr, reg_data);
|
||||
break;
|
||||
}
|
||||
case 3:
|
||||
{
|
||||
Status = Status + CPLD_Write(0x06, 0x0);
|
||||
Status = Status + CPLD_Write(0x07, 0x0);
|
||||
Status = Status + CPLD_Write(0x09, 0x0);
|
||||
reg_addr = 0x08;
|
||||
Status = Status + CPLD_Write(reg_addr, reg_data);
|
||||
break;
|
||||
}
|
||||
case 4:
|
||||
{
|
||||
Status = Status + CPLD_Write(0x06, 0x0);
|
||||
Status = Status + CPLD_Write(0x07, 0x0);
|
||||
Status = Status + CPLD_Write(0x08, 0x0);
|
||||
reg_addr = 0x09;
|
||||
Status = Status + CPLD_Write(reg_addr, reg_data);
|
||||
break;
|
||||
}
|
||||
default: //You should NOT be here
|
||||
{
|
||||
xil_printf("[E] Error Reaching Invaild Slot CPLD Formatting, Check PS Code!\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
|
||||
xil_printf("[E] Error Writing CPLD Reg! Check Log ABOVE!\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
xil_printf("[D] CPLD Write Successfully Done!\r\n");
|
||||
}
|
||||
|
||||
Status = CPLD_exec();
|
||||
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
xil_printf("[E] Error Exec CPLD ! Check Log ABOVE!\r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
xil_printf("[D] CPLD Exec Successfully Done!\r\n");
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
u8 sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
|
||||
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
|
||||
|
||||
xil_printf("cpld_addr: %d\n\r", cpld_addr);
|
||||
xil_printf("cpld_dat: %d\n\r", cpld_dat);
|
||||
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
slot_en = 0x00000000;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* cal_meas.h
|
||||
*
|
||||
* Created on: 2023年7月19日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_CAL_MEAS_H_
|
||||
#define SRC_CAL_MEAS_H_
|
||||
|
||||
#include "sleep.h"
|
||||
#include "stdio.h"
|
||||
#include "xstatus.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
#include "GPIO_Driv.h"
|
||||
#include "CPLD_Con.h"
|
||||
|
||||
#define CPLD_SPI_WRITE 5
|
||||
#define CPLD_SPI_READ 2
|
||||
#define DC_CMD_LEN 6
|
||||
#define Freq_CMD_LEN 7 //TODO: Update sw_config()!
|
||||
|
||||
int Command_Parser(u8 *recvbuffer, u8 len);
|
||||
int DC_Control(u8* idata);
|
||||
int CPLD_Write(u8 addr,u32 data);
|
||||
int CPLD_exec();
|
||||
void sw_config(char *slot_start);
|
||||
|
||||
|
||||
#endif /* SRC_CAL_MEAS_H_ */
|
||||
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* crc16.c
|
||||
*
|
||||
* Created on: 2022年2月24日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "crc16.h"
|
||||
|
||||
const unsigned int crc_table[256] = {
|
||||
0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
|
||||
0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
|
||||
0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
|
||||
0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
|
||||
0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
|
||||
0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
|
||||
0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
|
||||
0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
|
||||
0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
|
||||
0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
|
||||
0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
|
||||
0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
|
||||
0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
|
||||
0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
|
||||
0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
|
||||
0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
|
||||
0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
|
||||
0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
|
||||
0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
|
||||
0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
|
||||
0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
|
||||
0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
|
||||
0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
|
||||
0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
|
||||
0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
|
||||
0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
|
||||
0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
|
||||
0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
|
||||
0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
|
||||
0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
|
||||
0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
|
||||
0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
|
||||
};
|
||||
|
||||
unsigned short do_crc_table(unsigned char* ptr, int len)
|
||||
{
|
||||
unsigned short crc = 0x0000;
|
||||
|
||||
|
||||
while (len--)
|
||||
{
|
||||
crc = (crc >> 8) ^ crc_table[(crc ^ *ptr++) & 0xff];
|
||||
}
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* crc16.h
|
||||
*
|
||||
* Created on: 2022年2月24日
|
||||
* Author: Administrator
|
||||
*/
|
||||
|
||||
#ifndef SRC_CRC16_H_
|
||||
#define SRC_CRC16_H_
|
||||
|
||||
unsigned short do_crc_table(unsigned char* ptr, int len);
|
||||
|
||||
#endif /* SRC_CRC16_H_ */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* dna_read.c
|
||||
*
|
||||
* Created on: 2023年6月27日
|
||||
* Author: dell
|
||||
*/
|
||||
#include "dna_read.h"
|
||||
|
||||
#include <unistd.h>
|
||||
#include "xil_io.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
#define DNA_ADDR XPAR_MYDNA_READ_V1_0_0_BASEADDR
|
||||
|
||||
|
||||
void dna_port_read(char* read_data) //addr_change, because the board is 88d_a.
|
||||
{
|
||||
unsigned read_data_mem[2] = {0};
|
||||
Xil_Out32(DNA_ADDR,0x01);
|
||||
usleep(20);
|
||||
|
||||
read_data_mem[0] = Xil_In32(DNA_ADDR+4);
|
||||
read_data_mem[1] = Xil_In32(DNA_ADDR+8);
|
||||
|
||||
for(int i = 0; i < 8; i++)
|
||||
{
|
||||
*(read_data+i) = (u8)(read_data_mem[i/4]>> (24 - (8*(i%4))));
|
||||
}
|
||||
|
||||
}
|
||||
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* dna_read.h
|
||||
*
|
||||
* Created on: 2023年6月27日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_DNA_READ_H_
|
||||
#define SRC_DNA_READ_H_
|
||||
|
||||
void dna_port_read(char* read_data); //addr_change, because the board is 88d_a.
|
||||
|
||||
|
||||
#endif /* SRC_DNA_READ_H_ */
|
||||
@@ -0,0 +1,420 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file i2c_lib.c
|
||||
*
|
||||
* This file contains library functions to initialize, control and access
|
||||
* IIC devices.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------------
|
||||
* 1.0 srt 10/19/13 Initial Version
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xparameters.h"
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
|
||||
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
#include "xil_exception.h"
|
||||
#include "xil_printf.h"
|
||||
#include "xiicps.h"
|
||||
#include "sleep.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define IIC_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID
|
||||
#define XIIC XIicPs
|
||||
#define XIICCFG XIicPs_Config
|
||||
#define I2cSetStatusHandler XIicPs_SetStatusHandler
|
||||
#define I2cLookupConfig XIicPs_LookupConfig
|
||||
#define I2cCfgInitialize XIicPs_CfgInitialize
|
||||
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
|
||||
#define IIC_INTR_ID XPAR_XIICPS_0_INTR
|
||||
#define INTC_HANDLER XScuGic_InterruptHandler
|
||||
#define IIC_HANDLER XIicPs_IntrHandler
|
||||
#define INTC XScuGic
|
||||
#define IIC_SCLK_RATE 100000
|
||||
/**************************** Type Definitions *******************************/
|
||||
typedef struct {
|
||||
XIIC I2cInstance;
|
||||
INTC IntcInstance;
|
||||
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
|
||||
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
|
||||
volatile u32 TotalErrorCount;
|
||||
} XIIC_LIB;
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
|
||||
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
|
||||
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
|
||||
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
|
||||
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
|
||||
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr);
|
||||
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event);
|
||||
|
||||
/************************* Global Definitions *****************************/
|
||||
|
||||
/************************** Function Definitions *****************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function configures the IIC hardware.
|
||||
*
|
||||
* @param I2cLibPtr contains a pointer to the instance of the IIC library
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int I2cSetupHardware(XIIC_LIB *I2cLibPtr)
|
||||
{
|
||||
int Status;
|
||||
XIICCFG *ConfigPtr;
|
||||
XIIC *I2cInstancePtr;
|
||||
|
||||
I2cInstancePtr = &I2cLibPtr->I2cInstance;
|
||||
|
||||
/*
|
||||
* Initialize the IIC driver so that it is ready to use.
|
||||
*/
|
||||
ConfigPtr = I2cLookupConfig(IIC_DEVICE_ID);
|
||||
if (ConfigPtr == NULL) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = I2cCfgInitialize(I2cInstancePtr, ConfigPtr,
|
||||
ConfigPtr->BaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* GPIO Code to pull MUX out of reset.
|
||||
*/
|
||||
Xil_Out32(0xe000a204, 0x2000);
|
||||
Xil_Out32(0xe000a208, 0x2000);
|
||||
Xil_Out32(0xe000a040, 0x2000);
|
||||
|
||||
/*
|
||||
* Setup the Interrupt System.
|
||||
*/
|
||||
Status = SetupInterruptSystem(I2cLibPtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
I2cSetStatusHandler(I2cInstancePtr, I2cLibPtr, (IIC_HANDLER) StatusHandler);
|
||||
|
||||
/*
|
||||
* Set the IIC serial clock rate.
|
||||
*/
|
||||
XIicPs_SetSClk(I2cInstancePtr, IIC_SCLK_RATE);
|
||||
|
||||
I2cLibPtr->TotalErrorCount = 0;
|
||||
I2cLibPtr->TransmitComplete = FALSE;
|
||||
I2cLibPtr->ReceiveComplete = FALSE;
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function writes data to the PHY.
|
||||
*
|
||||
* @param I2cLibPtr contains a pointer to the instance of the IIC library
|
||||
* @param PhyAddr is the address of PHY to be written
|
||||
* @param Reg is the register address to be written to
|
||||
* @param Data is the pointer which contains the data to be written
|
||||
* @param SlaveAddr is the address of the slave we are sending to.
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr)
|
||||
{
|
||||
int Status;
|
||||
u8 WrBuffer[3];
|
||||
|
||||
WrBuffer[0] = Reg;
|
||||
WrBuffer[1] = Data >> 8;
|
||||
WrBuffer[2] = Data;
|
||||
|
||||
Status = I2cWriteData(I2cLibPtr, WrBuffer, 3, SlaveAddr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("PhyWrite: Writing data failed\n\r");
|
||||
return Status;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function reads data from the PHY.
|
||||
*
|
||||
* @param I2cLibPtr contains a pointer to the instance of the IIC library
|
||||
* @param PhyAddr is the address of PHY to be read from
|
||||
* @param Reg is the register address to be read from
|
||||
* @param Data is the pointer which stores the data read
|
||||
* @param SlaveAddr is the address of the slave we are sending to.
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr)
|
||||
{
|
||||
int Status;
|
||||
u8 WrBuffer[2];
|
||||
u8 RdBuffer[2];
|
||||
|
||||
WrBuffer[0] = Reg;
|
||||
|
||||
Status = I2cWriteData(I2cLibPtr, WrBuffer, 1, SlaveAddr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("PhyWrite: Writing data failed\n\r");
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = I2cReadData(I2cLibPtr, RdBuffer, 2, SlaveAddr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("PhyRead: Reading data failed\n\r");
|
||||
return Status;
|
||||
}
|
||||
|
||||
*Data = RdBuffer[0] << 8 | RdBuffer[1];
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function writes a buffer of data to the IIC Device.
|
||||
*
|
||||
* @param I2cLibPtr contains a pointer to the instance of the IIC library
|
||||
* @param WrBuffer is the buffer which contains data to be written
|
||||
* @param ByteCount contains the number of bytes in the buffer to be
|
||||
* written.
|
||||
* @param SlaveAddr is the address of the slave we are sending to.
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount,
|
||||
u16 SlaveAddr)
|
||||
{
|
||||
XIIC *I2cInstancePtr;
|
||||
|
||||
I2cInstancePtr = &I2cLibPtr->I2cInstance;
|
||||
|
||||
I2cLibPtr->TransmitComplete = FALSE;
|
||||
|
||||
/*
|
||||
* Send the Data.
|
||||
*/
|
||||
XIicPs_MasterSend(I2cInstancePtr, WrBuffer, ByteCount, SlaveAddr);
|
||||
|
||||
/*
|
||||
* Wait for the entire buffer to be sent, letting the interrupt
|
||||
* processing work in the background, this function may get
|
||||
* locked up in this loop if the interrupts are not working
|
||||
* correctly.
|
||||
*/
|
||||
while (I2cLibPtr->TransmitComplete == FALSE) {
|
||||
if (0 != I2cLibPtr->TotalErrorCount) {
|
||||
xil_printf("I2cWriteData: Failed due to errors\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait until bus is idle to start another transfer.
|
||||
*/
|
||||
while (XIicPs_BusIsBusy(I2cInstancePtr));
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function read data from the IIC Device.
|
||||
*
|
||||
* @param I2cLibPtr contains a pointer to the instance of the IIC library
|
||||
* @param RdBuffer is the buffer into which data read
|
||||
* @param ByteCount contains the number of bytes in the buffer to be
|
||||
* written.
|
||||
* @param SlaveAddr is the address of the slave we are sending to.
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr)
|
||||
{
|
||||
XIIC *I2cInstancePtr;
|
||||
|
||||
I2cInstancePtr = &I2cLibPtr->I2cInstance;
|
||||
|
||||
I2cLibPtr->ReceiveComplete = FALSE;
|
||||
|
||||
/*
|
||||
* Receive the Data.
|
||||
*/
|
||||
XIicPs_MasterRecv(I2cInstancePtr, RdBuffer, ByteCount, SlaveAddr);
|
||||
|
||||
while (I2cLibPtr->ReceiveComplete == FALSE) {
|
||||
if (0 != I2cLibPtr->TotalErrorCount) {
|
||||
xil_printf("I2cReadData: Failed due to errors %d\n\r",
|
||||
I2cLibPtr->TotalErrorCount);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait until bus is idle to start another transfer.
|
||||
*/
|
||||
while (XIicPs_BusIsBusy(I2cInstancePtr))
|
||||
;
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function setups the interrupt system so interrupts can occur for the
|
||||
* IIC device. The function is application-specific since the actual system may
|
||||
* or may not have an interrupt controller. The IIC device could be directly
|
||||
* connected to a processor without an interrupt controller. The user should
|
||||
* modify this function to fit the application.
|
||||
*
|
||||
* @param IicInstPtr contains a pointer to the instance of the IIC device
|
||||
* which is going to be connected to the interrupt controller.
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
|
||||
{
|
||||
int Status;
|
||||
XIIC *I2cInstancePtr;
|
||||
INTC *IntcPtr;
|
||||
|
||||
I2cInstancePtr = &I2cLibPtr->I2cInstance;
|
||||
IntcPtr = &I2cLibPtr->IntcInstance;
|
||||
|
||||
XScuGic_Config *IntcConfig;
|
||||
|
||||
/*
|
||||
* Initialize the interrupt controller driver so that it is ready to
|
||||
* use.
|
||||
*/
|
||||
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
|
||||
if (NULL == IntcConfig) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
|
||||
IntcConfig->CpuBaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
|
||||
|
||||
/*
|
||||
* Connect the interrupt handler that will be called when an
|
||||
* interrupt occurs for the device.
|
||||
*/
|
||||
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
|
||||
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
|
||||
I2cInstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the interrupt for the IIC device.
|
||||
*/
|
||||
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
|
||||
|
||||
/*
|
||||
* Initialize the exception table and register the interrupt
|
||||
* controller handler with the exception table
|
||||
*/
|
||||
Xil_ExceptionInit();
|
||||
|
||||
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
||||
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
|
||||
|
||||
/* Enable non-critical exceptions */Xil_ExceptionEnable();
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This Status handler is called asynchronously from an interrupt
|
||||
* context and indicates the events that have occurred.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the IIC driver instance for which
|
||||
* the handler is being called for.
|
||||
* @param Event indicates the condition that has occurred.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void StatusHandler(XIIC_LIB *I2cLibPtr, int Event)
|
||||
{
|
||||
/*
|
||||
* All of the data transfer has been finished.
|
||||
*/
|
||||
if (0 != (Event & XIICPS_EVENT_COMPLETE_RECV)) {
|
||||
I2cLibPtr->ReceiveComplete = TRUE;
|
||||
} else if (0 != (Event & XIICPS_EVENT_COMPLETE_SEND)) {
|
||||
I2cLibPtr->TransmitComplete = TRUE;
|
||||
} else if (0 == (Event & XIICPS_EVENT_SLAVE_RDY)) {
|
||||
/*
|
||||
* If it is other interrupt but not slave ready interrupt, it is
|
||||
* an error.
|
||||
* Data was received with an error.
|
||||
*/
|
||||
I2cLibPtr->TotalErrorCount++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
* Copyright (C) 2016 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
#if defined (__arm__) || defined(__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
#ifdef XPAR_XIICPS_0_DEVICE_ID
|
||||
#include "xiicps.h"
|
||||
|
||||
#define BUF_LEN 10U
|
||||
|
||||
#define IOEXPANDER1_ADDR 0x20U
|
||||
|
||||
#define IIC_SCLK_RATE_IOEXP 400000
|
||||
|
||||
#define CMD_CFG_0_REG 0x06U
|
||||
#define CMD_OUTPUT_0_REG 0x02U
|
||||
#define DATA_OUTPUT 0x0U
|
||||
|
||||
#define DATA_COMMON_CFG 0xE0U
|
||||
#define DATA_GT_0000_CFG 0x00U
|
||||
|
||||
XIicPs I2c0InstancePtr;
|
||||
|
||||
int IicPhyReset(void)
|
||||
{
|
||||
|
||||
u8 WriteBuffer[BUF_LEN] = {0};
|
||||
XIicPs_Config *I2c0CfgPtr;
|
||||
int Status = XST_SUCCESS;
|
||||
|
||||
/* Initialize the IIC0 driver so that it is ready to use */
|
||||
I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
|
||||
if (I2c0CfgPtr == NULL) {
|
||||
Status = XST_FAILURE;
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
|
||||
I2c0CfgPtr->BaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
return Status;
|
||||
}
|
||||
|
||||
/* Set the IIC serial clock rate */
|
||||
XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
|
||||
|
||||
/* Configure I/O pins as Output */
|
||||
WriteBuffer[0] = CMD_CFG_0_REG;
|
||||
WriteBuffer[1] = DATA_OUTPUT;
|
||||
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
|
||||
WriteBuffer, 2, IOEXPANDER1_ADDR);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
return Status;
|
||||
}
|
||||
|
||||
/* Wait until bus is idle to start another transfer */
|
||||
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
|
||||
|
||||
/*
|
||||
* Deasserting I2C_MUX_RESETB
|
||||
* And GEM3 Resetb
|
||||
* Selecting lanes based on configuration
|
||||
*/
|
||||
WriteBuffer[0] = CMD_OUTPUT_0_REG;
|
||||
/* gt0000 or no GT configuration */
|
||||
WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
|
||||
|
||||
/* Send the Data */
|
||||
Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
|
||||
WriteBuffer, 2, IOEXPANDER1_ADDR);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
return Status;
|
||||
}
|
||||
|
||||
/* Wait until bus is idle */
|
||||
while (XIicPs_BusIsBusy(&I2c0InstancePtr));
|
||||
|
||||
xil_printf("IIC PHY reset on ZCU102 successful \n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,293 @@
|
||||
/*******************************************************************/
|
||||
/* */
|
||||
/* This file is automatically generated by linker script generator.*/
|
||||
/* */
|
||||
/* Version: 2018.3 */
|
||||
/* */
|
||||
/* Copyright (c) 2010-2019 Xilinx, Inc. All rights reserved. */
|
||||
/* */
|
||||
/* Description : Cortex-A9 Linker Script */
|
||||
/* */
|
||||
/*******************************************************************/
|
||||
|
||||
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
|
||||
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
|
||||
|
||||
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
|
||||
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
|
||||
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
|
||||
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
|
||||
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
|
||||
|
||||
/* Define Memories in the system */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
|
||||
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000
|
||||
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
|
||||
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
|
||||
}
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_vector_table)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
. = ALIGN(2048);
|
||||
KEEP (*(.vectors))
|
||||
*(.boot)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu_warning)
|
||||
*(.gcc_execpt_table)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.vfp11_veneer)
|
||||
*(.ARM.extab)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
} > ps7_ddr_0
|
||||
|
||||
.init : {
|
||||
KEEP (*(.init))
|
||||
} > ps7_ddr_0
|
||||
|
||||
.fini : {
|
||||
KEEP (*(.fini))
|
||||
} > ps7_ddr_0
|
||||
|
||||
.rodata : {
|
||||
__rodata_start = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
__rodata_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.rodata1 : {
|
||||
__rodata1_start = .;
|
||||
*(.rodata1)
|
||||
*(.rodata1.*)
|
||||
__rodata1_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.sdata2 : {
|
||||
__sdata2_start = .;
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
__sdata2_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.sbss2 : {
|
||||
__sbss2_start = .;
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
__sbss2_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.data : {
|
||||
__data_start = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.jcr)
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
__data_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.data1 : {
|
||||
__data1_start = .;
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
__data1_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.got : {
|
||||
*(.got)
|
||||
} > ps7_ddr_0
|
||||
|
||||
.note.gnu.build-id : {
|
||||
KEEP (*(.note.gnu.build-id))
|
||||
} > ps7_ddr_0
|
||||
|
||||
.ctors : {
|
||||
__CTOR_LIST__ = .;
|
||||
___CTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
___CTORS_END___ = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.dtors : {
|
||||
__DTOR_LIST__ = .;
|
||||
___DTORS_LIST___ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
___DTORS_END___ = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.fixup : {
|
||||
__fixup_start = .;
|
||||
*(.fixup)
|
||||
__fixup_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.eh_frame : {
|
||||
*(.eh_frame)
|
||||
} > ps7_ddr_0
|
||||
|
||||
.eh_framehdr : {
|
||||
__eh_framehdr_start = .;
|
||||
*(.eh_framehdr)
|
||||
__eh_framehdr_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.gcc_except_table : {
|
||||
*(.gcc_except_table)
|
||||
} > ps7_ddr_0
|
||||
|
||||
.mmu_tbl (ALIGN(16384)) : {
|
||||
__mmu_tbl_start = .;
|
||||
*(.mmu_tbl)
|
||||
__mmu_tbl_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidix.*.*)
|
||||
__exidx_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.preinit_array : {
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(SORT(.preinit_array.*)))
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.init_array : {
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.fini_array : {
|
||||
__fini_array_start = .;
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.ARM.attributes : {
|
||||
__ARM.attributes_start = .;
|
||||
*(.ARM.attributes)
|
||||
__ARM.attributes_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.sdata : {
|
||||
__sdata_start = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
__sdata_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.sbss (NOLOAD) : {
|
||||
__sbss_start = .;
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
__sbss_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.tdata : {
|
||||
__tdata_start = .;
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
__tdata_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.tbss : {
|
||||
__tbss_start = .;
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
__tbss_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
__bss_start = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
__bss_end = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
|
||||
|
||||
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
|
||||
|
||||
/* Generate Stack and Heap definitions */
|
||||
|
||||
.heap (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
HeapBase = .;
|
||||
_heap_start = .;
|
||||
. += _HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
HeapLimit = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
.stack (NOLOAD) : {
|
||||
. = ALIGN(16);
|
||||
_stack_end = .;
|
||||
. += _STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
_stack = .;
|
||||
__stack = _stack;
|
||||
. = ALIGN(16);
|
||||
_irq_stack_end = .;
|
||||
. += _IRQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__irq_stack = .;
|
||||
_supervisor_stack_end = .;
|
||||
. += _SUPERVISOR_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__supervisor_stack = .;
|
||||
_abort_stack_end = .;
|
||||
. += _ABORT_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__abort_stack = .;
|
||||
_fiq_stack_end = .;
|
||||
. += _FIQ_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__fiq_stack = .;
|
||||
_undef_stack_end = .;
|
||||
. += _UNDEF_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
__undef_stack = .;
|
||||
} > ps7_ddr_0
|
||||
|
||||
_end = .;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xparameters.h"
|
||||
#include "platform.h"
|
||||
#include "platform_config.h"
|
||||
#if defined (__arm__) || defined(__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
#include "xil_cache.h"
|
||||
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
#include "uart_IO.h"
|
||||
|
||||
#include "lwip/tcp.h"
|
||||
extern void tcp_tmr(void); /* declared in tcp_priv.h, not in public tcp.h */
|
||||
#include "xil_cache.h"
|
||||
|
||||
#if LWIP_DHCP==1
|
||||
#include "lwip/dhcp.h"
|
||||
#endif
|
||||
|
||||
u8 recvbuffer[1024] = {0};
|
||||
|
||||
/* defined by each RAW mode application */
|
||||
void print_app_header();
|
||||
int start_application();
|
||||
int transfer_data();
|
||||
|
||||
/* missing declaration in lwIP */
|
||||
void lwip_init();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
extern volatile int dhcp_timoutcntr;
|
||||
err_t dhcp_start(struct netif *netif);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static struct netif server_netif;
|
||||
struct netif *echo_netif;
|
||||
|
||||
int main()
|
||||
{
|
||||
int iMainCom = 1;
|
||||
|
||||
init_platform();
|
||||
|
||||
xil_printf("=====================\r\n[I] System Init Done!\r\n");
|
||||
|
||||
xil_printf("[D] Start EMIO Config\r\n");
|
||||
EMIO_config();
|
||||
xil_printf("[D] End of EMIO Config\r\n");
|
||||
|
||||
xil_printf("[D] Start CPLD Reset\r\n");
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
rst_CPLD(CPLD_U3,4);
|
||||
xil_printf("[D] End of CPLD Reset\r\n");
|
||||
|
||||
xil_printf("[D] Config CPLD SPI to known state\r\n");
|
||||
interface_initial(CPLD_U1);
|
||||
interface_initial(CPLD_U2);
|
||||
interface_initial(CPLD_U3);
|
||||
|
||||
|
||||
|
||||
xil_printf("[I] Board Init Complete!\r\n[I] Waiting for Command...\r\n");
|
||||
/* receive and process Instructions */
|
||||
while (1)
|
||||
{
|
||||
int Status = -255;
|
||||
Status = UART_RecvInstr(recvbuffer);
|
||||
if (Status < 0)
|
||||
{
|
||||
xil_printf("[E] UART Receive ERROR!!! Check PrintOut Ahead\r\n");
|
||||
}
|
||||
else if (Status > 0)
|
||||
{
|
||||
Command_Parser(recvbuffer,Status); //Here Status should equal to length
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* never reached */
|
||||
cleanup_platform();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,86 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xil_cache.h"
|
||||
|
||||
#ifndef SDT
|
||||
#include "platform_config.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Uncomment one of the following two lines, depending on the target,
|
||||
* if ps7/psu init source files are added in the source directory for
|
||||
* compiling example outside of SDK.
|
||||
*/
|
||||
/*#include "ps7_init.h"*/
|
||||
/*#include "psu_init.h"*/
|
||||
|
||||
#ifdef STDOUT_IS_16550
|
||||
#include "xuartns550_l.h"
|
||||
|
||||
#define UART_BAUD 9600
|
||||
#endif
|
||||
|
||||
void
|
||||
enable_caches()
|
||||
{
|
||||
#ifdef __PPC__
|
||||
Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
|
||||
Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
|
||||
#elif __MICROBLAZE__
|
||||
#ifdef XPAR_MICROBLAZE_USE_ICACHE
|
||||
Xil_ICacheEnable();
|
||||
#endif
|
||||
#ifdef XPAR_MICROBLAZE_USE_DCACHE
|
||||
Xil_DCacheEnable();
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
disable_caches()
|
||||
{
|
||||
#ifdef __MICROBLAZE__
|
||||
#ifdef XPAR_MICROBLAZE_USE_DCACHE
|
||||
Xil_DCacheDisable();
|
||||
#endif
|
||||
#ifdef XPAR_MICROBLAZE_USE_ICACHE
|
||||
Xil_ICacheDisable();
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
init_uart()
|
||||
{
|
||||
#ifdef STDOUT_IS_16550
|
||||
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
|
||||
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
|
||||
#endif
|
||||
/* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
|
||||
}
|
||||
|
||||
void
|
||||
init_platform()
|
||||
{
|
||||
/*
|
||||
* If you want to run this example outside of SDK,
|
||||
* uncomment one of the following two lines and also #include "ps7_init.h"
|
||||
* or #include "ps7_init.h" at the top, depending on the target.
|
||||
* Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
|
||||
* along with this example source files for compilation.
|
||||
*/
|
||||
/* ps7_init();*/
|
||||
/* psu_init();*/
|
||||
enable_caches();
|
||||
init_uart();
|
||||
}
|
||||
|
||||
void
|
||||
cleanup_platform()
|
||||
{
|
||||
disable_caches();
|
||||
}
|
||||
@@ -0,0 +1,16 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PLATFORM_H_
|
||||
#define __PLATFORM_H_
|
||||
|
||||
#ifndef SDT
|
||||
#include "platform_config.h"
|
||||
#endif
|
||||
|
||||
void init_platform();
|
||||
void cleanup_platform();
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
#ifndef __PLATFORM_CONFIG_H_
|
||||
#define __PLATFORM_CONFIG_H_
|
||||
|
||||
#define STDOUT_IS_PS7_UART
|
||||
#define UART_DEVICE_ID 0
|
||||
|
||||
#define PLATFORM_EMAC_BASEADDR XPAR_XEMACPS_0_BASEADDR
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,192 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file sfp.c
|
||||
*
|
||||
* This file programs sfp phy chip.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------------
|
||||
* 1.0 srt 10/19/13 Initial Version
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xparameters.h"
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
|
||||
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
#include "xil_printf.h"
|
||||
#include "xiicps.h"
|
||||
#include "sleep.h"
|
||||
#include "xscugic.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define IIC_SLAVE_ADDR 0x56
|
||||
#define IIC_MUX_ADDRESS 0x74
|
||||
#define IIC_CHANNEL_ADDRESS 0x01
|
||||
|
||||
#define XIIC XIicPs
|
||||
#define INTC XScuGic
|
||||
/**************************** Type Definitions *******************************/
|
||||
typedef struct {
|
||||
XIIC I2cInstance;
|
||||
INTC IntcInstance;
|
||||
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
|
||||
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
|
||||
volatile u32 TotalErrorCount;
|
||||
} XIIC_LIB;
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
|
||||
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
|
||||
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
|
||||
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
|
||||
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
|
||||
/************************** Function Definitions *****************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function initializes ZC706 MUX.
|
||||
*
|
||||
* @param I2cLibPtr contains a pointer to the instance of the IIC library
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int ZC706MuxInit(XIIC_LIB *I2cLibInstancePtr)
|
||||
{
|
||||
u8 WrBuffer;
|
||||
int Status;
|
||||
|
||||
WrBuffer = IIC_CHANNEL_ADDRESS;
|
||||
|
||||
Status = I2cWriteData(I2cLibInstancePtr, &WrBuffer, 1, IIC_MUX_ADDRESS);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("SFP_PHY: Writing failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This function program SFP PHY.
|
||||
*
|
||||
* @return XST_SUCCESS if successful else XST_FAILURE.
|
||||
*
|
||||
******************************************************************************/
|
||||
int ProgramSfpPhy(void)
|
||||
{
|
||||
XIIC_LIB I2cLibInstance;
|
||||
int Status;
|
||||
u8 WrBuffer[2];
|
||||
u16 phy_read_val;
|
||||
|
||||
Status = I2cSetupHardware(&I2cLibInstance);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Fail!!!\n\r");
|
||||
xil_printf("SFP_PHY: Configuring HW failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
Status = ZC706MuxInit(&I2cLibInstance);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("SFP_PHY: Mux Init failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
WrBuffer[0] = 0;
|
||||
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 1, IIC_SLAVE_ADDR);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("SFP_PHY: Writing failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
/* Enabling 1000BASEX */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9088, IIC_SLAVE_ADDR);
|
||||
#else
|
||||
/* Enabling SGMII */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x1B, 0x9084, IIC_SLAVE_ADDR);
|
||||
#endif
|
||||
|
||||
/* Apply Soft Reset */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
|
||||
|
||||
/* Enable 1000BaseT Full Duplex capabilities */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x09, 0x0E00, IIC_SLAVE_ADDR);
|
||||
|
||||
/* Apply Soft Reset */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
|
||||
|
||||
/* Advertise 10/100 Capabilities else change the capabilities */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x04, 0x0141, IIC_SLAVE_ADDR);
|
||||
|
||||
/* Apply Soft Reset */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
|
||||
|
||||
/* Apply Soft Reset */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
|
||||
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x10, 0xF079, IIC_SLAVE_ADDR);
|
||||
/* Apply Soft Reset */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
|
||||
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9140, IIC_SLAVE_ADDR);
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
|
||||
usleep(1);
|
||||
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
|
||||
phy_read_val = 0x0;
|
||||
|
||||
while((phy_read_val & 0x0C00) != 0x0C00) {
|
||||
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
|
||||
}
|
||||
usleep(1);
|
||||
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
|
||||
I2cPhyRead(&I2cLibInstance, IIC_SLAVE_ADDR, 0x11, &phy_read_val, IIC_SLAVE_ADDR);
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0001, IIC_SLAVE_ADDR);
|
||||
|
||||
/* configure speed */
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x14, 0x0c61, IIC_SLAVE_ADDR);
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x00, 0x9340, IIC_SLAVE_ADDR);
|
||||
I2cPhyWrite(&I2cLibInstance, IIC_SLAVE_ADDR, 0x16, 0x0, IIC_SLAVE_ADDR);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file si5324.c
|
||||
*
|
||||
* This file programs si5324 chip which generates clock for the peripherals.
|
||||
*
|
||||
* Please refer to Si5324 Datasheet for more information
|
||||
* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
|
||||
*
|
||||
* Tested on Zynq ZC706 platform
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------------
|
||||
* 1.0 srt 10/19/13 Initial Version
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xparameters.h"
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || \
|
||||
XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
#include "xil_printf.h"
|
||||
#include "xiicps.h"
|
||||
#include "sleep.h"
|
||||
#include "xscugic.h"
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define IIC_SLAVE_ADDR 0x68
|
||||
#define IIC_MUX_ADDRESS 0x74
|
||||
#define IIC_CHANNEL_ADDRESS 0x10
|
||||
|
||||
#define XIIC XIicPs
|
||||
#define INTC XScuGic
|
||||
/**************************** Type Definitions *******************************/
|
||||
typedef struct SI324Info
|
||||
{
|
||||
u32 RegIndex; /* Register Number */
|
||||
u32 Value; /* Value to be Written */
|
||||
} SI324Info;
|
||||
|
||||
typedef struct {
|
||||
XIIC I2cInstance;
|
||||
INTC IntcInstance;
|
||||
volatile u8 TransmitComplete; /* Flag to check completion of Transmission */
|
||||
volatile u8 ReceiveComplete; /* Flag to check completion of Reception */
|
||||
volatile u32 TotalErrorCount;
|
||||
} XIIC_LIB;
|
||||
/************************** Function Prototypes *****************************/
|
||||
int I2cWriteData(XIIC_LIB *I2cLibPtr, u8 *WrBuffer, u16 ByteCount, u16 SlaveAddr);
|
||||
int I2cReadData(XIIC_LIB *I2cLibPtr, u8 *RdBuffer, u16 ByteCount, u16 SlaveAddr);
|
||||
int I2cPhyWrite(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 Data, u16 SlaveAddr);
|
||||
int I2cPhyRead(XIIC_LIB *I2cLibPtr, u8 PhyAddr, u8 Reg, u16 *Data, u16 SlaveAddr);
|
||||
int I2cSetupHardware(XIIC_LIB *I2cLibPtr);
|
||||
/************************* Global Definitions *****************************/
|
||||
/*
|
||||
* These configuration values generates 125MHz clock
|
||||
* For more information please refer to Si5324 Datasheet.
|
||||
*/
|
||||
SI324Info InitTable[] = {
|
||||
{ 0, 0x54}, /* Register 0 */
|
||||
{ 1, 0xE4}, /* Register 1 */
|
||||
{ 2, 0x12}, /* Register 2 */
|
||||
{ 3, 0x15}, /* Register 3 */
|
||||
{ 4, 0x92}, /* Register 4 */
|
||||
{ 5, 0xed}, /* Register 5 */
|
||||
{ 6, 0x2d}, /* Register 6 */
|
||||
{ 7, 0x2a}, /* Register 7 */
|
||||
{ 8, 0x00}, /* Register 8 */
|
||||
{ 9, 0xc0}, /* Register 9 */
|
||||
{ 10, 0x08}, /* Register 10 */
|
||||
{ 11, 0x40}, /* Register 11 */
|
||||
{ 19, 0x29}, /* Register 19 */
|
||||
{ 20, 0x3e}, /* Register 20 */
|
||||
{ 21, 0xff}, /* Register 21 */
|
||||
{ 22, 0xdf}, /* Register 22 */
|
||||
{ 23, 0x1f}, /* Register 23 */
|
||||
{ 24, 0x3f}, /* Register 24 */
|
||||
{ 25, 0x60}, /* Register 25 */
|
||||
{ 31, 0x00}, /* Register 31 */
|
||||
{ 32, 0x00}, /* Register 32 */
|
||||
{ 33, 0x05}, /* Register 33 */
|
||||
{ 34, 0x00}, /* Register 34 */
|
||||
{ 35, 0x00}, /* Register 35 */
|
||||
{ 36, 0x05}, /* Register 36 */
|
||||
{ 40, 0xc2}, /* Register 40 */
|
||||
{ 41, 0x22}, /* Register 41 */
|
||||
{ 42, 0xdf}, /* Register 42 */
|
||||
{ 43, 0x00}, /* Register 43 */
|
||||
{ 44, 0x77}, /* Register 44 */
|
||||
{ 45, 0x0b}, /* Register 45 */
|
||||
{ 46, 0x00}, /* Register 46 */
|
||||
{ 47, 0x77}, /* Register 47 */
|
||||
{ 48, 0x0b}, /* Register 48 */
|
||||
{ 55, 0x00}, /* Register 55 */
|
||||
{131, 0x1f}, /* Register 131 */
|
||||
{132, 0x02}, /* Register 132 */
|
||||
{137, 0x01}, /* Register 137 */
|
||||
{138, 0x0f}, /* Register 138 */
|
||||
{139, 0xff}, /* Register 139 */
|
||||
{142, 0x00}, /* Register 142 */
|
||||
{143, 0x00}, /* Register 143 */
|
||||
{136, 0x40} /* Register 136 */
|
||||
};
|
||||
|
||||
/************************** Function Definitions *****************************/
|
||||
int MuxInit(XIIC_LIB *I2cLibInstancePtr)
|
||||
{
|
||||
u8 WrBuffer[0];
|
||||
int Status;
|
||||
|
||||
WrBuffer[0] = IIC_CHANNEL_ADDRESS;
|
||||
|
||||
Status = I2cWriteData(I2cLibInstancePtr,
|
||||
WrBuffer, 1, IIC_MUX_ADDRESS);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Si5324: Writing failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
int ProgramSi5324(void)
|
||||
{
|
||||
XIIC_LIB I2cLibInstance;
|
||||
int Index;
|
||||
int Status;
|
||||
u8 WrBuffer[2];
|
||||
|
||||
Status = I2cSetupHardware(&I2cLibInstance);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Si5324: Configuring HW failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = MuxInit(&I2cLibInstance);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Si5324: Mux Init failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
for (Index = 0; Index < sizeof(InitTable)/8; Index++) {
|
||||
WrBuffer[0] = InitTable[Index].RegIndex;
|
||||
WrBuffer[1] = InitTable[Index].Value;
|
||||
|
||||
Status = I2cWriteData(&I2cLibInstance, WrBuffer, 2, IIC_SLAVE_ADDR);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Si5324: Writing failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
}
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,156 @@
|
||||
|
||||
#include "uart_IO.h"
|
||||
|
||||
int String_HexToVal_Multi(const char* str, u8* hex, u16 hex_max)
|
||||
{
|
||||
int num;
|
||||
u16 idx = 0;
|
||||
u8 tmp = 0;
|
||||
u8 high_nibble = 1;
|
||||
|
||||
if( str == NULL || hex == NULL || hex_max == 0 )
|
||||
{
|
||||
xil_printf("[E] We received something from UART but lost at converting stage(Pointer Problem?)\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
for( u16 i = 0; str[i] != '\0' && str[i] != '\r' && str[i] != '\n'; i++ )
|
||||
{
|
||||
char c = str[i];
|
||||
|
||||
// Skip whitespace (spaces, tabs)
|
||||
if( c == ' ' || c == '\t' ) continue;
|
||||
|
||||
// Convert hex char to nibble
|
||||
if( c >= '0' && c <= '9' ) num = c - '0';
|
||||
else if( c >= 'A' && c <= 'F' ) num = 10 + c - 'A';
|
||||
else if( c >= 'a' && c <= 'f' ) num = 10 + c - 'a';
|
||||
else
|
||||
{
|
||||
xil_printf("[E] Invalid hex '%c' at pos %d\r\n", c, i);
|
||||
return -2;
|
||||
}
|
||||
|
||||
if( high_nibble )
|
||||
{
|
||||
tmp = (u8)(num << 4);
|
||||
high_nibble = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp |= (u8)num;
|
||||
|
||||
if( idx >= hex_max )
|
||||
{
|
||||
xil_printf("[E] Output buffer overflow\r\n");
|
||||
return -3;
|
||||
}
|
||||
|
||||
hex[idx++] = tmp;
|
||||
high_nibble = 1;
|
||||
}
|
||||
}
|
||||
|
||||
// Check for incomplete final byte (odd number of hex chars)
|
||||
if( high_nibble == 0 )
|
||||
{
|
||||
xil_printf("[E] Odd-length hex string, last byte incomplete\r\n");
|
||||
return -4; // Incomplete byte is an error
|
||||
}
|
||||
|
||||
if( idx == 0 ) return 0;
|
||||
return (int)idx;
|
||||
}
|
||||
|
||||
|
||||
int Console_In( char* str, int max_len )
|
||||
{
|
||||
static char pending = 0; // Hold char after \r when not followed by \n
|
||||
// Persistent across calls for proper \r\n handling
|
||||
int i = 0;
|
||||
char c = pending;
|
||||
pending = 0; // Clear pending for this call
|
||||
|
||||
if( str == NULL || max_len < 2 ) return -1;
|
||||
|
||||
for( ; ; i++ )
|
||||
{
|
||||
// If we have a pending character, use it first
|
||||
if( c == 0 )
|
||||
{
|
||||
// Bounds check FIRST, BEFORE writing
|
||||
if( i >= max_len - 1 )
|
||||
{
|
||||
str[i] = '\0';
|
||||
xil_printf("[E] UART Input buffer overflow!\r\n");
|
||||
return -1; /* Buffer overflow */
|
||||
}
|
||||
|
||||
c = (char)inbyte();
|
||||
}
|
||||
|
||||
// Handle line endings
|
||||
if( c == '\r' )
|
||||
{
|
||||
// Consume potential \n after \r (Windows line ending)
|
||||
char next = (char)inbyte();
|
||||
if( next == '\n' )
|
||||
{
|
||||
// \r\n - consume both
|
||||
str[i] = '\0';
|
||||
pending = 0;
|
||||
return i;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Just \r - the next byte is not \n
|
||||
// Store it for next call (it might be the start of the next command)
|
||||
pending = next;
|
||||
str[i] = '\0';
|
||||
return i;
|
||||
}
|
||||
}
|
||||
else if( c == '\n' )
|
||||
{
|
||||
// Unix line ending
|
||||
str[i] = '\0';
|
||||
pending = 0;
|
||||
return i;
|
||||
}
|
||||
else
|
||||
{
|
||||
str[i] = c;
|
||||
c = 0; // Clear so we read next character
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int UART_RecvInstr(u8* recvbuffer)
|
||||
{
|
||||
char cin[4096] = {0};
|
||||
int len = 0;
|
||||
|
||||
int inCount = 0;
|
||||
inCount = Console_In( cin, 4096 );
|
||||
xil_printf("[I] Console_InByte: %d\r\n", inCount);
|
||||
len = String_HexToVal_Multi( cin, recvbuffer, HEX_MAX_LEN );
|
||||
if( len <= 0 ) return 0; /* 0 = no input, <0 = parse error */
|
||||
|
||||
// Validate command length
|
||||
if( len < CMD_LEN_MIN )
|
||||
{
|
||||
xil_printf("[E] Cmd too short: %d < %d\r\n", len, CMD_LEN_MIN);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if( len > CMD_LEN_MAX )
|
||||
{
|
||||
xil_printf("[E] Cmd too long: %d > %d\r\n", len, CMD_LEN_MAX);
|
||||
return -2;
|
||||
}
|
||||
xil_printf("[D] HexToVal: " );
|
||||
for( int i=0; i<len; i++ ) xil_printf(" %02x", recvbuffer[i] );
|
||||
xil_printf("\r\n");
|
||||
xil_printf("[D] Total Intake %d bytes\r\n",len);
|
||||
return len;
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
#ifndef __UART_IO_H_
|
||||
#define __UART_IO_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xparameters.h"
|
||||
#include "platform.h"
|
||||
#include "platform.h"
|
||||
#include "xil_types.h"
|
||||
#include "xil_printf.h"
|
||||
|
||||
// Command validation constants
|
||||
#define CMD_LEN_MIN 1 // Command code only (minimum)
|
||||
#define CMD_LEN_MAX 64 // Maximum reasonable command length
|
||||
#define HEX_MAX_LEN 1024 // Buffer size for hex parsing (matches buffer[] size)
|
||||
|
||||
int String_HexToVal_Multi(const char* str, u8* hex, u16 hex_max);
|
||||
int Console_In( char* str, int max_len );
|
||||
int UART_RecvInstr(u8* recvbuffer);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user